diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-shmobile/smp-r8a7779.c | 32 |
1 files changed, 5 insertions, 27 deletions
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 63c8db966fb2..bdd38091dc9e 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c | |||
@@ -58,9 +58,6 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { | |||
58 | [3] = &r8a7779_ch_cpu3, | 58 | [3] = &r8a7779_ch_cpu3, |
59 | }; | 59 | }; |
60 | 60 | ||
61 | static DEFINE_SPINLOCK(scu_lock); | ||
62 | static unsigned long tmp; | ||
63 | |||
64 | #ifdef CONFIG_HAVE_ARM_TWD | 61 | #ifdef CONFIG_HAVE_ARM_TWD |
65 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); | 62 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); |
66 | void __init r8a7779_register_twd(void) | 63 | void __init r8a7779_register_twd(void) |
@@ -79,20 +76,6 @@ static int r8a7779_scu_psr_core_disabled(int cpu) | |||
79 | return 0; | 76 | return 0; |
80 | } | 77 | } |
81 | 78 | ||
82 | static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) | ||
83 | { | ||
84 | void __iomem *scu_base = shmobile_scu_base; | ||
85 | |||
86 | spin_lock(&scu_lock); | ||
87 | tmp = __raw_readl(scu_base + 8); | ||
88 | tmp &= ~clr; | ||
89 | tmp |= set; | ||
90 | spin_unlock(&scu_lock); | ||
91 | |||
92 | /* disable cache coherency after releasing the lock */ | ||
93 | __raw_writel(tmp, scu_base + 8); | ||
94 | } | ||
95 | |||
96 | static int r8a7779_platform_cpu_kill(unsigned int cpu) | 79 | static int r8a7779_platform_cpu_kill(unsigned int cpu) |
97 | { | 80 | { |
98 | struct r8a7779_pm_ch *ch = NULL; | 81 | struct r8a7779_pm_ch *ch = NULL; |
@@ -133,7 +116,7 @@ static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) | |||
133 | flush_cache_all(); | 116 | flush_cache_all(); |
134 | 117 | ||
135 | /* disable cache coherency */ | 118 | /* disable cache coherency */ |
136 | modify_scu_cpu_psr(3 << (cpu * 8), 0); | 119 | scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); |
137 | 120 | ||
138 | /* Endless loop until power off from r8a7779_cpu_kill() */ | 121 | /* Endless loop until power off from r8a7779_cpu_kill() */ |
139 | while (1) | 122 | while (1) |
@@ -158,9 +141,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct | |||
158 | 141 | ||
159 | cpu = cpu_logical_map(cpu); | 142 | cpu = cpu_logical_map(cpu); |
160 | 143 | ||
161 | /* enable cache coherency */ | ||
162 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | ||
163 | |||
164 | if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) | 144 | if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) |
165 | ch = r8a7779_ch_cpu[cpu]; | 145 | ch = r8a7779_ch_cpu[cpu]; |
166 | 146 | ||
@@ -172,15 +152,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct | |||
172 | 152 | ||
173 | static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) | 153 | static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) |
174 | { | 154 | { |
175 | int cpu = cpu_logical_map(0); | ||
176 | |||
177 | scu_enable(shmobile_scu_base); | 155 | scu_enable(shmobile_scu_base); |
178 | 156 | ||
179 | /* Map the reset vector (in headsmp.S) */ | 157 | /* Map the reset vector (in headsmp-scu.S) */ |
180 | __raw_writel(__pa(shmobile_secondary_vector), AVECR); | 158 | __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); |
181 | 159 | ||
182 | /* enable cache coherency on CPU0 */ | 160 | /* enable cache coherency on booting CPU */ |
183 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | 161 | scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); |
184 | 162 | ||
185 | r8a7779_pm_init(); | 163 | r8a7779_pm_init(); |
186 | 164 | ||