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-rw-r--r--arch/arm/mach-imx/Kconfig9
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/clock-imx27.c2
-rw-r--r--arch/arm/mach-imx/devices.c52
-rw-r--r--arch/arm/mach-imx/devices.h2
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c180
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c95
-rw-r--r--arch/arm/mach-imx/mach-pca100.c91
-rw-r--r--arch/arm/mach-imx/pm-imx27.c46
-rw-r--r--arch/arm/mach-mx25/Kconfig21
-rw-r--r--arch/arm/mach-mx25/Makefile2
-rw-r--r--arch/arm/mach-mx25/clock.c63
-rw-r--r--arch/arm/mach-mx25/devices.c82
-rw-r--r--arch/arm/mach-mx25/devices.h4
-rw-r--r--arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c261
-rw-r--r--arch/arm/mach-mx25/mach-cpuimx25.c173
-rw-r--r--arch/arm/mach-mx25/mach-mx25_3ds.c37
-rw-r--r--arch/arm/mach-mx3/Kconfig25
-rw-r--r--arch/arm/mach-mx3/Makefile2
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c2
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c264
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c227
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c23
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c1
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c3
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c2
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c28
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c11
-rw-r--r--arch/arm/mach-mx5/devices.c58
-rw-r--r--arch/arm/mach-mx5/devices.h3
-rw-r--r--arch/arm/plat-mxc/Kconfig1
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c15
-rw-r--r--arch/arm/plat-mxc/clock.c37
-rw-r--r--arch/arm/plat-mxc/ehci.c46
-rw-r--r--arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h40
-rw-r--r--arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h40
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h553
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/mmc.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_nand.h4
42 files changed, 2210 insertions, 353 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3da53557c665..c5c0369bb481 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -130,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2
130 bool "CPUIMX27 integrates SDHC2 module" 130 bool "CPUIMX27 integrates SDHC2 module"
131 depends on MACH_CPUIMX27 131 depends on MACH_CPUIMX27
132 help 132 help
133 This adds support for the internal SDHC2 used on CPUIMX27 used 133 This adds support for the internal SDHC2 used on CPUIMX27
134 for wifi or eMMC. 134 for wifi or eMMC.
135 135
136config MACH_EUKREA_CPUIMX27_USEUART4
137 bool "CPUIMX27 integrates UART4 module"
138 depends on MACH_CPUIMX27
139 help
140 This adds support for the internal UART4 used on CPUIMX27
141 for bluetooth.
142
136choice 143choice
137 prompt "Baseboard" 144 prompt "Baseboard"
138 depends on MACH_CPUIMX27 145 depends on MACH_CPUIMX27
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 86b53e6bc94e..46a9fdfbbd15 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
11obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o 11obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
12obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o 12obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
13 13
14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o 14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o 15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
16 16
17# Support for CMOS sensor interface 17# Support for CMOS sensor interface
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 0f0823c8b170..5a1aa15c8a16 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
644 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 644 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
645 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) 645 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
646 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 646 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
647 _REGISTER_CLOCK(NULL, "csi", csi_clk) 647 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
648 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) 648 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
649 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) 649 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
650 _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) 650 _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 9510687c4be3..9c271a752b84 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -187,6 +187,38 @@ int __init imx1_register_gpios(void)
187#endif 187#endif
188 188
189#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) 189#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
190
191#ifdef CONFIG_MACH_MX27
192static struct resource mx27_camera_resources[] = {
193 {
194 .start = MX27_CSI_BASE_ADDR,
195 .end = MX27_CSI_BASE_ADDR + 0x1f,
196 .flags = IORESOURCE_MEM,
197 }, {
198 .start = MX27_EMMA_PRP_BASE_ADDR,
199 .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
200 .flags = IORESOURCE_MEM,
201 }, {
202 .start = MX27_INT_CSI,
203 .end = MX27_INT_CSI,
204 .flags = IORESOURCE_IRQ,
205 },{
206 .start = MX27_INT_EMMAPRP,
207 .end = MX27_INT_EMMAPRP,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211struct platform_device mx27_camera_device = {
212 .name = "mx2-camera",
213 .id = 0,
214 .num_resources = ARRAY_SIZE(mx27_camera_resources),
215 .resource = mx27_camera_resources,
216 .dev = {
217 .coherent_dma_mask = 0xffffffff,
218 },
219};
220#endif
221
190/* 222/*
191 * General Purpose Timer 223 * General Purpose Timer
192 * - i.MX21: 3 timers 224 * - i.MX21: 3 timers
@@ -554,4 +586,24 @@ struct platform_device mx21_usbhc_device = {
554 .resource = mx21_usbhc_resources, 586 .resource = mx21_usbhc_resources,
555}; 587};
556#endif 588#endif
589
590static struct resource imx_kpp_resources[] = {
591 {
592 .start = MX2x_KPP_BASE_ADDR,
593 .end = MX2x_KPP_BASE_ADDR + 0xf,
594 .flags = IORESOURCE_MEM
595 }, {
596 .start = MX2x_INT_KPP,
597 .end = MX2x_INT_KPP,
598 .flags = IORESOURCE_IRQ,
599 },
600};
601
602struct platform_device imx_kpp_device = {
603 .name = "imx-keypad",
604 .id = -1,
605 .num_resources = ARRAY_SIZE(imx_kpp_resources),
606 .resource = imx_kpp_resources,
607};
608
557#endif 609#endif
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 109f26cd3b1b..efd4527506a5 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -21,10 +21,12 @@ extern struct platform_device mxc_pwm_device;
21extern struct platform_device mxc_sdhc_device0; 21extern struct platform_device mxc_sdhc_device0;
22extern struct platform_device mxc_sdhc_device1; 22extern struct platform_device mxc_sdhc_device1;
23extern struct platform_device mxc_otg_udc_device; 23extern struct platform_device mxc_otg_udc_device;
24extern struct platform_device mx27_camera_device;
24extern struct platform_device mxc_otg_host; 25extern struct platform_device mxc_otg_host;
25extern struct platform_device mxc_usbh1; 26extern struct platform_device mxc_usbh1;
26extern struct platform_device mxc_usbh2; 27extern struct platform_device mxc_usbh2;
27extern struct platform_device mx21_usbhc_device; 28extern struct platform_device mx21_usbhc_device;
28extern struct platform_device imx_ssi_device0; 29extern struct platform_device imx_ssi_device0;
29extern struct platform_device imx_ssi_device1; 30extern struct platform_device imx_ssi_device1;
31extern struct platform_device imx_kpp_device;
30#endif 32#endif
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 1fb34f375b22..27e7226ec9d4 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com 2 * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
3 * 3 *
4 * Based on pcm970-baseboard.c which is : 4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -24,6 +24,9 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h> 26#include <linux/spi/ads7846.h>
27#include <linux/backlight.h>
28#include <video/platform_lcd.h>
29#include <linux/input/matrix_keypad.h>
27 30
28#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
29 32
@@ -32,6 +35,9 @@
32#include <mach/imxfb.h> 35#include <mach/imxfb.h>
33#include <mach/hardware.h> 36#include <mach/hardware.h>
34#include <mach/mmc.h> 37#include <mach/mmc.h>
38#include <mach/spi.h>
39#include <mach/ssi.h>
40#include <mach/audmux.h>
35 41
36#include "devices-imx27.h" 42#include "devices-imx27.h"
37#include "devices.h" 43#include "devices.h"
@@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = {
48 PE10_PF_UART3_CTS, 54 PE10_PF_UART3_CTS,
49 PE11_PF_UART3_RTS, 55 PE11_PF_UART3_RTS,
50 /* UART4 */ 56 /* UART4 */
57#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
51 PB26_AF_UART4_RTS, 58 PB26_AF_UART4_RTS,
52 PB28_AF_UART4_TXD, 59 PB28_AF_UART4_TXD,
53 PB29_AF_UART4_CTS, 60 PB29_AF_UART4_CTS,
54 PB31_AF_UART4_RXD, 61 PB31_AF_UART4_RXD,
62#endif
55 /* SDHC1*/ 63 /* SDHC1*/
56 PE18_PF_SD1_D0, 64 PE18_PF_SD1_D0,
57 PE19_PF_SD1_D1, 65 PE19_PF_SD1_D1,
@@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = {
84 PA30_PF_CONTRAST, 92 PA30_PF_CONTRAST,
85 PA31_PF_OE_ACD, 93 PA31_PF_OE_ACD,
86 /* SPI1 */ 94 /* SPI1 */
87 PD28_PF_CSPI1_SS0,
88 PD29_PF_CSPI1_SCLK, 95 PD29_PF_CSPI1_SCLK,
89 PD30_PF_CSPI1_MISO, 96 PD30_PF_CSPI1_MISO,
90 PD31_PF_CSPI1_MOSI, 97 PD31_PF_CSPI1_MOSI,
98 /* SSI4 */
99#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
100 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
101 PC16_PF_SSI4_FS,
102 PC17_PF_SSI4_RXD | GPIO_PUEN,
103 PC18_PF_SSI4_TXD | GPIO_PUEN,
104 PC19_PF_SSI4_CLK,
105#endif
106};
107
108static const uint32_t eukrea_mbimx27_keymap[] = {
109 KEY(0, 0, KEY_UP),
110 KEY(0, 1, KEY_DOWN),
111 KEY(1, 0, KEY_RIGHT),
112 KEY(1, 1, KEY_LEFT),
113};
114
115static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
116 .keymap = eukrea_mbimx27_keymap,
117 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
91}; 118};
92 119
93static struct gpio_led gpio_leds[] = { 120static struct gpio_led gpio_leds[] = {
@@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = {
103 .active_low = 1, 130 .active_low = 1,
104 .gpio = GPIO_PORTF | 19, 131 .gpio = GPIO_PORTF | 19,
105 }, 132 },
106 {
107 .name = "backlight",
108 .default_trigger = "backlight",
109 .active_low = 0,
110 .gpio = GPIO_PORTE | 5,
111 },
112}; 133};
113 134
114static struct gpio_led_platform_data gpio_led_info = { 135static struct gpio_led_platform_data gpio_led_info = {
@@ -127,7 +148,7 @@ static struct platform_device leds_gpio = {
127static struct imx_fb_videomode eukrea_mbimx27_modes[] = { 148static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
128 { 149 {
129 .mode = { 150 .mode = {
130 .name = "CMO-QGVA", 151 .name = "CMO-QVGA",
131 .refresh = 60, 152 .refresh = 60,
132 .xres = 320, 153 .xres = 320,
133 .yres = 240, 154 .yres = 240,
@@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
141 }, 162 },
142 .pcr = 0xFAD08B80, 163 .pcr = 0xFAD08B80,
143 .bpp = 16, 164 .bpp = 16,
165 }, {
166 .mode = {
167 .name = "DVI-VGA",
168 .refresh = 60,
169 .xres = 640,
170 .yres = 480,
171 .pixclock = 32000,
172 .hsync_len = 1,
173 .left_margin = 35,
174 .right_margin = 0,
175 .vsync_len = 1,
176 .upper_margin = 7,
177 .lower_margin = 0,
178 },
179 .pcr = 0xFA208B80,
180 .bpp = 16,
181 }, {
182 .mode = {
183 .name = "DVI-SVGA",
184 .refresh = 60,
185 .xres = 800,
186 .yres = 600,
187 .pixclock = 25000,
188 .hsync_len = 1,
189 .left_margin = 35,
190 .right_margin = 0,
191 .vsync_len = 1,
192 .upper_margin = 7,
193 .lower_margin = 0,
194 },
195 .pcr = 0xFA208B80,
196 .bpp = 16,
144 }, 197 },
145}; 198};
146 199
@@ -153,11 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
153 .dmacr = 0x00040060, 206 .dmacr = 0x00040060,
154}; 207};
155 208
209static void eukrea_mbimx27_bl_set_intensity(int intensity)
210{
211 if (intensity)
212 gpio_direction_output(GPIO_PORTE | 5, 1);
213 else
214 gpio_direction_output(GPIO_PORTE | 5, 0);
215}
216
217static struct generic_bl_info eukrea_mbimx27_bl_info = {
218 .name = "eukrea_mbimx27-bl",
219 .max_intensity = 0xff,
220 .default_intensity = 0xff,
221 .set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
222};
223
224static struct platform_device eukrea_mbimx27_bl_dev = {
225 .name = "generic-bl",
226 .id = 1,
227 .dev = {
228 .platform_data = &eukrea_mbimx27_bl_info,
229 },
230};
231
232static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
233 unsigned int power)
234{
235 if (power)
236 gpio_direction_output(GPIO_PORTA | 25, 1);
237 else
238 gpio_direction_output(GPIO_PORTA | 25, 0);
239}
240
241static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
242 .set_power = eukrea_mbimx27_lcd_power_set,
243};
244
245static struct platform_device eukrea_mbimx27_lcd_powerdev = {
246 .name = "platform-lcd",
247 .dev.platform_data = &eukrea_mbimx27_lcd_power_data,
248};
249
156static const struct imxuart_platform_data uart_pdata __initconst = { 250static const struct imxuart_platform_data uart_pdata __initconst = {
157 .flags = IMXUART_HAVE_RTSCTS, 251 .flags = IMXUART_HAVE_RTSCTS,
158}; 252};
159 253
160#if defined(CONFIG_TOUCHSCREEN_ADS7846) 254#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
161 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 255 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
162 256
163#define ADS7846_PENDOWN (GPIO_PORTD | 25) 257#define ADS7846_PENDOWN (GPIO_PORTD | 25)
@@ -168,7 +262,6 @@ static void ads7846_dev_init(void)
168 printk(KERN_ERR "can't get ads746 pen down GPIO\n"); 262 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
169 return; 263 return;
170 } 264 }
171
172 gpio_direction_input(ADS7846_PENDOWN); 265 gpio_direction_input(ADS7846_PENDOWN);
173} 266}
174 267
@@ -181,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = {
181 .get_pendown_state = ads7846_get_pendown_state, 274 .get_pendown_state = ads7846_get_pendown_state,
182 .keep_vref_on = 1, 275 .keep_vref_on = 1,
183}; 276};
277#endif
184 278
279#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
185static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { 280static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
186 [0] = { 281 [0] = {
187 .modalias = "ads7846", 282 .modalias = "ads7846",
@@ -194,6 +289,12 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
194 }, 289 },
195}; 290};
196 291
292static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
293 {
294 I2C_BOARD_INFO("tlv320aic23", 0x1a),
295 },
296};
297
197static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28}; 298static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
198 299
199static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = { 300static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
@@ -206,6 +307,14 @@ static struct platform_device *platform_devices[] __initdata = {
206 &leds_gpio, 307 &leds_gpio,
207}; 308};
208 309
310static struct imxmmc_platform_data sdhc_pdata = {
311 .dat3_card_detect = 1,
312};
313
314struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
315 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
316};
317
209/* 318/*
210 * system init for baseboard usage. Will be called by cpuimx27 init. 319 * system init for baseboard usage. Will be called by cpuimx27 init.
211 * 320 *
@@ -217,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void)
217 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, 326 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
218 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); 327 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
219 328
329#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
330 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
331 /* SSI unit master I2S codec connected to SSI_PINS_4*/
332 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
333 MXC_AUDMUX_V1_PCR_SYN |
334 MXC_AUDMUX_V1_PCR_TFSDIR |
335 MXC_AUDMUX_V1_PCR_TCLKDIR |
336 MXC_AUDMUX_V1_PCR_RFSDIR |
337 MXC_AUDMUX_V1_PCR_RCLKDIR |
338 MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
339 MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
340 MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
341 );
342 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
343 MXC_AUDMUX_V1_PCR_SYN |
344 MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
345 );
346#endif
347
220 imx27_add_imx_uart1(&uart_pdata); 348 imx27_add_imx_uart1(&uart_pdata);
221 imx27_add_imx_uart2(&uart_pdata); 349 imx27_add_imx_uart2(&uart_pdata);
350#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
351 imx27_add_imx_uart3(&uart_pdata);
352#endif
222 353
223 mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); 354 mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
224 mxc_register_device(&mxc_sdhc_device0, NULL); 355 mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
225 356
226#if defined(CONFIG_TOUCHSCREEN_ADS7846) 357 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
358 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
359
360 mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
361
362#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
227 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 363 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
228 /* SPI and ADS7846 Touchscreen controler init */ 364 /* ADS7846 Touchscreen controller init */
229 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
230 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN); 365 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
366 ads7846_dev_init();
367#endif
368
369#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
370 /* SPI_CS0 init */
371 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
231 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); 372 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
232 spi_register_board_info(eukrea_mbimx27_spi_board_info, 373 spi_register_board_info(eukrea_mbimx27_spi_board_info,
233 ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); 374 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
234 ads7846_dev_init();
235#endif 375#endif
236 376
237 /* Leds configuration */ 377 /* Leds configuration */
@@ -239,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void)
239 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT); 379 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
240 /* Backlight */ 380 /* Backlight */
241 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT); 381 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
382 gpio_request(GPIO_PORTE | 5, "backlight");
383 platform_device_register(&eukrea_mbimx27_bl_dev);
384 /* LCD Reset */
385 mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
386 gpio_request(GPIO_PORTA | 25, "lcd_enable");
387 platform_device_register(&eukrea_mbimx27_lcd_powerdev);
388
389 mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
242 390
243 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 391 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
244} 392}
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 09cc0c5c2513..2a135449e52c 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -26,6 +26,9 @@
26#include <linux/mtd/physmap.h> 26#include <linux/mtd/physmap.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/serial_8250.h> 28#include <linux/serial_8250.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/ulpi.h>
31#include <linux/fsl_devices.h>
29 32
30#include <asm/mach-types.h> 33#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
@@ -37,6 +40,8 @@
37#include <mach/hardware.h> 40#include <mach/hardware.h>
38#include <mach/iomux-mx27.h> 41#include <mach/iomux-mx27.h>
39#include <mach/mxc_nand.h> 42#include <mach/mxc_nand.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h>
40 45
41#include "devices-imx27.h" 46#include "devices-imx27.h"
42#include "devices.h" 47#include "devices.h"
@@ -48,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = {
48 PE14_PF_UART1_CTS, 53 PE14_PF_UART1_CTS,
49 PE15_PF_UART1_RTS, 54 PE15_PF_UART1_RTS,
50 /* UART4 */ 55 /* UART4 */
56#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
51 PB26_AF_UART4_RTS, 57 PB26_AF_UART4_RTS,
52 PB28_AF_UART4_TXD, 58 PB28_AF_UART4_TXD,
53 PB29_AF_UART4_CTS, 59 PB29_AF_UART4_CTS,
54 PB31_AF_UART4_RXD, 60 PB31_AF_UART4_RXD,
61#endif
55 /* FEC */ 62 /* FEC */
56 PD0_AIN_FEC_TXD0, 63 PD0_AIN_FEC_TXD0,
57 PD1_AIN_FEC_TXD1, 64 PD1_AIN_FEC_TXD1,
@@ -75,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = {
75 PD17_PF_I2C_DATA, 82 PD17_PF_I2C_DATA,
76 PD18_PF_I2C_CLK, 83 PD18_PF_I2C_CLK,
77 /* SDHC2 */ 84 /* SDHC2 */
85#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
78 PB4_PF_SD2_D0, 86 PB4_PF_SD2_D0,
79 PB5_PF_SD2_D1, 87 PB5_PF_SD2_D1,
80 PB6_PF_SD2_D2, 88 PB6_PF_SD2_D2,
81 PB7_PF_SD2_D3, 89 PB7_PF_SD2_D3,
82 PB8_PF_SD2_CMD, 90 PB8_PF_SD2_CMD,
83 PB9_PF_SD2_CLK, 91 PB9_PF_SD2_CLK,
92#endif
84#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 93#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
85 /* Quad UART's IRQ */ 94 /* Quad UART's IRQ */
86 GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN, 95 GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
87 GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN, 96 GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
88 GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN, 97 GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
89 GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN, 98 GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
90#endif 99#endif
100 /* OTG */
101 PC7_PF_USBOTG_DATA5,
102 PC8_PF_USBOTG_DATA6,
103 PC9_PF_USBOTG_DATA0,
104 PC10_PF_USBOTG_DATA2,
105 PC11_PF_USBOTG_DATA1,
106 PC12_PF_USBOTG_DATA4,
107 PC13_PF_USBOTG_DATA3,
108 PE0_PF_USBOTG_NXT,
109 PE1_PF_USBOTG_STP,
110 PE2_PF_USBOTG_DIR,
111 PE24_PF_USBOTG_CLK,
112 PE25_PF_USBOTG_DATA7,
113 /* USBH2 */
114 PA0_PF_USBH2_CLK,
115 PA1_PF_USBH2_DIR,
116 PA2_PF_USBH2_DATA7,
117 PA3_PF_USBH2_NXT,
118 PA4_PF_USBH2_STP,
119 PD19_AF_USBH2_DATA4,
120 PD20_AF_USBH2_DATA3,
121 PD21_AF_USBH2_DATA6,
122 PD22_AF_USBH2_DATA0,
123 PD23_AF_USBH2_DATA2,
124 PD24_AF_USBH2_DATA1,
125 PD26_AF_USBH2_DATA5,
91}; 126};
92 127
93static struct physmap_flash_data eukrea_cpuimx27_flash_data = { 128static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
@@ -123,6 +158,8 @@ cpuimx27_nand_board_info __initconst = {
123static struct platform_device *platform_devices[] __initdata = { 158static struct platform_device *platform_devices[] __initdata = {
124 &eukrea_cpuimx27_nor_mtd_device, 159 &eukrea_cpuimx27_nor_mtd_device,
125 &mxc_fec_device, 160 &mxc_fec_device,
161 &mxc_wdt,
162 &mxc_w1_master_device,
126}; 163};
127 164
128static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { 165static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
@@ -178,6 +215,38 @@ static struct platform_device serial_device = {
178}; 215};
179#endif 216#endif
180 217
218#if defined(CONFIG_USB_ULPI)
219static struct mxc_usbh_platform_data otg_pdata = {
220 .portsc = MXC_EHCI_MODE_ULPI,
221 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
222};
223
224static struct mxc_usbh_platform_data usbh2_pdata = {
225 .portsc = MXC_EHCI_MODE_ULPI,
226 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
227};
228#endif
229
230static struct fsl_usb2_platform_data otg_device_pdata = {
231 .operating_mode = FSL_USB2_DR_DEVICE,
232 .phy_mode = FSL_USB2_PHY_ULPI,
233};
234
235static int otg_mode_host;
236
237static int __init eukrea_cpuimx27_otg_mode(char *options)
238{
239 if (!strcmp(options, "host"))
240 otg_mode_host = 1;
241 else if (!strcmp(options, "device"))
242 otg_mode_host = 0;
243 else
244 pr_info("otg_mode neither \"host\" nor \"device\". "
245 "Defaulting to device\n");
246 return 0;
247}
248__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
249
181static void __init eukrea_cpuimx27_init(void) 250static void __init eukrea_cpuimx27_init(void)
182{ 251{
183 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, 252 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
@@ -197,6 +266,8 @@ static void __init eukrea_cpuimx27_init(void)
197#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) 266#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
198 /* SDHC2 can be used for Wifi */ 267 /* SDHC2 can be used for Wifi */
199 mxc_register_device(&mxc_sdhc_device1, NULL); 268 mxc_register_device(&mxc_sdhc_device1, NULL);
269#endif
270#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
200 /* in which case UART4 is also used for Bluetooth */ 271 /* in which case UART4 is also used for Bluetooth */
201 imx27_add_imx_uart3(&uart_pdata); 272 imx27_add_imx_uart3(&uart_pdata);
202#endif 273#endif
@@ -205,6 +276,22 @@ static void __init eukrea_cpuimx27_init(void)
205 platform_device_register(&serial_device); 276 platform_device_register(&serial_device);
206#endif 277#endif
207 278
279#if defined(CONFIG_USB_ULPI)
280 if (otg_mode_host) {
281 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
282 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
283
284 mxc_register_device(&mxc_otg_host, &otg_pdata);
285 }
286
287 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
288 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
289
290 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
291#endif
292 if (!otg_mode_host)
293 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
294
208#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD 295#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
209 eukrea_mbimx27_baseboard_init(); 296 eukrea_mbimx27_baseboard_init();
210#endif 297#endif
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index ff3cf1ef31b4..6c92deaf468f 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -44,12 +44,16 @@
44#include <mach/mmc.h> 44#include <mach/mmc.h>
45#include <mach/mxc_ehci.h> 45#include <mach/mxc_ehci.h>
46#include <mach/ulpi.h> 46#include <mach/ulpi.h>
47#include <mach/imxfb.h>
47 48
48#include "devices-imx27.h" 49#include "devices-imx27.h"
49#include "devices.h" 50#include "devices.h"
50 51
51#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) 52#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
52#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) 53#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
54#define SPI1_SS0 (GPIO_PORTD + 28)
55#define SPI1_SS1 (GPIO_PORTD + 27)
56#define SD2_CD (GPIO_PORTC + 29)
53 57
54static int pca100_pins[] = { 58static int pca100_pins[] = {
55 /* UART1 */ 59 /* UART1 */
@@ -64,6 +68,7 @@ static int pca100_pins[] = {
64 PB7_PF_SD2_D3, 68 PB7_PF_SD2_D3,
65 PB8_PF_SD2_CMD, 69 PB8_PF_SD2_CMD,
66 PB9_PF_SD2_CLK, 70 PB9_PF_SD2_CLK,
71 SD2_CD | GPIO_GPIO | GPIO_IN,
67 /* FEC */ 72 /* FEC */
68 PD0_AIN_FEC_TXD0, 73 PD0_AIN_FEC_TXD0,
69 PD1_AIN_FEC_TXD1, 74 PD1_AIN_FEC_TXD1,
@@ -127,6 +132,34 @@ static int pca100_pins[] = {
127 PD23_AF_USBH2_DATA2, 132 PD23_AF_USBH2_DATA2,
128 PD24_AF_USBH2_DATA1, 133 PD24_AF_USBH2_DATA1,
129 PD26_AF_USBH2_DATA5, 134 PD26_AF_USBH2_DATA5,
135 /* display */
136 PA5_PF_LSCLK,
137 PA6_PF_LD0,
138 PA7_PF_LD1,
139 PA8_PF_LD2,
140 PA9_PF_LD3,
141 PA10_PF_LD4,
142 PA11_PF_LD5,
143 PA12_PF_LD6,
144 PA13_PF_LD7,
145 PA14_PF_LD8,
146 PA15_PF_LD9,
147 PA16_PF_LD10,
148 PA17_PF_LD11,
149 PA18_PF_LD12,
150 PA19_PF_LD13,
151 PA20_PF_LD14,
152 PA21_PF_LD15,
153 PA22_PF_LD16,
154 PA23_PF_LD17,
155 PA26_PF_PS,
156 PA28_PF_HSYNC,
157 PA29_PF_VSYNC,
158 PA31_PF_OE_ACD,
159 /* free GPIO */
160 GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
161 GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
162 GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
130}; 163};
131 164
132static const struct imxuart_platform_data uart_pdata __initconst = { 165static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -186,7 +219,7 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
186 }, 219 },
187}; 220};
188 221
189static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27}; 222static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
190 223
191static const struct spi_imx_master pca100_spi0_data __initconst = { 224static const struct spi_imx_master pca100_spi0_data __initconst = {
192 .chipselect = pca100_spi_cs, 225 .chipselect = pca100_spi_cs,
@@ -250,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = {
250 .exit = pca100_sdhc2_exit, 283 .exit = pca100_sdhc2_exit,
251}; 284};
252 285
286#if defined(CONFIG_USB_ULPI)
253static int otg_phy_init(struct platform_device *pdev) 287static int otg_phy_init(struct platform_device *pdev)
254{ 288{
255 gpio_set_value(OTG_PHY_CS_GPIO, 0); 289 gpio_set_value(OTG_PHY_CS_GPIO, 0);
@@ -273,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
273 .portsc = MXC_EHCI_MODE_ULPI, 307 .portsc = MXC_EHCI_MODE_ULPI,
274 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 308 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
275}; 309};
310#endif
276 311
277static struct fsl_usb2_platform_data otg_device_pdata = { 312static struct fsl_usb2_platform_data otg_device_pdata = {
278 .operating_mode = FSL_USB2_DR_DEVICE, 313 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -294,6 +329,45 @@ static int __init pca100_otg_mode(char *options)
294} 329}
295__setup("otg_mode=", pca100_otg_mode); 330__setup("otg_mode=", pca100_otg_mode);
296 331
332/* framebuffer info */
333static struct imx_fb_videomode pca100_fb_modes[] = {
334 {
335 .mode = {
336 .name = "EMERGING-ETV570G0DHU",
337 .refresh = 60,
338 .xres = 640,
339 .yres = 480,
340 .pixclock = 39722, /* in ps (25.175 MHz) */
341 .hsync_len = 30,
342 .left_margin = 114,
343 .right_margin = 16,
344 .vsync_len = 3,
345 .upper_margin = 32,
346 .lower_margin = 0,
347 },
348 /*
349 * TFT
350 * Pixel pol active high
351 * HSYNC active low
352 * VSYNC active low
353 * use HSYNC for ACD count
354 * line clock disable while idle
355 * always enable line clock even if no data
356 */
357 .pcr = 0xf0c08080,
358 .bpp = 16,
359 },
360};
361
362static struct imx_fb_platform_data pca100_fb_data = {
363 .mode = pca100_fb_modes,
364 .num_modes = ARRAY_SIZE(pca100_fb_modes),
365
366 .pwmr = 0x00A903FF,
367 .lscr1 = 0x00120300,
368 .dmacr = 0x00020010,
369};
370
297static void __init pca100_init(void) 371static void __init pca100_init(void)
298{ 372{
299 int ret; 373 int ret;
@@ -319,7 +393,6 @@ static void __init pca100_init(void)
319 393
320 imx27_add_imx_uart0(&uart_pdata); 394 imx27_add_imx_uart0(&uart_pdata);
321 395
322 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
323 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 396 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
324 397
325 imx27_add_mxc_nand(&pca100_nand_board_info); 398 imx27_add_mxc_nand(&pca100_nand_board_info);
@@ -330,17 +403,9 @@ static void __init pca100_init(void)
330 403
331 imx27_add_i2c_imx1(&pca100_i2c1_data); 404 imx27_add_i2c_imx1(&pca100_i2c1_data);
332 405
333 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
334 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
335
336 /* GPIO0_IRQ */
337 mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
338 /* GPIO1_IRQ */
339 mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
340 /* GPIO2_IRQ */
341 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
342
343#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 406#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
407 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
408 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
344 spi_register_board_info(pca100_spi_board_info, 409 spi_register_board_info(pca100_spi_board_info,
345 ARRAY_SIZE(pca100_spi_board_info)); 410 ARRAY_SIZE(pca100_spi_board_info));
346 imx27_add_spi_imx0(&pca100_spi_0_data); 411 imx27_add_spi_imx0(&pca100_spi_0_data);
@@ -369,6 +434,8 @@ static void __init pca100_init(void)
369 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 434 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
370 } 435 }
371 436
437 mxc_register_device(&mxc_fb_device, &pca100_fb_data);
438
372 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 439 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
373} 440}
374 441
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
new file mode 100644
index 000000000000..afc17ce0bb54
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -0,0 +1,46 @@
1/*
2 * i.MX27 Power Management Routines
3 *
4 * Based on Freescale's BSP
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License.
8 */
9
10#include <linux/kernel.h>
11#include <linux/suspend.h>
12#include <linux/io.h>
13#include <mach/system.h>
14#include <mach/mx27.h>
15
16static int mx27_suspend_enter(suspend_state_t state)
17{
18 u32 cscr;
19 switch (state) {
20 case PM_SUSPEND_MEM:
21 /* Clear MPEN and SPEN to disable MPLL/SPLL */
22 cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
23 cscr &= 0xFFFFFFFC;
24 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
25 /* Executes WFI */
26 arch_idle();
27 break;
28
29 default:
30 return -EINVAL;
31 }
32 return 0;
33}
34
35static struct platform_suspend_ops mx27_suspend_ops = {
36 .enter = mx27_suspend_enter,
37 .valid = suspend_valid_only_mem,
38};
39
40static int __init mx27_pm_init(void)
41{
42 suspend_set_ops(&mx27_suspend_ops);
43 return 0;
44}
45
46device_initcall(mx27_pm_init);
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index febf8413100a..67e0b54218ae 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -7,4 +7,25 @@ config MACH_MX25_3DS
7 select IMX_HAVE_PLATFORM_IMX_UART 7 select IMX_HAVE_PLATFORM_IMX_UART
8 select IMX_HAVE_PLATFORM_MXC_NAND 8 select IMX_HAVE_PLATFORM_MXC_NAND
9 9
10config MACH_EUKREA_CPUIMX25
11 bool "Support Eukrea CPUIMX25 Platform"
12 select IMX_HAVE_PLATFORM_IMX_I2C
13 select IMX_HAVE_PLATFORM_IMX_UART
14 select IMX_HAVE_PLATFORM_MXC_NAND
15 select MXC_ULPI if USB_ULPI
16
17choice
18 prompt "Baseboard"
19 depends on MACH_EUKREA_CPUIMX25
20 default MACH_EUKREA_MBIMXSD_BASEBOARD
21
22config MACH_EUKREA_MBIMXSD_BASEBOARD
23 prompt "Eukrea MBIMXSD development board"
24 bool
25 help
26 This adds board specific devices that can be found on Eukrea's
27 MBIMXSD evaluation board.
28
29endchoice
30
10endif 31endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 6db9603ad197..87ffb9c2f90a 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,5 @@
1obj-y := mm.o devices.o 1obj-y := mm.o devices.o
2obj-$(CONFIG_ARCH_MX25) += clock.o 2obj-$(CONFIG_ARCH_MX25) += clock.o
3obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o 3obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
4obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
5obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD) += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 155014993b13..1a58cae4d5e8 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk)
109 return get_rate_per(15); 109 return get_rate_per(15);
110} 110}
111 111
112static unsigned long get_rate_ssi2(struct clk *clk)
113{
114 return get_rate_per(14);
115}
116
117static unsigned long get_rate_ssi1(struct clk *clk)
118{
119 return get_rate_per(13);
120}
121
112static unsigned long get_rate_i2c(struct clk *clk) 122static unsigned long get_rate_i2c(struct clk *clk)
113{ 123{
114 return get_rate_per(6); 124 return get_rate_per(6);
@@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk)
129 return get_rate_per(7); 139 return get_rate_per(7);
130} 140}
131 141
142static unsigned long get_rate_csi(struct clk *clk)
143{
144 return get_rate_per(0);
145}
146
132static unsigned long get_rate_otg(struct clk *clk) 147static unsigned long get_rate_otg(struct clk *clk)
133{ 148{
134 return 48000000; /* FIXME */ 149 unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
150 unsigned long rate = get_rate_upll();
151
152 return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
135} 153}
136 154
137static int clk_cgcr_enable(struct clk *clk) 155static int clk_cgcr_enable(struct clk *clk)
@@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk)
166 .secondary = s, \ 184 .secondary = s, \
167 } 185 }
168 186
187/*
188 * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
189 * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
190 * taken from the Freescale released BSP.
191 *
192 * bit reg offset clock
193 *
194 * 0 CGCR1 0 AUDMUX
195 * 12 CGCR1 12 ESAI
196 * 16 CGCR1 16 GPIO1
197 * 17 CGCR1 17 GPIO2
198 * 18 CGCR1 18 GPIO3
199 * 23 CGCR1 23 I2C1
200 * 24 CGCR1 24 I2C2
201 * 25 CGCR1 25 I2C3
202 * 27 CGCR1 27 IOMUXC
203 * 28 CGCR1 28 KPP
204 * 30 CGCR1 30 OWIRE
205 * 36 CGCR2 4 RTIC
206 * 51 CGCR2 19 WDOG
207 */
208
169DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); 209DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
170DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); 210DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
211DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
212DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
171DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); 213DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
172DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); 214DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
173DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); 215DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
174DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 216DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
175DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 217DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
176DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 218DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
219DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
220DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
177DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); 221DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
178DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); 222DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
179DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); 223DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -191,6 +235,11 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
191DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); 235DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
192DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); 236DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
193DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); 237DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
238DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
239DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
240DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
241DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
242DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
194 243
195#define _REGISTER_CLOCK(d, n, c) \ 244#define _REGISTER_CLOCK(d, n, c) \
196 { \ 245 { \
@@ -217,7 +266,7 @@ static struct clk_lookup lookups[] = {
217 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) 266 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
218 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) 267 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
219 _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) 268 _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
220 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) 269 _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
221 _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) 270 _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
222 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 271 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
223 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) 272 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
@@ -225,6 +274,11 @@ static struct clk_lookup lookups[] = {
225 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 274 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
226 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) 275 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
227 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 276 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
277 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
278 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
279 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
280 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
281 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
228}; 282};
229 283
230int __init mx25_clocks_init(void) 284int __init mx25_clocks_init(void)
@@ -239,8 +293,9 @@ int __init mx25_clocks_init(void)
239 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); 293 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
240 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); 294 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
241 295
242 /* Clock source for lcdc is upll */ 296 /* Clock source for lcdc and csi is upll */
243 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); 297 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
298 CRM_BASE + 0x64);
244 299
245 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 300 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
246 301
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 6f98d23c8216..3468eb15b236 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -22,8 +22,6 @@
22#include <mach/mx25.h> 22#include <mach/mx25.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24 24
25#define MX25_OTG_BASE_ADDR 0x53FF4000
26
27static u64 otg_dmamask = DMA_BIT_MASK(32); 25static u64 otg_dmamask = DMA_BIT_MASK(32);
28 26
29static struct resource mxc_otg_resources[] = { 27static struct resource mxc_otg_resources[] = {
@@ -286,3 +284,83 @@ struct platform_device mxc_wdt = {
286 .num_resources = ARRAY_SIZE(mxc_wdt_resources), 284 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
287 .resource = mxc_wdt_resources, 285 .resource = mxc_wdt_resources,
288}; 286};
287
288static struct resource mx25_kpp_resources[] = {
289 {
290 .start = MX25_KPP_BASE_ADDR,
291 .end = MX25_KPP_BASE_ADDR + 0xf,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = MX25_INT_KPP,
296 .end = MX25_INT_KPP,
297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301struct platform_device mx25_kpp_device = {
302 .name = "imx-keypad",
303 .id = -1,
304 .num_resources = ARRAY_SIZE(mx25_kpp_resources),
305 .resource = mx25_kpp_resources,
306};
307
308static struct resource imx_ssi_resources0[] = {
309 {
310 .start = MX25_SSI1_BASE_ADDR,
311 .end = MX25_SSI1_BASE_ADDR + 0x3fff,
312 .flags = IORESOURCE_MEM,
313 }, {
314 .start = MX25_INT_SSI1,
315 .end = MX25_INT_SSI1,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct resource imx_ssi_resources1[] = {
321 {
322 .start = MX25_SSI2_BASE_ADDR,
323 .end = MX25_SSI2_BASE_ADDR + 0x3fff,
324 .flags = IORESOURCE_MEM
325 }, {
326 .start = MX25_INT_SSI2,
327 .end = MX25_INT_SSI2,
328 .flags = IORESOURCE_IRQ,
329 },
330};
331
332struct platform_device imx_ssi_device0 = {
333 .name = "imx-ssi",
334 .id = 0,
335 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
336 .resource = imx_ssi_resources0,
337};
338
339struct platform_device imx_ssi_device1 = {
340 .name = "imx-ssi",
341 .id = 1,
342 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
343 .resource = imx_ssi_resources1,
344};
345
346static struct resource mx25_csi_resources[] = {
347 {
348 .start = MX25_CSI_BASE_ADDR,
349 .end = MX25_CSI_BASE_ADDR + 0xfff,
350 .flags = IORESOURCE_MEM,
351 },
352 {
353 .start = MX25_INT_CSI,
354 .flags = IORESOURCE_IRQ
355 },
356};
357
358struct platform_device mx25_csi_device = {
359 .name = "mx2-camera",
360 .id = 0,
361 .num_resources = ARRAY_SIZE(mx25_csi_resources),
362 .resource = mx25_csi_resources,
363 .dev = {
364 .coherent_dma_mask = 0xffffffff,
365 },
366};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 31d22e1f3ae4..4aceb68e35a7 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -10,3 +10,7 @@ extern struct platform_device mx25_fec_device;
10extern struct platform_device mx25_rtc_device; 10extern struct platform_device mx25_rtc_device;
11extern struct platform_device mx25_fb_device; 11extern struct platform_device mx25_fb_device;
12extern struct platform_device mxc_wdt; 12extern struct platform_device mxc_wdt;
13extern struct platform_device mx25_kpp_device;
14extern struct platform_device imx_ssi_device0;
15extern struct platform_device imx_ssi_device1;
16extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..f07b1f95ac76
--- /dev/null
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,261 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/leds.h>
24#include <linux/platform_device.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h>
27#include <video/platform_lcd.h>
28
29#include <mach/board-eukrea_cpuimx25.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx25.h>
32#include <mach/common.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <mach/mx25.h>
36#include <mach/imx-uart.h>
37#include <mach/imxfb.h>
38#include <mach/ssi.h>
39#include <mach/audmux.h>
40
41#include "devices-imx25.h"
42#include "devices.h"
43
44static struct pad_desc eukrea_mbimxsd_pads[] = {
45 /* LCD */
46 MX25_PAD_LD0__LD0,
47 MX25_PAD_LD1__LD1,
48 MX25_PAD_LD2__LD2,
49 MX25_PAD_LD3__LD3,
50 MX25_PAD_LD4__LD4,
51 MX25_PAD_LD5__LD5,
52 MX25_PAD_LD6__LD6,
53 MX25_PAD_LD7__LD7,
54 MX25_PAD_LD8__LD8,
55 MX25_PAD_LD9__LD9,
56 MX25_PAD_LD10__LD10,
57 MX25_PAD_LD11__LD11,
58 MX25_PAD_LD12__LD12,
59 MX25_PAD_LD13__LD13,
60 MX25_PAD_LD14__LD14,
61 MX25_PAD_LD15__LD15,
62 MX25_PAD_GPIO_E__LD16,
63 MX25_PAD_GPIO_F__LD17,
64 MX25_PAD_HSYNC__HSYNC,
65 MX25_PAD_VSYNC__VSYNC,
66 MX25_PAD_LSCLK__LSCLK,
67 MX25_PAD_OE_ACD__OE_ACD,
68 MX25_PAD_CONTRAST__CONTRAST,
69 /* LCD_PWR */
70 MX25_PAD_PWM__GPIO_1_26,
71 /* LED */
72 MX25_PAD_POWER_FAIL__GPIO_3_19,
73 /* SWITCH */
74 MX25_PAD_VSTBY_ACK__GPIO_3_18,
75 /* UART2 */
76 MX25_PAD_UART2_RTS__UART2_RTS,
77 MX25_PAD_UART2_CTS__UART2_CTS,
78 MX25_PAD_UART2_TXD__UART2_TXD,
79 MX25_PAD_UART2_RXD__UART2_RXD,
80 /* SD1 */
81 MX25_PAD_SD1_CMD__SD1_CMD,
82 MX25_PAD_SD1_CLK__SD1_CLK,
83 MX25_PAD_SD1_DATA0__SD1_DATA0,
84 MX25_PAD_SD1_DATA1__SD1_DATA1,
85 MX25_PAD_SD1_DATA2__SD1_DATA2,
86 MX25_PAD_SD1_DATA3__SD1_DATA3,
87 /* SD1 CD */
88 MX25_PAD_DE_B__GPIO_2_20,
89 /* I2S */
90 MX25_PAD_KPP_COL3__AUD5_TXFS,
91 MX25_PAD_KPP_COL2__AUD5_TXC,
92 MX25_PAD_KPP_COL1__AUD5_RXD,
93 MX25_PAD_KPP_COL0__AUD5_TXD,
94};
95
96#define GPIO_LED1 83
97#define GPIO_SWITCH1 82
98#define GPIO_SD1CD 52
99#define GPIO_LCDPWR 26
100
101static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
102 {
103 .mode = {
104 .name = "CMO-QVGA",
105 .refresh = 60,
106 .xres = 320,
107 .yres = 240,
108 .pixclock = KHZ2PICOS(6500),
109 .left_margin = 30,
110 .right_margin = 38,
111 .upper_margin = 20,
112 .lower_margin = 3,
113 .hsync_len = 15,
114 .vsync_len = 4,
115 },
116 .bpp = 16,
117 .pcr = 0xCAD08B80,
118 },
119};
120
121static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
122 .mode = eukrea_mximxsd_modes,
123 .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
124 .pwmr = 0x00A903FF,
125 .lscr1 = 0x00120300,
126 .dmacr = 0x00040060,
127};
128
129static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
130 unsigned int power)
131{
132 if (power)
133 gpio_direction_output(GPIO_LCDPWR, 1);
134 else
135 gpio_direction_output(GPIO_LCDPWR, 0);
136}
137
138static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
139 .set_power = eukrea_mbimxsd_lcd_power_set,
140};
141
142static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
143 .name = "platform-lcd",
144 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
145};
146
147static struct gpio_led eukrea_mbimxsd_leds[] = {
148 {
149 .name = "led1",
150 .default_trigger = "heartbeat",
151 .active_low = 1,
152 .gpio = GPIO_LED1,
153 },
154};
155
156static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
157 .leds = eukrea_mbimxsd_leds,
158 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
159};
160
161static struct platform_device eukrea_mbimxsd_leds_gpio = {
162 .name = "leds-gpio",
163 .id = -1,
164 .dev = {
165 .platform_data = &eukrea_mbimxsd_led_info,
166 },
167};
168
169static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
170 {
171 .gpio = GPIO_SWITCH1,
172 .code = BTN_0,
173 .desc = "BP1",
174 .active_low = 1,
175 .wakeup = 1,
176 },
177};
178
179static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
180 .buttons = eukrea_mbimxsd_gpio_buttons,
181 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
182};
183
184static struct platform_device eukrea_mbimxsd_button_device = {
185 .name = "gpio-keys",
186 .id = -1,
187 .num_resources = 0,
188 .dev = {
189 .platform_data = &eukrea_mbimxsd_button_data,
190 }
191};
192
193static struct platform_device *platform_devices[] __initdata = {
194 &eukrea_mbimxsd_leds_gpio,
195 &eukrea_mbimxsd_button_device,
196 &eukrea_mbimxsd_lcd_powerdev,
197};
198
199static const struct imxuart_platform_data uart_pdata __initconst = {
200 .flags = IMXUART_HAVE_RTSCTS,
201};
202
203static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
204 {
205 I2C_BOARD_INFO("tlv320aic23", 0x1a),
206 },
207};
208
209struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
210 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
211};
212
213/*
214 * system init for baseboard usage. Will be called by cpuimx25 init.
215 *
216 * Add platform devices present on this baseboard and init
217 * them from CPU side as far as required to use them later on
218 */
219void __init eukrea_mbimxsd_baseboard_init(void)
220{
221 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
222 ARRAY_SIZE(eukrea_mbimxsd_pads)))
223 printk(KERN_ERR "error setting mbimxsd pads !\n");
224
225#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
226 /* SSI unit master I2S codec connected to SSI_AUD5*/
227 mxc_audmux_v2_configure_port(0,
228 MXC_AUDMUX_V2_PTCR_SYN |
229 MXC_AUDMUX_V2_PTCR_TFSDIR |
230 MXC_AUDMUX_V2_PTCR_TFSEL(4) |
231 MXC_AUDMUX_V2_PTCR_TCLKDIR |
232 MXC_AUDMUX_V2_PTCR_TCSEL(4),
233 MXC_AUDMUX_V2_PDCR_RXDSEL(4)
234 );
235 mxc_audmux_v2_configure_port(4,
236 MXC_AUDMUX_V2_PTCR_SYN,
237 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
238 );
239#endif
240
241 imx25_add_imx_uart1(&uart_pdata);
242 mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
243 mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
244
245 gpio_request(GPIO_LED1, "LED1");
246 gpio_direction_output(GPIO_LED1, 1);
247 gpio_free(GPIO_LED1);
248
249 gpio_request(GPIO_SWITCH1, "SWITCH1");
250 gpio_direction_input(GPIO_SWITCH1);
251 gpio_free(GPIO_SWITCH1);
252
253 gpio_request(GPIO_LCDPWR, "LCDPWR");
254 gpio_direction_output(GPIO_LCDPWR, 1);
255 gpio_free(GPIO_SWITCH1);
256
257 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
258 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
259
260 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
261}
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
new file mode 100644
index 000000000000..d39f9ccd4be0
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
3 * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/gpio.h>
26#include <linux/fec.h>
27#include <linux/platform_device.h>
28#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h>
30#include <linux/fsl_devices.h>
31
32#include <mach/board-eukrea_cpuimx25.h>
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/memory.h>
38#include <asm/mach/map.h>
39#include <mach/common.h>
40#include <mach/mx25.h>
41#include <mach/mxc_nand.h>
42#include <mach/imxfb.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h>
45#include <mach/iomux-mx25.h>
46
47#include "devices-imx25.h"
48#include "devices.h"
49
50static const struct imxuart_platform_data uart_pdata __initconst = {
51 .flags = IMXUART_HAVE_RTSCTS,
52};
53
54static struct pad_desc eukrea_cpuimx25_pads[] = {
55 /* FEC - RMII */
56 MX25_PAD_FEC_MDC__FEC_MDC,
57 MX25_PAD_FEC_MDIO__FEC_MDIO,
58 MX25_PAD_FEC_TDATA0__FEC_TDATA0,
59 MX25_PAD_FEC_TDATA1__FEC_TDATA1,
60 MX25_PAD_FEC_TX_EN__FEC_TX_EN,
61 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
62 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
63 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
64 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
65 /* I2C1 */
66 MX25_PAD_I2C1_CLK__I2C1_CLK,
67 MX25_PAD_I2C1_DAT__I2C1_DAT,
68};
69
70static struct fec_platform_data mx25_fec_pdata = {
71 .phy = PHY_INTERFACE_MODE_RMII,
72};
73
74static const struct mxc_nand_platform_data
75eukrea_cpuimx25_nand_board_info __initconst = {
76 .width = 1,
77 .hw_ecc = 1,
78 .flash_bbt = 1,
79};
80
81static const struct imxi2c_platform_data
82eukrea_cpuimx25_i2c0_data __initconst = {
83 .bitrate = 100000,
84};
85
86static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
87 {
88 I2C_BOARD_INFO("pcf8563", 0x51),
89 },
90};
91
92static struct mxc_usbh_platform_data otg_pdata = {
93 .portsc = MXC_EHCI_MODE_UTMI,
94 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
95};
96
97static struct mxc_usbh_platform_data usbh2_pdata = {
98 .portsc = MXC_EHCI_MODE_SERIAL,
99 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
100 MXC_EHCI_IPPUE_DOWN,
101};
102
103static struct fsl_usb2_platform_data otg_device_pdata = {
104 .operating_mode = FSL_USB2_DR_DEVICE,
105 .phy_mode = FSL_USB2_PHY_UTMI,
106};
107
108static int otg_mode_host;
109
110static int __init eukrea_cpuimx25_otg_mode(char *options)
111{
112 if (!strcmp(options, "host"))
113 otg_mode_host = 1;
114 else if (!strcmp(options, "device"))
115 otg_mode_host = 0;
116 else
117 pr_info("otg_mode neither \"host\" nor \"device\". "
118 "Defaulting to device\n");
119 return 0;
120}
121__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
122
123static void __init eukrea_cpuimx25_init(void)
124{
125 if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
126 ARRAY_SIZE(eukrea_cpuimx25_pads)))
127 printk(KERN_ERR "error setting cpuimx25 pads !\n");
128
129 imx25_add_imx_uart0(&uart_pdata);
130 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
131 mxc_register_device(&mx25_rtc_device, NULL);
132 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
133
134 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
135 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
136 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
137
138#if defined(CONFIG_USB_ULPI)
139 if (otg_mode_host) {
140 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
141 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
142
143 mxc_register_device(&mxc_otg, &otg_pdata);
144 }
145 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
146#endif
147 if (!otg_mode_host)
148 mxc_register_device(&otg_udc_device, &otg_device_pdata);
149
150#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
151 eukrea_mbimxsd_baseboard_init();
152#endif
153}
154
155static void __init eukrea_cpuimx25_timer_init(void)
156{
157 mx25_clocks_init();
158}
159
160static struct sys_timer eukrea_cpuimx25_timer = {
161 .init = eukrea_cpuimx25_timer_init,
162};
163
164MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
165 /* Maintainer: Eukrea Electromatique */
166 .phys_io = MX25_AIPS1_BASE_ADDR,
167 .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
168 .boot_params = MX25_PHYS_OFFSET + 0x100,
169 .map_io = mx25_map_io,
170 .init_irq = mx25_init_irq,
171 .init_machine = eukrea_cpuimx25_init,
172 .timer = &eukrea_cpuimx25_timer,
173MACHINE_END
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 978ad00b807c..62bc21f11a71 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -30,6 +30,7 @@
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/fec.h> 31#include <linux/fec.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/input/matrix_keypad.h>
33 34
34#include <mach/hardware.h> 35#include <mach/hardware.h>
35#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -86,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = {
86 MX25_PAD_LSCLK__LSCLK, 87 MX25_PAD_LSCLK__LSCLK,
87 MX25_PAD_OE_ACD__OE_ACD, 88 MX25_PAD_OE_ACD__OE_ACD,
88 MX25_PAD_CONTRAST__CONTRAST, 89 MX25_PAD_CONTRAST__CONTRAST,
90
91 /* Keypad */
92 MX25_PAD_KPP_ROW0__KPP_ROW0,
93 MX25_PAD_KPP_ROW1__KPP_ROW1,
94 MX25_PAD_KPP_ROW2__KPP_ROW2,
95 MX25_PAD_KPP_ROW3__KPP_ROW3,
96 MX25_PAD_KPP_COL0__KPP_COL0,
97 MX25_PAD_KPP_COL1__KPP_COL1,
98 MX25_PAD_KPP_COL2__KPP_COL2,
99 MX25_PAD_KPP_COL3__KPP_COL3,
89}; 100};
90 101
91static struct fec_platform_data mx25_fec_pdata = { 102static struct fec_platform_data mx25_fec_pdata = {
@@ -144,6 +155,30 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = {
144 .dmacr = 0x00020010, 155 .dmacr = 0x00020010,
145}; 156};
146 157
158static const uint32_t mx25pdk_keymap[] = {
159 KEY(0, 0, KEY_UP),
160 KEY(0, 1, KEY_DOWN),
161 KEY(0, 2, KEY_VOLUMEDOWN),
162 KEY(0, 3, KEY_HOME),
163 KEY(1, 0, KEY_RIGHT),
164 KEY(1, 1, KEY_LEFT),
165 KEY(1, 2, KEY_ENTER),
166 KEY(1, 3, KEY_VOLUMEUP),
167 KEY(2, 0, KEY_F6),
168 KEY(2, 1, KEY_F8),
169 KEY(2, 2, KEY_F9),
170 KEY(2, 3, KEY_F10),
171 KEY(3, 0, KEY_F1),
172 KEY(3, 1, KEY_F2),
173 KEY(3, 2, KEY_F3),
174 KEY(3, 3, KEY_POWER),
175};
176
177static struct matrix_keymap_data mx25pdk_keymap_data = {
178 .keymap = mx25pdk_keymap,
179 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
180};
181
147static void __init mx25pdk_init(void) 182static void __init mx25pdk_init(void)
148{ 183{
149 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, 184 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -154,9 +189,11 @@ static void __init mx25pdk_init(void)
154 imx25_add_mxc_nand(&mx25pdk_nand_board_info); 189 imx25_add_mxc_nand(&mx25pdk_nand_board_info);
155 mxc_register_device(&mx25_rtc_device, NULL); 190 mxc_register_device(&mx25_rtc_device, NULL);
156 mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); 191 mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
192 mxc_register_device(&mxc_wdt, NULL);
157 193
158 mx25pdk_fec_reset(); 194 mx25pdk_fec_reset();
159 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); 195 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
196 mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
160} 197}
161 198
162static void __init mx25pdk_timer_init(void) 199static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 594502a4e574..a11112afde5e 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -151,4 +151,29 @@ config MACH_KZM_ARM11_01
151 Include support for KZM-ARM11-01. This includes specific 151 Include support for KZM-ARM11-01. This includes specific
152 configurations for the board and its peripherals. 152 configurations for the board and its peripherals.
153 153
154config MACH_EUKREA_CPUIMX35
155 bool "Support Eukrea CPUIMX35 Platform"
156 select ARCH_MX35
157 select IMX_HAVE_PLATFORM_IMX_UART
158 select IMX_HAVE_PLATFORM_IMX_I2C
159 select IMX_HAVE_PLATFORM_MXC_NAND
160 select MXC_ULPI if USB_ULPI
161 help
162 Include support for Eukrea CPUIMX35 platform. This includes
163 specific configurations for the board and its peripherals.
164
165choice
166 prompt "Baseboard"
167 depends on MACH_EUKREA_CPUIMX35
168 default MACH_EUKREA_MBIMXSD_BASEBOARD
169
170config MACH_EUKREA_MBIMXSD_BASEBOARD
171 prompt "Eukrea MBIMXSD development board"
172 bool
173 help
174 This adds board specific devices that can be found on Eukrea's
175 MBIMXSD evaluation board.
176
177endchoice
178
154endif 179endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 2a4798d26f23..54bc935acdc6 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -24,3 +24,5 @@ obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
24obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o 24obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
25obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o 25obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
26obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o 26obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
27obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
28obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD) += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 9f3e943e2232..28be011dace6 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
359DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); 359DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
360DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); 360DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
361DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); 361DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
362DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); 362DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_ahb, NULL);
363DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); 363DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
364DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); 364DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
365DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); 365DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..368a603accfe
--- /dev/null
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,264 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <video/platform_lcd.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include <mach/board-eukrea_cpuimx35.h>
40#include <mach/hardware.h>
41#include <mach/common.h>
42#include <mach/imx-uart.h>
43#include <mach/iomux-mx35.h>
44#include <mach/ipu.h>
45#include <mach/mx3fb.h>
46#include <mach/audmux.h>
47#include <mach/ssi.h>
48
49#include "devices-imx35.h"
50#include "devices.h"
51
52static const struct fb_videomode fb_modedb[] = {
53 {
54 .name = "CMO_QVGA",
55 .refresh = 60,
56 .xres = 320,
57 .yres = 240,
58 .pixclock = KHZ2PICOS(6500),
59 .left_margin = 68,
60 .right_margin = 20,
61 .upper_margin = 15,
62 .lower_margin = 4,
63 .hsync_len = 30,
64 .vsync_len = 3,
65 .sync = 0,
66 .vmode = FB_VMODE_NONINTERLACED,
67 .flag = 0,
68 },
69};
70
71static struct ipu_platform_data mx3_ipu_data = {
72 .irq_base = MXC_IPU_IRQ_START,
73};
74
75static struct mx3fb_platform_data mx3fb_pdata = {
76 .dma_dev = &mx3_ipu.dev,
77 .name = "CMO_QVGA",
78 .mode = fb_modedb,
79 .num_modes = ARRAY_SIZE(fb_modedb),
80};
81
82static struct pad_desc eukrea_mbimxsd_pads[] = {
83 /* LCD */
84 MX35_PAD_LD0__IPU_DISPB_DAT_0,
85 MX35_PAD_LD1__IPU_DISPB_DAT_1,
86 MX35_PAD_LD2__IPU_DISPB_DAT_2,
87 MX35_PAD_LD3__IPU_DISPB_DAT_3,
88 MX35_PAD_LD4__IPU_DISPB_DAT_4,
89 MX35_PAD_LD5__IPU_DISPB_DAT_5,
90 MX35_PAD_LD6__IPU_DISPB_DAT_6,
91 MX35_PAD_LD7__IPU_DISPB_DAT_7,
92 MX35_PAD_LD8__IPU_DISPB_DAT_8,
93 MX35_PAD_LD9__IPU_DISPB_DAT_9,
94 MX35_PAD_LD10__IPU_DISPB_DAT_10,
95 MX35_PAD_LD11__IPU_DISPB_DAT_11,
96 MX35_PAD_LD12__IPU_DISPB_DAT_12,
97 MX35_PAD_LD13__IPU_DISPB_DAT_13,
98 MX35_PAD_LD14__IPU_DISPB_DAT_14,
99 MX35_PAD_LD15__IPU_DISPB_DAT_15,
100 MX35_PAD_LD16__IPU_DISPB_DAT_16,
101 MX35_PAD_LD17__IPU_DISPB_DAT_17,
102 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
103 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
104 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
105 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
106 /* Backlight */
107 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
108 /* LCD_PWR */
109 MX35_PAD_D3_CLS__GPIO1_4,
110 /* LED */
111 MX35_PAD_LD23__GPIO3_29,
112 /* SWITCH */
113 MX35_PAD_LD19__GPIO3_25,
114 /* UART2 */
115 MX35_PAD_CTS2__UART2_CTS,
116 MX35_PAD_RTS2__UART2_RTS,
117 MX35_PAD_TXD2__UART2_TXD_MUX,
118 MX35_PAD_RXD2__UART2_RXD_MUX,
119 /* I2S */
120 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
121 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
122 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
123 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
124};
125
126#define GPIO_LED1 (2 * 32 + 29)
127#define GPIO_SWITCH1 (2 * 32 + 25)
128#define GPIO_LCDPWR (4)
129
130static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
131 unsigned int power)
132{
133 if (power)
134 gpio_direction_output(GPIO_LCDPWR, 1);
135 else
136 gpio_direction_output(GPIO_LCDPWR, 0);
137}
138
139static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
140 .set_power = eukrea_mbimxsd_lcd_power_set,
141};
142
143static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
144 .name = "platform-lcd",
145 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
146};
147
148static struct gpio_led eukrea_mbimxsd_leds[] = {
149 {
150 .name = "led1",
151 .default_trigger = "heartbeat",
152 .active_low = 1,
153 .gpio = GPIO_LED1,
154 },
155};
156
157static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
158 .leds = eukrea_mbimxsd_leds,
159 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
160};
161
162static struct platform_device eukrea_mbimxsd_leds_gpio = {
163 .name = "leds-gpio",
164 .id = -1,
165 .dev = {
166 .platform_data = &eukrea_mbimxsd_led_info,
167 },
168};
169
170static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
171 {
172 .gpio = GPIO_SWITCH1,
173 .code = BTN_0,
174 .desc = "BP1",
175 .active_low = 1,
176 .wakeup = 1,
177 },
178};
179
180static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
181 .buttons = eukrea_mbimxsd_gpio_buttons,
182 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
183};
184
185static struct platform_device eukrea_mbimxsd_button_device = {
186 .name = "gpio-keys",
187 .id = -1,
188 .num_resources = 0,
189 .dev = {
190 .platform_data = &eukrea_mbimxsd_button_data,
191 }
192};
193
194static struct platform_device *platform_devices[] __initdata = {
195 &eukrea_mbimxsd_leds_gpio,
196 &eukrea_mbimxsd_button_device,
197 &eukrea_mbimxsd_lcd_powerdev,
198};
199
200static const struct imxuart_platform_data uart_pdata __initconst = {
201 .flags = IMXUART_HAVE_RTSCTS,
202};
203
204static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
205 {
206 I2C_BOARD_INFO("tlv320aic23", 0x1a),
207 },
208};
209
210struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
211 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
212};
213
214/*
215 * system init for baseboard usage. Will be called by cpuimx35 init.
216 *
217 * Add platform devices present on this baseboard and init
218 * them from CPU side as far as required to use them later on
219 */
220void __init eukrea_mbimxsd_baseboard_init(void)
221{
222 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
223 ARRAY_SIZE(eukrea_mbimxsd_pads)))
224 printk(KERN_ERR "error setting mbimxsd pads !\n");
225
226#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
227 /* SSI unit master I2S codec connected to SSI_AUD4 */
228 mxc_audmux_v2_configure_port(0,
229 MXC_AUDMUX_V2_PTCR_SYN |
230 MXC_AUDMUX_V2_PTCR_TFSDIR |
231 MXC_AUDMUX_V2_PTCR_TFSEL(3) |
232 MXC_AUDMUX_V2_PTCR_TCLKDIR |
233 MXC_AUDMUX_V2_PTCR_TCSEL(3),
234 MXC_AUDMUX_V2_PDCR_RXDSEL(3)
235 );
236 mxc_audmux_v2_configure_port(3,
237 MXC_AUDMUX_V2_PTCR_SYN,
238 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
239 );
240#endif
241
242 imx35_add_imx_uart1(&uart_pdata);
243 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
244 mxc_register_device(&mx3_fb, &mx3fb_pdata);
245
246 mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
247
248 gpio_request(GPIO_LED1, "LED1");
249 gpio_direction_output(GPIO_LED1, 1);
250 gpio_free(GPIO_LED1);
251
252 gpio_request(GPIO_SWITCH1, "SWITCH1");
253 gpio_direction_input(GPIO_SWITCH1);
254 gpio_free(GPIO_SWITCH1);
255
256 gpio_request(GPIO_LCDPWR, "LCDPWR");
257 gpio_direction_output(GPIO_LCDPWR, 1);
258 gpio_free(GPIO_SWITCH1);
259
260 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
261 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
262
263 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
264}
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
new file mode 100644
index 000000000000..4f6146d31328
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -0,0 +1,227 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22
23#include <linux/platform_device.h>
24#include <linux/mtd/physmap.h>
25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/i2c/tsc2007.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/fsl_devices.h>
34
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
38#include <asm/mach/map.h>
39
40#include <mach/board-eukrea_cpuimx35.h>
41#include <mach/hardware.h>
42#include <mach/common.h>
43#include <mach/iomux-mx35.h>
44#include <mach/mxc_nand.h>
45#include <mach/mxc_ehci.h>
46#include <mach/ulpi.h>
47
48#include "devices-imx35.h"
49#include "devices.h"
50
51static const struct imxuart_platform_data uart_pdata __initconst = {
52 .flags = IMXUART_HAVE_RTSCTS,
53};
54
55static const struct imxi2c_platform_data
56eukrea_cpuimx35_i2c0_data __initconst = {
57 .bitrate = 50000,
58};
59
60#define TSC2007_IRQGPIO (2 * 32 + 2)
61static int ts_get_pendown_state(void)
62{
63 int val = 0;
64 gpio_free(TSC2007_IRQGPIO);
65 gpio_request(TSC2007_IRQGPIO, NULL);
66 gpio_direction_input(TSC2007_IRQGPIO);
67
68 val = gpio_get_value(TSC2007_IRQGPIO);
69
70 gpio_free(TSC2007_IRQGPIO);
71 gpio_request(TSC2007_IRQGPIO, NULL);
72
73 return val ? 0 : 1;
74}
75
76static int ts_init(void)
77{
78 gpio_request(TSC2007_IRQGPIO, NULL);
79 return 0;
80}
81
82static struct tsc2007_platform_data tsc2007_info = {
83 .model = 2007,
84 .x_plate_ohms = 180,
85 .get_pendown_state = ts_get_pendown_state,
86 .init_platform_hw = ts_init,
87};
88
89static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
90 {
91 I2C_BOARD_INFO("pcf8563", 0x51),
92 }, {
93 I2C_BOARD_INFO("tsc2007", 0x48),
94 .type = "tsc2007",
95 .platform_data = &tsc2007_info,
96 .irq = gpio_to_irq(TSC2007_IRQGPIO),
97 },
98};
99
100static struct platform_device *devices[] __initdata = {
101 &mxc_fec_device,
102 &imx_wdt_device0,
103};
104
105static struct pad_desc eukrea_cpuimx35_pads[] = {
106 /* UART1 */
107 MX35_PAD_CTS1__UART1_CTS,
108 MX35_PAD_RTS1__UART1_RTS,
109 MX35_PAD_TXD1__UART1_TXD_MUX,
110 MX35_PAD_RXD1__UART1_RXD_MUX,
111 /* FEC */
112 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
113 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
114 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
115 MX35_PAD_FEC_COL__FEC_COL,
116 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
117 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
118 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
119 MX35_PAD_FEC_MDC__FEC_MDC,
120 MX35_PAD_FEC_MDIO__FEC_MDIO,
121 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
122 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
123 MX35_PAD_FEC_CRS__FEC_CRS,
124 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
125 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
126 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
127 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
128 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
129 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
130 /* I2C1 */
131 MX35_PAD_I2C1_CLK__I2C1_SCL,
132 MX35_PAD_I2C1_DAT__I2C1_SDA,
133 /* TSC2007 IRQ */
134 MX35_PAD_ATA_DA2__GPIO3_2,
135};
136
137static const struct mxc_nand_platform_data
138eukrea_cpuimx35_nand_board_info __initconst = {
139 .width = 1,
140 .hw_ecc = 1,
141 .flash_bbt = 1,
142};
143
144static struct mxc_usbh_platform_data otg_pdata = {
145 .portsc = MXC_EHCI_MODE_UTMI,
146 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
147};
148
149static struct mxc_usbh_platform_data usbh1_pdata = {
150 .portsc = MXC_EHCI_MODE_SERIAL,
151 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
152 MXC_EHCI_IPPUE_DOWN,
153};
154
155static struct fsl_usb2_platform_data otg_device_pdata = {
156 .operating_mode = FSL_USB2_DR_DEVICE,
157 .phy_mode = FSL_USB2_PHY_UTMI,
158};
159
160static int otg_mode_host;
161
162static int __init eukrea_cpuimx35_otg_mode(char *options)
163{
164 if (!strcmp(options, "host"))
165 otg_mode_host = 1;
166 else if (!strcmp(options, "device"))
167 otg_mode_host = 0;
168 else
169 pr_info("otg_mode neither \"host\" nor \"device\". "
170 "Defaulting to device\n");
171 return 0;
172}
173__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
174
175/*
176 * Board specific initialization.
177 */
178static void __init mxc_board_init(void)
179{
180 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
181 ARRAY_SIZE(eukrea_cpuimx35_pads));
182
183 platform_add_devices(devices, ARRAY_SIZE(devices));
184
185 imx35_add_imx_uart0(&uart_pdata);
186 imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
187
188 i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
189 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
190 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
191
192#if defined(CONFIG_USB_ULPI)
193 if (otg_mode_host) {
194 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
195 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
196
197 mxc_register_device(&mxc_otg_host, &otg_pdata);
198 }
199 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
200#endif
201 if (!otg_mode_host)
202 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
203
204#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
205 eukrea_mbimxsd_baseboard_init();
206#endif
207}
208
209static void __init eukrea_cpuimx35_timer_init(void)
210{
211 mx35_clocks_init();
212}
213
214struct sys_timer eukrea_cpuimx35_timer = {
215 .init = eukrea_cpuimx35_timer_init,
216};
217
218MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
219 /* Maintainer: Eukrea Electromatique */
220 .phys_io = MX35_AIPS1_BASE_ADDR,
221 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
222 .boot_params = MX3x_PHYS_OFFSET + 0x100,
223 .map_io = mx35_map_io,
224 .init_irq = mx35_init_irq,
225 .init_machine = mxc_board_init,
226 .timer = &eukrea_cpuimx35_timer,
227MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 4c021c590306..d4d9e7a1f735 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -206,8 +206,10 @@ mx31_3ds_nand_board_info __initconst = {
206 206
207#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) 207#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
208 208
209static void mx31_3ds_usbotg_init(void) 209static int mx31_3ds_usbotg_init(void)
210{ 210{
211 int err;
212
211 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); 213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
212 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); 214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); 215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
@@ -221,10 +223,25 @@ static void mx31_3ds_usbotg_init(void)
221 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); 223 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
222 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); 224 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
223 225
224 gpio_request(USBOTG_RST_B, "otgusb-reset"); 226 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
225 gpio_direction_output(USBOTG_RST_B, 0); 227 if (err) {
228 pr_err("Failed to request the USB OTG reset gpio\n");
229 return err;
230 }
231
232 err = gpio_direction_output(USBOTG_RST_B, 0);
233 if (err) {
234 pr_err("Failed to drive the USB OTG reset gpio\n");
235 goto usbotg_free_reset;
236 }
237
226 mdelay(1); 238 mdelay(1);
227 gpio_set_value(USBOTG_RST_B, 1); 239 gpio_set_value(USBOTG_RST_B, 1);
240 return 0;
241
242usbotg_free_reset:
243 gpio_free(USBOTG_RST_B);
244 return err;
228} 245}
229 246
230static struct fsl_usb2_platform_data usbotg_pdata = { 247static struct fsl_usb2_platform_data usbotg_pdata = {
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index d228b9e6701a..84942cf41b63 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -273,6 +273,7 @@ static struct spi_board_info mc13783_dev __initdata = {
273 .bus_num = 1, 273 .bus_num = 1,
274 .chip_select = 0, 274 .chip_select = 0,
275 .platform_data = &mc13783_pdata, 275 .platform_data = &mc13783_pdata,
276 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
276}; 277};
277 278
278static int mx31lilly_baseboard; 279static int mx31lilly_baseboard;
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index e71e3904cff9..8a292dd1a714 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -539,6 +539,7 @@ static struct platform_device pcm970_sja1000 = {
539 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), 539 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
540}; 540};
541 541
542#if defined(CONFIG_USB_ULPI)
542static struct mxc_usbh_platform_data otg_pdata = { 543static struct mxc_usbh_platform_data otg_pdata = {
543 .portsc = MXC_EHCI_MODE_ULPI, 544 .portsc = MXC_EHCI_MODE_ULPI,
544 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 545 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -548,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
548 .portsc = MXC_EHCI_MODE_ULPI, 549 .portsc = MXC_EHCI_MODE_ULPI,
549 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 550 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
550}; 551};
552#endif
551 553
552static struct fsl_usb2_platform_data otg_device_pdata = { 554static struct fsl_usb2_platform_data otg_device_pdata = {
553 .operating_mode = FSL_USB2_DR_DEVICE, 555 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -575,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode);
575static void __init mxc_board_init(void) 577static void __init mxc_board_init(void)
576{ 578{
577 int ret; 579 int ret;
578 u32 tmp;
579 580
580 mxc_iomux_set_gpr(MUX_PGP_UH2, 1); 581 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
581 582
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 97cc3642f805..b92f624c755e 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -302,6 +302,7 @@ pcm037_nand_board_info __initconst = {
302 .hw_ecc = 1, 302 .hw_ecc = 1,
303}; 303};
304 304
305#if defined(CONFIG_USB_ULPI)
305static struct mxc_usbh_platform_data otg_pdata = { 306static struct mxc_usbh_platform_data otg_pdata = {
306 .portsc = MXC_EHCI_MODE_UTMI, 307 .portsc = MXC_EHCI_MODE_UTMI,
307 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 308 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -312,6 +313,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
312 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 313 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
313 MXC_EHCI_IPPUE_DOWN, 314 MXC_EHCI_IPPUE_DOWN,
314}; 315};
316#endif
315 317
316static struct fsl_usb2_platform_data otg_device_pdata = { 318static struct fsl_usb2_platform_data otg_device_pdata = {
317 .operating_mode = FSL_USB2_DR_DEVICE, 319 .operating_mode = FSL_USB2_DR_DEVICE,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9d7b73..6e384d92e625 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/i2c.h>
15#include <linux/gpio.h> 16#include <linux/gpio.h>
16#include <linux/delay.h> 17#include <linux/delay.h>
17#include <linux/io.h> 18#include <linux/io.h>
@@ -21,6 +22,7 @@
21#include <mach/hardware.h> 22#include <mach/hardware.h>
22#include <mach/imx-uart.h> 23#include <mach/imx-uart.h>
23#include <mach/iomux-mx51.h> 24#include <mach/iomux-mx51.h>
25#include <mach/i2c.h>
24#include <mach/mxc_ehci.h> 26#include <mach/mxc_ehci.h>
25 27
26#include <asm/irq.h> 28#include <asm/irq.h>
@@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = {
64 MX51_PAD_EIM_D27__UART3_RTS, 66 MX51_PAD_EIM_D27__UART3_RTS,
65 MX51_PAD_EIM_D24__UART3_CTS, 67 MX51_PAD_EIM_D24__UART3_CTS,
66 68
69 /* I2C1 */
70 MX51_PAD_EIM_D16__I2C1_SDA,
71 MX51_PAD_EIM_D19__I2C1_SCL,
72
73 /* I2C2 */
74 MX51_PAD_KEY_COL4__I2C2_SCL,
75 MX51_PAD_KEY_COL5__I2C2_SDA,
76
77 /* HSI2C */
78 MX51_PAD_I2C1_CLK__HSI2C_CLK,
79 MX51_PAD_I2C1_DAT__HSI2C_DAT,
80
67 /* USB HOST1 */ 81 /* USB HOST1 */
68 MX51_PAD_USBH1_CLK__USBH1_CLK, 82 MX51_PAD_USBH1_CLK__USBH1_CLK,
69 MX51_PAD_USBH1_DIR__USBH1_DIR, 83 MX51_PAD_USBH1_DIR__USBH1_DIR,
@@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = {
78 MX51_PAD_USBH1_DATA7__USBH1_DATA7, 92 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
79 93
80 /* USB HUB reset line*/ 94 /* USB HUB reset line*/
81 MX51_PAD_GPIO_1_7__GPIO1_7, 95 MX51_PAD_GPIO_1_7__GPIO_1_7,
82}; 96};
83 97
84/* Serial ports */ 98/* Serial ports */
@@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void)
99} 113}
100#endif /* SERIAL_IMX */ 114#endif /* SERIAL_IMX */
101 115
116static struct imxi2c_platform_data babbage_i2c_data = {
117 .bitrate = 100000,
118};
119
120static struct imxi2c_platform_data babbage_hsi2c_data = {
121 .bitrate = 400000,
122};
123
102static int gpio_usbh1_active(void) 124static int gpio_usbh1_active(void)
103{ 125{
104 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; 126 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
@@ -230,6 +252,10 @@ static void __init mxc_board_init(void)
230 mxc_init_imx_uart(); 252 mxc_init_imx_uart();
231 platform_add_devices(devices, ARRAY_SIZE(devices)); 253 platform_add_devices(devices, ARRAY_SIZE(devices));
232 254
255 mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
256 mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
257 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
258
233 if (otg_mode_host) 259 if (otg_mode_host)
234 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); 260 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
235 else { 261 else {
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d3370e..fd24092154b5 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -798,6 +798,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
798DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, 798DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
799 NULL, NULL, &ipg_clk, NULL); 799 NULL, NULL, &ipg_clk, NULL);
800 800
801/* I2C */
802DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
803 NULL, NULL, &ipg_clk, NULL);
804DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
805 NULL, NULL, &ipg_clk, NULL);
806DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
807 NULL, NULL, &ipg_clk, NULL);
808
801/* FEC */ 809/* FEC */
802DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, 810DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
803 NULL, NULL, &ipg_clk, NULL); 811 NULL, NULL, &ipg_clk, NULL);
@@ -815,6 +823,9 @@ static struct clk_lookup lookups[] = {
815 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 823 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
816 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 824 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
817 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 825 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
826 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
827 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
828 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
818 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) 829 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
819 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) 830 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
820 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) 831 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index f40778f1a877..fa118646c99e 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = {
93 .resource = mxc_fec_resources, 93 .resource = mxc_fec_resources,
94}; 94};
95 95
96static struct resource mxc_i2c0_resources[] = {
97 {
98 .start = MX51_I2C1_BASE_ADDR,
99 .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX51_MXC_INT_I2C1,
103 .end = MX51_MXC_INT_I2C1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108struct platform_device mxc_i2c_device0 = {
109 .name = "imx-i2c",
110 .id = 0,
111 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
112 .resource = mxc_i2c0_resources,
113};
114
115static struct resource mxc_i2c1_resources[] = {
116 {
117 .start = MX51_I2C2_BASE_ADDR,
118 .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX51_MXC_INT_I2C2,
122 .end = MX51_MXC_INT_I2C2,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device mxc_i2c_device1 = {
128 .name = "imx-i2c",
129 .id = 1,
130 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
131 .resource = mxc_i2c1_resources,
132};
133
134static struct resource mxc_hsi2c_resources[] = {
135 {
136 .start = MX51_HSI2C_DMA_BASE_ADDR,
137 .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
138 .flags = IORESOURCE_MEM,
139 },
140 {
141 .start = MX51_MXC_INT_HS_I2C,
142 .end = MX51_MXC_INT_HS_I2C,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147struct platform_device mxc_hsi2c_device = {
148 .name = "imx-i2c",
149 .id = 2,
150 .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
151 .resource = mxc_hsi2c_resources
152};
153
96static u64 usb_dma_mask = DMA_BIT_MASK(32); 154static u64 usb_dma_mask = DMA_BIT_MASK(32);
97 155
98static struct resource usbotg_resources[] = { 156static struct resource usbotg_resources[] = {
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae71cd5b..a853933682e7 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,6 @@ extern struct platform_device mxc_usbdr_host_device;
6extern struct platform_device mxc_usbh1_device; 6extern struct platform_device mxc_usbh1_device;
7extern struct platform_device mxc_usbdr_udc_device; 7extern struct platform_device mxc_usbdr_udc_device;
8extern struct platform_device mxc_wdt; 8extern struct platform_device mxc_wdt;
9extern struct platform_device mxc_i2c_device0;
10extern struct platform_device mxc_i2c_device1;
11extern struct platform_device mxc_hsi2c_device;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index cf053d7e5261..20b2e79e54f2 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -24,6 +24,7 @@ config ARCH_MX25
24 select CPU_ARM926T 24 select CPU_ARM926T
25 select ARCH_MXC_IOMUX_V3 25 select ARCH_MXC_IOMUX_V3
26 select HAVE_FB_IMX 26 select HAVE_FB_IMX
27 select ARCH_MXC_AUDMUX_V2
27 help 28 help
28 This enables support for systems based on the Freescale i.MX25 family 29 This enables support for systems based on the Freescale i.MX25 family
29 30
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 1b5e4df92073..f9e7cdbd0005 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -187,6 +187,7 @@ static int mxc_audmux_v2_init(void)
187{ 187{
188 int ret; 188 int ret;
189 189
190#if defined(CONFIG_ARCH_MX3)
190 if (cpu_is_mx31()) 191 if (cpu_is_mx31())
191 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); 192 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
192 193
@@ -200,7 +201,19 @@ static int mxc_audmux_v2_init(void)
200 } 201 }
201 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); 202 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
202 } 203 }
203 204#endif
205#if defined(CONFIG_ARCH_MX25)
206 if (cpu_is_mx25()) {
207 audmux_clk = clk_get(NULL, "audmux");
208 if (IS_ERR(audmux_clk)) {
209 ret = PTR_ERR(audmux_clk);
210 printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
211 ret);
212 return ret;
213 }
214 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
215 }
216#endif
204 audmux_debugfs_init(); 217 audmux_debugfs_init();
205 218
206 return 0; 219 return 0;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 323ff8ccc877..2ed3ab173add 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk)
52{ 52{
53 if (clk == NULL || IS_ERR(clk)) 53 if (clk == NULL || IS_ERR(clk))
54 return; 54 return;
55
56 __clk_disable(clk->parent);
57 __clk_disable(clk->secondary);
58
59 WARN_ON(!clk->usecount); 55 WARN_ON(!clk->usecount);
60 if (!(--clk->usecount) && clk->disable) 56
61 clk->disable(clk); 57 if (!(--clk->usecount)) {
58 if (clk->disable)
59 clk->disable(clk);
60 __clk_disable(clk->parent);
61 __clk_disable(clk->secondary);
62 }
62} 63}
63 64
64static int __clk_enable(struct clk *clk) 65static int __clk_enable(struct clk *clk)
@@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk)
66 if (clk == NULL || IS_ERR(clk)) 67 if (clk == NULL || IS_ERR(clk))
67 return -EINVAL; 68 return -EINVAL;
68 69
69 __clk_enable(clk->parent); 70 if (clk->usecount++ == 0) {
70 __clk_enable(clk->secondary); 71 __clk_enable(clk->parent);
71 72 __clk_enable(clk->secondary);
72 if (clk->usecount++ == 0 && clk->enable)
73 clk->enable(clk);
74 73
74 if (clk->enable)
75 clk->enable(clk);
76 }
75 return 0; 77 return 0;
76} 78}
77 79
@@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate);
160int clk_set_parent(struct clk *clk, struct clk *parent) 162int clk_set_parent(struct clk *clk, struct clk *parent)
161{ 163{
162 int ret = -EINVAL; 164 int ret = -EINVAL;
165 struct clk *old;
163 166
164 if (clk == NULL || IS_ERR(clk) || parent == NULL || 167 if (clk == NULL || IS_ERR(clk) || parent == NULL ||
165 IS_ERR(parent) || clk->set_parent == NULL) 168 IS_ERR(parent) || clk->set_parent == NULL)
166 return ret; 169 return ret;
167 170
171 if (clk->usecount)
172 clk_enable(parent);
173
168 mutex_lock(&clocks_mutex); 174 mutex_lock(&clocks_mutex);
169 ret = clk->set_parent(clk, parent); 175 ret = clk->set_parent(clk, parent);
170 if (ret == 0) 176 if (ret == 0) {
177 old = clk->parent;
171 clk->parent = parent; 178 clk->parent = parent;
179 } else {
180 old = parent;
181 }
172 mutex_unlock(&clocks_mutex); 182 mutex_unlock(&clocks_mutex);
173 183
184 if (clk->usecount)
185 clk_disable(old);
186
174 return ret; 187 return ret;
175} 188}
176EXPORT_SYMBOL(clk_set_parent); 189EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 6cedd5d23939..35a064ff02ba 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -69,7 +69,51 @@
69int mxc_initialize_usb_hw(int port, unsigned int flags) 69int mxc_initialize_usb_hw(int port, unsigned int flags)
70{ 70{
71 unsigned int v; 71 unsigned int v;
72#ifdef CONFIG_ARCH_MX3 72#if defined(CONFIG_ARCH_MX25)
73 if (cpu_is_mx25()) {
74 v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
75 USBCTRL_OTGBASE_OFFSET));
76
77 switch (port) {
78 case 0: /* OTG port */
79 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
80 v |= (flags & MXC_EHCI_INTERFACE_MASK)
81 << MX35_OTG_SIC_SHIFT;
82 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
83 v |= MX35_OTG_PM_BIT;
84
85 break;
86 case 1: /* H1 port */
87 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
88 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
89 v |= (flags & MXC_EHCI_INTERFACE_MASK)
90 << MX35_H1_SIC_SHIFT;
91 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
92 v |= MX35_H1_PM_BIT;
93
94 if (!(flags & MXC_EHCI_TTL_ENABLED))
95 v |= MX35_H1_TLL_BIT;
96
97 if (flags & MXC_EHCI_INTERNAL_PHY)
98 v |= MX35_H1_USBTE_BIT;
99
100 if (flags & MXC_EHCI_IPPUE_DOWN)
101 v |= MX35_H1_IPPUE_DOWN_BIT;
102
103 if (flags & MXC_EHCI_IPPUE_UP)
104 v |= MX35_H1_IPPUE_UP_BIT;
105
106 break;
107 default:
108 return -EINVAL;
109 }
110
111 writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
112 USBCTRL_OTGBASE_OFFSET));
113 return 0;
114 }
115#endif /* CONFIG_ARCH_MX25 */
116#if defined(CONFIG_ARCH_MX3)
73 if (cpu_is_mx31()) { 117 if (cpu_is_mx31()) {
74 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + 118 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
75 USBCTRL_OTGBASE_OFFSET)); 119 USBCTRL_OTGBASE_OFFSET));
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h
new file mode 100644
index 000000000000..5c9901e7d8d0
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on board-pcm038.h which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__
23#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__
24
25#ifndef __ASSEMBLY__
26/*
27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init().
31 *
32 * This example here is for the development board. Refer
33 * eukrea_mbimx25-baseboard.c
34 */
35
36extern void eukrea_mbimxsd_baseboard_init(void);
37
38#endif
39
40#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
new file mode 100644
index 000000000000..116eee723455
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on board-pcm038.h which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__
23#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__
24
25#ifndef __ASSEMBLY__
26/*
27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init().
31 *
32 * This example here is for the development board. Refer
33 * eukrea_mbimx25-baseboard.c
34 */
35
36extern void eukrea_mbimxsd_baseboard_init(void);
37
38#endif
39
40#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f39220d1b67a..d7f52c91f82e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
252#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) 252#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
253 253
254#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) 254#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
255#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
255#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL) 256#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
256 257
257#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) 258#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
@@ -371,30 +372,41 @@
371#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL) 372#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
372#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) 373#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
373 374
374#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) 375#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
376#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
377
378#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
375#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) 379#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
376 380
377#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE) 381#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
378#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) 382#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
379 383
380#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE) 384#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
381#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) 385#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
382#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) 386#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
383 387
384#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE) 388#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
385#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) 389#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
386#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) 390#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
387 391
388#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 392#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
393#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
394#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
389#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) 395#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
390 396
391#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 397#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
398#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
399#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
392#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) 400#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
393 401
394#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 402#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
403#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
404#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
395#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) 405#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
396 406
397#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 407#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
408#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
409#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
398#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) 410#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
399 411
400#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL) 412#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d953d0..56ed0a6ac5e6 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
27 IOMUX_CONFIG_ALT5, 27 IOMUX_CONFIG_ALT5,
28 IOMUX_CONFIG_ALT6, 28 IOMUX_CONFIG_ALT6,
29 IOMUX_CONFIG_ALT7, 29 IOMUX_CONFIG_ALT7,
30 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ 30 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
31 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ 31 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
32} iomux_pin_cfg_t; 32} iomux_pin_cfg_t;
33 33
34/* Pad control groupings */ 34/* Pad control groupings */
@@ -38,6 +38,8 @@ typedef enum iomux_config {
38 PAD_CTL_SRE_FAST) 38 PAD_CTL_SRE_FAST)
39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
40 PAD_CTL_SRE_FAST) 40 PAD_CTL_SRE_FAST)
41#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
42 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
41#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 43#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 44 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_PKE | PAD_CTL_HYS) 45 PAD_CTL_PKE | PAD_CTL_HYS)
@@ -46,289 +48,272 @@ typedef enum iomux_config {
46 48
47/* 49/*
48 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 50 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
49 * If <padname> or <padmode> refers to a GPIO, it is named 51 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
50 * GPIO_<unit>_<num> see also iomux-v3.h 52 * See also iomux-v3.h
51 */ 53 */
52 54
53/* 55/* PAD MUX ALT INPSE PATH PADCTRL */
54 * FIXME: This was converted using scripts from existing Freescale code to 56#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
55 * this form used upstream. Need to verify the name format. 57#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
56 */ 58#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
57 59#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
58/* PAD MUX ALT INPSE PATH PADCTRL */ 60#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
59 61#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) 62#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) 63#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
62#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) 64#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
63#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) 65#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
64#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) 66#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
65#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) 67#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
66#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) 68#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
67#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) 69#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
68#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) 70#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
69 71#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
70/* Babbage UART3 */ 72#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
71#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) 73#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
72#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) 74 0x09b4, 0, MX51_I2C_PAD_CTRL)
73#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) 75#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
74#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) 76#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
75 77#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
76#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) 78#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
77#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) 79 0x09b0, 0, MX51_I2C_PAD_CTRL)
78#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) 80#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
79#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) 81#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
80 82#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
81#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) 83#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
82#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) 84#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL)
83#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) 85#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
84#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) 86#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL)
85#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) 87#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL)
86#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) 88#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
87#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) 89#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
88#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) 90#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
89 91#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
90#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) 92#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
91#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) 93#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
92#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) 94#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
93#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) 95#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) 96#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
95#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) 97#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
96#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) 98#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
97#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) 99#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
98 100#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) 101#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
100#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) 102#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
101#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) 103#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
102#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) 104#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
103#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) 105#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
104#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) 106#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
105#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) 107#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
106#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) 108#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
107 109#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) 110#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
109#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) 111#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
110#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) 112#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) 113#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) 114#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) 115#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
114#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) 116#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
115#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) 117#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
116#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) 118#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
117#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) 119#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
118#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) 120#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
119#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) 121#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
120#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) 122#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
121/* REVISIT: Not sure of these values 123#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
122 124#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
123 #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) 125#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
124 #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 126#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
125 #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 127#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
126*/ 128#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 129#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 130#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
129#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 131#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 132#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) 133#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) 134#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) 135#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) 136#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
135#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) 137#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
136#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 138#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
137#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 139#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
138#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) 140#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
139#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) 141#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
140#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) 142#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
141#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) 143#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) 144#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) 145#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
144#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) 146#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
145#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) 147#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
146#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) 148#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) 149#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
148#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) 150#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
149#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) 151#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) 152#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
151#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) 153#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
152#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) 154#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
153#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) 155#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
154#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) 156#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
155#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) 157#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
156#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) 158#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
157#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) 159#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) 160#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
159#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) 161#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) 162#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
161#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) 163#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) 164#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) 165#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) 166#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
165#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) 167#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) 168#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
167#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 169#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 170#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
169#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 171#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) 172#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
171#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) 173#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) 174#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
173#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) 175#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
174#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) 176#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
175#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) 177#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
176#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) 178#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
177#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) 179#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
178#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) 180#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
179#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) 181#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
180#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) 182#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
181#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 183#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
182#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) 184#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
183#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) 185#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
184#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) 186#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
185#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) 187#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) 188#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
187#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) 189#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
188#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) 190#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
189#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) 191#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
190#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) 192#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
191#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) 193#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
192#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) 194#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
193#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) 195#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
194 196#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
195/* Babbage UART1 */ 197#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
196#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 198#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
197#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 199#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
198#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) 200#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
199#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) 201#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL)
200 202#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
201/* Babbage UART2 */ 203#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL)
202#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) 204#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
203#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) 205#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
204 206#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL)
205#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) 207#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
206#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) 208#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
207#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) 209#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
208#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) 210#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) 211#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) 212#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) 213#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
212#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) 214#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
213#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) 215#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
214#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) 216#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
215#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) 217#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
216#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) 218#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
217#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) 219 0x09b8, 1, MX51_I2C_PAD_CTRL)
218#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 220#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
219#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 221#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
220#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 222 0x09bc, 1, MX51_I2C_PAD_CTRL)
221#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) 223#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
222#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 224#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
223#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 225#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
224#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 226#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL)
225#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 227#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
226#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 228#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
227#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 229#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
228#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 230#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
229#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 231#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
230#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 232#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
231#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 233#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
232#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) 234#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
233#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) 235#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
234#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) 236#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
235#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) 237#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) 238#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
237#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) 239#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) 240#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) 241#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
240#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) 242#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
241#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) 243#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
242#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) 244#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
243#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) 245#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
244#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) 246#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
245#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) 247#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
246#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) 248#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) 249#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) 250#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) 251#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
250#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) 252#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
251#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) 253#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
252#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) 254#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
253#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) 255#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
254#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) 256#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
255#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) 257#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
256#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) 258#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
257#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) 259#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) 260#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
259#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) 261#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
260#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) 262#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) 263#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
262#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) 264#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
263#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) 265#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) 266#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
265#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) 267#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
266#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) 268#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
267#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) 269#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
268#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) 270#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
269#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) 271#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) 272#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
271#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) 273#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
272#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) 274#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
273#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) 275#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
274#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) 276#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
275#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) 277#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
276#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) 278#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
277#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) 279#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) 280#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
279#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) 281#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
280#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) 282#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
281#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) 283#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
282#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) 284#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
283#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) 285#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
284#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) 286#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
285#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) 287#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
286#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) 288#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
287#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 289#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
288#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 290#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
289#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 291#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
290#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) 292#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
291#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) 293#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
292#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) 294#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
293#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) 295#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
294#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) 296#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) 297#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) 298#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) 299#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
298#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) 300#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
299#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) 301#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) 302#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) 303#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) 304#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
303#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) 305#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
304#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) 306#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
305#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) 307#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
306#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 308#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
307#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 309#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
308#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 310#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
309#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) 311#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
310#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 312#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ 313#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
312 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) 314#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
313#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 315#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
314 316#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL)
315/* EIM */ 317#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
316#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
317#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
319#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
321#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
322#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
323#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
324
325#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
326#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
327#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
328#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
329#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
330#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
331#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
332#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
333 318
334#endif /* __MACH_IOMUX_MX51_H__ */ 319#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba..0880a4a1aed1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
89#define PAD_CTL_SRE_FAST (1 << 0) 89#define PAD_CTL_SRE_FAST (1 << 0)
90#define PAD_CTL_SRE_SLOW (0 << 0) 90#define PAD_CTL_SRE_SLOW (0 << 0)
91 91
92
93#define MX51_NUM_GPIO_PORT 4
94
95#define GPIO_PIN_MASK 0x1f
96
97#define GPIO_PORT_SHIFT 5
98#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
99
100#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
101#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
102#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
103#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
104#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
105#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
106
92/* 107/*
93 * setups a single pad in the iomuxer 108 * setups a single pad in the iomuxer
94 */ 109 */
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index de2128dada5c..29115f405af9 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -31,6 +31,9 @@ struct imxmmc_platform_data {
31 31
32 /* adjust slot voltage */ 32 /* adjust slot voltage */
33 void (*setpower)(struct device *, unsigned int vdd); 33 void (*setpower)(struct device *, unsigned int vdd);
34
35 /* enable card detect using DAT3 */
36 int dat3_card_detect;
34}; 37};
35 38
36#endif 39#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ca95b1ed5fea..2f2aad1032c1 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -33,6 +33,7 @@
33 33
34#define MX25_UART1_BASE_ADDR 0x43f90000 34#define MX25_UART1_BASE_ADDR 0x43f90000
35#define MX25_UART2_BASE_ADDR 0x43f94000 35#define MX25_UART2_BASE_ADDR 0x43f94000
36#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
36#define MX25_UART3_BASE_ADDR 0x5000c000 37#define MX25_UART3_BASE_ADDR 0x5000c000
37#define MX25_UART4_BASE_ADDR 0x50008000 38#define MX25_UART4_BASE_ADDR 0x50008000
38#define MX25_UART5_BASE_ADDR 0x5002c000 39#define MX25_UART5_BASE_ADDR 0x5002c000
@@ -40,18 +41,27 @@
40#define MX25_CSPI3_BASE_ADDR 0x50004000 41#define MX25_CSPI3_BASE_ADDR 0x50004000
41#define MX25_CSPI2_BASE_ADDR 0x50010000 42#define MX25_CSPI2_BASE_ADDR 0x50010000
42#define MX25_FEC_BASE_ADDR 0x50038000 43#define MX25_FEC_BASE_ADDR 0x50038000
44#define MX25_SSI2_BASE_ADDR 0x50014000
45#define MX25_SSI1_BASE_ADDR 0x50034000
43#define MX25_NFC_BASE_ADDR 0xbb000000 46#define MX25_NFC_BASE_ADDR 0xbb000000
44#define MX25_DRYICE_BASE_ADDR 0x53ffc000 47#define MX25_DRYICE_BASE_ADDR 0x53ffc000
45#define MX25_LCDC_BASE_ADDR 0x53fbc000 48#define MX25_LCDC_BASE_ADDR 0x53fbc000
49#define MX25_KPP_BASE_ADDR 0x43fa8000
50#define MX25_OTG_BASE_ADDR 0x53ff4000
51#define MX25_CSI_BASE_ADDR 0x53ff8000
46 52
47#define MX25_INT_CSPI3 0 53#define MX25_INT_CSPI3 0
48#define MX25_INT_I2C1 3 54#define MX25_INT_I2C1 3
49#define MX25_INT_I2C2 4 55#define MX25_INT_I2C2 4
50#define MX25_INT_UART4 5 56#define MX25_INT_UART4 5
51#define MX25_INT_I2C3 10 57#define MX25_INT_I2C3 10
58#define MX25_INT_SSI2 11
59#define MX25_INT_SSI1 12
52#define MX25_INT_CSPI2 13 60#define MX25_INT_CSPI2 13
53#define MX25_INT_CSPI1 14 61#define MX25_INT_CSPI1 14
62#define MX25_INT_CSI 17
54#define MX25_INT_UART3 18 63#define MX25_INT_UART3 18
64#define MX25_INT_KPP 24
55#define MX25_INT_DRYICE 25 65#define MX25_INT_DRYICE 25
56#define MX25_INT_UART2 32 66#define MX25_INT_UART2 32
57#define MX25_INT_NANDFC 33 67#define MX25_INT_NANDFC 33
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 28988c7365f5..04c0d060d814 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -20,9 +20,13 @@
20#ifndef __ASM_ARCH_NAND_H 20#ifndef __ASM_ARCH_NAND_H
21#define __ASM_ARCH_NAND_H 21#define __ASM_ARCH_NAND_H
22 22
23#include <linux/mtd/partitions.h>
24
23struct mxc_nand_platform_data { 25struct mxc_nand_platform_data {
24 unsigned int width; /* data bus width in bytes */ 26 unsigned int width; /* data bus width in bytes */
25 unsigned int hw_ecc:1; /* 0 if supress hardware ECC */ 27 unsigned int hw_ecc:1; /* 0 if supress hardware ECC */
26 unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ 28 unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
29 struct mtd_partition *parts; /* partition table */
30 int nr_parts; /* size of parts */
27}; 31};
28#endif /* __ASM_ARCH_NAND_H */ 32#endif /* __ASM_ARCH_NAND_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 14:02:49 -0500