267 files changed, 6364 insertions, 3951 deletions

diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 1e6956a90608..14db93e4c8a8 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -445,7 +445,7 @@ struct procfs_args {
  * unhappy with OSF UFS. [CHECKME]
  */
 static int
-osf_ufs_mount(char *dirname, struct ufs_args __user *args, int flags)
+osf_ufs_mount(const char *dirname, struct ufs_args __user *args, int flags)
 {
         int retval;
         struct cdfs_args tmp;
@@ -465,7 +465,7 @@ osf_ufs_mount(char *dirname, struct ufs_args __user *args, int flags)
 }
 
 static int
-osf_cdfs_mount(char *dirname, struct cdfs_args __user *args, int flags)
+osf_cdfs_mount(const char *dirname, struct cdfs_args __user *args, int flags)
 {
         int retval;
         struct cdfs_args tmp;
@@ -485,7 +485,7 @@ osf_cdfs_mount(char *dirname, struct cdfs_args __user *args, int flags)
 }
 
 static int
-osf_procfs_mount(char *dirname, struct procfs_args __user *args, int flags)
+osf_procfs_mount(const char *dirname, struct procfs_args __user *args, int flags)
 {
         struct procfs_args tmp;
 
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index f2aa09eb658e..9137df539b61 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -33,7 +33,7 @@ ifeq ($(CONFIG_XIP_KERNEL),y)
 
 $(obj)/xipImage: vmlinux FORCE
         $(call if_changed,objcopy)
-        $(kecho) '  Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
+        @$(kecho) '  Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
 
 $(obj)/Image $(obj)/zImage: FORCE
         @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)'
@@ -48,14 +48,14 @@ $(obj)/xipImage: FORCE
 
 $(obj)/Image: vmlinux FORCE
         $(call if_changed,objcopy)
-        $(kecho) '  Kernel: $@ is ready'
+        @$(kecho) '  Kernel: $@ is ready'
 
 $(obj)/compressed/vmlinux: $(obj)/Image FORCE
         $(Q)$(MAKE) $(build)=$(obj)/compressed $@
 
 $(obj)/zImage:  $(obj)/compressed/vmlinux FORCE
         $(call if_changed,objcopy)
-        $(kecho) '  Kernel: $@ is ready'
+        @$(kecho) '  Kernel: $@ is ready'
 
 endif
 
@@ -90,7 +90,7 @@ fi
 $(obj)/uImage:  $(obj)/zImage FORCE
         @$(check_for_multiple_loadaddr)
         $(call if_changed,uimage)
-        $(kecho) '  Image $@ is ready'
+        @$(kecho) '  Image $@ is ready'
 
 $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
         $(Q)$(MAKE) $(build)=$(obj)/bootp $@
@@ -98,7 +98,7 @@ $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
 
 $(obj)/bootpImage: $(obj)/bootp/bootp FORCE
         $(call if_changed,objcopy)
-        $(kecho) '  Kernel: $@ is ready'
+        @$(kecho) '  Kernel: $@ is ready'
 
 PHONY += initrd FORCE
 initrd:
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d68..df7f2270fc91 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -73,8 +73,8 @@
 
         pinmux: pinmux {
                 compatible = "nvidia,tegra30-pinmux";
-                reg = <0x70000868 0xd0    /* Pad control registers */
-                       0x70003000 0x3e0>; /* Mux registers */
+                reg = <0x70000868 0xd4    /* Pad control registers */
+                       0x70003000 0x3e4>; /* Mux registers */
         };
 
         serial@70006000 {
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 1e122bcd7845..3cee0e6ea7c3 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -68,7 +68,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 
         /* Enable overcurrent notification */
         for (i = 0; i < data->ports; i++) {
-                if (data->overcurrent_pin[i])
+                if (gpio_is_valid(data->overcurrent_pin[i]))
                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
         }
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index aa1e58729885..414bd855fb0c 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 
         /* Enable overcurrent notification */
         for (i = 0; i < data->ports; i++) {
-                if (data->overcurrent_pin[i])
+                if (gpio_is_valid(data->overcurrent_pin[i]))
                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
         }
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index b9487696b7be..cd604aad8e96 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 
         /* Enable overcurrent notification */
         for (i = 0; i < data->ports; i++) {
-                if (data->overcurrent_pin[i])
+                if (gpio_is_valid(data->overcurrent_pin[i]))
                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
         }
 
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index cb85da2eccea..9c61e59a2104 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -78,7 +78,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 
         /* Enable overcurrent notification */
         for (i = 0; i < data->ports; i++) {
-                if (data->overcurrent_pin[i])
+                if (gpio_is_valid(data->overcurrent_pin[i]))
                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
         }
 
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b1596072dcc2..fcd233cb33d2 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -1841,8 +1841,8 @@ static struct resource sha_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_AESTDESSHA,
-                .end    = AT91SAM9G45_ID_AESTDESSHA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1874,8 +1874,8 @@ static struct resource tdes_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_AESTDESSHA,
-                .end    = AT91SAM9G45_ID_AESTDESSHA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1910,8 +1910,8 @@ static struct resource aes_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_AESTDESSHA,
-                .end    = AT91SAM9G45_ID_AESTDESSHA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index cd0c8b1e1ecf..14e9947bad6e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -713,8 +713,7 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
                 break;
         case VPBE_ENC_CUSTOM_TIMINGS:
                 if (pclock <= 27000000) {
-                        v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
-                             DM644X_VPSS_DACCLKEN;
+                        v |= DM644X_VPSS_DACCLKEN;
                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
                 } else {
                         /*
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 21d568b3b149..87e07d6fc615 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -275,6 +275,9 @@ static int __init exynos_dma_init(void)
                 exynos_pdma1_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4210_pdma1_peri);
                 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+
+                if (samsung_rev() == EXYNOS4210_REV_0)
+                        exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
                 exynos_pdma0_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4212_pdma0_peri);
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 8480849affb9..ed4da4544cd2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -90,6 +90,7 @@
 
 #define EXYNOS4_PA_MDMA0                0x10810000
 #define EXYNOS4_PA_MDMA1                0x12850000
+#define EXYNOS4_PA_S_MDMA1              0x12840000
 #define EXYNOS4_PA_PDMA0                0x12680000
 #define EXYNOS4_PA_PDMA1                0x12690000
 #define EXYNOS5_PA_MDMA0                0x10800000
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 82c27230d4a9..86e37cd9376c 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -28,6 +28,7 @@ void highbank_restart(char mode, const char *cmd)
                 hignbank_set_pwr_soft_reset();
 
         scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
-        cpu_do_idle();
+        while (1)
+                cpu_do_idle();
 }
 
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 3c1b8ff9a0a6..cc49c7ae186e 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -112,7 +112,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
 
         clk = clk_register(dev, &gate->hw);
         if (IS_ERR(clk))
-                kfree(clk);
+                kfree(gate);
 
         return clk;
 }
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 412c583a24b0..576af7446952 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -30,7 +30,7 @@
 #define MX25_H1_SIC_SHIFT       21
 #define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
 #define MX25_H1_PP_BIT          (1 << 18)
-#define MX25_H1_PM_BIT          (1 << 8)
+#define MX25_H1_PM_BIT          (1 << 16)
 #define MX25_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX25_H1_TLL_BIT         (1 << 5)
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 779e16eb65cb..293397852e4e 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -30,7 +30,7 @@
 #define MX35_H1_SIC_SHIFT       21
 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
 #define MX35_H1_PP_BIT          (1 << 18)
-#define MX35_H1_PM_BIT          (1 << 8)
+#define MX35_H1_PM_BIT          (1 << 16)
 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX35_H1_TLL_BIT         (1 << 5)
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 48d5e41dfbfa..378590694447 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -580,6 +580,11 @@ static void __init igep_wlan_bt_init(void)
         } else
                 return;
 
+        /* Make sure that the GPIO pins are muxed correctly */
+        omap_mux_init_gpio(igep_wlan_bt_gpios[0].gpio, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(igep_wlan_bt_gpios[1].gpio, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(igep_wlan_bt_gpios[2].gpio, OMAP_PIN_OUTPUT);
+
         err = gpio_request_array(igep_wlan_bt_gpios,
                                  ARRAY_SIZE(igep_wlan_bt_gpios));
         if (err) {
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index b56d06b48782..95192a062d5d 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -359,7 +359,7 @@ static struct clockdomain iss_44xx_clkdm = {
         .clkdm_offs       = OMAP4430_CM2_CAM_CAM_CDOFFS,
         .wkdep_srcs       = iss_wkup_sleep_deps,
         .sleepdep_srcs    = iss_wkup_sleep_deps,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .flags            = CLKDM_CAN_SWSUP,
 };
 
 static struct clockdomain l3_dss_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 48daac2581b4..84551f205e46 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -64,30 +64,36 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
         struct spi_board_info *spi_bi = &ads7846_spi_board_info;
         int err;
 
-        err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
-        if (err) {
-                pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
-                return;
-        }
+        /*
+         * If a board defines get_pendown_state() function, request the pendown
+         * GPIO and set the GPIO debounce time.
+         * If a board does not define the get_pendown_state() function, then
+         * the ads7846 driver will setup the pendown GPIO itself.
+         */
+        if (board_pdata && board_pdata->get_pendown_state) {
+                err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
+                if (err) {
+                        pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
+                        return;
+                }
 
-        if (gpio_debounce)
-                gpio_set_debounce(gpio_pendown, gpio_debounce);
+                if (gpio_debounce)
+                        gpio_set_debounce(gpio_pendown, gpio_debounce);
+
+                gpio_export(gpio_pendown, 0);
+        }
 
         spi_bi->bus_num = bus_num;
         spi_bi->irq     = gpio_to_irq(gpio_pendown);
 
+        ads7846_config.gpio_pendown = gpio_pendown;
+
         if (board_pdata) {
                 board_pdata->gpio_pendown = gpio_pendown;
+                board_pdata->gpio_pendown_debounce = gpio_debounce;
                 spi_bi->platform_data = board_pdata;
-                if (board_pdata->get_pendown_state)
-                        gpio_export(gpio_pendown, 0);
-        } else {
-                ads7846_config.gpio_pendown = gpio_pendown;
         }
 
-        if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state))
-                gpio_free(gpio_pendown);
-
         spi_register_board_info(&ads7846_spi_board_info, 1);
 }
 #else
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index cba60e05e32e..c72b5a727720 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,6 +19,7 @@
 #include <linux/of.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
+#include <linux/platform_data/omap_ocp2scp.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -613,6 +614,83 @@ static void omap_init_vout(void)
 static inline void omap_init_vout(void) {}
 #endif
 
+#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE)
+static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
+{
+        int cnt = 0;
+
+        while (ocp2scp_dev->drv_name != NULL) {
+                cnt++;
+                ocp2scp_dev++;
+        }
+
+        return cnt;
+}
+
+static void omap_init_ocp2scp(void)
+{
+        struct omap_hwmod       *oh;
+        struct platform_device  *pdev;
+        int                     bus_id = -1, dev_cnt = 0, i;
+        struct omap_ocp2scp_dev *ocp2scp_dev;
+        const char              *oh_name, *name;
+        struct omap_ocp2scp_platform_data *pdata;
+
+        if (!cpu_is_omap44xx())
+                return;
+
+        oh_name = "ocp2scp_usb_phy";
+        name    = "omap-ocp2scp";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("%s: could not find omap_hwmod for %s\n", __func__,
+                                                                oh_name);
+                return;
+        }
+
+        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("%s: No memory for ocp2scp pdata\n", __func__);
+                return;
+        }
+
+        ocp2scp_dev = oh->dev_attr;
+        dev_cnt = count_ocp2scp_devices(ocp2scp_dev);
+
+        if (!dev_cnt) {
+                pr_err("%s: No devices connected to ocp2scp\n", __func__);
+                kfree(pdata);
+                return;
+        }
+
+        pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *)
+                                        * dev_cnt, GFP_KERNEL);
+        if (!pdata->devices) {
+                pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
+                kfree(pdata);
+                return;
+        }
+
+        for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
+                pdata->devices[i] = ocp2scp_dev;
+
+        pdata->dev_cnt  = dev_cnt;
+
+        pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata), NULL,
+                                                                0, false);
+        if (IS_ERR(pdev)) {
+                pr_err("Could not build omap_device for %s %s\n",
+                                                name, oh_name);
+                kfree(pdata->devices);
+                kfree(pdata);
+                return;
+        }
+}
+#else
+static inline void omap_init_ocp2scp(void) { }
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static int __init omap2_init_devices(void)
@@ -640,6 +718,7 @@ static int __init omap2_init_devices(void)
         omap_init_sham();
         omap_init_aes();
         omap_init_vout();
+        omap_init_ocp2scp();
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b969ab1d258b..87cc6d058de2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -422,6 +422,38 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
 }
 
 /**
+ * _wait_softreset_complete - wait for an OCP softreset to complete
+ * @oh: struct omap_hwmod * to wait on
+ *
+ * Wait until the IP block represented by @oh reports that its OCP
+ * softreset is complete.  This can be triggered by software (see
+ * _ocp_softreset()) or by hardware upon returning from off-mode (one
+ * example is HSMMC).  Waits for up to MAX_MODULE_SOFTRESET_WAIT
+ * microseconds.  Returns the number of microseconds waited.
+ */
+static int _wait_softreset_complete(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_class_sysconfig *sysc;
+        u32 softrst_mask;
+        int c = 0;
+
+        sysc = oh->class->sysc;
+
+        if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
+                omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs)
+                                   & SYSS_RESETDONE_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+        else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
+                softrst_mask = (0x1 << sysc->sysc_fields->srst_shift);
+                omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs)
+                                    & softrst_mask),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+        }
+
+        return c;
+}
+
+/**
  * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
  * @oh: struct omap_hwmod *
  *
@@ -1282,6 +1314,18 @@ static void _enable_sysc(struct omap_hwmod *oh)
         if (!oh->class->sysc)
                 return;
 
+        /*
+         * Wait until reset has completed, this is needed as the IP
+         * block is reset automatically by hardware in some cases
+         * (off-mode for example), and the drivers require the
+         * IP to be ready when they access it
+         */
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _enable_optional_clocks(oh);
+        _wait_softreset_complete(oh);
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _disable_optional_clocks(oh);
+
         v = oh->_sysc_cache;
         sf = oh->class->sysc->sysc_flags;
 
@@ -1804,7 +1848,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh)
  */
 static int _ocp_softreset(struct omap_hwmod *oh)
 {
-        u32 v, softrst_mask;
+        u32 v;
         int c = 0;
         int ret = 0;
 
@@ -1834,19 +1878,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
         if (oh->class->sysc->srst_udelay)
                 udelay(oh->class->sysc->srst_udelay);
 
-        if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
-                omap_test_timeout((omap_hwmod_read(oh,
-                                                    oh->class->sysc->syss_offs)
-                                   & SYSS_RESETDONE_MASK),
-                                  MAX_MODULE_SOFTRESET_WAIT, c);
-        else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
-                softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
-                omap_test_timeout(!(omap_hwmod_read(oh,
-                                                     oh->class->sysc->sysc_offs)
-                                   & softrst_mask),
-                                  MAX_MODULE_SOFTRESET_WAIT, c);
-        }
-
+        c = _wait_softreset_complete(oh);
         if (c == MAX_MODULE_SOFTRESET_WAIT)
                 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
                            oh->name, MAX_MODULE_SOFTRESET_WAIT);
@@ -2352,6 +2384,9 @@ static int __init _setup_reset(struct omap_hwmod *oh)
         if (oh->_state != _HWMOD_STATE_INITIALIZED)
                 return -EINVAL;
 
+        if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK)
+                return -EPERM;
+
         if (oh->rst_lines_cnt == 0) {
                 r = _enable(oh);
                 if (r) {
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 652d0285bd6d..0b1249e00398 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,6 +21,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
+#include <linux/platform_data/omap_ocp2scp.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/i2c.h>
@@ -2125,6 +2126,14 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         .name           = "mcpdm",
         .class          = &omap44xx_mcpdm_hwmod_class,
         .clkdm_name     = "abe_clkdm",
+        /*
+         * It's suspected that the McPDM requires an off-chip main
+         * functional clock, controlled via I2C.  This IP block is
+         * currently reset very early during boot, before I2C is
+         * available, so it doesn't seem that we have any choice in
+         * the kernel other than to avoid resetting it.
+         */
+        .flags          = HWMOD_EXT_OPT_MAIN_CLK,
         .mpu_irqs       = omap44xx_mcpdm_irqs,
         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
         .main_clk       = "mcpdm_fck",
@@ -2681,6 +2690,32 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
         .sysc   = &omap44xx_ocp2scp_sysc,
 };
 
+/* ocp2scp dev_attr */
+static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
+        {
+                .name           = "usb_phy",
+                .start          = 0x4a0ad080,
+                .end            = 0x4a0ae000,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                /* XXX: Remove this once control module driver is in place */
+                .name           = "ctrl_dev",
+                .start          = 0x4a002300,
+                .end            = 0x4a002303,
+                .flags          = IORESOURCE_MEM,
+        },
+        { }
+};
+
+static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
+        {
+                .drv_name       = "omap-usb2",
+                .res            = omap44xx_usb_phy_and_pll_addrs,
+        },
+        { }
+};
+
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
@@ -2694,6 +2729,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
+        .dev_attr       = ocp2scp_dev_attr,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 635e109f5ad3..a256135d8e48 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -73,6 +73,7 @@ void __init omap4_pmic_init(const char *pmic_type,
 {
         /* PMIC part*/
         omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
+        omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
         omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
 
         /* Register additional devices on i2c1 bus if needed */
@@ -366,7 +367,7 @@ static struct regulator_init_data omap4_clk32kg_idata = {
 };
 
 static struct regulator_consumer_supply omap4_vdd1_supply[] = {
-        REGULATOR_SUPPLY("vcc", "mpu.0"),
+        REGULATOR_SUPPLY("vcc", "cpu0"),
 };
 
 static struct regulator_consumer_supply omap4_vdd2_supply[] = {
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 880249b17012..75878c37959b 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -264,7 +264,7 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
 
         if (initialized) {
                 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
-                        pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
+                        pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
                                 __func__, voltdm->name, i2c_high_speed);
                 return;
         }
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 5ecbd17b5641..e2c6391863fe 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -28,6 +28,7 @@
 #include <linux/mfd/asic3.h>
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/gpio-regulator.h>
@@ -556,7 +557,7 @@ static struct platform_device hx4700_lcd = {
  */
 
 static struct platform_pwm_backlight_data backlight_data = {
-        .pwm_id         = 1,
+        .pwm_id         = -1,   /* Superseded by pwm_lookup */
         .max_brightness = 200,
         .dft_brightness = 100,
         .pwm_period_ns  = 30923,
@@ -571,6 +572,10 @@ static struct platform_device backlight = {
         },
 };
 
+static struct pwm_lookup hx4700_pwm_lookup[] = {
+        PWM_LOOKUP("pxa27x-pwm.1", 0, "pwm-backlight", NULL),
+};
+
 /*
  * USB "Transceiver"
  */
@@ -872,6 +877,7 @@ static void __init hx4700_init(void)
         pxa_set_stuart_info(NULL);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup));
 
         pxa_set_ficp_info(&ficp_info);
         pxa27x_set_i2c_power_info(NULL);
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 438f02fe122a..842596d4d31e 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -86,10 +86,7 @@ static void spitz_discharge1(int on)
         gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
 }
 
-static unsigned long gpio18_config[] = {
-        GPIO18_RDY,
-        GPIO18_GPIO,
-};
+static unsigned long gpio18_config = GPIO18_GPIO;
 
 static void spitz_presuspend(void)
 {
@@ -112,7 +109,7 @@ static void spitz_presuspend(void)
         PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
         PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
 
-        pxa2xx_mfp_config(&gpio18_config[0], 1);
+        pxa2xx_mfp_config(&gpio18_config, 1);
         gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown");
         gpio_free(18);
 
@@ -131,7 +128,6 @@ static void spitz_presuspend(void)
 
 static void spitz_postsuspend(void)
 {
-        pxa2xx_mfp_config(&gpio18_config[1], 1);
 }
 
 static int spitz_should_wakeup(unsigned int resume_on_alarm)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5683a84c6ee..6013831a043e 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,12 +26,14 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
+#include <linux/i2c-omap.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 
 #include <mach/irqs.h>
 #include <plat/i2c.h>
+#include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 
 #define OMAP_I2C_SIZE           0x3f
@@ -127,6 +129,16 @@ static inline int omap1_i2c_add_bus(int bus_id)
 
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
+/*
+ * XXX This function is a temporary compatibility wrapper - only
+ * needed until the I2C driver can be converted to call
+ * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
+ */
+static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
+{
+        omap_pm_set_max_mpu_wakeup_lat(dev, t);
+}
+
 static inline int omap2_i2c_add_bus(int bus_id)
 {
         int l;
@@ -158,6 +170,15 @@ static inline int omap2_i2c_add_bus(int bus_id)
         dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
         pdata->flags = dev_attr->flags;
 
+        /*
+         * When waiting for completion of a i2c transfer, we need to
+         * set a wake up latency constraint for the MPU. This is to
+         * ensure quick enough wakeup from idle, when transfer
+         * completes.
+         * Only omap3 has support for constraints
+         */
+        if (cpu_is_omap34xx())
+                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
         pdev = omap_device_build(name, bus_id, oh, pdata,
                         sizeof(struct omap_i2c_bus_platform_data),
                         NULL, 0, 0);
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index b3349f7b1a2c..1db029438022 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -443,6 +443,11 @@ struct omap_hwmod_omap4_prcm {
  *     in order to complete the reset. Optional clocks will be disabled
  *     again after the reset.
  * HWMOD_16BIT_REG: Module has 16bit registers
+ * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for
+ *     this IP block comes from an off-chip source and is not always
+ *     enabled.  This prevents the hwmod code from being able to
+ *     enable and reset the IP block early.  XXX Eventually it should
+ *     be possible to query the clock framework for this information.
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -453,6 +458,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_NO_IDLEST                         (1 << 6)
 #define HWMOD_CONTROL_OPT_CLKS_IN_RESET         (1 << 7)
 #define HWMOD_16BIT_REG                         (1 << 8)
+#define HWMOD_EXT_OPT_MAIN_CLK                  (1 << 9)
 
 /*
  * omap_hwmod._int_flags definitions
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index cd60a81163e9..32d05c8219dc 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -5,6 +5,6 @@
 #
 
 include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
-        $(kecho) '  Generating $@'
+        @$(kecho) '  Generating $@'
         @mkdir -p $(dir $@)
         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 59bcb96ac369..f57609275449 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -166,3 +166,14 @@ void free_xenballooned_pages(int nr_pages, struct page **pages)
         *pages = NULL;
 }
 EXPORT_SYMBOL_GPL(free_xenballooned_pages);
+
+/* In the hypervisor.S file. */
+EXPORT_SYMBOL_GPL(HYPERVISOR_event_channel_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_grant_table_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_xen_version);
+EXPORT_SYMBOL_GPL(HYPERVISOR_console_io);
+EXPORT_SYMBOL_GPL(HYPERVISOR_sched_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_hvm_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_memory_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_physdev_op);
+EXPORT_SYMBOL_GPL(privcmd_call);
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ef54a59a9e89..15ac18a56c93 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,6 +1,7 @@
 config ARM64
         def_bool y
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
+        select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
         select GENERIC_CLOCKEVENTS
         select GENERIC_HARDIRQS_NO_DEPRECATED
         select GENERIC_IOMAP
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index cf284649dfcb..07fea290d7c1 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -25,12 +25,10 @@
 #include <asm/user.h>
 
 typedef unsigned long elf_greg_t;
-typedef unsigned long elf_freg_t[3];
 
 #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_fp elf_fpregset_t;
+typedef struct user_fpsimd_state elf_fpregset_t;
 
 #define EM_AARCH64              183
 
@@ -87,7 +85,6 @@ typedef struct user_fp elf_fpregset_t;
 #define R_AARCH64_MOVW_PREL_G2_NC       292
 #define R_AARCH64_MOVW_PREL_G3          293
 
-
 /*
  * These are used to set parameters in the core dumps.
  */
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index b42fab9f62a9..c43b4ac13008 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -25,9 +25,8 @@
  *  - FPSR and FPCR
  *  - 32 128-bit data registers
  *
- * Note that user_fp forms a prefix of this structure, which is relied
- * upon in the ptrace FP/SIMD accessors. struct user_fpsimd_state must
- * form a prefix of struct fpsimd_state.
+ * Note that user_fpsimd forms a prefix of this structure, which is
+ * relied upon in the ptrace FP/SIMD accessors.
  */
 struct fpsimd_state {
         union {
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 74a2a7d304a9..d2f05a608274 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -114,7 +114,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
  *  I/O port access primitives.
  */
 #define IO_SPACE_LIMIT          0xffff
-#define PCI_IOBASE              ((void __iomem *)0xffffffbbfffe0000UL)
+#define PCI_IOBASE              ((void __iomem *)(MODULES_VADDR - SZ_2M))
 
 static inline u8 inb(unsigned long addr)
 {
@@ -222,12 +222,12 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot
 extern void __iounmap(volatile void __iomem *addr);
 
 #define PROT_DEFAULT            (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
-#define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_XN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
+#define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
 
-#define ioremap(addr, size)             __ioremap((addr), (size), PROT_DEVICE_nGnRE)
-#define ioremap_nocache(addr, size)     __ioremap((addr), (size), PROT_DEVICE_nGnRE)
-#define ioremap_wc(addr, size)          __ioremap((addr), (size), PROT_NORMAL_NC)
+#define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+#define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+#define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 #define iounmap                         __iounmap
 
 #define ARCH_HAS_IOREMAP_WC
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 0f3b4581d925..75fd13d289b9 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -38,7 +38,8 @@
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_NG             (_AT(pmdval_t, 1) << 11)
-#define PMD_SECT_XN             (_AT(pmdval_t, 1) << 54)
+#define PMD_SECT_PXN            (_AT(pmdval_t, 1) << 53)
+#define PMD_SECT_UXN            (_AT(pmdval_t, 1) << 54)
 
 /*
  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
@@ -57,7 +58,8 @@
 #define PTE_SHARED              (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
 #define PTE_AF                  (_AT(pteval_t, 1) << 10)        /* Access Flag */
 #define PTE_NG                  (_AT(pteval_t, 1) << 11)        /* nG */
-#define PTE_XN                  (_AT(pteval_t, 1) << 54)        /* XN */
+#define PTE_PXN                 (_AT(pteval_t, 1) << 53)        /* Privileged XN */
+#define PTE_UXN                 (_AT(pteval_t, 1) << 54)        /* User XN */
 
 /*
  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 8960239be722..14aba2db6776 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -62,23 +62,23 @@ extern pgprot_t pgprot_default;
 
 #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
 
-#define PAGE_NONE               _MOD_PROT(pgprot_default, PTE_NG | PTE_XN | PTE_RDONLY)
-#define PAGE_SHARED             _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN)
-#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_default, PTE_USER | PTE_NG)
-#define PAGE_COPY               _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
-#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_RDONLY)
-#define PAGE_READONLY           _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
-#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_RDONLY)
-#define PAGE_KERNEL             _MOD_PROT(pgprot_default, PTE_XN | PTE_DIRTY)
-#define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_default, PTE_DIRTY)
-
-#define __PAGE_NONE             __pgprot(_PAGE_DEFAULT | PTE_NG | PTE_XN | PTE_RDONLY)
-#define __PAGE_SHARED           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN)
-#define __PAGE_SHARED_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG)
-#define __PAGE_COPY             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
-#define __PAGE_COPY_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_RDONLY)
-#define __PAGE_READONLY         __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
-#define __PAGE_READONLY_EXEC    __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_RDONLY)
+#define PAGE_NONE               _MOD_PROT(pgprot_default, PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
+#define PAGE_SHARED             _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
+#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
+#define PAGE_COPY               _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
+#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
+#define PAGE_READONLY           _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
+#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
+#define PAGE_KERNEL             _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
+#define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
+
+#define __PAGE_NONE             __pgprot(_PAGE_DEFAULT | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
+#define __PAGE_SHARED           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
+#define __PAGE_SHARED_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
+#define __PAGE_COPY             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
+#define __PAGE_COPY_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
+#define __PAGE_READONLY         __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
+#define __PAGE_READONLY_EXEC    __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
 
 #endif /* __ASSEMBLY__ */
 
@@ -130,10 +130,10 @@ extern struct page *empty_zero_page;
 #define pte_young(pte)          (pte_val(pte) & PTE_AF)
 #define pte_special(pte)        (pte_val(pte) & PTE_SPECIAL)
 #define pte_write(pte)          (!(pte_val(pte) & PTE_RDONLY))
-#define pte_exec(pte)           (!(pte_val(pte) & PTE_XN))
+#define pte_exec(pte)           (!(pte_val(pte) & PTE_UXN))
 
 #define pte_present_exec_user(pte) \
-        ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_XN)) == \
+        ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == \
          (PTE_VALID | PTE_USER))
 
 #define PTE_BIT_FUNC(fn,op) \
@@ -262,7 +262,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        const pteval_t mask = PTE_USER | PTE_XN | PTE_RDONLY;
+        const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY;
         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
         return pte;
 }
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 5d810044feda..77f696c14339 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -43,6 +43,8 @@
 #else
 #define STACK_TOP               STACK_TOP_MAX
 #endif /* CONFIG_COMPAT */
+
+#define ARCH_LOW_ADDRESS_LIMIT  PHYS_MASK
 #endif /* __KERNEL__ */
 
 struct debug_info {
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index 63f853f8b718..68aff2816e86 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -14,7 +14,6 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #ifdef CONFIG_COMPAT
-#define __ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 #define __ARCH_WANT_COMPAT_STAT64
 #define __ARCH_WANT_SYS_GETHOSTNAME
 #define __ARCH_WANT_SYS_PAUSE
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index ecbf2d81ec5c..c76c7241125b 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -613,17 +613,11 @@ enum armv8_pmuv3_perf_types {
         ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          = 0x19,
         ARMV8_PMUV3_PERFCTR_MEM_ERROR                           = 0x1A,
         ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          = 0x1D,
-
-        /*
-         * This isn't an architected event.
-         * We detect this event number and use the cycle counter instead.
-         */
-        ARMV8_PMUV3_PERFCTR_CPU_CYCLES                          = 0xFF,
 };
 
 /* PMUv3 HW events mapping. */
 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
@@ -1106,7 +1100,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
         unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
 
         /* Always place a cycle counter into the cycle counter. */
-        if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
+        if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
                         return -EAGAIN;
 
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index f22965ea1cfc..e04cebdbb47f 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -310,24 +310,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
 }
 
 /*
- * Fill in the task's elfregs structure for a core dump.
- */
-int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
-{
-        elf_core_copy_regs(elfregs, task_pt_regs(t));
-        return 1;
-}
-
-/*
- * fill in the fpe structure for a core dump...
- */
-int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
-{
-        return 0;
-}
-EXPORT_SYMBOL(dump_fpu);
-
-/*
  * Shuffle the argument into the correct register before calling the
  * thread function.  x1 is the thread argument, x2 is the pointer to
  * the thread function, and x3 points to the exit function.
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 226b6bf6e9c2..538300f2273d 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -211,8 +211,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
          * before we continue.
          */
         set_cpu_online(cpu, true);
-        while (!cpu_active(cpu))
-                cpu_relax();
+        complete(&cpu_running);
 
         /*
          * OK, it's off to the idle thread for us
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index efbf7df05d3f..4cd28931dba9 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -80,7 +80,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
 #ifdef CONFIG_ZONE_DMA32
         /* 4GB maximum for 32-bit only capable devices */
         max_dma32 = min(max, MAX_DMA32_PFN);
-        zone_size[ZONE_DMA32] = max_dma32 - min;
+        zone_size[ZONE_DMA32] = max(min, max_dma32) - min;
 #endif
         zone_size[ZONE_NORMAL] = max - max_dma32;
 
diff --git a/arch/h8300/include/asm/cache.h b/arch/h8300/include/asm/cache.h
index c6350283649d..05887a1d80e5 100644
--- a/arch/h8300/include/asm/cache.h
+++ b/arch/h8300/include/asm/cache.h
@@ -2,7 +2,8 @@
 #define __ARCH_H8300_CACHE_H
 
 /* bytes per L1 cache line */
-#define        L1_CACHE_BYTES  4
+#define        L1_CACHE_SHIFT  2
+#define        L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
 
 /* m68k-elf-gcc  2.95.2 doesn't like these */
 
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index acd5b68e8871..082e383c1b6f 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -637,7 +637,6 @@ mem_init (void)
 
         high_memory = __va(max_low_pfn * PAGE_SIZE);
 
-        reset_zone_present_pages();
         for_each_online_pgdat(pgdat)
                 if (pgdat->bdata->node_bootmem_map)
                         totalram_pages += free_all_bootmem_node(pgdat);
diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h
index 67e489d8d1bd..2df26b57c26a 100644
--- a/arch/m68k/include/asm/signal.h
+++ b/arch/m68k/include/asm/signal.h
@@ -41,7 +41,7 @@ struct k_sigaction {
 static inline void sigaddset(sigset_t *set, int _sig)
 {
         asm ("bfset %0{%1,#1}"
-                : "+od" (*set)
+                : "+o" (*set)
                 : "id" ((_sig - 1) ^ 31)
                 : "cc");
 }
@@ -49,7 +49,7 @@ static inline void sigaddset(sigset_t *set, int _sig)
 static inline void sigdelset(sigset_t *set, int _sig)
 {
         asm ("bfclr %0{%1,#1}"
-                : "+od" (*set)
+                : "+o" (*set)
                 : "id" ((_sig - 1) ^ 31)
                 : "cc");
 }
@@ -65,7 +65,7 @@ static inline int __gen_sigismember(sigset_t *set, int _sig)
         int ret;
         asm ("bfextu %1{%2,#1},%0"
                 : "=d" (ret)
-                : "od" (*set), "id" ((_sig-1) ^ 31)
+                : "o" (*set), "id" ((_sig-1) ^ 31)
                 : "cc");
         return ret;
 }
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1f495eb077d8..b7dc39c6c849 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -19,6 +19,7 @@ config MIPS
         select HAVE_KRETPROBES
         select HAVE_DEBUG_KMEMLEAK
         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -53,8 +54,8 @@ choice
 config MIPS_ALCHEMY
         bool "Alchemy processor based machines"
         select 64BIT_PHYS_ADDR
-        select CEVT_R4K_LIB
-        select CSRC_R4K_LIB
+        select CEVT_R4K
+        select CSRC_R4K
         select IRQ_CPU
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
@@ -109,12 +110,12 @@ config BCM47XX
         select CEVT_R4K
         select CSRC_R4K
         select DMA_NONCOHERENT
+        select FW_CFE
         select HW_HAS_PCI
         select IRQ_CPU
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
-        select CFE
         help
          Support for BCM47XX based boards
 
@@ -191,8 +192,8 @@ config MACH_DECSTATION
 
 config MACH_JAZZ
         bool "Jazz family of machines"
-        select ARC
-        select ARC32
+        select FW_ARC
+        select FW_ARC32
         select ARCH_MAY_HAVE_PC_FDC
         select CEVT_R4K
         select CSRC_R4K
@@ -415,27 +416,6 @@ config PMC_MSP
           of integrated peripherals, interfaces and DSPs in addition to
           a variety of MIPS cores.
 
-config PMC_YOSEMITE
-        bool "PMC-Sierra Yosemite eval board"
-        select CEVT_R4K
-        select CSRC_R4K
-        select DMA_COHERENT
-        select HW_HAS_PCI
-        select IRQ_CPU
-        select IRQ_CPU_RM7K
-        select IRQ_CPU_RM9K
-        select SWAP_IO_SPACE
-        select SYS_HAS_CPU_RM9000
-        select SYS_HAS_EARLY_PRINTK
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_64BIT_KERNEL
-        select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_HIGHMEM
-        select SYS_SUPPORTS_SMP
-        help
-          Yosemite is an evaluation board for the RM9000x2 processor
-          manufactured by PMC-Sierra.
-
 config POWERTV
         bool "Cisco PowerTV"
         select BOOT_ELF32
@@ -456,8 +436,8 @@ config POWERTV
 
 config SGI_IP22
         bool "SGI IP22 (Indy/Indigo2)"
-        select ARC
-        select ARC32
+        select FW_ARC
+        select FW_ARC32
         select BOOT_ELF32
         select CEVT_R4K
         select CSRC_R4K
@@ -496,8 +476,8 @@ config SGI_IP22
 
 config SGI_IP27
         bool "SGI IP27 (Origin200/2000)"
-        select ARC
-        select ARC64
+        select FW_ARC
+        select FW_ARC64
         select BOOT_ELF64
         select DEFAULT_SGI_PARTITION
         select DMA_COHERENT
@@ -517,8 +497,8 @@ config SGI_IP27
 config SGI_IP28
         bool "SGI IP28 (Indigo2 R10k) (EXPERIMENTAL)"
         depends on EXPERIMENTAL
-        select ARC
-        select ARC64
+        select FW_ARC
+        select FW_ARC64
         select BOOT_ELF64
         select CEVT_R4K
         select CSRC_R4K
@@ -553,8 +533,8 @@ config SGI_IP28
 
 config SGI_IP32
         bool "SGI IP32 (O2)"
-        select ARC
-        select ARC32
+        select FW_ARC
+        select FW_ARC32
         select BOOT_ELF32
         select CEVT_R4K
         select CSRC_R4K
@@ -672,8 +652,8 @@ config SIBYTE_BIGSUR
 
 config SNI_RM
         bool "SNI RM200/300/400"
-        select ARC if CPU_LITTLE_ENDIAN
-        select ARC32 if CPU_LITTLE_ENDIAN
+        select FW_ARC if CPU_LITTLE_ENDIAN
+        select FW_ARC32 if CPU_LITTLE_ENDIAN
         select SNIPROM if CPU_BIG_ENDIAN
         select ARCH_MAY_HAVE_PC_FDC
         select BOOT_ELF32
@@ -774,6 +754,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
         select DMA_COHERENT
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
+        select EDAC_SUPPORT
         select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_EARLY_PRINTK
         select SYS_HAS_CPU_CAVIUM_OCTEON
@@ -906,7 +887,7 @@ config SCHED_OMIT_FRAME_POINTER
 #
 # Select some configuration options automatically based on user selections.
 #
-config ARC
+config FW_ARC
         bool
 
 config ARCH_MAY_HAVE_PC_FDC
@@ -924,11 +905,7 @@ config CEVT_DS1287
 config CEVT_GT641XX
         bool
 
-config CEVT_R4K_LIB
-        bool
-
 config CEVT_R4K
-        select CEVT_R4K_LIB
         bool
 
 config CEVT_SB1250
@@ -946,11 +923,7 @@ config CSRC_IOASIC
 config CSRC_POWERTV
         bool
 
-config CSRC_R4K_LIB
-        bool
-
 config CSRC_R4K
-        select CSRC_R4K_LIB
         bool
 
 config CSRC_SB1250
@@ -961,7 +934,7 @@ config GPIO_TXX9
         select ARCH_REQUIRE_GPIOLIB
         bool
 
-config CFE
+config FW_CFE
         bool
 
 config ARCH_DMA_ADDR_T_64BIT
@@ -1077,15 +1050,15 @@ config SYS_SUPPORTS_HUGETLBFS
         depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
         default y
 
+config MIPS_HUGE_TLB_SUPPORT
+        def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
+
 config IRQ_CPU
         bool
 
 config IRQ_CPU_RM7K
         bool
 
-config IRQ_CPU_RM9K
-        bool
-
 config IRQ_MSP_SLP
         bool
 
@@ -1110,10 +1083,6 @@ config PCI_GT64XXX_PCI0
 config NO_EXCEPT_FILL
         bool
 
-config MIPS_RM9122
-        bool
-        select SERIAL_RM9000
-
 config SOC_EMMA2RH
         bool
         select CEVT_R4K
@@ -1159,9 +1128,6 @@ config SOC_PNX8550
 config SWAP_IO_SPACE
         bool
 
-config SERIAL_RM9000
-        bool
-
 config SGI_HAS_INDYDOG
         bool
 
@@ -1183,7 +1149,7 @@ config SGI_HAS_I8042
 config DEFAULT_SGI_PARTITION
         bool
 
-config ARC32
+config FW_ARC32
         bool
 
 config SNIPROM
@@ -1216,7 +1182,7 @@ config ARC_PROMLIB
         depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
         default y
 
-config ARC64
+config FW_ARC64
         bool
 
 config BOOT_ELF64
@@ -1368,6 +1334,7 @@ config CPU_R4X00
         depends on SYS_HAS_CPU_R4X00
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HUGEPAGES
         help
           MIPS Technologies R4000-series processors other than 4300, including
           the R4000, R4400, R4600, and 4700.
@@ -1378,12 +1345,14 @@ config CPU_TX49XX
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HUGEPAGES
 
 config CPU_R5000
         bool "R5000"
         depends on SYS_HAS_CPU_R5000
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HUGEPAGES
         help
           MIPS Technologies R5000-series processors other than the Nevada.
 
@@ -1392,6 +1361,7 @@ config CPU_R5432
         depends on SYS_HAS_CPU_R5432
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HUGEPAGES
 
 config CPU_R5500
         bool "R5500"
@@ -1417,6 +1387,7 @@ config CPU_NEVADA
         depends on SYS_HAS_CPU_NEVADA
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HUGEPAGES
         help
           QED / PMC-Sierra RM52xx-series ("Nevada") processors.
 
@@ -1437,6 +1408,7 @@ config CPU_R10000
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
         help
           MIPS Technologies R10000-series processors.
 
@@ -1447,15 +1419,7 @@ config CPU_RM7000
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
-
-config CPU_RM9000
-        bool "RM9000"
-        depends on SYS_HAS_CPU_RM9000
-        select CPU_HAS_PREFETCH
-        select CPU_SUPPORTS_32BIT_KERNEL
-        select CPU_SUPPORTS_64BIT_KERNEL
-        select CPU_SUPPORTS_HIGHMEM
-        select WEAK_ORDERING
+        select CPU_SUPPORTS_HUGEPAGES
 
 config CPU_SB1
         bool "SB1"
@@ -1463,6 +1427,7 @@ config CPU_SB1
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
         select WEAK_ORDERING
 
 config CPU_CAVIUM_OCTEON
@@ -1526,9 +1491,9 @@ config CPU_XLR
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
         select WEAK_ORDERING
         select WEAK_REORDERING_BEYOND_LLSC
-        select CPU_SUPPORTS_HUGEPAGES
         help
           Netlogic Microsystems XLR/XLS processors.
 
@@ -1590,6 +1555,7 @@ config CPU_LOONGSON2
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
 
 config CPU_LOONGSON1
         bool
@@ -1674,9 +1640,6 @@ config SYS_HAS_CPU_R10000
 config SYS_HAS_CPU_RM7000
         bool
 
-config SYS_HAS_CPU_RM9000
-        bool
-
 config SYS_HAS_CPU_SB1
         bool
 
@@ -2365,6 +2328,29 @@ config KEXEC
           support.  As of this writing the exact hardware interface is
           strongly in flux, so no good recommendation can be made.
 
+config CRASH_DUMP
+          bool "Kernel crash dumps"
+          help
+          Generate crash dump after being started by kexec.
+          This should be normally only set in special crash dump kernels
+          which are loaded in the main kernel with kexec-tools into
+          a specially reserved region and then later executed after
+          a crash by kdump/kexec. The crash dump kernel must be compiled
+          to a memory address not used by the main kernel or firmware using
+          PHYSICAL_START.
+
+config PHYSICAL_START
+          hex "Physical address where the kernel is loaded"
+          default "0xffffffff84000000" if 64BIT
+          default "0x84000000" if 32BIT
+          depends on CRASH_DUMP
+          help
+          This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
+          If you plan to use kernel for capturing the crash dump change
+          this value to start of the reserved region (the "X" value as
+          specified in the "crashkernel=YM@XM" command line boot parameter
+          passed to the panic-ed kernel).
+
 config SECCOMP
         bool "Enable seccomp to safely compute untrusted bytecode"
         depends on PROC_FS
@@ -2571,6 +2557,8 @@ source "net/Kconfig"
 
 source "drivers/Kconfig"
 
+source "drivers/firmware/Kconfig"
+
 source "fs/Kconfig"
 
 source "arch/mips/Kconfig.debug"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 654b1ad39f05..f2dfd404550c 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -145,8 +145,6 @@ cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=r5000) \
                         -Wa,--trap
 cflags-$(CONFIG_CPU_RM7000)     += $(call cc-option,-march=rm7000,-march=r5000) \
                         -Wa,--trap
-cflags-$(CONFIG_CPU_RM9000)     += $(call cc-option,-march=rm9000,-march=r5000) \
-                        -Wa,--trap
 cflags-$(CONFIG_CPU_SB1)        += $(call cc-option,-march=sb1,-march=r5000) \
                         -Wa,--trap
 cflags-$(CONFIG_CPU_R8000)      += -march=r8000 -Wa,--trap
@@ -173,9 +171,9 @@ endif
 #
 # Firmware support
 #
-libs-$(CONFIG_ARC)              += arch/mips/fw/arc/
-libs-$(CONFIG_CFE)              += arch/mips/fw/cfe/
-libs-$(CONFIG_SNIPROM)          += arch/mips/fw/sni/
+libs-$(CONFIG_FW_ARC)           += arch/mips/fw/arc/
+libs-$(CONFIG_FW_CFE)           += arch/mips/fw/cfe/
+libs-$(CONFIG_FW_SNIPROM)       += arch/mips/fw/sni/
 libs-y                          += arch/mips/fw/lib/
 
 #
@@ -192,6 +190,10 @@ endif
 #
 include $(srctree)/arch/mips/Kbuild.platforms
 
+ifdef CONFIG_PHYSICAL_START
+load-y                                  = $(CONFIG_PHYSICAL_START)
+endif
+
 cflags-y                        += -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)           += arch/mips/pci/
 
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 1bbc24b08685..7477fd2127ad 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -202,8 +202,11 @@ static struct resource physmap_flash_resource = {
         .end    = 0x107fffff,
 };
 
+static const char *ar7_probe_types[] = { "ar7part", NULL };
+
 static struct physmap_flash_data physmap_flash_data = {
         .width  = 2,
+        .part_probe_types = ar7_probe_types,
 };
 
 static struct platform_device physmap_flash = {
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index fdf5f19bfdb0..6d5ddbc112cc 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -688,3 +688,8 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
                 cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
         return addr_allocated;
 }
+
+struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void)
+{
+        return cvmx_bootmem_desc;
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index d38246e33ddb..9f883bf76953 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -30,6 +30,7 @@
  * measurement, and debugging facilities.
  */
 
+#include <linux/irqflags.h>
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-l2c.h>
 #include <asm/octeon/cvmx-spinlock.h>
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 02b15eed4bcd..46f5dbceeecc 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1266,7 +1266,6 @@ static void __init octeon_irq_init_ciu(void)
                 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
 
         octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
-        octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);
 
         /* CIU_1 */
         for (i = 0; i < 16; i++)
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
index db478dbb9c7b..0ba0eb96d9ac 100644
--- a/arch/mips/cavium-octeon/octeon-memcpy.S
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -79,11 +79,6 @@
 /*
  * Only on the 64-bit kernel we can made use of 64-bit registers.
  */
-#ifdef CONFIG_64BIT
-#define USE_DOUBLE
-#endif
-
-#ifdef USE_DOUBLE
 
 #define LOAD   ld
 #define LOADL  ldl
@@ -119,26 +114,6 @@
 #define t6      $14
 #define t7      $15
 
-#else
-
-#define LOAD   lw
-#define LOADL  lwl
-#define LOADR  lwr
-#define STOREL swl
-#define STORER swr
-#define STORE  sw
-#define ADD    addu
-#define SUB    subu
-#define SRL    srl
-#define SLL    sll
-#define SRA    sra
-#define SLLV   sllv
-#define SRLV   srlv
-#define NBYTES 4
-#define LOG_NBYTES 2
-
-#endif /* USE_DOUBLE */
-
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
 #define LDREST  LOADL
@@ -395,12 +370,10 @@ EXC(	 sb	t0, N(dst), s_exc_p1)
 
         COPY_BYTE(0)
         COPY_BYTE(1)
-#ifdef USE_DOUBLE
         COPY_BYTE(2)
         COPY_BYTE(3)
         COPY_BYTE(4)
         COPY_BYTE(5)
-#endif
 EXC(    lb      t0, NBYTES-2(src), l_exc)
         SUB     len, len, 1
         jr      ra
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 0938df10a71c..3c1b625a5859 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -24,108 +24,6 @@
 #include <asm/octeon/cvmx-helper.h>
 #include <asm/octeon/cvmx-helper-board.h>
 
-static struct octeon_cf_data octeon_cf_data;
-
-static int __init octeon_cf_device_init(void)
-{
-        union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
-        unsigned long base_ptr, region_base, region_size;
-        struct platform_device *pd;
-        struct resource cf_resources[3];
-        unsigned int num_resources;
-        int i;
-        int ret = 0;
-
-        /* Setup octeon-cf platform device if present. */
-        base_ptr = 0;
-        if (octeon_bootinfo->major_version == 1
-                && octeon_bootinfo->minor_version >= 1) {
-                if (octeon_bootinfo->compact_flash_common_base_addr)
-                        base_ptr =
-                                octeon_bootinfo->compact_flash_common_base_addr;
-        } else {
-                base_ptr = 0x1d000800;
-        }
-
-        if (!base_ptr)
-                return ret;
-
-        /* Find CS0 region. */
-        for (i = 0; i < 8; i++) {
-                mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
-                region_base = mio_boot_reg_cfg.s.base << 16;
-                region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
-                if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
-                    && base_ptr < region_base + region_size)
-                        break;
-        }
-        if (i >= 7) {
-                /* i and i + 1 are CS0 and CS1, both must be less than 8. */
-                goto out;
-        }
-        octeon_cf_data.base_region = i;
-        octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
-        octeon_cf_data.base_region_bias = base_ptr - region_base;
-        memset(cf_resources, 0, sizeof(cf_resources));
-        num_resources = 0;
-        cf_resources[num_resources].flags       = IORESOURCE_MEM;
-        cf_resources[num_resources].start       = region_base;
-        cf_resources[num_resources].end = region_base + region_size - 1;
-        num_resources++;
-
-
-        if (!(base_ptr & 0xfffful)) {
-                /*
-                 * Boot loader signals availability of DMA (true_ide
-                 * mode) by setting low order bits of base_ptr to
-                 * zero.
-                 */
-
-                /* Assume that CS1 immediately follows. */
-                mio_boot_reg_cfg.u64 =
-                        cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
-                region_base = mio_boot_reg_cfg.s.base << 16;
-                region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
-                if (!mio_boot_reg_cfg.s.en)
-                        goto out;
-
-                cf_resources[num_resources].flags       = IORESOURCE_MEM;
-                cf_resources[num_resources].start       = region_base;
-                cf_resources[num_resources].end = region_base + region_size - 1;
-                num_resources++;
-
-                octeon_cf_data.dma_engine = 0;
-                cf_resources[num_resources].flags       = IORESOURCE_IRQ;
-                cf_resources[num_resources].start       = OCTEON_IRQ_BOOTDMA;
-                cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
-                num_resources++;
-        } else {
-                octeon_cf_data.dma_engine = -1;
-        }
-
-        pd = platform_device_alloc("pata_octeon_cf", -1);
-        if (!pd) {
-                ret = -ENOMEM;
-                goto out;
-        }
-        pd->dev.platform_data = &octeon_cf_data;
-
-        ret = platform_device_add_resources(pd, cf_resources, num_resources);
-        if (ret)
-                goto fail;
-
-        ret = platform_device_add(pd);
-        if (ret)
-                goto fail;
-
-        return ret;
-fail:
-        platform_device_put(pd);
-out:
-        return ret;
-}
-device_initcall(octeon_cf_device_init);
-
 /* Octeon Random Number Generator.  */
 static int __init octeon_rng_device_init(void)
 {
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 04dd8ff0e0d8..d7e0a09f77c2 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -4,9 +4,11 @@
  * for more details.
  *
  * Copyright (C) 2004-2007 Cavium Networks
- * Copyright (C) 2008 Wind River Systems
+ * Copyright (C) 2008, 2009 Wind River Systems
+ *   written by Ralf Baechle <ralf@linux-mips.org>
  */
 #include <linux/init.h>
+#include <linux/kernel.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/export.h>
@@ -23,6 +25,7 @@
 #include <linux/serial_8250.h>
 #include <linux/of_fdt.h>
 #include <linux/libfdt.h>
+#include <linux/kexec.h>
 
 #include <asm/processor.h>
 #include <asm/reboot.h>
@@ -56,11 +59,208 @@ struct octeon_boot_descriptor *octeon_boot_desc_ptr;
 struct cvmx_bootinfo *octeon_bootinfo;
 EXPORT_SYMBOL(octeon_bootinfo);
 
+static unsigned long long RESERVE_LOW_MEM = 0ull;
+#ifdef CONFIG_KEXEC
+#ifdef CONFIG_SMP
+/*
+ * Wait for relocation code is prepared and send
+ * secondary CPUs to spin until kernel is relocated.
+ */
+static void octeon_kexec_smp_down(void *ignored)
+{
+        int cpu = smp_processor_id();
+
+        local_irq_disable();
+        set_cpu_online(cpu, false);
+        while (!atomic_read(&kexec_ready_to_reboot))
+                cpu_relax();
+
+        asm volatile (
+        "       sync                                            \n"
+        "       synci   ($0)                                    \n");
+
+        relocated_kexec_smp_wait(NULL);
+}
+#endif
+
+#define OCTEON_DDR0_BASE    (0x0ULL)
+#define OCTEON_DDR0_SIZE    (0x010000000ULL)
+#define OCTEON_DDR1_BASE    (0x410000000ULL)
+#define OCTEON_DDR1_SIZE    (0x010000000ULL)
+#define OCTEON_DDR2_BASE    (0x020000000ULL)
+#define OCTEON_DDR2_SIZE    (0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
+
+static struct kimage *kimage_ptr;
+
+static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
+{
+        int64_t addr;
+        struct cvmx_bootmem_desc *bootmem_desc;
+
+        bootmem_desc = cvmx_bootmem_get_desc();
+
+        if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
+                mem_size = OCTEON_MAX_PHY_MEM_SIZE;
+                pr_err("Error: requested memory too large,"
+                       "truncating to maximum size\n");
+        }
+
+        bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
+        bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
+
+        addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
+        bootmem_desc->head_addr = 0;
+
+        if (mem_size <= OCTEON_DDR0_SIZE) {
+                __cvmx_bootmem_phy_free(addr,
+                                mem_size - RESERVE_LOW_MEM -
+                                low_reserved_bytes, 0);
+                return;
+        }
+
+        __cvmx_bootmem_phy_free(addr,
+                        OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
+                        low_reserved_bytes, 0);
+
+        mem_size -= OCTEON_DDR0_SIZE;
+
+        if (mem_size > OCTEON_DDR1_SIZE) {
+                __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
+                __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
+                                mem_size - OCTEON_DDR1_SIZE, 0);
+        } else
+                __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
+}
+
+static int octeon_kexec_prepare(struct kimage *image)
+{
+        int i;
+        char *bootloader = "kexec";
+
+        octeon_boot_desc_ptr->argc = 0;
+        for (i = 0; i < image->nr_segments; i++) {
+                if (!strncmp(bootloader, (char *)image->segment[i].buf,
+                                strlen(bootloader))) {
+                        /*
+                         * convert command line string to array
+                         * of parameters (as bootloader does).
+                         */
+                        int argc = 0, offt;
+                        char *str = (char *)image->segment[i].buf;
+                        char *ptr = strchr(str, ' ');
+                        while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
+                                *ptr = '\0';
+                                if (ptr[1] != ' ') {
+                                        offt = (int)(ptr - str + 1);
+                                        octeon_boot_desc_ptr->argv[argc] =
+                                                image->segment[i].mem + offt;
+                                        argc++;
+                                }
+                                ptr = strchr(ptr + 1, ' ');
+                        }
+                        octeon_boot_desc_ptr->argc = argc;
+                        break;
+                }
+        }
+
+        /*
+         * Information about segments will be needed during pre-boot memory
+         * initialization.
+         */
+        kimage_ptr = image;
+        return 0;
+}
+
+static void octeon_generic_shutdown(void)
+{
+        int cpu, i;
+        struct cvmx_bootmem_desc *bootmem_desc;
+        void *named_block_array_ptr;
+
+        bootmem_desc = cvmx_bootmem_get_desc();
+        named_block_array_ptr =
+                cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
+
+#ifdef CONFIG_SMP
+        /* disable watchdogs */
+        for_each_online_cpu(cpu)
+                cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
+#else
+        cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
+#endif
+        if (kimage_ptr != kexec_crash_image) {
+                memset(named_block_array_ptr,
+                        0x0,
+                        CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
+                        sizeof(struct cvmx_bootmem_named_block_desc));
+                /*
+                 * Mark all memory (except low 0x100000 bytes) as free.
+                 * It is the same thing that bootloader does.
+                 */
+                kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
+                                0x100000);
+                /*
+                 * Allocate all segments to avoid their corruption during boot.
+                 */
+                for (i = 0; i < kimage_ptr->nr_segments; i++)
+                        cvmx_bootmem_alloc_address(
+                                kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
+                                kimage_ptr->segment[i].mem - PAGE_SIZE,
+                                PAGE_SIZE);
+        } else {
+                /*
+                 * Do not mark all memory as free. Free only named sections
+                 * leaving the rest of memory unchanged.
+                 */
+                struct cvmx_bootmem_named_block_desc *ptr =
+                        (struct cvmx_bootmem_named_block_desc *)
+                        named_block_array_ptr;
+
+                for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
+                        if (ptr[i].size)
+                                cvmx_bootmem_free_named(ptr[i].name);
+        }
+        kexec_args[2] = 1UL; /* running on octeon_main_processor */
+        kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
+#ifdef CONFIG_SMP
+        secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
+        secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
+#endif
+}
+
+static void octeon_shutdown(void)
+{
+        octeon_generic_shutdown();
+#ifdef CONFIG_SMP
+        smp_call_function(octeon_kexec_smp_down, NULL, 0);
+        smp_wmb();
+        while (num_online_cpus() > 1) {
+                cpu_relax();
+                mdelay(1);
+        }
+#endif
+}
+
+static void octeon_crash_shutdown(struct pt_regs *regs)
+{
+        octeon_generic_shutdown();
+        default_machine_crash_shutdown(regs);
+}
+
+#endif /* CONFIG_KEXEC */
+
 #ifdef CONFIG_CAVIUM_RESERVE32
 uint64_t octeon_reserve32_memory;
 EXPORT_SYMBOL(octeon_reserve32_memory);
 #endif
 
+#ifdef CONFIG_KEXEC
+/* crashkernel cmdline parameter is parsed _after_ memory setup
+ * we also parse it here (workaround for EHB5200) */
+static uint64_t crashk_size, crashk_base;
+#endif
+
 static int octeon_uart;
 
 extern asmlinkage void handle_int(void);
@@ -415,6 +615,8 @@ void octeon_user_io_init(void)
 void __init prom_init(void)
 {
         struct cvmx_sysinfo *sysinfo;
+        const char *arg;
+        char *p;
         int i;
         int argc;
 #ifdef CONFIG_CAVIUM_RESERVE32
@@ -566,6 +768,15 @@ void __init prom_init(void)
         if (octeon_is_simulation())
                 MAX_MEMORY = 64ull << 20;
 
+        arg = strstr(arcs_cmdline, "mem=");
+        if (arg) {
+                MAX_MEMORY = memparse(arg + 4, &p);
+                if (MAX_MEMORY == 0)
+                        MAX_MEMORY = 32ull << 30;
+                if (*p == '@')
+                        RESERVE_LOW_MEM = memparse(p + 1, &p);
+        }
+
         arcs_cmdline[0] = 0;
         argc = octeon_boot_desc_ptr->argc;
         for (i = 0; i < argc; i++) {
@@ -573,16 +784,30 @@ void __init prom_init(void)
                         cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
                 if ((strncmp(arg, "MEM=", 4) == 0) ||
                     (strncmp(arg, "mem=", 4) == 0)) {
-                        sscanf(arg + 4, "%llu", &MAX_MEMORY);
-                        MAX_MEMORY <<= 20;
+                        MAX_MEMORY = memparse(arg + 4, &p);
                         if (MAX_MEMORY == 0)
                                 MAX_MEMORY = 32ull << 30;
+                        if (*p == '@')
+                                RESERVE_LOW_MEM = memparse(p + 1, &p);
                 } else if (strcmp(arg, "ecc_verbose") == 0) {
 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
                         __cvmx_interrupt_ecc_report_single_bit_errors = 1;
                         pr_notice("Reporting of single bit ECC errors is "
                                   "turned on\n");
 #endif
+#ifdef CONFIG_KEXEC
+                } else if (strncmp(arg, "crashkernel=", 12) == 0) {
+                        crashk_size = memparse(arg+12, &p);
+                        if (*p == '@')
+                                crashk_base = memparse(p+1, &p);
+                        strcat(arcs_cmdline, " ");
+                        strcat(arcs_cmdline, arg);
+                        /*
+                         * To do: switch parsing to new style, something like:
+                         * parse_crashkernel(arg, sysinfo->system_dram_size,
+                         *                &crashk_size, &crashk_base);
+                         */
+#endif
                 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
                            sizeof(arcs_cmdline) - 1) {
                         strcat(arcs_cmdline, " ");
@@ -617,11 +842,18 @@ void __init prom_init(void)
         _machine_restart = octeon_restart;
         _machine_halt = octeon_halt;
 
+#ifdef CONFIG_KEXEC
+        _machine_kexec_shutdown = octeon_shutdown;
+        _machine_crash_shutdown = octeon_crash_shutdown;
+        _machine_kexec_prepare = octeon_kexec_prepare;
+#endif
+
         octeon_user_io_init();
         register_smp_ops(&octeon_smp_ops);
 }
 
 /* Exclude a single page from the regions obtained in plat_mem_setup. */
+#ifndef CONFIG_CRASH_DUMP
 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
 {
         if (addr > *mem && addr < *mem + *size) {
@@ -636,14 +868,21 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
                 *size -= PAGE_SIZE;
         }
 }
+#endif /* CONFIG_CRASH_DUMP */
 
 void __init plat_mem_setup(void)
 {
         uint64_t mem_alloc_size;
         uint64_t total;
+        uint64_t crashk_end;
+#ifndef CONFIG_CRASH_DUMP
         int64_t memory;
+        uint64_t kernel_start;
+        uint64_t kernel_size;
+#endif
 
         total = 0;
+        crashk_end = 0;
 
         /*
          * The Mips memory init uses the first memory location for
@@ -656,6 +895,17 @@ void __init plat_mem_setup(void)
         if (mem_alloc_size > MAX_MEMORY)
                 mem_alloc_size = MAX_MEMORY;
 
+/* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
+#ifdef CONFIG_CRASH_DUMP
+        add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
+        total += MAX_MEMORY;
+#else
+#ifdef CONFIG_KEXEC
+        if (crashk_size > 0) {
+                add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
+                crashk_end = crashk_base + crashk_size;
+        }
+#endif
         /*
          * When allocating memory, we want incrementing addresses from
          * bootmem_alloc so the code in add_memory_region can merge
@@ -664,22 +914,15 @@ void __init plat_mem_setup(void)
         cvmx_bootmem_lock();
         while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
                 && (total < MAX_MEMORY)) {
-#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
                 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
                                                 __pa_symbol(&__init_end), -1,
                                                 0x100000,
                                                 CVMX_BOOTMEM_FLAG_NO_LOCKING);
-#elif defined(CONFIG_HIGHMEM)
-                memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
-                                                0x100000,
-                                                CVMX_BOOTMEM_FLAG_NO_LOCKING);
-#else
-                memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
-                                                0x100000,
-                                                CVMX_BOOTMEM_FLAG_NO_LOCKING);
-#endif
                 if (memory >= 0) {
                         u64 size = mem_alloc_size;
+#ifdef CONFIG_KEXEC
+                        uint64_t end;
+#endif
 
                         /*
                          * exclude a page at the beginning and end of
@@ -692,20 +935,67 @@ void __init plat_mem_setup(void)
                         memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
                                             CVMX_PCIE_BAR1_PHYS_SIZE,
                                             &memory, &size);
+#ifdef CONFIG_KEXEC
+                        end = memory + mem_alloc_size;
 
                         /*
-                         * This function automatically merges address
-                         * regions next to each other if they are
-                         * received in incrementing order.
+                         * This function automatically merges address regions
+                         * next to each other if they are received in
+                         * incrementing order
                          */
-                        if (size)
-                                add_memory_region(memory, size, BOOT_MEM_RAM);
+                        if (memory < crashk_base && end >  crashk_end) {
+                                /* region is fully in */
+                                add_memory_region(memory,
+                                                  crashk_base - memory,
+                                                  BOOT_MEM_RAM);
+                                total += crashk_base - memory;
+                                add_memory_region(crashk_end,
+                                                  end - crashk_end,
+                                                  BOOT_MEM_RAM);
+                                total += end - crashk_end;
+                                continue;
+                        }
+
+                        if (memory >= crashk_base && end <= crashk_end)
+                                /*
+                                 * Entire memory region is within the new
+                                 *  kernel's memory, ignore it.
+                                 */
+                                continue;
+
+                        if (memory > crashk_base && memory < crashk_end &&
+                            end > crashk_end) {
+                                /*
+                                 * Overlap with the beginning of the region,
+                                 * reserve the beginning.
+                                  */
+                                mem_alloc_size -= crashk_end - memory;
+                                memory = crashk_end;
+                        } else if (memory < crashk_base && end > crashk_base &&
+                                   end < crashk_end)
+                                /*
+                                 * Overlap with the beginning of the region,
+                                 * chop of end.
+                                 */
+                                mem_alloc_size -= end - crashk_base;
+#endif
+                        add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
                         total += mem_alloc_size;
+                        /* Recovering mem_alloc_size */
+                        mem_alloc_size = 4 << 20;
                 } else {
                         break;
                 }
         }
         cvmx_bootmem_unlock();
+        /* Add the memory region for the kernel. */
+        kernel_start = (unsigned long) _text;
+        kernel_size = ALIGN(_end - _text, 0x100000);
+
+        /* Adjust for physical offset. */
+        kernel_start &= ~0xffffffff80000000ULL;
+        add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
+#endif /* CONFIG_CRASH_DUMP */
 
 #ifdef CONFIG_CAVIUM_RESERVE32
         /*
@@ -821,3 +1111,51 @@ void __init device_tree_init(void)
         }
         unflatten_device_tree();
 }
+
+static int __initdata disable_octeon_edac_p;
+
+static int __init disable_octeon_edac(char *str)
+{
+        disable_octeon_edac_p = 1;
+        return 0;
+}
+early_param("disable_octeon_edac", disable_octeon_edac);
+
+static char *edac_device_names[] = {
+        "octeon_l2c_edac",
+        "octeon_pc_edac",
+};
+
+static int __init edac_devinit(void)
+{
+        struct platform_device *dev;
+        int i, err = 0;
+        int num_lmc;
+        char *name;
+
+        if (disable_octeon_edac_p)
+                return 0;
+
+        for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
+                name = edac_device_names[i];
+                dev = platform_device_register_simple(name, -1, NULL, 0);
+                if (IS_ERR(dev)) {
+                        pr_err("Registation of %s failed!\n", name);
+                        err = PTR_ERR(dev);
+                }
+        }
+
+        num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
+                (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
+        for (i = 0; i < num_lmc; i++) {
+                dev = platform_device_register_simple("octeon_lmc_edac",
+                                                      i, NULL, 0);
+                if (IS_ERR(dev)) {
+                        pr_err("Registation of octeon_lmc_edac %d failed!\n", i);
+                        err = PTR_ERR(dev);
+                }
+        }
+
+        return err;
+}
+device_initcall(edac_devinit);
diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig
index 75165dfa60c1..014ba4bbba7d 100644
--- a/arch/mips/configs/cavium_octeon_defconfig
+++ b/arch/mips/configs/cavium_octeon_defconfig
@@ -1,7 +1,11 @@
 CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
+CONFIG_CAVIUM_CN63XXP1=y
 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
 CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=32
+CONFIG_HZ_100=y
 CONFIG_PREEMPT=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
@@ -11,16 +15,15 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
 CONFIG_MIPS32_COMPAT=y
 CONFIG_MIPS32_O32=y
 CONFIG_MIPS32_N32=y
@@ -42,22 +45,68 @@ CONFIG_IP_PIMSM_V1=y
 CONFIG_IP_PIMSM_V2=y
 CONFIG_SYN_COOKIES=y
 # CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_OF_PARTS is not set
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SLRAM=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_PATA_OCTEON_CF=y
+CONFIG_SATA_SIL=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_BCM87XX_PHY=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
@@ -66,24 +115,39 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=2
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_OCTEON=y
+CONFIG_SPI=y
+CONFIG_SPI_OCTEON=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_STAGING=y
+CONFIG_OCTEON_ETHERNET=y
+# CONFIG_NET_VENDOR_SILICOM is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS=y
+CONFIG_HUGETLBFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_SCHED_DEBUG is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_EARLY_PRINTK is not set
 CONFIG_SECURITY=y
 CONFIG_SECURITY_NETWORK=y
 CONFIG_CRYPTO_CBC=y
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
deleted file mode 100644
index f72d305a3f08..000000000000
--- a/arch/mips/configs/yosemite_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_PMC_YOSEMITE=y
-CONFIG_HIGHMEM=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_HZ_1000=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PCI=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_FW_LOADER=m
-CONFIG_CONNECTOR=m
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_ATA_OVER_ETH=m
-CONFIG_SGI_IOC4=m
-CONFIG_RAID_ATTRS=m
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=m
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_QLA3XXX=m
-CONFIG_CHELSIO_T3=m
-CONFIG_NETXEN_NIC=m
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_FUSE_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
-CONFIG_CRC32=m
-CONFIG_LIBCRC32C=m
diff --git a/arch/mips/fw/arc/misc.c b/arch/mips/fw/arc/misc.c
index 7cf80ca2c1d2..f9f5307434c2 100644
--- a/arch/mips/fw/arc/misc.c
+++ b/arch/mips/fw/arc/misc.c
@@ -11,6 +11,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/irqflags.h>
 
 #include <asm/bcache.h>
 
diff --git a/arch/mips/fw/sni/Makefile b/arch/mips/fw/sni/Makefile
index d9740a3788e2..3f01dd36e6b7 100644
--- a/arch/mips/fw/sni/Makefile
+++ b/arch/mips/fw/sni/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the SNI prom monitor routines under Linux.
 #
 
-lib-$(CONFIG_SNIPROM)   += sniprom.o
+lib-$(CONFIG_FW_SNIPROM)        += sniprom.o
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 82ad35ce2b45..46ac73abd5ee 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -14,7 +14,6 @@
 #endif
 
 #include <linux/compiler.h>
-#include <linux/irqflags.h>
 #include <linux/types.h>
 #include <asm/barrier.h>
 #include <asm/byteorder.h>              /* sigh ... */
@@ -44,6 +43,24 @@
 #define smp_mb__before_clear_bit()      smp_mb__before_llsc()
 #define smp_mb__after_clear_bit()       smp_llsc_mb()
 
+
+/*
+ * These are the "slower" versions of the functions and are in bitops.c.
+ * These functions call raw_local_irq_{save,restore}().
+ */
+void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
+void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
+void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
+int __mips_test_and_set_bit(unsigned long nr,
+                            volatile unsigned long *addr);
+int __mips_test_and_set_bit_lock(unsigned long nr,
+                                 volatile unsigned long *addr);
+int __mips_test_and_clear_bit(unsigned long nr,
+                              volatile unsigned long *addr);
+int __mips_test_and_change_bit(unsigned long nr,
+                               volatile unsigned long *addr);
+
+
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
@@ -57,7 +74,7 @@
 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 {
         unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
         unsigned long temp;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                         : "=&r" (temp), "+m" (*m)
                         : "ir" (1UL << bit));
                 } while (unlikely(!temp));
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                *a |= mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                __mips_set_bit(nr, addr);
 }
 
 /*
@@ -118,7 +126,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
         unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
         unsigned long temp;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                         : "=&r" (temp), "+m" (*m)
                         : "ir" (~(1UL << bit)));
                 } while (unlikely(!temp));
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                *a &= ~mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                __mips_clear_bit(nr, addr);
 }
 
 /*
@@ -191,7 +190,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad
  */
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                         : "=&r" (temp), "+m" (*m)
                         : "ir" (1UL << bit));
                 } while (unlikely(!temp));
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                *a ^= mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                __mips_change_bit(nr, addr);
 }
 
 /*
@@ -244,7 +234,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 static inline int test_and_set_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
         unsigned long res;
 
         smp_mb__before_llsc();
@@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a |= mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                res = __mips_test_and_set_bit(nr, addr);
 
         smp_llsc_mb();
 
@@ -310,7 +290,7 @@ static inline int test_and_set_bit(unsigned long nr,
 static inline int test_and_set_bit_lock(unsigned long nr,
         volatile unsigned long *addr)
 {
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
         unsigned long res;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a |= mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                res = __mips_test_and_set_bit_lock(nr, addr);
 
         smp_llsc_mb();
 
@@ -373,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
 static inline int test_and_clear_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
         unsigned long res;
 
         smp_mb__before_llsc();
@@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a &= ~mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                res = __mips_test_and_clear_bit(nr, addr);
 
         smp_llsc_mb();
 
@@ -457,7 +417,7 @@ static inline int test_and_clear_bit(unsigned long nr,
 static inline int test_and_change_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
-        unsigned short bit = nr & SZLONG_MASK;
+        int bit = nr & SZLONG_MASK;
         unsigned long res;
 
         smp_mb__before_llsc();
@@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a ^= mask;
-                raw_local_irq_restore(flags);
-        }
+        } else
+                res = __mips_test_and_change_bit(nr, addr);
 
         smp_llsc_mb();
 
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 58277e0e9cd4..3c5d1464b7bd 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -290,7 +290,7 @@ struct compat_shmid64_ds {
 
 static inline int is_compat_task(void)
 {
-        return test_thread_flag(TIF_32BIT);
+        return test_thread_flag(TIF_32BIT_ADDR);
 }
 
 #endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 52c4e914f95a..90112adb1940 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -243,9 +243,9 @@ enum cpu_type_enum {
          */
         CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
         CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
-        CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
-        CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
-        CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+        CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
+        CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
+        CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
         CPU_SR71000, CPU_RM9000, CPU_TX49XX,
 
         /*
diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
index b9adcd6f0860..2b11f87d6fb3 100644
--- a/arch/mips/include/asm/fw/arc/types.h
+++ b/arch/mips/include/asm/fw/arc/types.h
@@ -10,7 +10,7 @@
 #define _ASM_ARC_TYPES_H
 
 
-#ifdef CONFIG_ARC32
+#ifdef CONFIG_FW_ARC32
 
 typedef char            CHAR;
 typedef short           SHORT;
@@ -33,9 +33,9 @@ typedef LONG		_PUSHORT;
 typedef LONG            _PULONG;
 typedef LONG            _PVOID;
 
-#endif /* CONFIG_ARC32 */
+#endif /* CONFIG_FW_ARC32 */
 
-#ifdef CONFIG_ARC64
+#ifdef CONFIG_FW_ARC64
 
 typedef char            CHAR;
 typedef short           SHORT;
@@ -57,7 +57,7 @@ typedef USHORT		*_PUSHORT;
 typedef ULONG           *_PULONG;
 typedef VOID            *_PVOID;
 
-#endif /* CONFIG_ARC64  */
+#endif /* CONFIG_FW_ARC64  */
 
 typedef CHAR            *PCHAR;
 typedef SHORT           *PSHORT;
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index b4c20e4f87cd..f0324e92d089 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -161,31 +161,6 @@ ASMMACRO(back_to_back_c0_hazard,
         )
 #define instruction_hazard() do { } while (0)
 
-#elif defined(CONFIG_CPU_RM9000)
-
-/*
- * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-
-ASMMACRO(mtc0_tlbw_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(tlbw_use_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(tlb_probe_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(irq_enable_hazard,
-        )
-ASMMACRO(irq_disable_hazard,
-        )
-ASMMACRO(back_to_back_c0_hazard,
-        )
-#define instruction_hazard() do { } while (0)
-
 #elif defined(CONFIG_CPU_SB1)
 
 /*
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 29d9c23c20c7..ff2e0345e013 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -15,6 +15,7 @@
 #include <linux/compiler.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/irqflags.h>
 
 #include <asm/addrspace.h>
 #include <asm/bug.h>
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 309cbcd6909c..9f3384c789d7 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -16,83 +16,13 @@
 #include <linux/compiler.h>
 #include <asm/hazards.h>
 
-__asm__(
-        "       .macro  arch_local_irq_enable                           \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-        "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    $1, $2, 1       # SMTC - clear TCStatus.IXMT    \n"
-        "       ori     $1, 0x400                                       \n"
-        "       xori    $1, 0x400                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
-        "       ei                                                      \n"
-#else
-        "       mfc0    $1,$12                                          \n"
-        "       ori     $1,0x1f                                         \n"
-        "       xori    $1,0x1e                                         \n"
-        "       mtc0    $1,$12                                          \n"
-#endif
-        "       irq_enable_hazard                                       \n"
-        "       .set    pop                                             \n"
-        "       .endm");
+#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
 
-extern void smtc_ipi_replay(void);
-
-static inline void arch_local_irq_enable(void)
-{
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         * SMTC kernel needs to do a software replay of queued
-         * IPIs, at the cost of call overhead on each local_irq_enable()
-         */
-        smtc_ipi_replay();
-#endif
-        __asm__ __volatile__(
-                "arch_local_irq_enable"
-                : /* no outputs */
-                : /* no inputs */
-                : "memory");
-}
-
-
-/*
- * For cli() we have to insert nops to make sure that the new value
- * has actually arrived in the status register before the end of this
- * macro.
- * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
- * no nops at all.
- */
-/*
- * For TX49, operating only IE bit is not enough.
- *
- * If mfc0 $12 follows store and the mfc0 is last instruction of a
- * page and fetching the next instruction causes TLB miss, the result
- * of the mfc0 might wrongly contain EXL bit.
- *
- * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
- *
- * Workaround: mask EXL bit of the result or place a nop before mfc0.
- */
 __asm__(
         "       .macro  arch_local_irq_disable\n"
         "       .set    push                                            \n"
         "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    $1, $2, 1                                       \n"
-        "       ori     $1, 0x400                                       \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
         "       di                                                      \n"
-#else
-        "       mfc0    $1,$12                                          \n"
-        "       ori     $1,0x1f                                         \n"
-        "       xori    $1,0x1f                                         \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1,$12                                          \n"
-#endif
         "       irq_disable_hazard                                      \n"
         "       .set    pop                                             \n"
         "       .endm                                                   \n");
@@ -106,46 +36,14 @@ static inline void arch_local_irq_disable(void)
                 : "memory");
 }
 
-__asm__(
-        "       .macro  arch_local_save_flags flags                     \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    \\flags, $2, 1                                  \n"
-#else
-        "       mfc0    \\flags, $12                                    \n"
-#endif
-        "       .set    pop                                             \n"
-        "       .endm                                                   \n");
-
-static inline unsigned long arch_local_save_flags(void)
-{
-        unsigned long flags;
-        asm volatile("arch_local_save_flags %0" : "=r" (flags));
-        return flags;
-}
 
 __asm__(
         "       .macro  arch_local_irq_save result                      \n"
         "       .set    push                                            \n"
         "       .set    reorder                                         \n"
         "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    \\result, $2, 1                                 \n"
-        "       ori     $1, \\result, 0x400                             \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-        "       andi    \\result, \\result, 0x400                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
         "       di      \\result                                        \n"
         "       andi    \\result, 1                                     \n"
-#else
-        "       mfc0    \\result, $12                                   \n"
-        "       ori     $1, \\result, 0x1f                              \n"
-        "       xori    $1, 0x1f                                        \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1, $12                                         \n"
-#endif
         "       irq_disable_hazard                                      \n"
         "       .set    pop                                             \n"
         "       .endm                                                   \n");
@@ -160,61 +58,37 @@ static inline unsigned long arch_local_irq_save(void)
         return flags;
 }
 
+
 __asm__(
         "       .macro  arch_local_irq_restore flags                    \n"
         "       .set    push                                            \n"
         "       .set    noreorder                                       \n"
         "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "mfc0   $1, $2, 1                                               \n"
-        "andi   \\flags, 0x400                                          \n"
-        "ori    $1, 0x400                                               \n"
-        "xori   $1, 0x400                                               \n"
-        "or     \\flags, $1                                             \n"
-        "mtc0   \\flags, $2, 1                                          \n"
-#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+#if defined(CONFIG_IRQ_CPU)
         /*
          * Slow, but doesn't suffer from a relatively unlikely race
          * condition we're having since days 1.
          */
         "       beqz    \\flags, 1f                                     \n"
-        "        di                                                     \n"
+        "       di                                                      \n"
         "       ei                                                      \n"
         "1:                                                             \n"
-#elif defined(CONFIG_CPU_MIPSR2)
+#else
         /*
          * Fast, dangerous.  Life is fun, life is good.
          */
         "       mfc0    $1, $12                                         \n"
         "       ins     $1, \\flags, 0, 1                               \n"
         "       mtc0    $1, $12                                         \n"
-#else
-        "       mfc0    $1, $12                                         \n"
-        "       andi    \\flags, 1                                      \n"
-        "       ori     $1, 0x1f                                        \n"
-        "       xori    $1, 0x1f                                        \n"
-        "       or      \\flags, $1                                     \n"
-        "       mtc0    \\flags, $12                                    \n"
 #endif
         "       irq_disable_hazard                                      \n"
         "       .set    pop                                             \n"
         "       .endm                                                   \n");
 
-
 static inline void arch_local_irq_restore(unsigned long flags)
 {
         unsigned long __tmp1;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         * SMTC kernel needs to do a software replay of queued
-         * IPIs, at the cost of branch and call overhead on each
-         * local_irq_restore()
-         */
-        if (unlikely(!(flags & 0x0400)))
-                smtc_ipi_replay();
-#endif
-
         __asm__ __volatile__(
                 "arch_local_irq_restore\t%0"
                 : "=r" (__tmp1)
@@ -232,6 +106,75 @@ static inline void __arch_local_irq_restore(unsigned long flags)
                 : "0" (flags)
                 : "memory");
 }
+#else
+/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
+void arch_local_irq_disable(void);
+unsigned long arch_local_irq_save(void);
+void arch_local_irq_restore(unsigned long flags);
+void __arch_local_irq_restore(unsigned long flags);
+#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
+
+
+__asm__(
+        "       .macro  arch_local_irq_enable                           \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    $1, $2, 1       # SMTC - clear TCStatus.IXMT    \n"
+        "       ori     $1, 0x400                                       \n"
+        "       xori    $1, 0x400                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        "       ei                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1e                                         \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_enable_hazard                                       \n"
+        "       .set    pop                                             \n"
+        "       .endm");
+
+extern void smtc_ipi_replay(void);
+
+static inline void arch_local_irq_enable(void)
+{
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC kernel needs to do a software replay of queued
+         * IPIs, at the cost of call overhead on each local_irq_enable()
+         */
+        smtc_ipi_replay();
+#endif
+        __asm__ __volatile__(
+                "arch_local_irq_enable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+}
+
+
+__asm__(
+        "       .macro  arch_local_save_flags flags                     \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    \\flags, $2, 1                                  \n"
+#else
+        "       mfc0    \\flags, $12                                    \n"
+#endif
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+static inline unsigned long arch_local_save_flags(void)
+{
+        unsigned long flags;
+        asm volatile("arch_local_save_flags %0" : "=r" (flags));
+        return flags;
+}
+
 
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
@@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
 #endif
 }
 
-#endif
+#endif /* #ifndef __ASSEMBLY__ */
 
 /*
  * Do the CPU's IRQ-state tracing from assembly code.
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
index 4314892aaebb..ee25ebbf2a28 100644
--- a/arch/mips/include/asm/kexec.h
+++ b/arch/mips/include/asm/kexec.h
@@ -9,22 +9,43 @@
 #ifndef _MIPS_KEXEC
 # define _MIPS_KEXEC
 
+#include <asm/stacktrace.h>
+
 /* Maximum physical address we can use pages from */
 #define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
 /* Maximum address we can reach in physical address mode */
 #define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
  /* Maximum address we can use for the control code buffer */
 #define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
-
-#define KEXEC_CONTROL_PAGE_SIZE 4096
+/* Reserve 3*4096 bytes for board-specific info */
+#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096)
 
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_MIPS
+#define MAX_NOTE_BYTES 1024
 
 static inline void crash_setup_regs(struct pt_regs *newregs,
                                     struct pt_regs *oldregs)
 {
-        /* Dummy implementation for now */
+        if (oldregs)
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        else
+                prepare_frametrace(newregs);
 }
 
+#ifdef CONFIG_KEXEC
+struct kimage;
+extern unsigned long kexec_args[4];
+extern int (*_machine_kexec_prepare)(struct kimage *);
+extern void (*_machine_kexec_shutdown)(void);
+extern void (*_machine_crash_shutdown)(struct pt_regs *regs);
+extern void default_machine_crash_shutdown(struct pt_regs *regs);
+#ifdef CONFIG_SMP
+extern const unsigned char kexec_smp_wait[];
+extern unsigned long secondary_kexec_args[4];
+extern void (*relocated_kexec_smp_wait) (void *);
+extern atomic_t kexec_ready_to_reboot;
+#endif
+#endif
+
 #endif /* !_MIPS_KEXEC */
diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h
index f4862b563080..99071e50faab 100644
--- a/arch/mips/include/asm/mach-ar7/war.h
+++ b/arch/mips/include/asm/mach-ar7/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
index 323d9f1d8c45..0bb30905fd5b 100644
--- a/arch/mips/include/asm/mach-ath79/war.h
+++ b/arch/mips/include/asm/mach-ath79/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
index dd57d03d68ba..72e260d24e59 100644
--- a/arch/mips/include/asm/mach-au1x00/war.h
+++ b/arch/mips/include/asm/mach-au1x00/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
index 87cd4651dda3..a3d2f448b10e 100644
--- a/arch/mips/include/asm/mach-bcm47xx/war.h
+++ b/arch/mips/include/asm/mach-bcm47xx/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
index 8e3f3fdf3209..05ee8671bef1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index ff0d4909d848..502bb1815ae8 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -42,7 +42,6 @@ enum octeon_irq {
         OCTEON_IRQ_TIMER3,
         OCTEON_IRQ_USB0,
         OCTEON_IRQ_USB1,
-        OCTEON_IRQ_BOOTDMA,
 #ifndef CONFIG_PCI_MSI
         OCTEON_IRQ_LAST = 127
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index c4712d7cc81d..eb72b35cf04b 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -18,7 +18,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
index 97884fd18ac0..34ae4046541e 100644
--- a/arch/mips/include/asm/mach-cobalt/war.h
+++ b/arch/mips/include/asm/mach-cobalt/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
index ca5e2ef909ad..d29996feb3e7 100644
--- a/arch/mips/include/asm/mach-dec/war.h
+++ b/arch/mips/include/asm/mach-dec/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
index b660a4c30e6a..79ae82da3ec7 100644
--- a/arch/mips/include/asm/mach-emma2rh/war.h
+++ b/arch/mips/include/asm/mach-emma2rh/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 70d9a25132c5..e014264b2be2 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -34,12 +34,6 @@
 #endif
 #endif
 
-#ifdef CONFIG_IRQ_CPU_RM9K
-#ifndef RM9K_CPU_IRQ_BASE
-#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
-#endif
-#endif
-
 #endif /* CONFIG_IRQ_CPU */
 
 #endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index a44fa9656a82..fba640517f4f 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -21,7 +21,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e2ddcc9b1fff..4ee0e4bdf4fb 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 1
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index a1baafab486a..4821c7b7a38c 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 1
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index d194056dcd7a..7237a935a133 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
index 6158ee861bfd..5b18b9a3d0ec 100644
--- a/arch/mips/include/asm/mach-jazz/war.h
+++ b/arch/mips/include/asm/mach-jazz/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
index 3a5bc17e28fe..9b511d323838 100644
--- a/arch/mips/include/asm/mach-jz4740/war.h
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
index 01b08ef368d1..b6c568c280ef 100644
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -16,7 +16,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
index bb1e0325c9be..741ae724adc6 100644
--- a/arch/mips/include/asm/mach-lasat/war.h
+++ b/arch/mips/include/asm/mach-lasat/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h
index 4b971c3ffd8d..f2570df66bb5 100644
--- a/arch/mips/include/asm/mach-loongson/war.h
+++ b/arch/mips/include/asm/mach-loongson/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
index e3680a8fb349..8fb50d008131 100644
--- a/arch/mips/include/asm/mach-loongson1/war.h
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 7c6931d5f45f..d068fc411f47 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
index 22da89327352..2c7216840e18 100644
--- a/arch/mips/include/asm/mach-netlogic/war.h
+++ b/arch/mips/include/asm/mach-netlogic/war.h
@@ -18,7 +18,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
index 82cd1e97bc2e..edaa06d9d492 100644
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
index d0458dd082f9..de8894c46686 100644
--- a/arch/mips/include/asm/mach-pnx8550/war.h
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 7ac05ecc512b..c5651c8e58d1 100644
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -20,7 +20,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 3ddf187e98a6..1bfd489a3708 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 948d3129a114..a3dde98549bb 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -21,7 +21,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
index 7c6931d5f45f..d068fc411f47 100644
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ b/arch/mips/include/asm/mach-sead3/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 743385d7b5f2..176f5b32dc69 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -33,7 +33,6 @@ extern int sb1250_m3_workaround_needed(void);
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
index 433814616359..6a52e6534776 100644
--- a/arch/mips/include/asm/mach-tx39xx/war.h
+++ b/arch/mips/include/asm/mach-tx39xx/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 39b5d1177c57..a8e2c586a18c 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     1
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
index 56a38926412a..ffe31e736009 100644
--- a/arch/mips/include/asm/mach-vr41xx/war.h
+++ b/arch/mips/include/asm/mach-vr41xx/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
index ac48629bb1ce..e86084c0bd6b 100644
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ b/arch/mips/include/asm/mach-wrppmc/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
deleted file mode 100644
index 56bdd3298600..000000000000
--- a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Momentum Jaguar ATX always has the RM9000 processor.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_has_dsp2            0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-#define cpu_icache_snoops_remote_store  0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
deleted file mode 100644
index e5c6d53efc86..000000000000
--- a/arch/mips/include/asm/mach-yosemite/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
-#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             1
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index eb742895dcbe..7e4e6f8fab37 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -240,7 +240,7 @@
 #define PM_HUGE_MASK    PM_64M
 #elif defined(CONFIG_PAGE_SIZE_64KB)
 #define PM_HUGE_MASK    PM_256M
-#elif defined(CONFIG_HUGETLB_PAGE)
+#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 #error Bad page size configuration for hugetlbfs!
 #endif
 
@@ -977,10 +977,6 @@ do {									\
 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
-
 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 
@@ -1033,10 +1029,6 @@ do {									\
 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
 
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
-
 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
 
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 9b02cfba7449..45cfa1ad86a6 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -72,12 +72,6 @@ extern unsigned long pgd_current[];
 #define ASID_INC        0x10
 #define ASID_MASK       0xff0
 
-#elif defined(CONFIG_CPU_RM9000)
-
-#define ASID_INC        0x1
-#define ASID_MASK       0xfff
-
-/* SMTC/34K debug hack - but maybe we'll keep it */
 #elif defined(CONFIG_MIPS_MT_SMTC)
 
 #define ASID_INC        0x1
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 26137da1c713..44b705d08262 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,8 +120,6 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "R10000 "
 #elif defined CONFIG_CPU_RM7000
 #define MODULE_PROC_FAMILY "RM7000 "
-#elif defined CONFIG_CPU_RM9000
-#define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
 #elif defined CONFIG_CPU_LOONGSON1
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 877845b84b14..42db2be663f1 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -370,4 +370,6 @@ void cvmx_bootmem_lock(void);
  */
 void cvmx_bootmem_unlock(void);
 
+extern struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void);
+
 #endif /*   __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
new file mode 100644
index 000000000000..36f510721141
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
@@ -0,0 +1,3457 @@
+/***********************license start***************
+ * Author: Cavium Inc.
+ *
+ * Contact: support@cavium.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Inc. for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_LMCX_DEFS_H__
+#define __CVMX_LMCX_DEFS_H__
+
+#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull)
+static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
+}
+
+#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull)
+static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
+}
+
+#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
+#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
+#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull))
+#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull))
+#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull))
+#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull)
+
+union cvmx_lmcx_bist_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_bist_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t start:1;
+#else
+                uint64_t start:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+        struct cvmx_lmcx_bist_ctl_s cn50xx;
+        struct cvmx_lmcx_bist_ctl_s cn52xx;
+        struct cvmx_lmcx_bist_ctl_s cn52xxp1;
+        struct cvmx_lmcx_bist_ctl_s cn56xx;
+        struct cvmx_lmcx_bist_ctl_s cn56xxp1;
+};
+
+union cvmx_lmcx_bist_result {
+        uint64_t u64;
+        struct cvmx_lmcx_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t csrd2e:1;
+                uint64_t csre2d:1;
+                uint64_t mwf:1;
+                uint64_t mwd:3;
+                uint64_t mwc:1;
+                uint64_t mrf:1;
+                uint64_t mrd:3;
+#else
+                uint64_t mrd:3;
+                uint64_t mrf:1;
+                uint64_t mwc:1;
+                uint64_t mwd:3;
+                uint64_t mwf:1;
+                uint64_t csre2d:1;
+                uint64_t csrd2e:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+        struct cvmx_lmcx_bist_result_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t mwf:1;
+                uint64_t mwd:3;
+                uint64_t mwc:1;
+                uint64_t mrf:1;
+                uint64_t mrd:3;
+#else
+                uint64_t mrd:3;
+                uint64_t mrf:1;
+                uint64_t mwc:1;
+                uint64_t mwd:3;
+                uint64_t mwf:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_bist_result_s cn52xx;
+        struct cvmx_lmcx_bist_result_s cn52xxp1;
+        struct cvmx_lmcx_bist_result_s cn56xx;
+        struct cvmx_lmcx_bist_result_s cn56xxp1;
+};
+
+union cvmx_lmcx_char_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_char_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t dr:1;
+                uint64_t skew_on:1;
+                uint64_t en:1;
+                uint64_t sel:1;
+                uint64_t prog:8;
+                uint64_t prbs:32;
+#else
+                uint64_t prbs:32;
+                uint64_t prog:8;
+                uint64_t sel:1;
+                uint64_t en:1;
+                uint64_t skew_on:1;
+                uint64_t dr:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+        struct cvmx_lmcx_char_ctl_s cn61xx;
+        struct cvmx_lmcx_char_ctl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t en:1;
+                uint64_t sel:1;
+                uint64_t prog:8;
+                uint64_t prbs:32;
+#else
+                uint64_t prbs:32;
+                uint64_t prog:8;
+                uint64_t sel:1;
+                uint64_t en:1;
+                uint64_t reserved_42_63:22;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_char_ctl_cn63xx cn63xxp1;
+        struct cvmx_lmcx_char_ctl_s cn66xx;
+        struct cvmx_lmcx_char_ctl_s cn68xx;
+        struct cvmx_lmcx_char_ctl_cn63xx cn68xxp1;
+        struct cvmx_lmcx_char_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_char_mask0 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mask:64;
+#else
+                uint64_t mask:64;
+#endif
+        } s;
+        struct cvmx_lmcx_char_mask0_s cn61xx;
+        struct cvmx_lmcx_char_mask0_s cn63xx;
+        struct cvmx_lmcx_char_mask0_s cn63xxp1;
+        struct cvmx_lmcx_char_mask0_s cn66xx;
+        struct cvmx_lmcx_char_mask0_s cn68xx;
+        struct cvmx_lmcx_char_mask0_s cn68xxp1;
+        struct cvmx_lmcx_char_mask0_s cnf71xx;
+};
+
+union cvmx_lmcx_char_mask1 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t mask:8;
+#else
+                uint64_t mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_lmcx_char_mask1_s cn61xx;
+        struct cvmx_lmcx_char_mask1_s cn63xx;
+        struct cvmx_lmcx_char_mask1_s cn63xxp1;
+        struct cvmx_lmcx_char_mask1_s cn66xx;
+        struct cvmx_lmcx_char_mask1_s cn68xx;
+        struct cvmx_lmcx_char_mask1_s cn68xxp1;
+        struct cvmx_lmcx_char_mask1_s cnf71xx;
+};
+
+union cvmx_lmcx_char_mask2 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mask:64;
+#else
+                uint64_t mask:64;
+#endif
+        } s;
+        struct cvmx_lmcx_char_mask2_s cn61xx;
+        struct cvmx_lmcx_char_mask2_s cn63xx;
+        struct cvmx_lmcx_char_mask2_s cn63xxp1;
+        struct cvmx_lmcx_char_mask2_s cn66xx;
+        struct cvmx_lmcx_char_mask2_s cn68xx;
+        struct cvmx_lmcx_char_mask2_s cn68xxp1;
+        struct cvmx_lmcx_char_mask2_s cnf71xx;
+};
+
+union cvmx_lmcx_char_mask3 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t mask:8;
+#else
+                uint64_t mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_lmcx_char_mask3_s cn61xx;
+        struct cvmx_lmcx_char_mask3_s cn63xx;
+        struct cvmx_lmcx_char_mask3_s cn63xxp1;
+        struct cvmx_lmcx_char_mask3_s cn66xx;
+        struct cvmx_lmcx_char_mask3_s cn68xx;
+        struct cvmx_lmcx_char_mask3_s cn68xxp1;
+        struct cvmx_lmcx_char_mask3_s cnf71xx;
+};
+
+union cvmx_lmcx_char_mask4 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t reset_n_mask:1;
+                uint64_t a_mask:16;
+                uint64_t ba_mask:3;
+                uint64_t we_n_mask:1;
+                uint64_t cas_n_mask:1;
+                uint64_t ras_n_mask:1;
+                uint64_t odt1_mask:2;
+                uint64_t odt0_mask:2;
+                uint64_t cs1_n_mask:2;
+                uint64_t cs0_n_mask:2;
+                uint64_t cke_mask:2;
+#else
+                uint64_t cke_mask:2;
+                uint64_t cs0_n_mask:2;
+                uint64_t cs1_n_mask:2;
+                uint64_t odt0_mask:2;
+                uint64_t odt1_mask:2;
+                uint64_t ras_n_mask:1;
+                uint64_t cas_n_mask:1;
+                uint64_t we_n_mask:1;
+                uint64_t ba_mask:3;
+                uint64_t a_mask:16;
+                uint64_t reset_n_mask:1;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+        struct cvmx_lmcx_char_mask4_s cn61xx;
+        struct cvmx_lmcx_char_mask4_s cn63xx;
+        struct cvmx_lmcx_char_mask4_s cn63xxp1;
+        struct cvmx_lmcx_char_mask4_s cn66xx;
+        struct cvmx_lmcx_char_mask4_s cn68xx;
+        struct cvmx_lmcx_char_mask4_s cn68xxp1;
+        struct cvmx_lmcx_char_mask4_s cnf71xx;
+};
+
+union cvmx_lmcx_comp_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t pctl_clk:4;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t pctl_clk:4;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_comp_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t pctl_clk:4;
+                uint64_t pctl_cmd:4;
+                uint64_t pctl_dat:4;
+#else
+                uint64_t pctl_dat:4;
+                uint64_t pctl_cmd:4;
+                uint64_t pctl_clk:4;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_comp_ctl_cn30xx cn31xx;
+        struct cvmx_lmcx_comp_ctl_cn30xx cn38xx;
+        struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2;
+        struct cvmx_lmcx_comp_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t reserved_5_11:7;
+                uint64_t pctl_dat:5;
+#else
+                uint64_t pctl_dat:5;
+                uint64_t reserved_5_11:7;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_comp_ctl_cn50xx cn52xx;
+        struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1;
+        struct cvmx_lmcx_comp_ctl_cn50xx cn56xx;
+        struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1;
+        struct cvmx_lmcx_comp_ctl_cn50xx cn58xx;
+        struct cvmx_lmcx_comp_ctl_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t reserved_4_11:8;
+                uint64_t pctl_dat:4;
+#else
+                uint64_t pctl_dat:4;
+                uint64_t reserved_4_11:8;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn58xxp1;
+};
+
+union cvmx_lmcx_comp_ctl2 {
+        uint64_t u64;
+        struct cvmx_lmcx_comp_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ddr__ptune:4;
+                uint64_t ddr__ntune:4;
+                uint64_t m180:1;
+                uint64_t byp:1;
+                uint64_t ptune:4;
+                uint64_t ntune:4;
+                uint64_t rodt_ctl:4;
+                uint64_t cmd_ctl:4;
+                uint64_t ck_ctl:4;
+                uint64_t dqx_ctl:4;
+#else
+                uint64_t dqx_ctl:4;
+                uint64_t ck_ctl:4;
+                uint64_t cmd_ctl:4;
+                uint64_t rodt_ctl:4;
+                uint64_t ntune:4;
+                uint64_t ptune:4;
+                uint64_t byp:1;
+                uint64_t m180:1;
+                uint64_t ddr__ntune:4;
+                uint64_t ddr__ptune:4;
+                uint64_t reserved_34_63:30;
+#endif
+        } s;
+        struct cvmx_lmcx_comp_ctl2_s cn61xx;
+        struct cvmx_lmcx_comp_ctl2_s cn63xx;
+        struct cvmx_lmcx_comp_ctl2_s cn63xxp1;
+        struct cvmx_lmcx_comp_ctl2_s cn66xx;
+        struct cvmx_lmcx_comp_ctl2_s cn68xx;
+        struct cvmx_lmcx_comp_ctl2_s cn68xxp1;
+        struct cvmx_lmcx_comp_ctl2_s cnf71xx;
+};
+
+union cvmx_lmcx_config {
+        uint64_t u64;
+        struct cvmx_lmcx_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t mode32b:1;
+                uint64_t scrz:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t scrz:1;
+                uint64_t mode32b:1;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+        struct cvmx_lmcx_config_s cn61xx;
+        struct cvmx_lmcx_config_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_config_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_55_63:9;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t reserved_55_63:9;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_config_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t scrz:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t scrz:1;
+                uint64_t reserved_60_63:4;
+#endif
+        } cn66xx;
+        struct cvmx_lmcx_config_cn63xx cn68xx;
+        struct cvmx_lmcx_config_cn63xx cn68xxp1;
+        struct cvmx_lmcx_config_s cnf71xx;
+};
+
+union cvmx_lmcx_control {
+        uint64_t u64;
+        struct cvmx_lmcx_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t scramble_ena:1;
+                uint64_t thrcnt:12;
+                uint64_t persub:8;
+                uint64_t thrmax:4;
+                uint64_t crm_cnt:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_max:5;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t crm_max:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_cnt:5;
+                uint64_t thrmax:4;
+                uint64_t persub:8;
+                uint64_t thrcnt:12;
+                uint64_t scramble_ena:1;
+#endif
+        } s;
+        struct cvmx_lmcx_control_s cn61xx;
+        struct cvmx_lmcx_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_control_cn63xx cn63xxp1;
+        struct cvmx_lmcx_control_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t scramble_ena:1;
+                uint64_t reserved_24_62:39;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t reserved_24_62:39;
+                uint64_t scramble_ena:1;
+#endif
+        } cn66xx;
+        struct cvmx_lmcx_control_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t thrcnt:12;
+                uint64_t persub:8;
+                uint64_t thrmax:4;
+                uint64_t crm_cnt:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_max:5;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t crm_max:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_cnt:5;
+                uint64_t thrmax:4;
+                uint64_t persub:8;
+                uint64_t thrcnt:12;
+                uint64_t reserved_63_63:1;
+#endif
+        } cn68xx;
+        struct cvmx_lmcx_control_cn68xx cn68xxp1;
+        struct cvmx_lmcx_control_cn66xx cnf71xx;
+};
+
+union cvmx_lmcx_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t pll_div2:1;
+                uint64_t pll_bypass:1;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t reserved_10_11:2;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t reserved_10_11:2;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t pll_bypass:1;
+                uint64_t pll_div2:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t pll_div2:1;
+                uint64_t pll_bypass:1;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode32b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode32b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t pll_bypass:1;
+                uint64_t pll_div2:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_ctl_cn30xx cn31xx;
+        struct cvmx_lmcx_ctl_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_16_17:2;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t set_zero:1;
+                uint64_t mode128b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode128b:1;
+                uint64_t set_zero:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t reserved_16_17:2;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+        struct cvmx_lmcx_ctl_cn38xx cn38xxp2;
+        struct cvmx_lmcx_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_17_17:1;
+                uint64_t pll_bypass:1;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode32b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode32b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t pll_bypass:1;
+                uint64_t reserved_17_17:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_16_17:2;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode32b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode32b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t reserved_16_17:2;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn52xx;
+        struct cvmx_lmcx_ctl_cn52xx cn52xxp1;
+        struct cvmx_lmcx_ctl_cn52xx cn56xx;
+        struct cvmx_lmcx_ctl_cn52xx cn56xxp1;
+        struct cvmx_lmcx_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_16_17:2;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode128b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode128b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t reserved_16_17:2;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn58xx;
+        struct cvmx_lmcx_ctl_cn58xx cn58xxp1;
+};
+
+union cvmx_lmcx_ctl1 {
+        uint64_t u64;
+        struct cvmx_lmcx_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t sequence:3;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_2_7:6;
+                uint64_t data_layout:2;
+#else
+                uint64_t data_layout:2;
+                uint64_t reserved_2_7:6;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t sequence:3;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+        struct cvmx_lmcx_ctl1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t data_layout:2;
+#else
+                uint64_t data_layout:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_ctl1_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_2_7:6;
+                uint64_t data_layout:2;
+#else
+                uint64_t data_layout:2;
+                uint64_t reserved_2_7:6;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_ctl1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t sequence:3;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t sequence:3;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } cn52xx;
+        struct cvmx_lmcx_ctl1_cn52xx cn52xxp1;
+        struct cvmx_lmcx_ctl1_cn52xx cn56xx;
+        struct cvmx_lmcx_ctl1_cn52xx cn56xxp1;
+        struct cvmx_lmcx_ctl1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn58xx;
+        struct cvmx_lmcx_ctl1_cn58xx cn58xxp1;
+};
+
+union cvmx_lmcx_dclk_cnt {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dclkcnt:64;
+#else
+                uint64_t dclkcnt:64;
+#endif
+        } s;
+        struct cvmx_lmcx_dclk_cnt_s cn61xx;
+        struct cvmx_lmcx_dclk_cnt_s cn63xx;
+        struct cvmx_lmcx_dclk_cnt_s cn63xxp1;
+        struct cvmx_lmcx_dclk_cnt_s cn66xx;
+        struct cvmx_lmcx_dclk_cnt_s cn68xx;
+        struct cvmx_lmcx_dclk_cnt_s cn68xxp1;
+        struct cvmx_lmcx_dclk_cnt_s cnf71xx;
+};
+
+union cvmx_lmcx_dclk_cnt_hi {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dclkcnt_hi:32;
+#else
+                uint64_t dclkcnt_hi:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn30xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn31xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn38xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn50xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn52xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn56xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn58xx;
+        struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1;
+};
+
+union cvmx_lmcx_dclk_cnt_lo {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dclkcnt_lo:32;
+#else
+                uint64_t dclkcnt_lo:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn30xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn31xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn38xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn50xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn52xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn56xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn58xx;
+        struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1;
+};
+
+union cvmx_lmcx_dclk_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t off90_ena:1;
+                uint64_t dclk90_byp:1;
+                uint64_t dclk90_ld:1;
+                uint64_t dclk90_vlu:5;
+#else
+                uint64_t dclk90_vlu:5;
+                uint64_t dclk90_ld:1;
+                uint64_t dclk90_byp:1;
+                uint64_t off90_ena:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_lmcx_dclk_ctl_s cn56xx;
+        struct cvmx_lmcx_dclk_ctl_s cn56xxp1;
+};
+
+union cvmx_lmcx_ddr2_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_ddr2_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bank8:1;
+                uint64_t burst8:1;
+                uint64_t addlat:3;
+                uint64_t pocas:1;
+                uint64_t bwcnt:1;
+                uint64_t twr:3;
+                uint64_t silo_hc:1;
+                uint64_t ddr_eof:4;
+                uint64_t tfaw:5;
+                uint64_t crip_mode:1;
+                uint64_t ddr2t:1;
+                uint64_t odt_ena:1;
+                uint64_t qdll_ena:1;
+                uint64_t dll90_vlu:5;
+                uint64_t dll90_byp:1;
+                uint64_t rdqs:1;
+                uint64_t ddr2:1;
+#else
+                uint64_t ddr2:1;
+                uint64_t rdqs:1;
+                uint64_t dll90_byp:1;
+                uint64_t dll90_vlu:5;
+                uint64_t qdll_ena:1;
+                uint64_t odt_ena:1;
+                uint64_t ddr2t:1;
+                uint64_t crip_mode:1;
+                uint64_t tfaw:5;
+                uint64_t ddr_eof:4;
+                uint64_t silo_hc:1;
+                uint64_t twr:3;
+                uint64_t bwcnt:1;
+                uint64_t pocas:1;
+                uint64_t addlat:3;
+                uint64_t burst8:1;
+                uint64_t bank8:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ddr2_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bank8:1;
+                uint64_t burst8:1;
+                uint64_t addlat:3;
+                uint64_t pocas:1;
+                uint64_t bwcnt:1;
+                uint64_t twr:3;
+                uint64_t silo_hc:1;
+                uint64_t ddr_eof:4;
+                uint64_t tfaw:5;
+                uint64_t crip_mode:1;
+                uint64_t ddr2t:1;
+                uint64_t odt_ena:1;
+                uint64_t qdll_ena:1;
+                uint64_t dll90_vlu:5;
+                uint64_t dll90_byp:1;
+                uint64_t reserved_1_1:1;
+                uint64_t ddr2:1;
+#else
+                uint64_t ddr2:1;
+                uint64_t reserved_1_1:1;
+                uint64_t dll90_byp:1;
+                uint64_t dll90_vlu:5;
+                uint64_t qdll_ena:1;
+                uint64_t odt_ena:1;
+                uint64_t ddr2t:1;
+                uint64_t crip_mode:1;
+                uint64_t tfaw:5;
+                uint64_t ddr_eof:4;
+                uint64_t silo_hc:1;
+                uint64_t twr:3;
+                uint64_t bwcnt:1;
+                uint64_t pocas:1;
+                uint64_t addlat:3;
+                uint64_t burst8:1;
+                uint64_t bank8:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx;
+        struct cvmx_lmcx_ddr2_ctl_s cn38xx;
+        struct cvmx_lmcx_ddr2_ctl_s cn38xxp2;
+        struct cvmx_lmcx_ddr2_ctl_s cn50xx;
+        struct cvmx_lmcx_ddr2_ctl_s cn52xx;
+        struct cvmx_lmcx_ddr2_ctl_s cn52xxp1;
+        struct cvmx_lmcx_ddr2_ctl_s cn56xx;
+        struct cvmx_lmcx_ddr2_ctl_s cn56xxp1;
+        struct cvmx_lmcx_ddr2_ctl_s cn58xx;
+        struct cvmx_lmcx_ddr2_ctl_s cn58xxp1;
+};
+
+union cvmx_lmcx_ddr_pll_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_ddr_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t jtg_test_mode:1;
+                uint64_t dfm_div_reset:1;
+                uint64_t dfm_ps_en:3;
+                uint64_t ddr_div_reset:1;
+                uint64_t ddr_ps_en:3;
+                uint64_t diffamp:4;
+                uint64_t cps:3;
+                uint64_t cpb:3;
+                uint64_t reset_n:1;
+                uint64_t clkf:7;
+#else
+                uint64_t clkf:7;
+                uint64_t reset_n:1;
+                uint64_t cpb:3;
+                uint64_t cps:3;
+                uint64_t diffamp:4;
+                uint64_t ddr_ps_en:3;
+                uint64_t ddr_div_reset:1;
+                uint64_t dfm_ps_en:3;
+                uint64_t dfm_div_reset:1;
+                uint64_t jtg_test_mode:1;
+                uint64_t reserved_27_63:37;
+#endif
+        } s;
+        struct cvmx_lmcx_ddr_pll_ctl_s cn61xx;
+        struct cvmx_lmcx_ddr_pll_ctl_s cn63xx;
+        struct cvmx_lmcx_ddr_pll_ctl_s cn63xxp1;
+        struct cvmx_lmcx_ddr_pll_ctl_s cn66xx;
+        struct cvmx_lmcx_ddr_pll_ctl_s cn68xx;
+        struct cvmx_lmcx_ddr_pll_ctl_s cn68xxp1;
+        struct cvmx_lmcx_ddr_pll_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_delay_cfg {
+        uint64_t u64;
+        struct cvmx_lmcx_delay_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t dq:5;
+                uint64_t cmd:5;
+                uint64_t clk:5;
+#else
+                uint64_t clk:5;
+                uint64_t cmd:5;
+                uint64_t dq:5;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+        struct cvmx_lmcx_delay_cfg_s cn30xx;
+        struct cvmx_lmcx_delay_cfg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t dq:4;
+                uint64_t reserved_9_9:1;
+                uint64_t cmd:4;
+                uint64_t reserved_4_4:1;
+                uint64_t clk:4;
+#else
+                uint64_t clk:4;
+                uint64_t reserved_4_4:1;
+                uint64_t cmd:4;
+                uint64_t reserved_9_9:1;
+                uint64_t dq:4;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn38xx;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn50xx;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn52xx;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn56xx;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn58xx;
+        struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1;
+};
+
+union cvmx_lmcx_dimmx_params {
+        uint64_t u64;
+        struct cvmx_lmcx_dimmx_params_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rc15:4;
+                uint64_t rc14:4;
+                uint64_t rc13:4;
+                uint64_t rc12:4;
+                uint64_t rc11:4;
+                uint64_t rc10:4;
+                uint64_t rc9:4;
+                uint64_t rc8:4;
+                uint64_t rc7:4;
+                uint64_t rc6:4;
+                uint64_t rc5:4;
+                uint64_t rc4:4;
+                uint64_t rc3:4;
+                uint64_t rc2:4;
+                uint64_t rc1:4;
+                uint64_t rc0:4;
+#else
+                uint64_t rc0:4;
+                uint64_t rc1:4;
+                uint64_t rc2:4;
+                uint64_t rc3:4;
+                uint64_t rc4:4;
+                uint64_t rc5:4;
+                uint64_t rc6:4;
+                uint64_t rc7:4;
+                uint64_t rc8:4;
+                uint64_t rc9:4;
+                uint64_t rc10:4;
+                uint64_t rc11:4;
+                uint64_t rc12:4;
+                uint64_t rc13:4;
+                uint64_t rc14:4;
+                uint64_t rc15:4;
+#endif
+        } s;
+        struct cvmx_lmcx_dimmx_params_s cn61xx;
+        struct cvmx_lmcx_dimmx_params_s cn63xx;
+        struct cvmx_lmcx_dimmx_params_s cn63xxp1;
+        struct cvmx_lmcx_dimmx_params_s cn66xx;
+        struct cvmx_lmcx_dimmx_params_s cn68xx;
+        struct cvmx_lmcx_dimmx_params_s cn68xxp1;
+        struct cvmx_lmcx_dimmx_params_s cnf71xx;
+};
+
+union cvmx_lmcx_dimm_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_dimm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t parity:1;
+                uint64_t tcws:13;
+                uint64_t dimm1_wmask:16;
+                uint64_t dimm0_wmask:16;
+#else
+                uint64_t dimm0_wmask:16;
+                uint64_t dimm1_wmask:16;
+                uint64_t tcws:13;
+                uint64_t parity:1;
+                uint64_t reserved_46_63:18;
+#endif
+        } s;
+        struct cvmx_lmcx_dimm_ctl_s cn61xx;
+        struct cvmx_lmcx_dimm_ctl_s cn63xx;
+        struct cvmx_lmcx_dimm_ctl_s cn63xxp1;
+        struct cvmx_lmcx_dimm_ctl_s cn66xx;
+        struct cvmx_lmcx_dimm_ctl_s cn68xx;
+        struct cvmx_lmcx_dimm_ctl_s cn68xxp1;
+        struct cvmx_lmcx_dimm_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_dll_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_dll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dreset:1;
+                uint64_t dll90_byp:1;
+                uint64_t dll90_ena:1;
+                uint64_t dll90_vlu:5;
+#else
+                uint64_t dll90_vlu:5;
+                uint64_t dll90_ena:1;
+                uint64_t dll90_byp:1;
+                uint64_t dreset:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_lmcx_dll_ctl_s cn52xx;
+        struct cvmx_lmcx_dll_ctl_s cn52xxp1;
+        struct cvmx_lmcx_dll_ctl_s cn56xx;
+        struct cvmx_lmcx_dll_ctl_s cn56xxp1;
+};
+
+union cvmx_lmcx_dll_ctl2 {
+        uint64_t u64;
+        struct cvmx_lmcx_dll_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t intf_en:1;
+                uint64_t dll_bringup:1;
+                uint64_t dreset:1;
+                uint64_t quad_dll_ena:1;
+                uint64_t byp_sel:4;
+                uint64_t byp_setting:8;
+#else
+                uint64_t byp_setting:8;
+                uint64_t byp_sel:4;
+                uint64_t quad_dll_ena:1;
+                uint64_t dreset:1;
+                uint64_t dll_bringup:1;
+                uint64_t intf_en:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+        struct cvmx_lmcx_dll_ctl2_s cn61xx;
+        struct cvmx_lmcx_dll_ctl2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t dll_bringup:1;
+                uint64_t dreset:1;
+                uint64_t quad_dll_ena:1;
+                uint64_t byp_sel:4;
+                uint64_t byp_setting:8;
+#else
+                uint64_t byp_setting:8;
+                uint64_t byp_sel:4;
+                uint64_t quad_dll_ena:1;
+                uint64_t dreset:1;
+                uint64_t dll_bringup:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_dll_ctl2_cn63xx cn63xxp1;
+        struct cvmx_lmcx_dll_ctl2_cn63xx cn66xx;
+        struct cvmx_lmcx_dll_ctl2_s cn68xx;
+        struct cvmx_lmcx_dll_ctl2_s cn68xxp1;
+        struct cvmx_lmcx_dll_ctl2_s cnf71xx;
+};
+
+union cvmx_lmcx_dll_ctl3 {
+        uint64_t u64;
+        struct cvmx_lmcx_dll_ctl3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_41_63:23;
+                uint64_t dclk90_fwd:1;
+                uint64_t ddr_90_dly_byp:1;
+                uint64_t dclk90_recal_dis:1;
+                uint64_t dclk90_byp_sel:1;
+                uint64_t dclk90_byp_setting:8;
+                uint64_t dll_fast:1;
+                uint64_t dll90_setting:8;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll_mode:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t offset_ena:1;
+                uint64_t load_offset:1;
+                uint64_t mode_sel:2;
+                uint64_t byte_sel:4;
+                uint64_t offset:6;
+#else
+                uint64_t offset:6;
+                uint64_t byte_sel:4;
+                uint64_t mode_sel:2;
+                uint64_t load_offset:1;
+                uint64_t offset_ena:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t dll_mode:1;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll90_setting:8;
+                uint64_t dll_fast:1;
+                uint64_t dclk90_byp_setting:8;
+                uint64_t dclk90_byp_sel:1;
+                uint64_t dclk90_recal_dis:1;
+                uint64_t ddr_90_dly_byp:1;
+                uint64_t dclk90_fwd:1;
+                uint64_t reserved_41_63:23;
+#endif
+        } s;
+        struct cvmx_lmcx_dll_ctl3_s cn61xx;
+        struct cvmx_lmcx_dll_ctl3_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t dll_fast:1;
+                uint64_t dll90_setting:8;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll_mode:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t offset_ena:1;
+                uint64_t load_offset:1;
+                uint64_t mode_sel:2;
+                uint64_t byte_sel:4;
+                uint64_t offset:6;
+#else
+                uint64_t offset:6;
+                uint64_t byte_sel:4;
+                uint64_t mode_sel:2;
+                uint64_t load_offset:1;
+                uint64_t offset_ena:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t dll_mode:1;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll90_setting:8;
+                uint64_t dll_fast:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_dll_ctl3_cn63xx cn63xxp1;
+        struct cvmx_lmcx_dll_ctl3_cn63xx cn66xx;
+        struct cvmx_lmcx_dll_ctl3_s cn68xx;
+        struct cvmx_lmcx_dll_ctl3_s cn68xxp1;
+        struct cvmx_lmcx_dll_ctl3_s cnf71xx;
+};
+
+union cvmx_lmcx_dual_memcfg {
+        uint64_t u64;
+        struct cvmx_lmcx_dual_memcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t bank8:1;
+                uint64_t row_lsb:3;
+                uint64_t reserved_8_15:8;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t reserved_8_15:8;
+                uint64_t row_lsb:3;
+                uint64_t bank8:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_lmcx_dual_memcfg_s cn50xx;
+        struct cvmx_lmcx_dual_memcfg_s cn52xx;
+        struct cvmx_lmcx_dual_memcfg_s cn52xxp1;
+        struct cvmx_lmcx_dual_memcfg_s cn56xx;
+        struct cvmx_lmcx_dual_memcfg_s cn56xxp1;
+        struct cvmx_lmcx_dual_memcfg_s cn58xx;
+        struct cvmx_lmcx_dual_memcfg_s cn58xxp1;
+        struct cvmx_lmcx_dual_memcfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t row_lsb:3;
+                uint64_t reserved_8_15:8;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t reserved_8_15:8;
+                uint64_t row_lsb:3;
+                uint64_t reserved_19_63:45;
+#endif
+        } cn61xx;
+        struct cvmx_lmcx_dual_memcfg_cn61xx cn63xx;
+        struct cvmx_lmcx_dual_memcfg_cn61xx cn63xxp1;
+        struct cvmx_lmcx_dual_memcfg_cn61xx cn66xx;
+        struct cvmx_lmcx_dual_memcfg_cn61xx cn68xx;
+        struct cvmx_lmcx_dual_memcfg_cn61xx cn68xxp1;
+        struct cvmx_lmcx_dual_memcfg_cn61xx cnf71xx;
+};
+
+union cvmx_lmcx_ecc_synd {
+        uint64_t u64;
+        struct cvmx_lmcx_ecc_synd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t mrdsyn3:8;
+                uint64_t mrdsyn2:8;
+                uint64_t mrdsyn1:8;
+                uint64_t mrdsyn0:8;
+#else
+                uint64_t mrdsyn0:8;
+                uint64_t mrdsyn1:8;
+                uint64_t mrdsyn2:8;
+                uint64_t mrdsyn3:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ecc_synd_s cn30xx;
+        struct cvmx_lmcx_ecc_synd_s cn31xx;
+        struct cvmx_lmcx_ecc_synd_s cn38xx;
+        struct cvmx_lmcx_ecc_synd_s cn38xxp2;
+        struct cvmx_lmcx_ecc_synd_s cn50xx;
+        struct cvmx_lmcx_ecc_synd_s cn52xx;
+        struct cvmx_lmcx_ecc_synd_s cn52xxp1;
+        struct cvmx_lmcx_ecc_synd_s cn56xx;
+        struct cvmx_lmcx_ecc_synd_s cn56xxp1;
+        struct cvmx_lmcx_ecc_synd_s cn58xx;
+        struct cvmx_lmcx_ecc_synd_s cn58xxp1;
+        struct cvmx_lmcx_ecc_synd_s cn61xx;
+        struct cvmx_lmcx_ecc_synd_s cn63xx;
+        struct cvmx_lmcx_ecc_synd_s cn63xxp1;
+        struct cvmx_lmcx_ecc_synd_s cn66xx;
+        struct cvmx_lmcx_ecc_synd_s cn68xx;
+        struct cvmx_lmcx_ecc_synd_s cn68xxp1;
+        struct cvmx_lmcx_ecc_synd_s cnf71xx;
+};
+
+union cvmx_lmcx_fadr {
+        uint64_t u64;
+        struct cvmx_lmcx_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_lmcx_fadr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t fdimm:2;
+                uint64_t fbunk:1;
+                uint64_t fbank:3;
+                uint64_t frow:14;
+                uint64_t fcol:12;
+#else
+                uint64_t fcol:12;
+                uint64_t frow:14;
+                uint64_t fbank:3;
+                uint64_t fbunk:1;
+                uint64_t fdimm:2;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_fadr_cn30xx cn31xx;
+        struct cvmx_lmcx_fadr_cn30xx cn38xx;
+        struct cvmx_lmcx_fadr_cn30xx cn38xxp2;
+        struct cvmx_lmcx_fadr_cn30xx cn50xx;
+        struct cvmx_lmcx_fadr_cn30xx cn52xx;
+        struct cvmx_lmcx_fadr_cn30xx cn52xxp1;
+        struct cvmx_lmcx_fadr_cn30xx cn56xx;
+        struct cvmx_lmcx_fadr_cn30xx cn56xxp1;
+        struct cvmx_lmcx_fadr_cn30xx cn58xx;
+        struct cvmx_lmcx_fadr_cn30xx cn58xxp1;
+        struct cvmx_lmcx_fadr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t fdimm:2;
+                uint64_t fbunk:1;
+                uint64_t fbank:3;
+                uint64_t frow:16;
+                uint64_t fcol:14;
+#else
+                uint64_t fcol:14;
+                uint64_t frow:16;
+                uint64_t fbank:3;
+                uint64_t fbunk:1;
+                uint64_t fdimm:2;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn61xx;
+        struct cvmx_lmcx_fadr_cn61xx cn63xx;
+        struct cvmx_lmcx_fadr_cn61xx cn63xxp1;
+        struct cvmx_lmcx_fadr_cn61xx cn66xx;
+        struct cvmx_lmcx_fadr_cn61xx cn68xx;
+        struct cvmx_lmcx_fadr_cn61xx cn68xxp1;
+        struct cvmx_lmcx_fadr_cn61xx cnf71xx;
+};
+
+union cvmx_lmcx_ifb_cnt {
+        uint64_t u64;
+        struct cvmx_lmcx_ifb_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ifbcnt:64;
+#else
+                uint64_t ifbcnt:64;
+#endif
+        } s;
+        struct cvmx_lmcx_ifb_cnt_s cn61xx;
+        struct cvmx_lmcx_ifb_cnt_s cn63xx;
+        struct cvmx_lmcx_ifb_cnt_s cn63xxp1;
+        struct cvmx_lmcx_ifb_cnt_s cn66xx;
+        struct cvmx_lmcx_ifb_cnt_s cn68xx;
+        struct cvmx_lmcx_ifb_cnt_s cn68xxp1;
+        struct cvmx_lmcx_ifb_cnt_s cnf71xx;
+};
+
+union cvmx_lmcx_ifb_cnt_hi {
+        uint64_t u64;
+        struct cvmx_lmcx_ifb_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ifbcnt_hi:32;
+#else
+                uint64_t ifbcnt_hi:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn30xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn31xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn38xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn50xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn52xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn56xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn58xx;
+        struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1;
+};
+
+union cvmx_lmcx_ifb_cnt_lo {
+        uint64_t u64;
+        struct cvmx_lmcx_ifb_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ifbcnt_lo:32;
+#else
+                uint64_t ifbcnt_lo:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn30xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn31xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn38xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn50xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn52xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn56xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn58xx;
+        struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1;
+};
+
+union cvmx_lmcx_int {
+        uint64_t u64;
+        struct cvmx_lmcx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t ded_err:4;
+                uint64_t sec_err:4;
+                uint64_t nxm_wr_err:1;
+#else
+                uint64_t nxm_wr_err:1;
+                uint64_t sec_err:4;
+                uint64_t ded_err:4;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+        struct cvmx_lmcx_int_s cn61xx;
+        struct cvmx_lmcx_int_s cn63xx;
+        struct cvmx_lmcx_int_s cn63xxp1;
+        struct cvmx_lmcx_int_s cn66xx;
+        struct cvmx_lmcx_int_s cn68xx;
+        struct cvmx_lmcx_int_s cn68xxp1;
+        struct cvmx_lmcx_int_s cnf71xx;
+};
+
+union cvmx_lmcx_int_en {
+        uint64_t u64;
+        struct cvmx_lmcx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t intr_ded_ena:1;
+                uint64_t intr_sec_ena:1;
+                uint64_t intr_nxm_wr_ena:1;
+#else
+                uint64_t intr_nxm_wr_ena:1;
+                uint64_t intr_sec_ena:1;
+                uint64_t intr_ded_ena:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+        struct cvmx_lmcx_int_en_s cn61xx;
+        struct cvmx_lmcx_int_en_s cn63xx;
+        struct cvmx_lmcx_int_en_s cn63xxp1;
+        struct cvmx_lmcx_int_en_s cn66xx;
+        struct cvmx_lmcx_int_en_s cn68xx;
+        struct cvmx_lmcx_int_en_s cn68xxp1;
+        struct cvmx_lmcx_int_en_s cnf71xx;
+};
+
+union cvmx_lmcx_mem_cfg0 {
+        uint64_t u64;
+        struct cvmx_lmcx_mem_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t reset:1;
+                uint64_t silo_qc:1;
+                uint64_t bunk_ena:1;
+                uint64_t ded_err:4;
+                uint64_t sec_err:4;
+                uint64_t intr_ded_ena:1;
+                uint64_t intr_sec_ena:1;
+                uint64_t tcl:4;
+                uint64_t ref_int:6;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t ref_int:6;
+                uint64_t tcl:4;
+                uint64_t intr_sec_ena:1;
+                uint64_t intr_ded_ena:1;
+                uint64_t sec_err:4;
+                uint64_t ded_err:4;
+                uint64_t bunk_ena:1;
+                uint64_t silo_qc:1;
+                uint64_t reset:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_mem_cfg0_s cn30xx;
+        struct cvmx_lmcx_mem_cfg0_s cn31xx;
+        struct cvmx_lmcx_mem_cfg0_s cn38xx;
+        struct cvmx_lmcx_mem_cfg0_s cn38xxp2;
+        struct cvmx_lmcx_mem_cfg0_s cn50xx;
+        struct cvmx_lmcx_mem_cfg0_s cn52xx;
+        struct cvmx_lmcx_mem_cfg0_s cn52xxp1;
+        struct cvmx_lmcx_mem_cfg0_s cn56xx;
+        struct cvmx_lmcx_mem_cfg0_s cn56xxp1;
+        struct cvmx_lmcx_mem_cfg0_s cn58xx;
+        struct cvmx_lmcx_mem_cfg0_s cn58xxp1;
+};
+
+union cvmx_lmcx_mem_cfg1 {
+        uint64_t u64;
+        struct cvmx_lmcx_mem_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t comp_bypass:1;
+                uint64_t trrd:3;
+                uint64_t caslat:3;
+                uint64_t tmrd:3;
+                uint64_t trfc:5;
+                uint64_t trp:4;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+#else
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trp:4;
+                uint64_t trfc:5;
+                uint64_t tmrd:3;
+                uint64_t caslat:3;
+                uint64_t trrd:3;
+                uint64_t comp_bypass:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_mem_cfg1_s cn30xx;
+        struct cvmx_lmcx_mem_cfg1_s cn31xx;
+        struct cvmx_lmcx_mem_cfg1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t trrd:3;
+                uint64_t caslat:3;
+                uint64_t tmrd:3;
+                uint64_t trfc:5;
+                uint64_t trp:4;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+#else
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trp:4;
+                uint64_t trfc:5;
+                uint64_t tmrd:3;
+                uint64_t caslat:3;
+                uint64_t trrd:3;
+                uint64_t reserved_31_63:33;
+#endif
+        } cn38xx;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2;
+        struct cvmx_lmcx_mem_cfg1_s cn50xx;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx;
+        struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1;
+};
+
+union cvmx_lmcx_modereg_params0 {
+        uint64_t u64;
+        struct cvmx_lmcx_modereg_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t ppd:1;
+                uint64_t wrp:3;
+                uint64_t dllr:1;
+                uint64_t tm:1;
+                uint64_t rbt:1;
+                uint64_t cl:4;
+                uint64_t bl:2;
+                uint64_t qoff:1;
+                uint64_t tdqs:1;
+                uint64_t wlev:1;
+                uint64_t al:2;
+                uint64_t dll:1;
+                uint64_t mpr:1;
+                uint64_t mprloc:2;
+                uint64_t cwl:3;
+#else
+                uint64_t cwl:3;
+                uint64_t mprloc:2;
+                uint64_t mpr:1;
+                uint64_t dll:1;
+                uint64_t al:2;
+                uint64_t wlev:1;
+                uint64_t tdqs:1;
+                uint64_t qoff:1;
+                uint64_t bl:2;
+                uint64_t cl:4;
+                uint64_t rbt:1;
+                uint64_t tm:1;
+                uint64_t dllr:1;
+                uint64_t wrp:3;
+                uint64_t ppd:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+        struct cvmx_lmcx_modereg_params0_s cn61xx;
+        struct cvmx_lmcx_modereg_params0_s cn63xx;
+        struct cvmx_lmcx_modereg_params0_s cn63xxp1;
+        struct cvmx_lmcx_modereg_params0_s cn66xx;
+        struct cvmx_lmcx_modereg_params0_s cn68xx;
+        struct cvmx_lmcx_modereg_params0_s cn68xxp1;
+        struct cvmx_lmcx_modereg_params0_s cnf71xx;
+};
+
+union cvmx_lmcx_modereg_params1 {
+        uint64_t u64;
+        struct cvmx_lmcx_modereg_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t rtt_nom_11:3;
+                uint64_t dic_11:2;
+                uint64_t rtt_wr_11:2;
+                uint64_t srt_11:1;
+                uint64_t asr_11:1;
+                uint64_t pasr_11:3;
+                uint64_t rtt_nom_10:3;
+                uint64_t dic_10:2;
+                uint64_t rtt_wr_10:2;
+                uint64_t srt_10:1;
+                uint64_t asr_10:1;
+                uint64_t pasr_10:3;
+                uint64_t rtt_nom_01:3;
+                uint64_t dic_01:2;
+                uint64_t rtt_wr_01:2;
+                uint64_t srt_01:1;
+                uint64_t asr_01:1;
+                uint64_t pasr_01:3;
+                uint64_t rtt_nom_00:3;
+                uint64_t dic_00:2;
+                uint64_t rtt_wr_00:2;
+                uint64_t srt_00:1;
+                uint64_t asr_00:1;
+                uint64_t pasr_00:3;
+#else
+                uint64_t pasr_00:3;
+                uint64_t asr_00:1;
+                uint64_t srt_00:1;
+                uint64_t rtt_wr_00:2;
+                uint64_t dic_00:2;
+                uint64_t rtt_nom_00:3;
+                uint64_t pasr_01:3;
+                uint64_t asr_01:1;
+                uint64_t srt_01:1;
+                uint64_t rtt_wr_01:2;
+                uint64_t dic_01:2;
+                uint64_t rtt_nom_01:3;
+                uint64_t pasr_10:3;
+                uint64_t asr_10:1;
+                uint64_t srt_10:1;
+                uint64_t rtt_wr_10:2;
+                uint64_t dic_10:2;
+                uint64_t rtt_nom_10:3;
+                uint64_t pasr_11:3;
+                uint64_t asr_11:1;
+                uint64_t srt_11:1;
+                uint64_t rtt_wr_11:2;
+                uint64_t dic_11:2;
+                uint64_t rtt_nom_11:3;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_lmcx_modereg_params1_s cn61xx;
+        struct cvmx_lmcx_modereg_params1_s cn63xx;
+        struct cvmx_lmcx_modereg_params1_s cn63xxp1;
+        struct cvmx_lmcx_modereg_params1_s cn66xx;
+        struct cvmx_lmcx_modereg_params1_s cn68xx;
+        struct cvmx_lmcx_modereg_params1_s cn68xxp1;
+        struct cvmx_lmcx_modereg_params1_s cnf71xx;
+};
+
+union cvmx_lmcx_nxm {
+        uint64_t u64;
+        struct cvmx_lmcx_nxm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t mem_msb_d3_r1:4;
+                uint64_t mem_msb_d3_r0:4;
+                uint64_t mem_msb_d2_r1:4;
+                uint64_t mem_msb_d2_r0:4;
+                uint64_t mem_msb_d1_r1:4;
+                uint64_t mem_msb_d1_r0:4;
+                uint64_t mem_msb_d0_r1:4;
+                uint64_t mem_msb_d0_r0:4;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t mem_msb_d0_r0:4;
+                uint64_t mem_msb_d0_r1:4;
+                uint64_t mem_msb_d1_r0:4;
+                uint64_t mem_msb_d1_r1:4;
+                uint64_t mem_msb_d2_r0:4;
+                uint64_t mem_msb_d2_r1:4;
+                uint64_t mem_msb_d3_r0:4;
+                uint64_t mem_msb_d3_r1:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+        struct cvmx_lmcx_nxm_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn52xx;
+        struct cvmx_lmcx_nxm_cn52xx cn56xx;
+        struct cvmx_lmcx_nxm_cn52xx cn58xx;
+        struct cvmx_lmcx_nxm_s cn61xx;
+        struct cvmx_lmcx_nxm_s cn63xx;
+        struct cvmx_lmcx_nxm_s cn63xxp1;
+        struct cvmx_lmcx_nxm_s cn66xx;
+        struct cvmx_lmcx_nxm_s cn68xx;
+        struct cvmx_lmcx_nxm_s cn68xxp1;
+        struct cvmx_lmcx_nxm_s cnf71xx;
+};
+
+union cvmx_lmcx_ops_cnt {
+        uint64_t u64;
+        struct cvmx_lmcx_ops_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t opscnt:64;
+#else
+                uint64_t opscnt:64;
+#endif
+        } s;
+        struct cvmx_lmcx_ops_cnt_s cn61xx;
+        struct cvmx_lmcx_ops_cnt_s cn63xx;
+        struct cvmx_lmcx_ops_cnt_s cn63xxp1;
+        struct cvmx_lmcx_ops_cnt_s cn66xx;
+        struct cvmx_lmcx_ops_cnt_s cn68xx;
+        struct cvmx_lmcx_ops_cnt_s cn68xxp1;
+        struct cvmx_lmcx_ops_cnt_s cnf71xx;
+};
+
+union cvmx_lmcx_ops_cnt_hi {
+        uint64_t u64;
+        struct cvmx_lmcx_ops_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t opscnt_hi:32;
+#else
+                uint64_t opscnt_hi:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ops_cnt_hi_s cn30xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn31xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn38xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2;
+        struct cvmx_lmcx_ops_cnt_hi_s cn50xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn52xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1;
+        struct cvmx_lmcx_ops_cnt_hi_s cn56xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1;
+        struct cvmx_lmcx_ops_cnt_hi_s cn58xx;
+        struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1;
+};
+
+union cvmx_lmcx_ops_cnt_lo {
+        uint64_t u64;
+        struct cvmx_lmcx_ops_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t opscnt_lo:32;
+#else
+                uint64_t opscnt_lo:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ops_cnt_lo_s cn30xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn31xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn38xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2;
+        struct cvmx_lmcx_ops_cnt_lo_s cn50xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn52xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1;
+        struct cvmx_lmcx_ops_cnt_lo_s cn56xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1;
+        struct cvmx_lmcx_ops_cnt_lo_s cn58xx;
+        struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1;
+};
+
+union cvmx_lmcx_phy_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_phy_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t rx_always_on:1;
+                uint64_t lv_mode:1;
+                uint64_t ck_tune1:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t loopback:1;
+                uint64_t loopback_pos:1;
+                uint64_t ts_stagger:1;
+#else
+                uint64_t ts_stagger:1;
+                uint64_t loopback_pos:1;
+                uint64_t loopback:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune1:1;
+                uint64_t lv_mode:1;
+                uint64_t rx_always_on:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+        struct cvmx_lmcx_phy_ctl_s cn61xx;
+        struct cvmx_lmcx_phy_ctl_s cn63xx;
+        struct cvmx_lmcx_phy_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t lv_mode:1;
+                uint64_t ck_tune1:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t loopback:1;
+                uint64_t loopback_pos:1;
+                uint64_t ts_stagger:1;
+#else
+                uint64_t ts_stagger:1;
+                uint64_t loopback_pos:1;
+                uint64_t loopback:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune1:1;
+                uint64_t lv_mode:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_phy_ctl_s cn66xx;
+        struct cvmx_lmcx_phy_ctl_s cn68xx;
+        struct cvmx_lmcx_phy_ctl_s cn68xxp1;
+        struct cvmx_lmcx_phy_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_pll_bwctl {
+        uint64_t u64;
+        struct cvmx_lmcx_pll_bwctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t bwupd:1;
+                uint64_t bwctl:4;
+#else
+                uint64_t bwctl:4;
+                uint64_t bwupd:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+        struct cvmx_lmcx_pll_bwctl_s cn30xx;
+        struct cvmx_lmcx_pll_bwctl_s cn31xx;
+        struct cvmx_lmcx_pll_bwctl_s cn38xx;
+        struct cvmx_lmcx_pll_bwctl_s cn38xxp2;
+};
+
+union cvmx_lmcx_pll_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_30_63:34;
+                uint64_t bypass:1;
+                uint64_t fasten_n:1;
+                uint64_t div_reset:1;
+                uint64_t reset_n:1;
+                uint64_t clkf:12;
+                uint64_t clkr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t en16:1;
+                uint64_t en12:1;
+                uint64_t en8:1;
+                uint64_t en6:1;
+                uint64_t en4:1;
+                uint64_t en2:1;
+#else
+                uint64_t en2:1;
+                uint64_t en4:1;
+                uint64_t en6:1;
+                uint64_t en8:1;
+                uint64_t en12:1;
+                uint64_t en16:1;
+                uint64_t reserved_6_7:2;
+                uint64_t clkr:6;
+                uint64_t clkf:12;
+                uint64_t reset_n:1;
+                uint64_t div_reset:1;
+                uint64_t fasten_n:1;
+                uint64_t bypass:1;
+                uint64_t reserved_30_63:34;
+#endif
+        } s;
+        struct cvmx_lmcx_pll_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t fasten_n:1;
+                uint64_t div_reset:1;
+                uint64_t reset_n:1;
+                uint64_t clkf:12;
+                uint64_t clkr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t en16:1;
+                uint64_t en12:1;
+                uint64_t en8:1;
+                uint64_t en6:1;
+                uint64_t en4:1;
+                uint64_t en2:1;
+#else
+                uint64_t en2:1;
+                uint64_t en4:1;
+                uint64_t en6:1;
+                uint64_t en8:1;
+                uint64_t en12:1;
+                uint64_t en16:1;
+                uint64_t reserved_6_7:2;
+                uint64_t clkr:6;
+                uint64_t clkf:12;
+                uint64_t reset_n:1;
+                uint64_t div_reset:1;
+                uint64_t fasten_n:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_pll_ctl_s cn52xx;
+        struct cvmx_lmcx_pll_ctl_s cn52xxp1;
+        struct cvmx_lmcx_pll_ctl_cn50xx cn56xx;
+        struct cvmx_lmcx_pll_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t div_reset:1;
+                uint64_t reset_n:1;
+                uint64_t clkf:12;
+                uint64_t clkr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t en16:1;
+                uint64_t en12:1;
+                uint64_t en8:1;
+                uint64_t en6:1;
+                uint64_t en4:1;
+                uint64_t en2:1;
+#else
+                uint64_t en2:1;
+                uint64_t en4:1;
+                uint64_t en6:1;
+                uint64_t en8:1;
+                uint64_t en12:1;
+                uint64_t en16:1;
+                uint64_t reserved_6_7:2;
+                uint64_t clkr:6;
+                uint64_t clkf:12;
+                uint64_t reset_n:1;
+                uint64_t div_reset:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn56xxp1;
+        struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx;
+        struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1;
+};
+
+union cvmx_lmcx_pll_status {
+        uint64_t u64;
+        struct cvmx_lmcx_pll_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:5;
+                uint64_t ddr__pctl:5;
+                uint64_t reserved_2_21:20;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t reserved_2_21:20;
+                uint64_t ddr__pctl:5;
+                uint64_t ddr__nctl:5;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_pll_status_s cn50xx;
+        struct cvmx_lmcx_pll_status_s cn52xx;
+        struct cvmx_lmcx_pll_status_s cn52xxp1;
+        struct cvmx_lmcx_pll_status_s cn56xx;
+        struct cvmx_lmcx_pll_status_s cn56xxp1;
+        struct cvmx_lmcx_pll_status_s cn58xx;
+        struct cvmx_lmcx_pll_status_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn58xxp1;
+};
+
+union cvmx_lmcx_read_level_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_read_level_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t rankmask:4;
+                uint64_t pattern:8;
+                uint64_t row:16;
+                uint64_t col:12;
+                uint64_t reserved_3_3:1;
+                uint64_t bnk:3;
+#else
+                uint64_t bnk:3;
+                uint64_t reserved_3_3:1;
+                uint64_t col:12;
+                uint64_t row:16;
+                uint64_t pattern:8;
+                uint64_t rankmask:4;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+        struct cvmx_lmcx_read_level_ctl_s cn52xx;
+        struct cvmx_lmcx_read_level_ctl_s cn52xxp1;
+        struct cvmx_lmcx_read_level_ctl_s cn56xx;
+        struct cvmx_lmcx_read_level_ctl_s cn56xxp1;
+};
+
+union cvmx_lmcx_read_level_dbg {
+        uint64_t u64;
+        struct cvmx_lmcx_read_level_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bitmask:16;
+                uint64_t reserved_4_15:12;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t reserved_4_15:12;
+                uint64_t bitmask:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_read_level_dbg_s cn52xx;
+        struct cvmx_lmcx_read_level_dbg_s cn52xxp1;
+        struct cvmx_lmcx_read_level_dbg_s cn56xx;
+        struct cvmx_lmcx_read_level_dbg_s cn56xxp1;
+};
+
+union cvmx_lmcx_read_level_rankx {
+        uint64_t u64;
+        struct cvmx_lmcx_read_level_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t status:2;
+                uint64_t byte8:4;
+                uint64_t byte7:4;
+                uint64_t byte6:4;
+                uint64_t byte5:4;
+                uint64_t byte4:4;
+                uint64_t byte3:4;
+                uint64_t byte2:4;
+                uint64_t byte1:4;
+                uint64_t byte0:4;
+#else
+                uint64_t byte0:4;
+                uint64_t byte1:4;
+                uint64_t byte2:4;
+                uint64_t byte3:4;
+                uint64_t byte4:4;
+                uint64_t byte5:4;
+                uint64_t byte6:4;
+                uint64_t byte7:4;
+                uint64_t byte8:4;
+                uint64_t status:2;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+        struct cvmx_lmcx_read_level_rankx_s cn52xx;
+        struct cvmx_lmcx_read_level_rankx_s cn52xxp1;
+        struct cvmx_lmcx_read_level_rankx_s cn56xx;
+        struct cvmx_lmcx_read_level_rankx_s cn56xxp1;
+};
+
+union cvmx_lmcx_reset_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_reset_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t ddr3psv:1;
+                uint64_t ddr3psoft:1;
+                uint64_t ddr3pwarm:1;
+                uint64_t ddr3rst:1;
+#else
+                uint64_t ddr3rst:1;
+                uint64_t ddr3pwarm:1;
+                uint64_t ddr3psoft:1;
+                uint64_t ddr3psv:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+        struct cvmx_lmcx_reset_ctl_s cn61xx;
+        struct cvmx_lmcx_reset_ctl_s cn63xx;
+        struct cvmx_lmcx_reset_ctl_s cn63xxp1;
+        struct cvmx_lmcx_reset_ctl_s cn66xx;
+        struct cvmx_lmcx_reset_ctl_s cn68xx;
+        struct cvmx_lmcx_reset_ctl_s cn68xxp1;
+        struct cvmx_lmcx_reset_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_rlevel_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_rlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t delay_unload_3:1;
+                uint64_t delay_unload_2:1;
+                uint64_t delay_unload_1:1;
+                uint64_t delay_unload_0:1;
+                uint64_t bitmask:8;
+                uint64_t or_dis:1;
+                uint64_t offset_en:1;
+                uint64_t offset:4;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t offset:4;
+                uint64_t offset_en:1;
+                uint64_t or_dis:1;
+                uint64_t bitmask:8;
+                uint64_t delay_unload_0:1;
+                uint64_t delay_unload_1:1;
+                uint64_t delay_unload_2:1;
+                uint64_t delay_unload_3:1;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_lmcx_rlevel_ctl_s cn61xx;
+        struct cvmx_lmcx_rlevel_ctl_s cn63xx;
+        struct cvmx_lmcx_rlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t offset_en:1;
+                uint64_t offset:4;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t offset:4;
+                uint64_t offset_en:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_rlevel_ctl_s cn66xx;
+        struct cvmx_lmcx_rlevel_ctl_s cn68xx;
+        struct cvmx_lmcx_rlevel_ctl_s cn68xxp1;
+        struct cvmx_lmcx_rlevel_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_rlevel_dbg {
+        uint64_t u64;
+        struct cvmx_lmcx_rlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bitmask:64;
+#else
+                uint64_t bitmask:64;
+#endif
+        } s;
+        struct cvmx_lmcx_rlevel_dbg_s cn61xx;
+        struct cvmx_lmcx_rlevel_dbg_s cn63xx;
+        struct cvmx_lmcx_rlevel_dbg_s cn63xxp1;
+        struct cvmx_lmcx_rlevel_dbg_s cn66xx;
+        struct cvmx_lmcx_rlevel_dbg_s cn68xx;
+        struct cvmx_lmcx_rlevel_dbg_s cn68xxp1;
+        struct cvmx_lmcx_rlevel_dbg_s cnf71xx;
+};
+
+union cvmx_lmcx_rlevel_rankx {
+        uint64_t u64;
+        struct cvmx_lmcx_rlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t status:2;
+                uint64_t byte8:6;
+                uint64_t byte7:6;
+                uint64_t byte6:6;
+                uint64_t byte5:6;
+                uint64_t byte4:6;
+                uint64_t byte3:6;
+                uint64_t byte2:6;
+                uint64_t byte1:6;
+                uint64_t byte0:6;
+#else
+                uint64_t byte0:6;
+                uint64_t byte1:6;
+                uint64_t byte2:6;
+                uint64_t byte3:6;
+                uint64_t byte4:6;
+                uint64_t byte5:6;
+                uint64_t byte6:6;
+                uint64_t byte7:6;
+                uint64_t byte8:6;
+                uint64_t status:2;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+        struct cvmx_lmcx_rlevel_rankx_s cn61xx;
+        struct cvmx_lmcx_rlevel_rankx_s cn63xx;
+        struct cvmx_lmcx_rlevel_rankx_s cn63xxp1;
+        struct cvmx_lmcx_rlevel_rankx_s cn66xx;
+        struct cvmx_lmcx_rlevel_rankx_s cn68xx;
+        struct cvmx_lmcx_rlevel_rankx_s cn68xxp1;
+        struct cvmx_lmcx_rlevel_rankx_s cnf71xx;
+};
+
+union cvmx_lmcx_rodt_comp_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_rodt_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t enable:1;
+                uint64_t reserved_12_15:4;
+                uint64_t nctl:4;
+                uint64_t reserved_5_7:3;
+                uint64_t pctl:5;
+#else
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:4;
+                uint64_t reserved_12_15:4;
+                uint64_t enable:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn50xx;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn52xx;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn56xx;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn58xx;
+        struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1;
+};
+
+union cvmx_lmcx_rodt_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_rodt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rodt_hi3:4;
+                uint64_t rodt_hi2:4;
+                uint64_t rodt_hi1:4;
+                uint64_t rodt_hi0:4;
+                uint64_t rodt_lo3:4;
+                uint64_t rodt_lo2:4;
+                uint64_t rodt_lo1:4;
+                uint64_t rodt_lo0:4;
+#else
+                uint64_t rodt_lo0:4;
+                uint64_t rodt_lo1:4;
+                uint64_t rodt_lo2:4;
+                uint64_t rodt_lo3:4;
+                uint64_t rodt_hi0:4;
+                uint64_t rodt_hi1:4;
+                uint64_t rodt_hi2:4;
+                uint64_t rodt_hi3:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_rodt_ctl_s cn30xx;
+        struct cvmx_lmcx_rodt_ctl_s cn31xx;
+        struct cvmx_lmcx_rodt_ctl_s cn38xx;
+        struct cvmx_lmcx_rodt_ctl_s cn38xxp2;
+        struct cvmx_lmcx_rodt_ctl_s cn50xx;
+        struct cvmx_lmcx_rodt_ctl_s cn52xx;
+        struct cvmx_lmcx_rodt_ctl_s cn52xxp1;
+        struct cvmx_lmcx_rodt_ctl_s cn56xx;
+        struct cvmx_lmcx_rodt_ctl_s cn56xxp1;
+        struct cvmx_lmcx_rodt_ctl_s cn58xx;
+        struct cvmx_lmcx_rodt_ctl_s cn58xxp1;
+};
+
+union cvmx_lmcx_rodt_mask {
+        uint64_t u64;
+        struct cvmx_lmcx_rodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rodt_d3_r1:8;
+                uint64_t rodt_d3_r0:8;
+                uint64_t rodt_d2_r1:8;
+                uint64_t rodt_d2_r0:8;
+                uint64_t rodt_d1_r1:8;
+                uint64_t rodt_d1_r0:8;
+                uint64_t rodt_d0_r1:8;
+                uint64_t rodt_d0_r0:8;
+#else
+                uint64_t rodt_d0_r0:8;
+                uint64_t rodt_d0_r1:8;
+                uint64_t rodt_d1_r0:8;
+                uint64_t rodt_d1_r1:8;
+                uint64_t rodt_d2_r0:8;
+                uint64_t rodt_d2_r1:8;
+                uint64_t rodt_d3_r0:8;
+                uint64_t rodt_d3_r1:8;
+#endif
+        } s;
+        struct cvmx_lmcx_rodt_mask_s cn61xx;
+        struct cvmx_lmcx_rodt_mask_s cn63xx;
+        struct cvmx_lmcx_rodt_mask_s cn63xxp1;
+        struct cvmx_lmcx_rodt_mask_s cn66xx;
+        struct cvmx_lmcx_rodt_mask_s cn68xx;
+        struct cvmx_lmcx_rodt_mask_s cn68xxp1;
+        struct cvmx_lmcx_rodt_mask_s cnf71xx;
+};
+
+union cvmx_lmcx_scramble_cfg0 {
+        uint64_t u64;
+        struct cvmx_lmcx_scramble_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t key:64;
+#else
+                uint64_t key:64;
+#endif
+        } s;
+        struct cvmx_lmcx_scramble_cfg0_s cn61xx;
+        struct cvmx_lmcx_scramble_cfg0_s cn66xx;
+        struct cvmx_lmcx_scramble_cfg0_s cnf71xx;
+};
+
+union cvmx_lmcx_scramble_cfg1 {
+        uint64_t u64;
+        struct cvmx_lmcx_scramble_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t key:64;
+#else
+                uint64_t key:64;
+#endif
+        } s;
+        struct cvmx_lmcx_scramble_cfg1_s cn61xx;
+        struct cvmx_lmcx_scramble_cfg1_s cn66xx;
+        struct cvmx_lmcx_scramble_cfg1_s cnf71xx;
+};
+
+union cvmx_lmcx_scrambled_fadr {
+        uint64_t u64;
+        struct cvmx_lmcx_scrambled_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t fdimm:2;
+                uint64_t fbunk:1;
+                uint64_t fbank:3;
+                uint64_t frow:16;
+                uint64_t fcol:14;
+#else
+                uint64_t fcol:14;
+                uint64_t frow:16;
+                uint64_t fbank:3;
+                uint64_t fbunk:1;
+                uint64_t fdimm:2;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+        struct cvmx_lmcx_scrambled_fadr_s cn61xx;
+        struct cvmx_lmcx_scrambled_fadr_s cn66xx;
+        struct cvmx_lmcx_scrambled_fadr_s cnf71xx;
+};
+
+union cvmx_lmcx_slot_ctl0 {
+        uint64_t u64;
+        struct cvmx_lmcx_slot_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t w2w_init:6;
+                uint64_t w2r_init:6;
+                uint64_t r2w_init:6;
+                uint64_t r2r_init:6;
+#else
+                uint64_t r2r_init:6;
+                uint64_t r2w_init:6;
+                uint64_t w2r_init:6;
+                uint64_t w2w_init:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_lmcx_slot_ctl0_s cn61xx;
+        struct cvmx_lmcx_slot_ctl0_s cn63xx;
+        struct cvmx_lmcx_slot_ctl0_s cn63xxp1;
+        struct cvmx_lmcx_slot_ctl0_s cn66xx;
+        struct cvmx_lmcx_slot_ctl0_s cn68xx;
+        struct cvmx_lmcx_slot_ctl0_s cn68xxp1;
+        struct cvmx_lmcx_slot_ctl0_s cnf71xx;
+};
+
+union cvmx_lmcx_slot_ctl1 {
+        uint64_t u64;
+        struct cvmx_lmcx_slot_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t w2w_xrank_init:6;
+                uint64_t w2r_xrank_init:6;
+                uint64_t r2w_xrank_init:6;
+                uint64_t r2r_xrank_init:6;
+#else
+                uint64_t r2r_xrank_init:6;
+                uint64_t r2w_xrank_init:6;
+                uint64_t w2r_xrank_init:6;
+                uint64_t w2w_xrank_init:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_lmcx_slot_ctl1_s cn61xx;
+        struct cvmx_lmcx_slot_ctl1_s cn63xx;
+        struct cvmx_lmcx_slot_ctl1_s cn63xxp1;
+        struct cvmx_lmcx_slot_ctl1_s cn66xx;
+        struct cvmx_lmcx_slot_ctl1_s cn68xx;
+        struct cvmx_lmcx_slot_ctl1_s cn68xxp1;
+        struct cvmx_lmcx_slot_ctl1_s cnf71xx;
+};
+
+union cvmx_lmcx_slot_ctl2 {
+        uint64_t u64;
+        struct cvmx_lmcx_slot_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t w2w_xdimm_init:6;
+                uint64_t w2r_xdimm_init:6;
+                uint64_t r2w_xdimm_init:6;
+                uint64_t r2r_xdimm_init:6;
+#else
+                uint64_t r2r_xdimm_init:6;
+                uint64_t r2w_xdimm_init:6;
+                uint64_t w2r_xdimm_init:6;
+                uint64_t w2w_xdimm_init:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_lmcx_slot_ctl2_s cn61xx;
+        struct cvmx_lmcx_slot_ctl2_s cn63xx;
+        struct cvmx_lmcx_slot_ctl2_s cn63xxp1;
+        struct cvmx_lmcx_slot_ctl2_s cn66xx;
+        struct cvmx_lmcx_slot_ctl2_s cn68xx;
+        struct cvmx_lmcx_slot_ctl2_s cn68xxp1;
+        struct cvmx_lmcx_slot_ctl2_s cnf71xx;
+};
+
+union cvmx_lmcx_timing_params0 {
+        uint64_t u64;
+        struct cvmx_lmcx_timing_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t trp_ext:1;
+                uint64_t tcksre:4;
+                uint64_t trp:4;
+                uint64_t tzqinit:4;
+                uint64_t tdllk:4;
+                uint64_t tmod:4;
+                uint64_t tmrd:4;
+                uint64_t txpr:4;
+                uint64_t tcke:4;
+                uint64_t tzqcs:4;
+                uint64_t tckeon:10;
+#else
+                uint64_t tckeon:10;
+                uint64_t tzqcs:4;
+                uint64_t tcke:4;
+                uint64_t txpr:4;
+                uint64_t tmrd:4;
+                uint64_t tmod:4;
+                uint64_t tdllk:4;
+                uint64_t tzqinit:4;
+                uint64_t trp:4;
+                uint64_t tcksre:4;
+                uint64_t trp_ext:1;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+        struct cvmx_lmcx_timing_params0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t trp_ext:1;
+                uint64_t tcksre:4;
+                uint64_t trp:4;
+                uint64_t tzqinit:4;
+                uint64_t tdllk:4;
+                uint64_t tmod:4;
+                uint64_t tmrd:4;
+                uint64_t txpr:4;
+                uint64_t tcke:4;
+                uint64_t tzqcs:4;
+                uint64_t reserved_0_9:10;
+#else
+                uint64_t reserved_0_9:10;
+                uint64_t tzqcs:4;
+                uint64_t tcke:4;
+                uint64_t txpr:4;
+                uint64_t tmrd:4;
+                uint64_t tmod:4;
+                uint64_t tdllk:4;
+                uint64_t tzqinit:4;
+                uint64_t trp:4;
+                uint64_t tcksre:4;
+                uint64_t trp_ext:1;
+                uint64_t reserved_47_63:17;
+#endif
+        } cn61xx;
+        struct cvmx_lmcx_timing_params0_cn61xx cn63xx;
+        struct cvmx_lmcx_timing_params0_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t tcksre:4;
+                uint64_t trp:4;
+                uint64_t tzqinit:4;
+                uint64_t tdllk:4;
+                uint64_t tmod:4;
+                uint64_t tmrd:4;
+                uint64_t txpr:4;
+                uint64_t tcke:4;
+                uint64_t tzqcs:4;
+                uint64_t tckeon:10;
+#else
+                uint64_t tckeon:10;
+                uint64_t tzqcs:4;
+                uint64_t tcke:4;
+                uint64_t txpr:4;
+                uint64_t tmrd:4;
+                uint64_t tmod:4;
+                uint64_t tdllk:4;
+                uint64_t tzqinit:4;
+                uint64_t trp:4;
+                uint64_t tcksre:4;
+                uint64_t reserved_46_63:18;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_timing_params0_cn61xx cn66xx;
+        struct cvmx_lmcx_timing_params0_cn61xx cn68xx;
+        struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1;
+        struct cvmx_lmcx_timing_params0_cn61xx cnf71xx;
+};
+
+union cvmx_lmcx_timing_params1 {
+        uint64_t u64;
+        struct cvmx_lmcx_timing_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t tras_ext:1;
+                uint64_t txpdll:5;
+                uint64_t tfaw:5;
+                uint64_t twldqsen:4;
+                uint64_t twlmrd:4;
+                uint64_t txp:3;
+                uint64_t trrd:3;
+                uint64_t trfc:5;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+                uint64_t tmprr:4;
+#else
+                uint64_t tmprr:4;
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trfc:5;
+                uint64_t trrd:3;
+                uint64_t txp:3;
+                uint64_t twlmrd:4;
+                uint64_t twldqsen:4;
+                uint64_t tfaw:5;
+                uint64_t txpdll:5;
+                uint64_t tras_ext:1;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+        struct cvmx_lmcx_timing_params1_s cn61xx;
+        struct cvmx_lmcx_timing_params1_s cn63xx;
+        struct cvmx_lmcx_timing_params1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t txpdll:5;
+                uint64_t tfaw:5;
+                uint64_t twldqsen:4;
+                uint64_t twlmrd:4;
+                uint64_t txp:3;
+                uint64_t trrd:3;
+                uint64_t trfc:5;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+                uint64_t tmprr:4;
+#else
+                uint64_t tmprr:4;
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trfc:5;
+                uint64_t trrd:3;
+                uint64_t txp:3;
+                uint64_t twlmrd:4;
+                uint64_t twldqsen:4;
+                uint64_t tfaw:5;
+                uint64_t txpdll:5;
+                uint64_t reserved_46_63:18;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_timing_params1_s cn66xx;
+        struct cvmx_lmcx_timing_params1_s cn68xx;
+        struct cvmx_lmcx_timing_params1_s cn68xxp1;
+        struct cvmx_lmcx_timing_params1_s cnf71xx;
+};
+
+union cvmx_lmcx_tro_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_tro_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t rclk_cnt:32;
+                uint64_t treset:1;
+#else
+                uint64_t treset:1;
+                uint64_t rclk_cnt:32;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+        struct cvmx_lmcx_tro_ctl_s cn61xx;
+        struct cvmx_lmcx_tro_ctl_s cn63xx;
+        struct cvmx_lmcx_tro_ctl_s cn63xxp1;
+        struct cvmx_lmcx_tro_ctl_s cn66xx;
+        struct cvmx_lmcx_tro_ctl_s cn68xx;
+        struct cvmx_lmcx_tro_ctl_s cn68xxp1;
+        struct cvmx_lmcx_tro_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_tro_stat {
+        uint64_t u64;
+        struct cvmx_lmcx_tro_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ring_cnt:32;
+#else
+                uint64_t ring_cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_tro_stat_s cn61xx;
+        struct cvmx_lmcx_tro_stat_s cn63xx;
+        struct cvmx_lmcx_tro_stat_s cn63xxp1;
+        struct cvmx_lmcx_tro_stat_s cn66xx;
+        struct cvmx_lmcx_tro_stat_s cn68xx;
+        struct cvmx_lmcx_tro_stat_s cn68xxp1;
+        struct cvmx_lmcx_tro_stat_s cnf71xx;
+};
+
+union cvmx_lmcx_wlevel_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_wlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t rtt_nom:3;
+                uint64_t bitmask:8;
+                uint64_t or_dis:1;
+                uint64_t sset:1;
+                uint64_t lanemask:9;
+#else
+                uint64_t lanemask:9;
+                uint64_t sset:1;
+                uint64_t or_dis:1;
+                uint64_t bitmask:8;
+                uint64_t rtt_nom:3;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_lmcx_wlevel_ctl_s cn61xx;
+        struct cvmx_lmcx_wlevel_ctl_s cn63xx;
+        struct cvmx_lmcx_wlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t sset:1;
+                uint64_t lanemask:9;
+#else
+                uint64_t lanemask:9;
+                uint64_t sset:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_wlevel_ctl_s cn66xx;
+        struct cvmx_lmcx_wlevel_ctl_s cn68xx;
+        struct cvmx_lmcx_wlevel_ctl_s cn68xxp1;
+        struct cvmx_lmcx_wlevel_ctl_s cnf71xx;
+};
+
+union cvmx_lmcx_wlevel_dbg {
+        uint64_t u64;
+        struct cvmx_lmcx_wlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t bitmask:8;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t bitmask:8;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_lmcx_wlevel_dbg_s cn61xx;
+        struct cvmx_lmcx_wlevel_dbg_s cn63xx;
+        struct cvmx_lmcx_wlevel_dbg_s cn63xxp1;
+        struct cvmx_lmcx_wlevel_dbg_s cn66xx;
+        struct cvmx_lmcx_wlevel_dbg_s cn68xx;
+        struct cvmx_lmcx_wlevel_dbg_s cn68xxp1;
+        struct cvmx_lmcx_wlevel_dbg_s cnf71xx;
+};
+
+union cvmx_lmcx_wlevel_rankx {
+        uint64_t u64;
+        struct cvmx_lmcx_wlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t status:2;
+                uint64_t byte8:5;
+                uint64_t byte7:5;
+                uint64_t byte6:5;
+                uint64_t byte5:5;
+                uint64_t byte4:5;
+                uint64_t byte3:5;
+                uint64_t byte2:5;
+                uint64_t byte1:5;
+                uint64_t byte0:5;
+#else
+                uint64_t byte0:5;
+                uint64_t byte1:5;
+                uint64_t byte2:5;
+                uint64_t byte3:5;
+                uint64_t byte4:5;
+                uint64_t byte5:5;
+                uint64_t byte6:5;
+                uint64_t byte7:5;
+                uint64_t byte8:5;
+                uint64_t status:2;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+        struct cvmx_lmcx_wlevel_rankx_s cn61xx;
+        struct cvmx_lmcx_wlevel_rankx_s cn63xx;
+        struct cvmx_lmcx_wlevel_rankx_s cn63xxp1;
+        struct cvmx_lmcx_wlevel_rankx_s cn66xx;
+        struct cvmx_lmcx_wlevel_rankx_s cn68xx;
+        struct cvmx_lmcx_wlevel_rankx_s cn68xxp1;
+        struct cvmx_lmcx_wlevel_rankx_s cnf71xx;
+};
+
+union cvmx_lmcx_wodt_ctl0 {
+        uint64_t u64;
+        struct cvmx_lmcx_wodt_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wodt_d1_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d0_r0:8;
+#else
+                uint64_t wodt_d0_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d1_r1:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx;
+        struct cvmx_lmcx_wodt_ctl0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wodt_hi3:4;
+                uint64_t wodt_hi2:4;
+                uint64_t wodt_hi1:4;
+                uint64_t wodt_hi0:4;
+                uint64_t wodt_lo3:4;
+                uint64_t wodt_lo2:4;
+                uint64_t wodt_lo1:4;
+                uint64_t wodt_lo0:4;
+#else
+                uint64_t wodt_lo0:4;
+                uint64_t wodt_lo1:4;
+                uint64_t wodt_lo2:4;
+                uint64_t wodt_lo3:4;
+                uint64_t wodt_hi0:4;
+                uint64_t wodt_hi1:4;
+                uint64_t wodt_hi2:4;
+                uint64_t wodt_hi3:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+        struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2;
+        struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1;
+        struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx;
+        struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1;
+};
+
+union cvmx_lmcx_wodt_ctl1 {
+        uint64_t u64;
+        struct cvmx_lmcx_wodt_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wodt_d3_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d2_r0:8;
+#else
+                uint64_t wodt_d2_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d3_r1:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_wodt_ctl1_s cn30xx;
+        struct cvmx_lmcx_wodt_ctl1_s cn31xx;
+        struct cvmx_lmcx_wodt_ctl1_s cn52xx;
+        struct cvmx_lmcx_wodt_ctl1_s cn52xxp1;
+        struct cvmx_lmcx_wodt_ctl1_s cn56xx;
+        struct cvmx_lmcx_wodt_ctl1_s cn56xxp1;
+};
+
+union cvmx_lmcx_wodt_mask {
+        uint64_t u64;
+        struct cvmx_lmcx_wodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wodt_d3_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d2_r0:8;
+                uint64_t wodt_d1_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d0_r0:8;
+#else
+                uint64_t wodt_d0_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d1_r1:8;
+                uint64_t wodt_d2_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d3_r1:8;
+#endif
+        } s;
+        struct cvmx_lmcx_wodt_mask_s cn61xx;
+        struct cvmx_lmcx_wodt_mask_s cn63xx;
+        struct cvmx_lmcx_wodt_mask_s cn63xxp1;
+        struct cvmx_lmcx_wodt_mask_s cn66xx;
+        struct cvmx_lmcx_wodt_mask_s cn68xx;
+        struct cvmx_lmcx_wodt_mask_s cn68xxp1;
+        struct cvmx_lmcx_wodt_mask_s cnf71xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 14dd11f4492a..349bb2ba840c 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -218,6 +218,12 @@
 #define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
 #define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
 
+/* These are used to cover entire families of OCTEON processors */
+#define OCTEON_FAM_1            (OCTEON_CN3XXX)
+#define OCTEON_FAM_PLUS         (OCTEON_CN5XXX)
+#define OCTEON_FAM_1_PLUS       (OCTEON_FAM_PLUS | OM_MATCH_PREVIOUS_MODELS)
+#define OCTEON_FAM_2            (OCTEON_CN6XXX)
+
 /* The revision byte (low byte) has two different encodings.
  * CN3XXX:
  *
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 790939dd8244..254e9954ed71 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -209,13 +209,6 @@ union octeon_cvmemctl {
         } s;
 };
 
-struct octeon_cf_data {
-        unsigned long   base_region_bias;
-        unsigned int    base_region;    /* The chip select region used by CF */
-        int             is16bit;        /* 0 - 8bit, !0 - 16bit */
-        int             dma_engine;     /* -1 for no DMA */
-};
-
 extern void octeon_write_lcd(const char *s);
 extern void octeon_check_cpu_bist(void);
 extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index da9bd7d270d1..31ab10f02bad 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,19 +31,19 @@
 #define PAGE_SHIFT      16
 #endif
 #define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
+#define PAGE_MASK       (~(PAGE_SIZE - 1))
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 #define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
 #define HPAGE_SIZE      (_AC(1,UL) << HPAGE_SHIFT)
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
-#else /* !CONFIG_HUGETLB_PAGE */
+#else /* !CONFIG_MIPS_HUGE_TLB_SUPPORT */
 #define HPAGE_SHIFT     ({BUILD_BUG(); 0; })
 #define HPAGE_SIZE      ({BUILD_BUG(); 0; })
 #define HPAGE_MASK      ({BUILD_BUG(); 0; })
 #define HUGETLB_PAGE_ORDER      ({BUILD_BUG(); 0; })
-#endif /* CONFIG_HUGETLB_PAGE */
+#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index f5b521d5a67d..c63191055e69 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -175,7 +175,7 @@ static inline int pmd_none(pmd_t pmd)
 
 static inline int pmd_bad(pmd_t pmd)
 {
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         /* pmd_huge(pmd) but inline */
         if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
                 return 0;
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index da4ba49adcf6..f6a0439a4085 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -34,38 +34,72 @@
  */
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 
-#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
-#define _PAGE_READ                  (1<<7)  /* implemented in software */
-#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
-#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
-#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
-#define _PAGE_FILE                  (1<<10) /* set:pagecache unset:swap */
-
-#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
-#define _PAGE_GLOBAL                (1<<0)
-#define _PAGE_VALID                 (1<<1)
-#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
-#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE          (1<<2)
-#define _CACHE_SHIFT                3
-#define _CACHE_MASK                 (7<<3)
+/*
+ * The following bits are directly used by the TLB hardware
+ */
+#define _PAGE_R4KBUG            (1 << 0)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL            (1 << 0)
+#define _PAGE_VALID_SHIFT       1
+#define _PAGE_VALID             (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_SILENT_READ       (1 << 1)  /* synonym                 */
+#define _PAGE_DIRTY_SHIFT       2
+#define _PAGE_DIRTY             (1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE      (1 << 2)
+#define _CACHE_SHIFT            3
+#define _CACHE_MASK             (7 << 3)
+
+/*
+ * The following bits are implemented in software
+ *
+ * _PAGE_FILE semantics: set:pagecache unset:swap
+ */ 
+#define _PAGE_PRESENT_SHIFT     6
+#define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT        7
+#define _PAGE_READ              (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT       8
+#define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT    9
+#define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT    10
+#define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
+
+#define _PAGE_FILE              (1 << 10)
 
 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
-#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
-#define _PAGE_READ                  (1<<1)  /* implemented in software */
-#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
-#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
-#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
-#define _PAGE_FILE                  (1<<4)  /* set:pagecache unset:swap */
-
-#define _PAGE_GLOBAL                (1<<8)
-#define _PAGE_VALID                 (1<<9)
-#define _PAGE_SILENT_READ           (1<<9)  /* synonym                 */
-#define _PAGE_DIRTY                 (1<<10) /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE          (1<<10)
-#define _CACHE_UNCACHED             (1<<11)
-#define _CACHE_MASK                 (1<<11)
+/*
+ * The following are implemented by software
+ *
+ * _PAGE_FILE semantics: set:pagecache unset:swap
+ */
+#define _PAGE_PRESENT_SHIFT     0
+#define _PAGE_PRESENT           (1 <<  _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT        1
+#define _PAGE_READ              (1 <<  _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT       2
+#define _PAGE_WRITE             (1 <<  _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT    3
+#define _PAGE_ACCESSED          (1 <<  _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT    4
+#define _PAGE_MODIFIED          (1 <<  _PAGE_MODIFIED_SHIFT)
+#define _PAGE_FILE_SHIFT        4
+#define _PAGE_FILE              (1 <<  _PAGE_FILE_SHIFT)
+
+/*
+ * And these are the hardware TLB bits
+ */
+#define _PAGE_GLOBAL_SHIFT      8
+#define _PAGE_GLOBAL            (1 <<  _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT       9
+#define _PAGE_VALID             (1 <<  _PAGE_VALID_SHIFT)
+#define _PAGE_SILENT_READ       (1 <<  _PAGE_VALID_SHIFT)       /* synonym  */
+#define _PAGE_DIRTY_SHIFT       10
+#define _PAGE_DIRTY             (1 << _PAGE_DIRTY_SHIFT)
+#define _PAGE_SILENT_WRITE      (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_UNCACHED_SHIFT   11
+#define _CACHE_UNCACHED         (1 << _CACHE_UNCACHED_SHIFT)
+#define _CACHE_MASK             (1 << _CACHE_UNCACHED_SHIFT)
 
 #else /* 'Normal' r4K case */
 /*
@@ -76,25 +110,25 @@
  * which is more than we need right now.
  */
 
-/* implemented in software */
+/*
+ * The following bits are implemented in software
+ *
+ * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
+ * _PAGE_FILE semantics: set:pagecache unset:swap
+ */
 #define _PAGE_PRESENT_SHIFT     (0)
 #define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
-/* implemented in software, should be unused if cpu_has_rixi. */
 #define _PAGE_READ_SHIFT        (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
 #define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
-/* implemented in software */
 #define _PAGE_WRITE_SHIFT       (_PAGE_READ_SHIFT + 1)
 #define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
-/* implemented in software */
 #define _PAGE_ACCESSED_SHIFT    (_PAGE_WRITE_SHIFT + 1)
 #define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
-/* implemented in software */
 #define _PAGE_MODIFIED_SHIFT    (_PAGE_ACCESSED_SHIFT + 1)
 #define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
-/* set:pagecache unset:swap */
 #define _PAGE_FILE              (_PAGE_MODIFIED)
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 /* huge tlb page */
 #define _PAGE_HUGE_SHIFT        (_PAGE_MODIFIED_SHIFT + 1)
 #define _PAGE_HUGE              (1 << _PAGE_HUGE_SHIFT)
@@ -103,8 +137,17 @@
 #define _PAGE_HUGE              ({BUG(); 1; })  /* Dummy value */
 #endif
 
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+/* huge tlb page */
+#define _PAGE_SPLITTING_SHIFT   (_PAGE_HUGE_SHIFT + 1)
+#define _PAGE_SPLITTING         (1 << _PAGE_SPLITTING_SHIFT)
+#else
+#define _PAGE_SPLITTING_SHIFT   (_PAGE_HUGE_SHIFT)
+#define _PAGE_SPLITTING         ({BUG(); 1; })  /* Dummy value */
+#endif
+
 /* Page cannot be executed */
-#define _PAGE_NO_EXEC_SHIFT     (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
+#define _PAGE_NO_EXEC_SHIFT     (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT)
 #define _PAGE_NO_EXEC           ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
 
 /* Page cannot be read */
@@ -192,20 +235,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
-#elif defined(CONFIG_CPU_RM9000)
-
-#define _CACHE_WT                   (0<<_CACHE_SHIFT)
-#define _CACHE_WTWA                 (1<<_CACHE_SHIFT)
-#define _CACHE_UC_B                 (2<<_CACHE_SHIFT)
-#define _CACHE_WB                   (3<<_CACHE_SHIFT)
-#define _CACHE_CWBEA                (4<<_CACHE_SHIFT)
-#define _CACHE_CWB                  (5<<_CACHE_SHIFT)
-#define _CACHE_UCNB                 (6<<_CACHE_SHIFT)
-#define _CACHE_FPC                  (7<<_CACHE_SHIFT)
-
-#define _CACHE_UNCACHED             _CACHE_UC_B
-#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
-
 #else
 
 #define _CACHE_CACHABLE_NO_WA       (0<<_CACHE_SHIFT)  /* R4600 only      */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index c02158be836c..252202d24a84 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -8,6 +8,7 @@
 #ifndef _ASM_PGTABLE_H
 #define _ASM_PGTABLE_H
 
+#include <linux/mmzone.h>
 #ifdef CONFIG_32BIT
 #include <asm/pgtable-32.h>
 #endif
@@ -94,7 +95,12 @@ extern void paging_init(void);
  * and a page entry and page directory to the page they refer to.
  */
 #define pmd_phys(pmd)           virt_to_phys((void *)pmd_val(pmd))
-#define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
+
+#define __pmd_page(pmd)         (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
+#ifndef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_page(pmd)           __pmd_page(pmd)
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */
+
 #define pmd_page_vaddr(pmd)     pmd_val(pmd)
 
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
@@ -107,7 +113,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
         ptep->pte_high = pte.pte_high;
         smp_wmb();
         ptep->pte_low = pte.pte_low;
-        //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
 
         if (pte.pte_low & _PAGE_GLOBAL) {
                 pte_t *buddy = ptep_buddy(ptep);
@@ -375,6 +380,14 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
         __update_cache(vma, address, pte);
 }
 
+static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
+        unsigned long address, pmd_t *pmdp)
+{
+        pte_t pte = *(pte_t *)pmdp;
+
+        __update_tlb(vma, address, pte);
+}
+
 #define kern_addr_valid(addr)   (1)
 
 #ifdef CONFIG_64BIT_PHYS_ADDR
@@ -394,6 +407,157 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 #endif
 
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+extern int has_transparent_hugepage(void);
+
+static inline int pmd_trans_huge(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_HUGE);
+}
+
+static inline pmd_t pmd_mkhuge(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_HUGE;
+
+        return pmd;
+}
+
+static inline int pmd_trans_splitting(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_SPLITTING);
+}
+
+static inline pmd_t pmd_mksplitting(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_SPLITTING;
+
+        return pmd;
+}
+
+extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                       pmd_t *pmdp, pmd_t pmd);
+
+#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
+/* Extern to avoid header file madness */
+extern void pmdp_splitting_flush(struct vm_area_struct *vma,
+                                        unsigned long address,
+                                        pmd_t *pmdp);
+
+#define __HAVE_ARCH_PMD_WRITE
+static inline int pmd_write(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_WRITE);
+}
+
+static inline pmd_t pmd_wrprotect(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        return pmd;
+}
+
+static inline pmd_t pmd_mkwrite(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_WRITE;
+        if (pmd_val(pmd) & _PAGE_MODIFIED)
+                pmd_val(pmd) |= _PAGE_SILENT_WRITE;
+
+        return pmd;
+}
+
+static inline int pmd_dirty(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_MODIFIED);
+}
+
+static inline pmd_t pmd_mkclean(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
+        return pmd;
+}
+
+static inline pmd_t pmd_mkdirty(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_MODIFIED;
+        if (pmd_val(pmd) & _PAGE_WRITE)
+                pmd_val(pmd) |= _PAGE_SILENT_WRITE;
+
+        return pmd;
+}
+
+static inline int pmd_young(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_ACCESSED);
+}
+
+static inline pmd_t pmd_mkold(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+
+        return pmd;
+}
+
+static inline pmd_t pmd_mkyoung(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_ACCESSED;
+
+        if (cpu_has_rixi) {
+                if (!(pmd_val(pmd) & _PAGE_NO_READ))
+                        pmd_val(pmd) |= _PAGE_SILENT_READ;
+        } else {
+                if (pmd_val(pmd) & _PAGE_READ)
+                        pmd_val(pmd) |= _PAGE_SILENT_READ;
+        }
+
+        return pmd;
+}
+
+/* Extern to avoid header file madness */
+extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
+
+static inline unsigned long pmd_pfn(pmd_t pmd)
+{
+        return pmd_val(pmd) >> _PFN_SHIFT;
+}
+
+static inline struct page *pmd_page(pmd_t pmd)
+{
+        if (pmd_trans_huge(pmd))
+                return pfn_to_page(pmd_pfn(pmd));
+
+        return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
+}
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+        pmd_val(pmd) = (pmd_val(pmd) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+        return pmd;
+}
+
+static inline pmd_t pmd_mknotpresent(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
+
+        return pmd;
+}
+
+/*
+ * The generic version pmdp_get_and_clear uses a version of pmd_clear() with a
+ * different prototype.
+ */
+#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
+static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
+                                       unsigned long address, pmd_t *pmdp)
+{
+        pmd_t old = *pmdp;
+
+        pmd_clear(pmdp);
+
+        return old;
+}
+
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
 #include <asm-generic/pgtable.h>
 
 /*
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
index 9e2ee429c529..c74eb1657f5f 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 5e33fabe354d..8481c1a5219e 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -226,8 +226,6 @@ struct thread_struct {
         unsigned long cp0_badvaddr;     /* Last user fault */
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
         unsigned long error_code;
-        unsigned long irix_trampoline;  /* Wheee... */
-        unsigned long irix_oldctx;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
     struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
     struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
@@ -297,8 +295,6 @@ struct thread_struct {
         .cp0_badvaddr           = 0,                            \
         .cp0_baduaddr           = 0,                            \
         .error_code             = 0,                            \
-        .irix_trampoline        = 0,                            \
-        .irix_oldctx            = 0,                            \
         /*                                                      \
          * Cavium Octeon specifics (null if not Octeon)         \
          */                                                     \
diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
index 149342951436..3dce7c788b3e 100644
--- a/arch/mips/include/asm/sgiarcs.h
+++ b/arch/mips/include/asm/sgiarcs.h
@@ -366,7 +366,7 @@ struct linux_smonblock {
  * Macros for calling a 32-bit ARC implementation from 64-bit code
  */
 
-#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
+#if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
 
 #define __arc_clobbers                                                  \
         "$2", "$3" /* ... */, "$8", "$9", "$10", "$11",                         \
@@ -475,10 +475,10 @@ struct linux_smonblock {
         __res;                                                          \
 })
 
-#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */
+#endif /* defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32) */
 
-#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) ||         \
-    (defined(CONFIG_64BIT) && defined(CONFIG_ARC64))
+#if (defined(CONFIG_32BIT) && defined(CONFIG_FW_ARC32)) ||              \
+    (defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC64))
 
 #define ARC_CALL0(dest)                                                 \
 ({      long __res;                                                     \
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index d4fb4d852a6d..f33b5fd6972b 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -40,6 +40,8 @@ extern int __cpu_logical_map[NR_CPUS];
 #define SMP_CALL_FUNCTION       0x2
 /* Octeon - Tell another core to flush its icache */
 #define SMP_ICACHE_FLUSH        0x4
+/* Used by kexec crashdump to save all cpu's state */
+#define SMP_DUMP                0x8
 
 extern volatile cpumask_t cpu_callin_map;
 
@@ -91,4 +93,8 @@ static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
         mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
 }
 
+#if defined(CONFIG_KEXEC)
+extern void (*dump_ipi_function_ptr)(void *);
+void dump_send_ipi(void (*dump_ipi_callback)(void *));
+#endif
 #endif /* __ASM_SMP_H */
diff --git a/arch/mips/include/asm/smvp.h b/arch/mips/include/asm/smvp.h
deleted file mode 100644
index 0d0e80a39e8a..000000000000
--- a/arch/mips/include/asm/smvp.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_SMVP_H
-#define _ASM_SMVP_H
-
-/*
- * Definitions for SMVP multitasking on MIPS MT cores
- */
-struct task_struct;
-
-extern void smvp_smp_setup(void);
-extern void smvp_smp_finish(void);
-extern void smvp_boot_secondary(int cpu, struct task_struct *t);
-extern void smvp_init_secondary(void);
-extern void smvp_smp_finish(void);
-extern void smvp_cpus_done(void);
-extern void smvp_prepare_cpus(unsigned int max_cpus);
-
-/* This is platform specific */
-extern void smvp_send_ipi(int cpu, unsigned int action);
-#endif /*  _ASM_SMVP_H */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 4461198361c9..65900dab3ad3 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -6,7 +6,7 @@
  * SECTION_SIZE_BITS            2^N: how big each section will be
  * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
  */
-#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PAGE_SIZE_64KB)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
 # define SECTION_SIZE_BITS      29
 #else
 # define SECTION_SIZE_BITS      28
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 8debe9e91754..18806a52061c 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -112,12 +112,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_LOAD_WATCH          25      /* If set, load watch registers */
 #define TIF_SYSCALL_TRACE       31      /* syscall trace active */
 
-#ifdef CONFIG_MIPS32_O32
-#define TIF_32BIT TIF_32BIT_REGS
-#elif defined(CONFIG_MIPS32_N32)
-#define TIF_32BIT _TIF_32BIT_ADDR
-#endif /* CONFIG_MIPS32_O32 */
-
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index bc14447e69b5..761f2e92119e 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,10 +50,8 @@ extern int (*perf_irq)(void);
 /*
  * Initialize the calling CPU's compare interrupt as clockevent device
  */
-#ifdef CONFIG_CEVT_R4K_LIB
 extern unsigned int __weak get_c0_compare_int(void);
 extern int r4k_clockevent_init(void);
-#endif
 
 static inline int mips_clockevent_init(void)
 {
@@ -71,7 +69,7 @@ static inline int mips_clockevent_init(void)
 /*
  * Initialize the count register as a clocksource
  */
-#ifdef CONFIG_CSRC_R4K_LIB
+#ifdef CONFIG_CSRC_R4K
 extern int init_r4k_clocksource(void);
 #endif
 
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
deleted file mode 100644
index fee1908c65d2..000000000000
--- a/arch/mips/include/asm/titan_dep.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Board specific definititions for the PMC-Sierra Yosemite
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __TITAN_DEP_H__
-#define __TITAN_DEP_H__
-
-#include <asm/addrspace.h>              /* for KSEG1ADDR() */
-#include <asm/byteorder.h>              /* for cpu_to_le32() */
-
-#define TITAN_READ(ofs)                                                 \
-        (*(volatile u32 *)(ocd_base+(ofs)))
-#define TITAN_READ_16(ofs)                                              \
-        (*(volatile u16 *)(ocd_base+(ofs)))
-#define TITAN_READ_8(ofs)                                               \
-        (*(volatile u8 *)(ocd_base+(ofs)))
-
-#define TITAN_WRITE(ofs, data)                                          \
-        do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
-#define TITAN_WRITE_16(ofs, data)                                       \
-        do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
-#define TITAN_WRITE_8(ofs, data)                                        \
-        do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
-
-/*
- * PCI specific defines
- */
-#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
-#define TITAN_PCI_0_CONFIG_DATA         0x784
-
-/*
- * HT specific defines
- */
-#define RM9000x2_HTLINK_REG             0xbb000644
-#define RM9000x2_BASE_ADDR              0xbb000000
-
-#define OCD_BASE                        0xfb000000UL
-#define OCD_SIZE                        0x3000UL
-
-extern unsigned long ocd_base;
-
-/*
- * OCD Registers
- */
-#define RM9000x2_OCD_LKB5               0x0128          /* Ethernet */
-#define RM9000x2_OCD_LKM5               0x012c
-
-#define RM9000x2_OCD_LKB7               0x0138          /* HT Region 0 */
-#define RM9000x2_OCD_LKM7               0x013c
-#define RM9000x2_OCD_LKB8               0x0140          /* HT Region 1 */
-#define RM9000x2_OCD_LKM8               0x0144
-
-#define RM9000x2_OCD_LKB9               0x0148          /* Local Bus */
-#define RM9000x2_OCD_LKM9               0x014c
-#define RM9000x2_OCD_LKB10              0x0150
-#define RM9000x2_OCD_LKM10              0x0154
-#define RM9000x2_OCD_LKB11              0x0158
-#define RM9000x2_OCD_LKM11              0x015c
-#define RM9000x2_OCD_LKB12              0x0160
-#define RM9000x2_OCD_LKM12              0x0164
-
-#define RM9000x2_OCD_LKB13              0x0168          /* Scratch RAM */
-#define RM9000x2_OCD_LKM13              0x016c
-
-#define RM9000x2_OCD_LPD0               0x0200          /* Local Bus */
-#define RM9000x2_OCD_LPD1               0x0210
-#define RM9000x2_OCD_LPD2               0x0220
-#define RM9000x2_OCD_LPD3               0x0230
-
-#define RM9000x2_OCD_HTDVID             0x0600  /* HT Device Header */
-#define RM9000x2_OCD_HTSC               0x0604
-#define RM9000x2_OCD_HTCCR              0x0608
-#define RM9000x2_OCD_HTBHL              0x060c
-#define RM9000x2_OCD_HTBAR0             0x0610
-#define RM9000x2_OCD_HTBAR1             0x0614
-#define RM9000x2_OCD_HTBAR2             0x0618
-#define RM9000x2_OCD_HTBAR3             0x061c
-#define RM9000x2_OCD_HTBAR4             0x0620
-#define RM9000x2_OCD_HTBAR5             0x0624
-#define RM9000x2_OCD_HTCBCPT            0x0628
-#define RM9000x2_OCD_HTSDVID            0x062c
-#define RM9000x2_OCD_HTXRA              0x0630
-#define RM9000x2_OCD_HTCAP1             0x0634
-#define RM9000x2_OCD_HTIL               0x063c
-
-#define RM9000x2_OCD_HTLCC              0x0640  /* HT Capability Block */
-#define RM9000x2_OCD_HTLINK             0x0644
-#define RM9000x2_OCD_HTFQREV            0x0648
-
-#define RM9000x2_OCD_HTERCTL            0x0668  /* HT Controller */
-#define RM9000x2_OCD_HTRXDB             0x066c
-#define RM9000x2_OCD_HTIMPED            0x0670
-#define RM9000x2_OCD_HTSWIMP            0x0674
-#define RM9000x2_OCD_HTCAL              0x0678
-
-#define RM9000x2_OCD_HTBAA30            0x0680
-#define RM9000x2_OCD_HTBAA54            0x0684
-#define RM9000x2_OCD_HTMASK0            0x0688
-#define RM9000x2_OCD_HTMASK1            0x068c
-#define RM9000x2_OCD_HTMASK2            0x0690
-#define RM9000x2_OCD_HTMASK3            0x0694
-#define RM9000x2_OCD_HTMASK4            0x0698
-#define RM9000x2_OCD_HTMASK5            0x069c
-
-#define RM9000x2_OCD_HTIFCTL            0x06a0
-#define RM9000x2_OCD_HTPLL              0x06a4
-
-#define RM9000x2_OCD_HTSRI              0x06b0
-#define RM9000x2_OCD_HTRXNUM            0x06b4
-#define RM9000x2_OCD_HTTXNUM            0x06b8
-
-#define RM9000x2_OCD_HTTXCNT            0x06c8
-
-#define RM9000x2_OCD_HTERROR            0x06d8
-#define RM9000x2_OCD_HTRCRCE            0x06dc
-#define RM9000x2_OCD_HTEOI              0x06e0
-
-#define RM9000x2_OCD_CRCR               0x06f0
-
-#define RM9000x2_OCD_HTCFGA             0x06f8
-#define RM9000x2_OCD_HTCFGD             0x06fc
-
-#define RM9000x2_OCD_INTMSG             0x0a00
-
-#define RM9000x2_OCD_INTPIN0            0x0a40
-#define RM9000x2_OCD_INTPIN1            0x0a44
-#define RM9000x2_OCD_INTPIN2            0x0a48
-#define RM9000x2_OCD_INTPIN3            0x0a4c
-#define RM9000x2_OCD_INTPIN4            0x0a50
-#define RM9000x2_OCD_INTPIN5            0x0a54
-#define RM9000x2_OCD_INTPIN6            0x0a58
-#define RM9000x2_OCD_INTPIN7            0x0a5c
-#define RM9000x2_OCD_SEM                0x0a60
-#define RM9000x2_OCD_SEMSET             0x0a64
-#define RM9000x2_OCD_SEMCLR             0x0a68
-
-#define RM9000x2_OCD_TKT                0x0a70
-#define RM9000x2_OCD_TKTINC             0x0a74
-
-#define RM9000x2_OCD_NMICONFIG          0x0ac0          /* Interrupts */
-#define RM9000x2_OCD_INTP0PRI           0x1a80
-#define RM9000x2_OCD_INTP1PRI           0x1a80
-#define RM9000x2_OCD_INTP0STATUS0       0x1b00
-#define RM9000x2_OCD_INTP0MASK0         0x1b04
-#define RM9000x2_OCD_INTP0SET0          0x1b08
-#define RM9000x2_OCD_INTP0CLEAR0        0x1b0c
-#define RM9000x2_OCD_INTP0STATUS1       0x1b10
-#define RM9000x2_OCD_INTP0MASK1         0x1b14
-#define RM9000x2_OCD_INTP0SET1          0x1b18
-#define RM9000x2_OCD_INTP0CLEAR1        0x1b1c
-#define RM9000x2_OCD_INTP0STATUS2       0x1b20
-#define RM9000x2_OCD_INTP0MASK2         0x1b24
-#define RM9000x2_OCD_INTP0SET2          0x1b28
-#define RM9000x2_OCD_INTP0CLEAR2        0x1b2c
-#define RM9000x2_OCD_INTP0STATUS3       0x1b30
-#define RM9000x2_OCD_INTP0MASK3         0x1b34
-#define RM9000x2_OCD_INTP0SET3          0x1b38
-#define RM9000x2_OCD_INTP0CLEAR3        0x1b3c
-#define RM9000x2_OCD_INTP0STATUS4       0x1b40
-#define RM9000x2_OCD_INTP0MASK4         0x1b44
-#define RM9000x2_OCD_INTP0SET4          0x1b48
-#define RM9000x2_OCD_INTP0CLEAR4        0x1b4c
-#define RM9000x2_OCD_INTP0STATUS5       0x1b50
-#define RM9000x2_OCD_INTP0MASK5         0x1b54
-#define RM9000x2_OCD_INTP0SET5          0x1b58
-#define RM9000x2_OCD_INTP0CLEAR5        0x1b5c
-#define RM9000x2_OCD_INTP0STATUS6       0x1b60
-#define RM9000x2_OCD_INTP0MASK6         0x1b64
-#define RM9000x2_OCD_INTP0SET6          0x1b68
-#define RM9000x2_OCD_INTP0CLEAR6        0x1b6c
-#define RM9000x2_OCD_INTP0STATUS7       0x1b70
-#define RM9000x2_OCD_INTP0MASK7         0x1b74
-#define RM9000x2_OCD_INTP0SET7          0x1b78
-#define RM9000x2_OCD_INTP0CLEAR7        0x1b7c
-#define RM9000x2_OCD_INTP1STATUS0       0x2b00
-#define RM9000x2_OCD_INTP1MASK0         0x2b04
-#define RM9000x2_OCD_INTP1SET0          0x2b08
-#define RM9000x2_OCD_INTP1CLEAR0        0x2b0c
-#define RM9000x2_OCD_INTP1STATUS1       0x2b10
-#define RM9000x2_OCD_INTP1MASK1         0x2b14
-#define RM9000x2_OCD_INTP1SET1          0x2b18
-#define RM9000x2_OCD_INTP1CLEAR1        0x2b1c
-#define RM9000x2_OCD_INTP1STATUS2       0x2b20
-#define RM9000x2_OCD_INTP1MASK2         0x2b24
-#define RM9000x2_OCD_INTP1SET2          0x2b28
-#define RM9000x2_OCD_INTP1CLEAR2        0x2b2c
-#define RM9000x2_OCD_INTP1STATUS3       0x2b30
-#define RM9000x2_OCD_INTP1MASK3         0x2b34
-#define RM9000x2_OCD_INTP1SET3          0x2b38
-#define RM9000x2_OCD_INTP1CLEAR3        0x2b3c
-#define RM9000x2_OCD_INTP1STATUS4       0x2b40
-#define RM9000x2_OCD_INTP1MASK4         0x2b44
-#define RM9000x2_OCD_INTP1SET4          0x2b48
-#define RM9000x2_OCD_INTP1CLEAR4        0x2b4c
-#define RM9000x2_OCD_INTP1STATUS5       0x2b50
-#define RM9000x2_OCD_INTP1MASK5         0x2b54
-#define RM9000x2_OCD_INTP1SET5          0x2b58
-#define RM9000x2_OCD_INTP1CLEAR5        0x2b5c
-#define RM9000x2_OCD_INTP1STATUS6       0x2b60
-#define RM9000x2_OCD_INTP1MASK6         0x2b64
-#define RM9000x2_OCD_INTP1SET6          0x2b68
-#define RM9000x2_OCD_INTP1CLEAR6        0x2b6c
-#define RM9000x2_OCD_INTP1STATUS7       0x2b70
-#define RM9000x2_OCD_INTP1MASK7         0x2b74
-#define RM9000x2_OCD_INTP1SET7          0x2b78
-#define RM9000x2_OCD_INTP1CLEAR7        0x2b7c
-
-#define OCD_READ(reg)           (*(volatile unsigned int *)(ocd_base + (reg)))
-#define OCD_WRITE(reg, val)                                     \
-        do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
-
-/*
- * Hypertransport specific macros
- */
-#define RM9K_WRITE(ofs, data)   *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
-#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
-#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
-
-#define RM9K_READ(ofs, val)     *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
-#define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
-#define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
-
-#endif
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index fa133c1bc1f9..65e344532ded 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -209,14 +209,6 @@
 #endif
 
 /*
- * On the RM9000 there is a problem which makes the CreateDirtyExclusive
- * eache operation unusable on SMP systems.
- */
-#ifndef RM9000_CDEX_SMP_WAR
-#error Check setting of RM9000_CDEX_SMP_WAR for your platform
-#endif
-
-/*
  * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
  * opposes it being called that) where invalid instructions in the same
  * I-cache line worth of instructions being fetched may case spurious
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 8b28bc4e14ea..007c33d73715 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -16,7 +16,7 @@ CFLAGS_REMOVE_perf_event_mipsxx.o = -pg
 endif
 
 obj-$(CONFIG_CEVT_BCM1480)      += cevt-bcm1480.o
-obj-$(CONFIG_CEVT_R4K_LIB)      += cevt-r4k.o
+obj-$(CONFIG_CEVT_R4K)          += cevt-r4k.o
 obj-$(CONFIG_MIPS_MT_SMTC)      += cevt-smtc.o
 obj-$(CONFIG_CEVT_DS1287)       += cevt-ds1287.o
 obj-$(CONFIG_CEVT_GT641XX)      += cevt-gt641xx.o
@@ -25,7 +25,7 @@ obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
 obj-$(CONFIG_CSRC_BCM1480)      += csrc-bcm1480.o
 obj-$(CONFIG_CSRC_IOASIC)       += csrc-ioasic.o
 obj-$(CONFIG_CSRC_POWERTV)      += csrc-powertv.o
-obj-$(CONFIG_CSRC_R4K_LIB)      += csrc-r4k.o
+obj-$(CONFIG_CSRC_R4K)          += csrc-r4k.o
 obj-$(CONFIG_CSRC_SB1250)       += csrc-sb1250.o
 obj-$(CONFIG_SYNC_R4K)          += sync-r4k.o
 
@@ -58,7 +58,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API)	+= rtlx.o
 obj-$(CONFIG_I8259)             += i8259.o
 obj-$(CONFIG_IRQ_CPU)           += irq_cpu.o
 obj-$(CONFIG_IRQ_CPU_RM7K)      += irq-rm7000.o
-obj-$(CONFIG_IRQ_CPU_RM9K)      += irq-rm9000.o
 obj-$(CONFIG_MIPS_MSC)          += irq-msc01.o
 obj-$(CONFIG_IRQ_TXX9)          += irq_txx9.o
 obj-$(CONFIG_IRQ_GT641XX)       += irq-gt641xx.o
@@ -80,7 +79,8 @@ obj-$(CONFIG_I8253)		+= i8253.o
 
 obj-$(CONFIG_GPIO_TXX9)         += gpio_txx9.o
 
-obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
+obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o crash.o
+obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 obj-$(CONFIG_SPINLOCK_TEST)     += spinlock_test.o
 obj-$(CONFIG_MIPS_MACHINE)      += mips_machine.o
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 0c4bce4882a6..9690998d4ef3 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -125,10 +125,6 @@ void output_thread_defines(void)
                thread.cp0_baduaddr);
         OFFSET(THREAD_ECODE, task_struct, \
                thread.error_code);
-        OFFSET(THREAD_TRAMP, task_struct, \
-               thread.irix_trampoline);
-        OFFSET(THREAD_OLDCTX, task_struct, \
-               thread.irix_oldctx);
         BLANK();
 }
 
diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c
new file mode 100644
index 000000000000..0f53c39324bb
--- /dev/null
+++ b/arch/mips/kernel/crash.c
@@ -0,0 +1,71 @@
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/reboot.h>
+#include <linux/kexec.h>
+#include <linux/bootmem.h>
+#include <linux/crash_dump.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+
+/* This keeps a track of which one is crashing cpu. */
+static int crashing_cpu = -1;
+static cpumask_t cpus_in_crash = CPU_MASK_NONE;
+
+#ifdef CONFIG_SMP
+static void crash_shutdown_secondary(void *ignore)
+{
+        struct pt_regs *regs;
+        int cpu = smp_processor_id();
+
+        regs = task_pt_regs(current);
+
+        if (!cpu_online(cpu))
+                return;
+
+        local_irq_disable();
+        if (!cpu_isset(cpu, cpus_in_crash))
+                crash_save_cpu(regs, cpu);
+        cpu_set(cpu, cpus_in_crash);
+
+        while (!atomic_read(&kexec_ready_to_reboot))
+                cpu_relax();
+        relocated_kexec_smp_wait(NULL);
+        /* NOTREACHED */
+}
+
+static void crash_kexec_prepare_cpus(void)
+{
+        unsigned int msecs;
+
+        unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
+
+        dump_send_ipi(crash_shutdown_secondary);
+        smp_wmb();
+
+        /*
+         * The crash CPU sends an IPI and wait for other CPUs to
+         * respond. Delay of at least 10 seconds.
+         */
+        pr_emerg("Sending IPI to other cpus...\n");
+        msecs = 10000;
+        while ((cpus_weight(cpus_in_crash) < ncpus) && (--msecs > 0)) {
+                cpu_relax();
+                mdelay(1);
+        }
+}
+
+#else /* !defined(CONFIG_SMP)  */
+static void crash_kexec_prepare_cpus(void) {}
+#endif /* !defined(CONFIG_SMP)  */
+
+void default_machine_crash_shutdown(struct pt_regs *regs)
+{
+        local_irq_disable();
+        crashing_cpu = smp_processor_id();
+        crash_save_cpu(regs, crashing_cpu);
+        crash_kexec_prepare_cpus();
+        cpu_set(crashing_cpu, cpus_in_crash);
+}
diff --git a/arch/mips/kernel/crash_dump.c b/arch/mips/kernel/crash_dump.c
new file mode 100644
index 000000000000..35bed0d2342c
--- /dev/null
+++ b/arch/mips/kernel/crash_dump.c
@@ -0,0 +1,75 @@
+#include <linux/highmem.h>
+#include <linux/bootmem.h>
+#include <linux/crash_dump.h>
+#include <asm/uaccess.h>
+
+static int __init parse_savemaxmem(char *p)
+{
+        if (p)
+                saved_max_pfn = (memparse(p, &p) >> PAGE_SHIFT) - 1;
+
+        return 1;
+}
+__setup("savemaxmem=", parse_savemaxmem);
+
+
+static void *kdump_buf_page;
+
+/**
+ * copy_oldmem_page - copy one page from "oldmem"
+ * @pfn: page frame number to be copied
+ * @buf: target memory address for the copy; this can be in kernel address
+ *      space or user address space (see @userbuf)
+ * @csize: number of bytes to copy
+ * @offset: offset in bytes into the page (based on pfn) to begin the copy
+ * @userbuf: if set, @buf is in user address space, use copy_to_user(),
+ *      otherwise @buf is in kernel address space, use memcpy().
+ *
+ * Copy a page from "oldmem". For this page, there is no pte mapped
+ * in the current kernel.
+ *
+ * Calling copy_to_user() in atomic context is not desirable. Hence first
+ * copying the data to a pre-allocated kernel page and then copying to user
+ * space in non-atomic context.
+ */
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
+                         size_t csize, unsigned long offset, int userbuf)
+{
+        void  *vaddr;
+
+        if (!csize)
+                return 0;
+
+        vaddr = kmap_atomic_pfn(pfn);
+
+        if (!userbuf) {
+                memcpy(buf, (vaddr + offset), csize);
+                kunmap_atomic(vaddr);
+        } else {
+                if (!kdump_buf_page) {
+                        pr_warning("Kdump: Kdump buffer page not allocated\n");
+
+                        return -EFAULT;
+                }
+                copy_page(kdump_buf_page, vaddr);
+                kunmap_atomic(vaddr);
+                if (copy_to_user(buf, (kdump_buf_page + offset), csize))
+                        return -EFAULT;
+        }
+
+        return csize;
+}
+
+static int __init kdump_buf_page_init(void)
+{
+        int ret = 0;
+
+        kdump_buf_page = kmalloc(PAGE_SIZE, GFP_KERNEL);
+        if (!kdump_buf_page) {
+                pr_warning("Kdump: Failed to allocate kdump buffer page\n");
+                ret = -ENOMEM;
+        }
+
+        return ret;
+}
+arch_initcall(kdump_buf_page_init);
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
deleted file mode 100644
index 1282b9ae81c4..000000000000
--- a/arch/mips/kernel/irq-rm9000.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright (C) 2003 Ralf Baechle
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Handler for RM9000 extended interrupts.  These are a non-standard
- * feature so we handle them separately from standard interrupts.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-static inline void unmask_rm9k_irq(struct irq_data *d)
-{
-        set_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
-}
-
-static inline void mask_rm9k_irq(struct irq_data *d)
-{
-        clear_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
-}
-
-static inline void rm9k_cpu_irq_enable(struct irq_data *d)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-        unmask_rm9k_irq(d);
-        local_irq_restore(flags);
-}
-
-/*
- * Performance counter interrupts are global on all processors.
- */
-static void local_rm9k_perfcounter_irq_startup(void *args)
-{
-        rm9k_cpu_irq_enable(args);
-}
-
-static unsigned int rm9k_perfcounter_irq_startup(struct irq_data *d)
-{
-        on_each_cpu(local_rm9k_perfcounter_irq_startup, d, 1);
-
-        return 0;
-}
-
-static void local_rm9k_perfcounter_irq_shutdown(void *args)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-        mask_rm9k_irq(args);
-        local_irq_restore(flags);
-}
-
-static void rm9k_perfcounter_irq_shutdown(struct irq_data *d)
-{
-        on_each_cpu(local_rm9k_perfcounter_irq_shutdown, d, 1);
-}
-
-static struct irq_chip rm9k_irq_controller = {
-        .name = "RM9000",
-        .irq_ack = mask_rm9k_irq,
-        .irq_mask = mask_rm9k_irq,
-        .irq_mask_ack = mask_rm9k_irq,
-        .irq_unmask = unmask_rm9k_irq,
-        .irq_eoi = unmask_rm9k_irq
-};
-
-static struct irq_chip rm9k_perfcounter_irq = {
-        .name = "RM9000",
-        .irq_startup = rm9k_perfcounter_irq_startup,
-        .irq_shutdown = rm9k_perfcounter_irq_shutdown,
-        .irq_ack = mask_rm9k_irq,
-        .irq_mask = mask_rm9k_irq,
-        .irq_mask_ack = mask_rm9k_irq,
-        .irq_unmask = unmask_rm9k_irq,
-};
-
-unsigned int rm9000_perfcount_irq;
-
-EXPORT_SYMBOL(rm9000_perfcount_irq);
-
-void __init rm9k_cpu_irq_init(void)
-{
-        int base = RM9K_CPU_IRQ_BASE;
-        int i;
-
-        clear_c0_intcontrol(0x0000f000);                /* Mask all */
-
-        for (i = base; i < base + 4; i++)
-                irq_set_chip_and_handler(i, &rm9k_irq_controller,
-                                         handle_level_irq);
-
-        rm9000_perfcount_irq = base + 1;
-        irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
-                                 handle_percpu_irq);
-}
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
index 85beb9b0b2d0..992e18474da5 100644
--- a/arch/mips/kernel/machine_kexec.c
+++ b/arch/mips/kernel/machine_kexec.c
@@ -5,7 +5,7 @@
  * This source code is licensed under the GNU General Public License,
  * Version 2.  See the file COPYING for more details.
  */
-
+#include <linux/compiler.h>
 #include <linux/kexec.h>
 #include <linux/mm.h>
 #include <linux/delay.h>
@@ -19,9 +19,19 @@ extern const size_t relocate_new_kernel_size;
 extern unsigned long kexec_start_address;
 extern unsigned long kexec_indirection_page;
 
+int (*_machine_kexec_prepare)(struct kimage *) = NULL;
+void (*_machine_kexec_shutdown)(void) = NULL;
+void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL;
+#ifdef CONFIG_SMP
+void (*relocated_kexec_smp_wait) (void *);
+atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0);
+#endif
+
 int
 machine_kexec_prepare(struct kimage *kimage)
 {
+        if (_machine_kexec_prepare)
+                return _machine_kexec_prepare(kimage);
         return 0;
 }
 
@@ -33,14 +43,20 @@ machine_kexec_cleanup(struct kimage *kimage)
 void
 machine_shutdown(void)
 {
+        if (_machine_kexec_shutdown)
+                _machine_kexec_shutdown();
 }
 
 void
 machine_crash_shutdown(struct pt_regs *regs)
 {
+        if (_machine_crash_shutdown)
+                _machine_crash_shutdown(regs);
+        else
+                default_machine_crash_shutdown(regs);
 }
 
-typedef void (*noretfun_t)(void) __attribute__((noreturn));
+typedef void (*noretfun_t)(void) __noreturn;
 
 void
 machine_kexec(struct kimage *image)
@@ -52,7 +68,9 @@ machine_kexec(struct kimage *image)
         reboot_code_buffer =
           (unsigned long)page_address(image->control_code_page);
 
-        kexec_start_address = image->start;
+        kexec_start_address =
+                (unsigned long) phys_to_virt(image->start);
+
         kexec_indirection_page =
                 (unsigned long) phys_to_virt(image->head & PAGE_MASK);
 
@@ -63,7 +81,7 @@ machine_kexec(struct kimage *image)
          * The generic kexec code builds a page list with physical
          * addresses. they are directly accessible through KSEG0 (or
          * CKSEG0 or XPHYS if on 64bit system), hence the
-         * pys_to_virt() call.
+         * phys_to_virt() call.
          */
         for (ptr = &image->head; (entry = *ptr) && !(entry &IND_DONE);
              ptr = (entry & IND_INDIRECTION) ?
@@ -81,5 +99,12 @@ machine_kexec(struct kimage *image)
         printk("Will call new kernel at %08lx\n", image->start);
         printk("Bye ...\n");
         __flush_cache_all();
+#ifdef CONFIG_SMP
+        /* All secondary cpus now may jump to kexec_wait cycle */
+        relocated_kexec_smp_wait = reboot_code_buffer +
+                (void *)(kexec_smp_wait - relocate_new_kernel);
+        smp_wmb();
+        atomic_set(&kexec_ready_to_reboot, 1);
+#endif
         ((noretfun_t) reboot_code_buffer)();
 }
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index 33f63bab478a..fd814e08c945 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -50,8 +50,8 @@ static bool check_same_owner(struct task_struct *p)
 
         rcu_read_lock();
         pcred = __task_cred(p);
-        match = (cred->euid == pcred->euid ||
-                 cred->euid == pcred->uid);
+        match = (uid_eq(cred->euid, pcred->euid) ||
+                 uid_eq(cred->euid, pcred->uid));
         rcu_read_unlock();
         return match;
 }
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 3fc1691110dc..1ba8933683aa 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -11,7 +11,7 @@
 #include <linux/interrupt.h>
 #include <linux/export.h>
 #include <asm/checksum.h>
-#include <asm/pgtable.h>
+#include <linux/mm.h>
 #include <asm/uaccess.h>
 #include <asm/ftrace.h>
 
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index e9a5fd7277f4..69b17a920049 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -72,9 +72,7 @@ void __noreturn cpu_idle(void)
                         }
                 }
 #ifdef CONFIG_HOTPLUG_CPU
-                if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) &&
-                    (system_state == SYSTEM_RUNNING ||
-                     system_state == SYSTEM_BOOTING))
+                if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map))
                         play_dead();
 #endif
                 rcu_idle_exit();
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 87481f916a61..e4142c5f7c2b 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -15,6 +15,11 @@
 #include <asm/addrspace.h>
 
 LEAF(relocate_new_kernel)
+        PTR_L a0,       arg0
+        PTR_L a1,       arg1
+        PTR_L a2,       arg2
+        PTR_L a3,       arg3
+
         PTR_L           s0, kexec_indirection_page
         PTR_L           s1, kexec_start_address
 
@@ -26,7 +31,6 @@ process_entry:
         and             s3, s2, 0x1
         beq             s3, zero, 1f
         and             s4, s2, ~0x1    /* store destination addr in s4 */
-        move            a0, s4
         b               process_entry
 
 1:
@@ -60,10 +64,111 @@ copy_word:
         b               process_entry
 
 done:
+#ifdef CONFIG_SMP
+        /* kexec_flag reset is signal to other CPUs what kernel
+           was moved to it's location. Note - we need relocated address
+           of kexec_flag.  */
+
+        bal             1f
+ 1:     move            t1,ra;
+        PTR_LA          t2,1b
+        PTR_LA          t0,kexec_flag
+        PTR_SUB         t0,t0,t2;
+        PTR_ADD         t0,t1,t0;
+        LONG_S          zero,(t0)
+#endif
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        /* We need to flush I-cache before jumping to new kernel.
+         * Unfortunatelly, this code is cpu-specific.
+         */
+        .set push
+        .set noreorder
+        syncw
+        syncw
+        synci           0($0)
+        .set pop
+#else
+        sync
+#endif
         /* jump to kexec_start_address */
         j               s1
         END(relocate_new_kernel)
 
+#ifdef CONFIG_SMP
+/*
+ * Other CPUs should wait until code is relocated and
+ * then start at entry (?) point.
+ */
+LEAF(kexec_smp_wait)
+        PTR_L           a0, s_arg0
+        PTR_L           a1, s_arg1
+        PTR_L           a2, s_arg2
+        PTR_L           a3, s_arg3
+        PTR_L           s1, kexec_start_address
+
+        /* Non-relocated address works for args and kexec_start_address ( old
+         * kernel is not overwritten). But we need relocated address of
+         * kexec_flag.
+         */
+
+        bal             1f
+1:      move            t1,ra;
+        PTR_LA          t2,1b
+        PTR_LA          t0,kexec_flag
+        PTR_SUB         t0,t0,t2;
+        PTR_ADD         t0,t1,t0;
+
+1:      LONG_L          s0, (t0)
+        bne             s0, zero,1b
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        .set push
+        .set noreorder
+        synci           0($0)
+        .set pop
+#else
+        sync
+#endif
+        j               s1
+        END(kexec_smp_wait)
+#endif
+
+#ifdef __mips64
+       /* all PTR's must be aligned to 8 byte in 64-bit mode */
+       .align  3
+#endif
+
+/* All parameters to new kernel are passed in registers a0-a3.
+ * kexec_args[0..3] are uses to prepare register values.
+ */
+
+kexec_args:
+        EXPORT(kexec_args)
+arg0:   PTR             0x0
+arg1:   PTR             0x0
+arg2:   PTR             0x0
+arg3:   PTR             0x0
+        .size   kexec_args,PTRSIZE*4
+
+#ifdef CONFIG_SMP
+/*
+ * Secondary CPUs may have different kernel parameters in
+ * their registers a0-a3. secondary_kexec_args[0..3] are used
+ * to prepare register values.
+ */
+secondary_kexec_args:
+        EXPORT(secondary_kexec_args)
+s_arg0: PTR             0x0
+s_arg1: PTR             0x0
+s_arg2: PTR             0x0
+s_arg3: PTR             0x0
+        .size   secondary_kexec_args,PTRSIZE*4
+kexec_flag:
+        LONG            0x1
+
+#endif
+
 kexec_start_address:
         EXPORT(kexec_start_address)
         PTR             0x0
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index f6ba8381ee01..9c721dd84ba1 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -17,12 +17,6 @@
 #include <asm/thread_info.h>
 #include <asm/unistd.h>
 
-/* This duplicates the definition from <linux/sched.h> */
-#define PT_TRACESYS     0x00000002      /* tracing system calls */
-
-/* This duplicates the definition from <asm/signal.h> */
-#define SIGILL          4               /* Illegal instruction (ANSI).  */
-
 #ifndef CONFIG_MIPS32_O32
 /* No O32, so define handle_sys here */
 #define handle_sysn32 handle_sys
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index a53f8ec37aac..8c41187801ce 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -22,6 +22,7 @@
 #include <linux/console.h>
 #include <linux/pfn.h>
 #include <linux/debugfs.h>
+#include <linux/kexec.h>
 
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
@@ -79,7 +80,7 @@ static struct resource data_resource = { .name = "Kernel data", };
 void __init add_memory_region(phys_t start, phys_t size, long type)
 {
         int x = boot_mem_map.nr_map;
-        struct boot_mem_map_entry *prev = boot_mem_map.map + x - 1;
+        int i;
 
         /* Sanity check */
         if (start + size < start) {
@@ -88,15 +89,29 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
         }
 
         /*
-         * Try to merge with previous entry if any.  This is far less than
-         * perfect but is sufficient for most real world cases.
+         * Try to merge with existing entry, if any.
          */
-        if (x && prev->addr + prev->size == start && prev->type == type) {
-                prev->size += size;
+        for (i = 0; i < boot_mem_map.nr_map; i++) {
+                struct boot_mem_map_entry *entry = boot_mem_map.map + i;
+                unsigned long top;
+
+                if (entry->type != type)
+                        continue;
+
+                if (start + size < entry->addr)
+                        continue;                       /* no overlap */
+
+                if (entry->addr + entry->size < start)
+                        continue;                       /* no overlap */
+
+                top = max(entry->addr + entry->size, start + size);
+                entry->addr = min(entry->addr, start);
+                entry->size = top - entry->addr;
+
                 return;
         }
 
-        if (x == BOOT_MEM_MAP_MAX) {
+        if (boot_mem_map.nr_map == BOOT_MEM_MAP_MAX) {
                 pr_err("Ooops! Too many entries in the memory map!\n");
                 return;
         }
@@ -522,12 +537,64 @@ static void __init arch_mem_init(char **cmdline_p)
         }
 
         bootmem_init();
+#ifdef CONFIG_KEXEC
+        if (crashk_res.start != crashk_res.end)
+                reserve_bootmem(crashk_res.start,
+                                crashk_res.end - crashk_res.start + 1,
+                                BOOTMEM_DEFAULT);
+#endif
         device_tree_init();
         sparse_init();
         plat_swiotlb_setup();
         paging_init();
 }
 
+#ifdef CONFIG_KEXEC
+static inline unsigned long long get_total_mem(void)
+{
+        unsigned long long total;
+
+        total = max_pfn - min_low_pfn;
+        return total << PAGE_SHIFT;
+}
+
+static void __init mips_parse_crashkernel(void)
+{
+        unsigned long long total_mem;
+        unsigned long long crash_size, crash_base;
+        int ret;
+
+        total_mem = get_total_mem();
+        ret = parse_crashkernel(boot_command_line, total_mem,
+                                &crash_size, &crash_base);
+        if (ret != 0 || crash_size <= 0)
+                return;
+
+        crashk_res.start = crash_base;
+        crashk_res.end   = crash_base + crash_size - 1;
+}
+
+static void __init request_crashkernel(struct resource *res)
+{
+        int ret;
+
+        ret = request_resource(res, &crashk_res);
+        if (!ret)
+                pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
+                        (unsigned long)((crashk_res.end -
+                                crashk_res.start + 1) >> 20),
+                        (unsigned long)(crashk_res.start  >> 20));
+}
+#else /* !defined(CONFIG_KEXEC)  */
+static void __init mips_parse_crashkernel(void)
+{
+}
+
+static void __init request_crashkernel(struct resource *res)
+{
+}
+#endif /* !defined(CONFIG_KEXEC)  */
+
 static void __init resource_init(void)
 {
         int i;
@@ -543,6 +610,8 @@ static void __init resource_init(void)
         /*
          * Request address space for all standard RAM.
          */
+        mips_parse_crashkernel();
+
         for (i = 0; i < boot_mem_map.nr_map; i++) {
                 struct resource *res;
                 unsigned long start, end;
@@ -579,6 +648,7 @@ static void __init resource_init(void)
                  */
                 request_resource(res, &code_resource);
                 request_resource(res, &data_resource);
+                request_crashkernel(res);
         }
 }
 
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 0e1a5b8ae817..b6aa77035019 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -568,17 +568,20 @@ static void do_signal(struct pt_regs *regs)
         }
 
         if (regs->regs[0]) {
-                if (regs->regs[2] == ERESTARTNOHAND ||
-                    regs->regs[2] == ERESTARTSYS ||
-                    regs->regs[2] == ERESTARTNOINTR) {
+                switch (regs->regs[2]) {
+                case ERESTARTNOHAND:
+                case ERESTARTSYS:
+                case ERESTARTNOINTR:
                         regs->regs[2] = regs->regs[0];
                         regs->regs[7] = regs->regs[26];
                         regs->cp0_epc -= 4;
-                }
-                if (regs->regs[2] == ERESTART_RESTARTBLOCK) {
+                        break;
+
+                case ERESTART_RESTARTBLOCK:
                         regs->regs[2] = current->thread.abi->restart;
                         regs->regs[7] = regs->regs[26];
                         regs->cp0_epc -= 4;
+                        break;
                 }
                 regs->regs[0] = 0;      /* Don't deal with this again.  */
         }
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 9005bf9fb859..2e6374a589ec 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -386,3 +386,20 @@ void flush_tlb_one(unsigned long vaddr)
 
 EXPORT_SYMBOL(flush_tlb_page);
 EXPORT_SYMBOL(flush_tlb_one);
+
+#if defined(CONFIG_KEXEC)
+void (*dump_ipi_function_ptr)(void *) = NULL;
+void dump_send_ipi(void (*dump_ipi_callback)(void *))
+{
+        int i;
+        int cpu = smp_processor_id();
+
+        dump_ipi_function_ptr = dump_ipi_callback;
+        smp_mb();
+        for_each_online_cpu(i)
+                if (i != cpu)
+                        mp_ops->send_ipi_single(i, SMP_DUMP);
+
+}
+EXPORT_SYMBOL(dump_send_ipi);
+#endif
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9be3df1fa8a4..cf7ac5483f53 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -13,6 +13,7 @@
  */
 #include <linux/bug.h>
 #include <linux/compiler.h>
+#include <linux/kexec.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -409,6 +410,9 @@ void __noreturn die(const char *str, struct pt_regs *regs)
                 panic("Fatal exception");
         }
 
+        if (regs && kexec_should_crash(current))
+                crash_kexec(regs);
+
         do_exit(sig);
 }
 
@@ -1021,6 +1025,24 @@ asmlinkage void do_cpu(struct pt_regs *regs)
 
                 return;
 
+        case 3:
+                /*
+                 * Old (MIPS I and MIPS II) processors will set this code
+                 * for COP1X opcode instructions that replaced the original
+                 * COP3 space.  We don't limit COP1 space instructions in
+                 * the emulator according to the CPU ISA, so we want to
+                 * treat COP1X instructions consistently regardless of which
+                 * code the CPU chose.  Therefore we redirect this trap to
+                 * the FP emulator too.
+                 *
+                 * Then some newer FPU-less processors use this code
+                 * erroneously too, so they are covered by this choice
+                 * as well.
+                 */
+                if (raw_cpu_has_fpu)
+                        break;
+                /* Fall through.  */
+
         case 1:
                 if (used_math())        /* Using the FPU again.  */
                         own_fpu(1);
@@ -1044,9 +1066,6 @@ asmlinkage void do_cpu(struct pt_regs *regs)
         case 2:
                 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
                 return;
-
-        case 3:
-                break;
         }
 
         force_sig(SIGILL, current);
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index b5d76d1444c9..6453962ac898 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -49,7 +49,7 @@
 #define DMA_CLK_DIV4            BIT(6)          /* polling clock divider */
 #define DMA_2W_BURST            BIT(1)          /* 2 word burst length */
 #define DMA_MAX_CHANNEL         20              /* the soc has 20 channels */
-#define DMA_ETOP_ENDIANESS      (0xf << 8) /* endianess swap etop channels */
+#define DMA_ETOP_ENDIANNESS     (0xf << 8) /* endianness swap etop channels */
 #define DMA_WEIGHT      (BIT(17) | BIT(16))     /* default channel wheight */
 
 #define ltq_dma_r32(x)                  ltq_r32(ltq_dma_membase + (x))
@@ -192,10 +192,10 @@ ltq_dma_init_port(int p)
         switch (p) {
         case DMA_PORT_ETOP:
                 /*
-                 * Tell the DMA engine to swap the endianess of data frames and
+                 * Tell the DMA engine to swap the endianness of data frames and
                  * drop packets if the channel arbitration fails.
                  */
-                ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN,
+                ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
                         LTQ_DMA_PCTRL);
                 break;
 
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index c4a82e841c73..eeddc58802e1 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,8 +2,9 @@
 # Makefile for MIPS-specific library files..
 #
 
-lib-y   += csum_partial.o delay.o memcpy.o memset.o \
-           strlen_user.o strncpy_user.o strnlen_user.o uncached.o
+lib-y   += bitops.o csum_partial.o delay.o memcpy.o memset.o \
+           mips-atomic.o strlen_user.o strncpy_user.o \
+           strnlen_user.o uncached.o
 
 obj-y                   += iomap.o
 obj-$(CONFIG_PCI)       += iomap-pci.o
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
new file mode 100644
index 000000000000..239a9c957b02
--- /dev/null
+++ b/arch/mips/lib/bitops.c
@@ -0,0 +1,179 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
+ */
+#include <linux/bitops.h>
+#include <linux/irqflags.h>
+#include <linux/export.h>
+
+
+/**
+ * __mips_set_bit - Atomically set a bit in memory.  This is called by
+ * set_bit() if it cannot find a faster solution.
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ */
+void __mips_set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        *a |= mask;
+        raw_local_irq_restore(flags);
+}
+EXPORT_SYMBOL(__mips_set_bit);
+
+
+/**
+ * __mips_clear_bit - Clears a bit in memory.  This is called by clear_bit() if
+ * it cannot find a faster solution.
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ */
+void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        *a &= ~mask;
+        raw_local_irq_restore(flags);
+}
+EXPORT_SYMBOL(__mips_clear_bit);
+
+
+/**
+ * __mips_change_bit - Toggle a bit in memory.  This is called by change_bit()
+ * if it cannot find a faster solution.
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ */
+void __mips_change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        *a ^= mask;
+        raw_local_irq_restore(flags);
+}
+EXPORT_SYMBOL(__mips_change_bit);
+
+
+/**
+ * __mips_test_and_set_bit - Set a bit and return its old value.  This is
+ * called by test_and_set_bit() if it cannot find a faster solution.
+ * @nr: Bit to set
+ * @addr: Address to count from
+ */
+int __mips_test_and_set_bit(unsigned long nr,
+                            volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+        unsigned long res;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        res = (mask & *a);
+        *a |= mask;
+        raw_local_irq_restore(flags);
+        return res;
+}
+EXPORT_SYMBOL(__mips_test_and_set_bit);
+
+
+/**
+ * __mips_test_and_set_bit_lock - Set a bit and return its old value.  This is
+ * called by test_and_set_bit_lock() if it cannot find a faster solution.
+ * @nr: Bit to set
+ * @addr: Address to count from
+ */
+int __mips_test_and_set_bit_lock(unsigned long nr,
+                                 volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+        unsigned long res;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        res = (mask & *a);
+        *a |= mask;
+        raw_local_irq_restore(flags);
+        return res;
+}
+EXPORT_SYMBOL(__mips_test_and_set_bit_lock);
+
+
+/**
+ * __mips_test_and_clear_bit - Clear a bit and return its old value.  This is
+ * called by test_and_clear_bit() if it cannot find a faster solution.
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ */
+int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+        unsigned long res;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        res = (mask & *a);
+        *a &= ~mask;
+        raw_local_irq_restore(flags);
+        return res;
+}
+EXPORT_SYMBOL(__mips_test_and_clear_bit);
+
+
+/**
+ * __mips_test_and_change_bit - Change a bit and return its old value.  This is
+ * called by test_and_change_bit() if it cannot find a faster solution.
+ * @nr: Bit to change
+ * @addr: Address to count from
+ */
+int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned bit = nr & SZLONG_MASK;
+        unsigned long mask;
+        unsigned long flags;
+        unsigned long res;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << bit;
+        raw_local_irq_save(flags);
+        res = (mask & *a);
+        *a ^= mask;
+        raw_local_irq_restore(flags);
+        return res;
+}
+EXPORT_SYMBOL(__mips_test_and_change_bit);
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
new file mode 100644
index 000000000000..cd160be3ce4d
--- /dev/null
+++ b/arch/mips/lib/mips-atomic.c
@@ -0,0 +1,176 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#include <asm/irqflags.h>
+#include <asm/hazards.h>
+#include <linux/compiler.h>
+#include <linux/preempt.h>
+#include <linux/export.h>
+
+#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC)
+
+/*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+/*
+ * For TX49, operating only IE bit is not enough.
+ *
+ * If mfc0 $12 follows store and the mfc0 is last instruction of a
+ * page and fetching the next instruction causes TLB miss, the result
+ * of the mfc0 might wrongly contain EXL bit.
+ *
+ * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
+ *
+ * Workaround: mask EXL bit of the result or place a nop before mfc0.
+ */
+__asm__(
+        "       .macro  arch_local_irq_disable\n"
+        "       .set    push                                            \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    $1, $2, 1                                       \n"
+        "       ori     $1, 0x400                                       \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        /* see irqflags.h for inline function */
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1f                                         \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+notrace void arch_local_irq_disable(void)
+{
+        preempt_disable();
+        __asm__ __volatile__(
+                "arch_local_irq_disable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+        preempt_enable();
+}
+EXPORT_SYMBOL(arch_local_irq_disable);
+
+
+__asm__(
+        "       .macro  arch_local_irq_save result                      \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    \\result, $2, 1                                 \n"
+        "       ori     $1, \\result, 0x400                             \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+        "       andi    \\result, \\result, 0x400                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        /* see irqflags.h for inline function */
+#else
+        "       mfc0    \\result, $12                                   \n"
+        "       ori     $1, \\result, 0x1f                              \n"
+        "       xori    $1, 0x1f                                        \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $12                                         \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+notrace unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags;
+        preempt_disable();
+        asm volatile("arch_local_irq_save\t%0"
+                     : "=r" (flags)
+                     : /* no inputs */
+                     : "memory");
+        preempt_enable();
+        return flags;
+}
+EXPORT_SYMBOL(arch_local_irq_save);
+
+
+__asm__(
+        "       .macro  arch_local_irq_restore flags                    \n"
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "mfc0   $1, $2, 1                                               \n"
+        "andi   \\flags, 0x400                                          \n"
+        "ori    $1, 0x400                                               \n"
+        "xori   $1, 0x400                                               \n"
+        "or     \\flags, $1                                             \n"
+        "mtc0   \\flags, $2, 1                                          \n"
+#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+        /* see irqflags.h for inline function */
+#elif defined(CONFIG_CPU_MIPSR2)
+        /* see irqflags.h for inline function */
+#else
+        "       mfc0    $1, $12                                         \n"
+        "       andi    \\flags, 1                                      \n"
+        "       ori     $1, 0x1f                                        \n"
+        "       xori    $1, 0x1f                                        \n"
+        "       or      \\flags, $1                                     \n"
+        "       mtc0    \\flags, $12                                    \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+notrace void arch_local_irq_restore(unsigned long flags)
+{
+        unsigned long __tmp1;
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC kernel needs to do a software replay of queued
+         * IPIs, at the cost of branch and call overhead on each
+         * local_irq_restore()
+         */
+        if (unlikely(!(flags & 0x0400)))
+                smtc_ipi_replay();
+#endif
+        preempt_disable();
+        __asm__ __volatile__(
+                "arch_local_irq_restore\t%0"
+                : "=r" (__tmp1)
+                : "0" (flags)
+                : "memory");
+        preempt_enable();
+}
+EXPORT_SYMBOL(arch_local_irq_restore);
+
+
+notrace void __arch_local_irq_restore(unsigned long flags)
+{
+        unsigned long __tmp1;
+
+        preempt_disable();
+        __asm__ __volatile__(
+                "arch_local_irq_restore\t%0"
+                : "=r" (__tmp1)
+                : "0" (flags)
+                : "memory");
+        preempt_enable();
+}
+EXPORT_SYMBOL(__arch_local_irq_restore);
+
+#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index a03bf00a1a9c..47c77e7ffbf8 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -171,16 +171,17 @@ static int isBranchInstr(mips_instruction * i)
  * In the Linux kernel, we support selection of FPR format on the
  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
  * is hardwired to zero, which would imply a 32-bit FPU even for
- * 64-bit CPUs.  For 64-bit kernels with no FPU we use TIF_32BIT_REGS
- * as a proxy for the FR bit so that a 64-bit FPU is emulated.  In any
- * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
- * even FPRs are used (Status.FR = 0).
+ * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
+ * FPU emu is slow and bulky and optimizing this function offers fairly
+ * sizeable benefits so we try to be clever and make this function return
+ * a constant whenever possible, that is on 64-bit kernels without O32
+ * compatibility enabled and on 32-bit kernels.
  */
 static inline int cop1_64bit(struct pt_regs *xcp)
 {
-        if (cpu_has_fpu)
-                return xcp->cp0_status & ST0_FR;
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
+        return 1;
+#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
         return !test_thread_flag(TIF_32BIT_REGS);
 #else
         return 0;
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 44e69e7a4519..6ec04daf4231 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -5,6 +5,7 @@
  *
  * Copyright (C) 2005-2007 Cavium Networks
  */
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -28,6 +29,7 @@
 #include <asm/octeon/octeon.h>
 
 unsigned long long cache_err_dcache[NR_CPUS];
+EXPORT_SYMBOL_GPL(cache_err_dcache);
 
 /**
  * Octeon automatically flushes the dcache on tlb changes, so
@@ -284,39 +286,59 @@ void __cpuinit octeon_cache_init(void)
         board_cache_error_setup = octeon_cache_error_setup;
 }
 
-/**
+/*
  * Handle a cache error exception
  */
+static RAW_NOTIFIER_HEAD(co_cache_error_chain);
 
-static void  cache_parity_error_octeon(int non_recoverable)
+int register_co_cache_error_notifier(struct notifier_block *nb)
 {
-        unsigned long coreid = cvmx_get_core_num();
-        uint64_t icache_err = read_octeon_c0_icacheerr();
-
-        pr_err("Cache error exception:\n");
-        pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
-        if (icache_err & 1) {
-                pr_err("CacheErr (Icache) == %llx\n",
-                       (unsigned long long)icache_err);
-                write_octeon_c0_icacheerr(0);
-        }
-        if (cache_err_dcache[coreid] & 1) {
-                pr_err("CacheErr (Dcache) == %llx\n",
-                       (unsigned long long)cache_err_dcache[coreid]);
-                cache_err_dcache[coreid] = 0;
-        }
+        return raw_notifier_chain_register(&co_cache_error_chain, nb);
+}
+EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
+
+int unregister_co_cache_error_notifier(struct notifier_block *nb)
+{
+        return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
 
-        if (non_recoverable)
-                panic("Can't handle cache error: nested exception");
+static void co_cache_error_call_notifiers(unsigned long val)
+{
+        int rv = raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
+        if ((rv & ~NOTIFY_STOP_MASK) != NOTIFY_OK) {
+                u64 dcache_err;
+                unsigned long coreid = cvmx_get_core_num();
+                u64 icache_err = read_octeon_c0_icacheerr();
+
+                if (val) {
+                        dcache_err = cache_err_dcache[coreid];
+                        cache_err_dcache[coreid] = 0;
+                } else {
+                        dcache_err = read_octeon_c0_dcacheerr();
+                }
+
+                pr_err("Core%lu: Cache error exception:\n", coreid);
+                pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
+                if (icache_err & 1) {
+                        pr_err("CacheErr (Icache) == %llx\n",
+                               (unsigned long long)icache_err);
+                        write_octeon_c0_icacheerr(0);
+                }
+                if (dcache_err & 1) {
+                        pr_err("CacheErr (Dcache) == %llx\n",
+                               (unsigned long long)dcache_err);
+                }
+        }
 }
 
-/**
+/*
  * Called when the the exception is recoverable
  */
 
 asmlinkage void cache_parity_error_octeon_recoverable(void)
 {
-        cache_parity_error_octeon(0);
+        co_cache_error_call_notifiers(0);
 }
 
 /**
@@ -325,5 +347,6 @@ asmlinkage void cache_parity_error_octeon_recoverable(void)
 
 asmlinkage void cache_parity_error_octeon_non_recoverable(void)
 {
-        cache_parity_error_octeon(1);
+        co_cache_error_call_notifiers(1);
+        panic("Can't handle cache error: nested exception");
 }
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1d6fee48d0dd..0f7d788e8810 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -632,9 +632,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                 if (size >= scache_size)
                         r4k_blast_scache();
                 else {
-                        unsigned long lsize = cpu_scache_line_size();
-                        unsigned long almask = ~(lsize - 1);
-
                         /*
                          * There is no clearly documented alignment requirement
                          * for the cache instruction on MIPS processors and
@@ -643,9 +640,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                          * hit ops with insufficient alignment.  Solved by
                          * aligning the address to cache line size.
                          */
-                        cache_op(Hit_Writeback_Inv_SD, addr & almask);
-                        cache_op(Hit_Writeback_Inv_SD,
-                                 (addr + size - 1) & almask);
                         blast_inv_scache_range(addr, addr + size);
                 }
                 __sync();
@@ -655,12 +649,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
                 r4k_blast_dcache();
         } else {
-                unsigned long lsize = cpu_dcache_line_size();
-                unsigned long almask = ~(lsize - 1);
-
                 R4600_HIT_CACHEOP_WAR_IMPL;
-                cache_op(Hit_Writeback_Inv_D, addr & almask);
-                cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
                 blast_inv_dcache_range(addr, addr + size);
         }
 
@@ -947,7 +936,6 @@ static void __cpuinit probe_pcache(void)
         case CPU_RM7000:
                 rm7k_erratum31();
 
-        case CPU_RM9000:
                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                 c->icache.ways = 4;
@@ -958,9 +946,7 @@ static void __cpuinit probe_pcache(void)
                 c->dcache.ways = 4;
                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 
-#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
                 c->options |= MIPS_CPU_CACHE_CDEX_P;
-#endif
                 c->options |= MIPS_CPU_PREFETCH;
                 break;
 
@@ -1245,7 +1231,6 @@ static void __cpuinit setup_scache(void)
                 return;
 
         case CPU_RM7000:
-        case CPU_RM9000:
 #ifdef CONFIG_RM7000_CPU_SCACHE
                 rm7k_sc_init();
 #endif
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index aff57057a949..da815d295239 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -1,3 +1,4 @@
+#include <linux/compiler.h>
 #include <linux/module.h>
 #include <linux/highmem.h>
 #include <linux/sched.h>
@@ -67,7 +68,7 @@ EXPORT_SYMBOL(kmap_atomic);
 void __kunmap_atomic(void *kvaddr)
 {
         unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
-        int type;
+        int type __maybe_unused;
 
         if (vaddr < FIXADDR_START) { // FIXME
                 pagefault_enable();
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 98f530e18216..8e666c55f4d4 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -140,15 +140,6 @@ static void __cpuinit set_prefetch_parameters(void)
                         pref_bias_copy_load = 256;
                         break;
 
-                case CPU_RM9000:
-                        /*
-                         * As a workaround for erratum G105 which make the
-                         * PrepareForStore hint unusable we fall back to
-                         * StoreRetained on the RM9000.  Once it is known which
-                         * versions of the RM9000 we'll be able to condition-
-                         * alize this.
-                         */
-
                 case CPU_R10000:
                 case CPU_R12000:
                 case CPU_R14000:
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index 25407794edb4..ee331bbd8f8a 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -11,6 +11,7 @@
 #include <asm/fixmap.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
 
 void pgd_init(unsigned long page)
 {
@@ -61,6 +62,36 @@ void pmd_init(unsigned long addr, unsigned long pagetable)
 }
 #endif
 
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+void pmdp_splitting_flush(struct vm_area_struct *vma,
+                         unsigned long address,
+                         pmd_t *pmdp)
+{
+        if (!pmd_trans_splitting(*pmdp)) {
+                pmd_t pmd = pmd_mksplitting(*pmdp);
+                set_pmd_at(vma->vm_mm, address, pmdp, pmd);
+        }
+}
+
+#endif
+
+pmd_t mk_pmd(struct page *page, pgprot_t prot)
+{
+        pmd_t pmd;
+
+        pmd_val(pmd) = (page_to_pfn(page) << _PFN_SHIFT) | pgprot_val(prot);
+
+        return pmd;
+}
+
+void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                pmd_t *pmdp, pmd_t pmd)
+{
+        *pmdp = pmd;
+        flush_tlb_all();
+}
+
 void __init pagetable_init(void)
 {
         unsigned long vaddr;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 4b9b935a070e..94ad86d055c5 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -305,7 +305,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
         pudp = pud_offset(pgdp, address);
         pmdp = pmd_offset(pudp, address);
         idx = read_c0_index();
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         /* this could be a huge page  */
         if (pmd_huge(*pmdp)) {
                 unsigned long lo;
@@ -377,6 +377,26 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
         EXIT_CRITICAL(flags);
 }
 
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+int __init has_transparent_hugepage(void)
+{
+        unsigned int mask;
+        unsigned long flags;
+
+        ENTER_CRITICAL(flags);
+        write_c0_pagemask(PM_HUGE_MASK);
+        back_to_back_c0_hazard();
+        mask = read_c0_pagemask();
+        write_c0_pagemask(PM_DEFAULT_MASK);
+
+        EXIT_CRITICAL(flags);
+
+        return mask == PM_HUGE_MASK;
+}
+
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */
+
 static int __cpuinitdata ntlb;
 static int __init set_ntlb(char *str)
 {
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 818c525b1baf..05613355627b 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -158,7 +158,7 @@ enum label_id {
         label_smp_pgtable_change,
         label_r3000_write_probe_fail,
         label_large_segbits_fault,
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         label_tlb_huge_update,
 #endif
 };
@@ -177,7 +177,7 @@ UASM_L_LA(_nopage_tlbm)
 UASM_L_LA(_smp_pgtable_change)
 UASM_L_LA(_r3000_write_probe_fail)
 UASM_L_LA(_large_segbits_fault)
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 UASM_L_LA(_tlb_huge_update)
 #endif
 
@@ -210,19 +210,59 @@ static void __cpuinit uasm_bgezl_label(struct uasm_label **l,
 }
 
 /*
- * For debug purposes.
+ * pgtable bits are assigned dynamically depending on processor feature
+ * and statically based on kernel configuration.  This spits out the actual
+ * values the kernel is using.  Required to make sense from disassembled
+ * TLB exception handlers.
  */
-static inline void dump_handler(const u32 *handler, int count)
+static void output_pgtable_bits_defines(void)
+{
+#define pr_define(fmt, ...)                                     \
+        pr_debug("#define " fmt, ##__VA_ARGS__)
+
+        pr_debug("#include <asm/asm.h>\n");
+        pr_debug("#include <asm/regdef.h>\n");
+        pr_debug("\n");
+
+        pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
+        pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
+        pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
+        pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
+        pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+        pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
+        pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
+#endif
+        if (cpu_has_rixi) {
+#ifdef _PAGE_NO_EXEC_SHIFT
+                pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
+#endif
+#ifdef _PAGE_NO_READ_SHIFT
+                pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
+#endif
+        }
+        pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
+        pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
+        pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
+        pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
+        pr_debug("\n");
+}
+
+static inline void dump_handler(const char *symbol, const u32 *handler, int count)
 {
         int i;
 
+        pr_debug("LEAF(%s)\n", symbol);
+
         pr_debug("\t.set push\n");
         pr_debug("\t.set noreorder\n");
 
         for (i = 0; i < count; i++)
-                pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
+                pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
+
+        pr_debug("\t.set\tpop\n");
 
-        pr_debug("\t.set pop\n");
+        pr_debug("\tEND(%s)\n", symbol);
 }
 
 /* The only general purpose registers allowed in TLB handlers. */
@@ -405,7 +445,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
 
         memcpy((void *)ebase, tlb_handler, 0x80);
 
-        dump_handler((u32 *)ebase, 32);
+        dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
 }
 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
 
@@ -447,7 +487,6 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
         case CPU_R4600:
         case CPU_R4700:
         case CPU_R5000:
-        case CPU_R5000A:
         case CPU_NEVADA:
                 uasm_i_nop(p);
                 uasm_i_tlbp(p);
@@ -521,7 +560,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 break;
 
         case CPU_R5000:
-        case CPU_R5000A:
         case CPU_NEVADA:
                 uasm_i_nop(p); /* QED specifies 2 nops hazard */
                 uasm_i_nop(p); /* QED specifies 2 nops hazard */
@@ -569,24 +607,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 tlbw(p);
                 break;
 
-        case CPU_RM9000:
-                /*
-                 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
-                 * use of the JTLB for instructions should not occur for 4
-                 * cpu cycles and use for data translations should not occur
-                 * for 3 cpu cycles.
-                 */
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                tlbw(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                uasm_i_ssnop(p);
-                break;
-
         case CPU_VR4111:
         case CPU_VR4121:
         case CPU_VR4122:
@@ -633,7 +653,7 @@ static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
         }
 }
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 
 static __cpuinit void build_restore_pagemask(u32 **p,
                                              struct uasm_reloc **r,
@@ -759,7 +779,7 @@ static __cpuinit void build_huge_handler_tail(u32 **p,
         build_huge_update_entries(p, pte, ptr);
         build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
 }
-#endif /* CONFIG_HUGETLB_PAGE */
+#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
 
 #ifdef CONFIG_64BIT
 /*
@@ -1204,7 +1224,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
         /* Adjust the context during the load latency. */
         build_adjust_context(p, tmp);
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
         /*
          * The in the LWX case we don't want to do the load in the
@@ -1213,7 +1233,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
          */
         if (use_lwx_insns())
                 uasm_i_nop(p);
-#endif /* CONFIG_HUGETLB_PAGE */
+#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
 
 
         /* build_update_entries */
@@ -1316,7 +1336,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
                 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
 #endif
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
                 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
 #endif
 
@@ -1326,7 +1346,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
                 uasm_l_leave(&l, p);
                 uasm_i_eret(&p); /* return from trap */
         }
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         uasm_l_tlb_huge_update(&l, p);
         build_huge_update_entries(&p, htlb_info.huge_pte, K1);
         build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
@@ -1371,7 +1391,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
                 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
                 final_len = p - tlb_handler;
         } else {
-#if defined(CONFIG_HUGETLB_PAGE)
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
                 const enum label_id ls = label_tlb_huge_update;
 #else
                 const enum label_id ls = label_vmalloc;
@@ -1440,7 +1460,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
 
         memcpy((void *)ebase, final_handler, 0x100);
 
-        dump_handler((u32 *)ebase, 64);
+        dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
 }
 
 /*
@@ -1497,7 +1517,8 @@ static void __cpuinit build_r4000_setup_pgd(void)
         pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
                  (unsigned int)(p - tlbmiss_handler_setup_pgd));
 
-        dump_handler(tlbmiss_handler_setup_pgd,
+        dump_handler("tlbmiss_handler",
+                     tlbmiss_handler_setup_pgd,
                      ARRAY_SIZE(tlbmiss_handler_setup_pgd));
 }
 #endif
@@ -1767,7 +1788,7 @@ static void __cpuinit build_r3000_tlb_load_handler(void)
         pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
                  (unsigned int)(p - handle_tlbl));
 
-        dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
+        dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
 }
 
 static void __cpuinit build_r3000_tlb_store_handler(void)
@@ -1797,7 +1818,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void)
         pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
                  (unsigned int)(p - handle_tlbs));
 
-        dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
+        dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
 }
 
 static void __cpuinit build_r3000_tlb_modify_handler(void)
@@ -1827,7 +1848,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
         pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
                  (unsigned int)(p - handle_tlbm));
 
-        dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
+        dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
 }
 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
 
@@ -1846,7 +1867,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
         build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
 #endif
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         /*
          * For huge tlb entries, pmd doesn't contain an address but
          * instead contains the tlb pte. Check the PAGE_HUGE bit and
@@ -1962,7 +1983,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
         build_make_valid(&p, &r, wr.r1, wr.r2);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         /*
          * This is the entry point when build_r4000_tlbchange_handler_head
          * spots a huge page.
@@ -2034,7 +2055,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
         pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
                  (unsigned int)(p - handle_tlbl));
 
-        dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
+        dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
 }
 
 static void __cpuinit build_r4000_tlb_store_handler(void)
@@ -2055,7 +2076,7 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
         build_make_write(&p, &r, wr.r1, wr.r2);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         /*
          * This is the entry point when
          * build_r4000_tlbchange_handler_head spots a huge page.
@@ -2081,7 +2102,7 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
         pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
                  (unsigned int)(p - handle_tlbs));
 
-        dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
+        dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
 }
 
 static void __cpuinit build_r4000_tlb_modify_handler(void)
@@ -2103,7 +2124,7 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
         build_make_write(&p, &r, wr.r1, wr.r2);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
 
-#ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
         /*
          * This is the entry point when
          * build_r4000_tlbchange_handler_head spots a huge page.
@@ -2129,7 +2150,7 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
         pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
                  (unsigned int)(p - handle_tlbm));
 
-        dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
+        dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
 }
 
 void __cpuinit build_tlb_refill_handler(void)
@@ -2141,6 +2162,8 @@ void __cpuinit build_tlb_refill_handler(void)
          */
         static int run_once = 0;
 
+        output_pgtable_bits_defines();
+
 #ifdef CONFIG_64BIT
         check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
 #endif
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 80562b81f0f2..74732177851c 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <asm/mips-boards/maltaint.h>
 #include <mtd/mtd-abi.h>
 
 #define SMC_PORT(base, int)                                             \
@@ -48,7 +49,7 @@ static struct plat_serial8250_port uart8250_data[] = {
         SMC_PORT(0x2F8, 3),
         {
                 .mapbase        = 0x1f000900,   /* The CBUS UART */
-                .irq            = MIPS_CPU_IRQ_BASE + 2,
+                .irq            = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
                 .uartclk        = 3686400,      /* Twice the usual clk! */
                 .iotype         = UPIO_MEM32,
                 .flags          = CBUS_UART_FLAGS,
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 65f5237ec821..9c0a6782c091 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -13,5 +13,4 @@ oprofile-$(CONFIG_CPU_MIPS64)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_R10000)           += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_SB1)              += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_XLR)              += op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_RM9000)           += op_model_rm9000.o
 oprofile-$(CONFIG_CPU_LOONGSON2)        += op_model_loongson2.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index abd5a02f47cf..e32db1ff02c7 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -16,7 +16,6 @@
 #include "op_impl.h"
 
 extern struct op_mips_model op_model_mipsxx_ops __weak;
-extern struct op_mips_model op_model_rm9000_ops __weak;
 extern struct op_mips_model op_model_loongson2_ops __weak;
 
 static struct op_mips_model *model;
@@ -95,9 +94,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
                 lmodel = &op_model_mipsxx_ops;
                 break;
 
-        case CPU_RM9000:
-                lmodel = &op_model_rm9000_ops;
-                break;
         case CPU_LOONGSON2:
                 lmodel = &op_model_loongson2_ops;
                 break;
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
deleted file mode 100644
index 3aa81384966d..000000000000
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/oprofile.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-
-#include "op_impl.h"
-
-#define RM9K_COUNTER1_EVENT(event)      ((event) << 0)
-#define RM9K_COUNTER1_SUPERVISOR        (1ULL    <<  7)
-#define RM9K_COUNTER1_KERNEL            (1ULL    <<  8)
-#define RM9K_COUNTER1_USER              (1ULL    <<  9)
-#define RM9K_COUNTER1_ENABLE            (1ULL    << 10)
-#define RM9K_COUNTER1_OVERFLOW          (1ULL    << 15)
-
-#define RM9K_COUNTER2_EVENT(event)      ((event) << 16)
-#define RM9K_COUNTER2_SUPERVISOR        (1ULL    << 23)
-#define RM9K_COUNTER2_KERNEL            (1ULL    << 24)
-#define RM9K_COUNTER2_USER              (1ULL    << 25)
-#define RM9K_COUNTER2_ENABLE            (1ULL    << 26)
-#define RM9K_COUNTER2_OVERFLOW          (1ULL    << 31)
-
-extern unsigned int rm9000_perfcount_irq;
-
-static struct rm9k_register_config {
-        unsigned int control;
-        unsigned int reset_counter1;
-        unsigned int reset_counter2;
-} reg;
-
-/* Compute all of the registers in preparation for enabling profiling.  */
-
-static void rm9000_reg_setup(struct op_counter_config *ctr)
-{
-        unsigned int control = 0;
-
-        /* Compute the performance counter control word.  */
-        /* For now count kernel and user mode */
-        if (ctr[0].enabled)
-                control |= RM9K_COUNTER1_EVENT(ctr[0].event) |
-                           RM9K_COUNTER1_KERNEL |
-                           RM9K_COUNTER1_USER |
-                           RM9K_COUNTER1_ENABLE;
-        if (ctr[1].enabled)
-                control |= RM9K_COUNTER2_EVENT(ctr[1].event) |
-                           RM9K_COUNTER2_KERNEL |
-                           RM9K_COUNTER2_USER |
-                           RM9K_COUNTER2_ENABLE;
-        reg.control = control;
-
-        reg.reset_counter1 = 0x80000000 - ctr[0].count;
-        reg.reset_counter2 = 0x80000000 - ctr[1].count;
-}
-
-/* Program all of the registers in preparation for enabling profiling.  */
-
-static void rm9000_cpu_setup(void *args)
-{
-        uint64_t perfcount;
-
-        perfcount = ((uint64_t) reg.reset_counter2 << 32) | reg.reset_counter1;
-        write_c0_perfcount(perfcount);
-}
-
-static void rm9000_cpu_start(void *args)
-{
-        /* Start all counters on current CPU */
-        write_c0_perfcontrol(reg.control);
-}
-
-static void rm9000_cpu_stop(void *args)
-{
-        /* Stop all counters on current CPU */
-        write_c0_perfcontrol(0);
-}
-
-static irqreturn_t rm9000_perfcount_handler(int irq, void *dev_id)
-{
-        unsigned int control = read_c0_perfcontrol();
-        struct pt_regs *regs = get_irq_regs();
-        uint32_t counter1, counter2;
-        uint64_t counters;
-
-        /*
-         * RM9000 combines two 32-bit performance counters into a single
-         * 64-bit coprocessor zero register.  To avoid a race updating the
-         * registers we need to stop the counters while we're messing with
-         * them ...
-         */
-        write_c0_perfcontrol(0);
-
-        counters = read_c0_perfcount();
-        counter1 = counters;
-        counter2 = counters >> 32;
-
-        if (control & RM9K_COUNTER1_OVERFLOW) {
-                oprofile_add_sample(regs, 0);
-                counter1 = reg.reset_counter1;
-        }
-        if (control & RM9K_COUNTER2_OVERFLOW) {
-                oprofile_add_sample(regs, 1);
-                counter2 = reg.reset_counter2;
-        }
-
-        counters = ((uint64_t)counter2 << 32) | counter1;
-        write_c0_perfcount(counters);
-        write_c0_perfcontrol(reg.control);
-
-        return IRQ_HANDLED;
-}
-
-static int __init rm9000_init(void)
-{
-        return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
-                           0, "Perfcounter", NULL);
-}
-
-static void rm9000_exit(void)
-{
-        free_irq(rm9000_perfcount_irq, NULL);
-}
-
-struct op_mips_model op_model_rm9000_ops = {
-        .reg_setup      = rm9000_reg_setup,
-        .cpu_setup      = rm9000_cpu_setup,
-        .init           = rm9000_init,
-        .exit           = rm9000_exit,
-        .cpu_start      = rm9000_cpu_start,
-        .cpu_stop       = rm9000_cpu_stop,
-        .cpu_type       = "mips/rm9000",
-        .num_counters   = 2
-};
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index e13a71cbc3c7..ce995d3d9440 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -34,8 +34,6 @@ obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)    += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)  += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_FPGA)  += fixup-pmcmsp.o ops-pmcmsp.o
-obj-$(CONFIG_PMC_YOSEMITE)      += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
-                                   pci-yosemite.o
 obj-$(CONFIG_SGI_IP27)          += ops-bridge.o pci-ip27.o
 obj-$(CONFIG_SGI_IP32)          += fixup-ip32.o ops-mace.o pci-ip32.o
 obj-$(CONFIG_SIBYTE_SB1250)     += fixup-sb1250.o pci-sb1250.o
diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c
deleted file mode 100644
index fdafb13a793b..000000000000
--- a/arch/mips/pci/fixup-yosemite.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        if (pin == 0)
-                return -1;
-
-        return 3;                       /* Everything goes to one irq bit */
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-        return 0;
-}
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index b46b3e211775..438319465cb4 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -56,7 +56,7 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to look at it for real ...
          */
         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
@@ -76,7 +76,7 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
 oh_my_gawd:
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to look at the wrong register.
          */
         if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
@@ -85,7 +85,7 @@ oh_my_gawd:
         }
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't try to access
+         * IOC3 is fucking fucked beyond belief ...  Don't try to access
          * anything but 32-bit words ...
          */
         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
@@ -118,7 +118,7 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to look at it for real ...
          */
         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
@@ -139,7 +139,7 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
 oh_my_gawd:
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to look at the wrong register.
          */
         if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
@@ -148,7 +148,7 @@ oh_my_gawd:
         }
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't try to access
+         * IOC3 is fucking fucked beyond belief ...  Don't try to access
          * anything but 32-bit words ...
          */
         bridge->b_pci_cfg = (busno << 16) | (slot << 11);
@@ -189,7 +189,7 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to look at it for real ...
          */
         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
@@ -213,14 +213,14 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
 oh_my_gawd:
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to touch the wrong register.
          */
         if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
                 return PCIBIOS_SUCCESSFUL;
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't try to access
+         * IOC3 is fucking fucked beyond belief ...  Don't try to access
          * anything but 32-bit words ...
          */
         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
@@ -257,7 +257,7 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to look at it for real ...
          */
         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
@@ -281,14 +281,14 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
 oh_my_gawd:
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't even give the
+         * IOC3 is fucking fucked beyond belief ...  Don't even give the
          * generic PCI code a chance to touch the wrong register.
          */
         if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
                 return PCIBIOS_SUCCESSFUL;
 
         /*
-         * IOC3 is fucked fucked beyond believe ...  Don't try to access
+         * IOC3 is fucking fucked beyond belief ...  Don't try to access
          * anything but 32-bit words ...
          */
         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
deleted file mode 100644
index 57d54adc9e20..000000000000
--- a/arch/mips/pci/ops-titan-ht.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-
-#include <asm/titan_dep.h>
-
-static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
-        int offset, u32 *val)
-{
-        volatile uint32_t address;
-        int busno;
-
-        busno = bus->number;
-
-        address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
-        if (busno != 0)
-                address |= 1;
-
-        /*
-         * RM9000 HT Errata: Issue back to back HT config
-         * transcations. Issue a BIU sync before and
-         * after the HT cycle
-         */
-
-        *(volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-        udelay(30);
-
-        *(volatile int32_t *) 0xfb0006f8 = address;
-        *(val) = *(volatile int32_t *) 0xfb0006fc;
-
-        udelay(30);
-
-        * (volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
-        int offset, int size, u32 *val)
-{
-        uint32_t dword;
-
-        titan_ht_config_read_dword(bus, devfn, offset, &dword);
-
-        dword >>= ((offset & 3) << 3);
-        dword &= (0xffffffffU >> ((4 - size) << 8));
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static inline int titan_ht_config_write_dword(struct pci_bus *bus,
-        unsigned int devfn, int offset, u32 val)
-{
-        volatile uint32_t address;
-        int busno;
-
-        busno = bus->number;
-
-        address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
-        if (busno != 0)
-                address |= 1;
-
-        *(volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-        udelay(30);
-
-        *(volatile int32_t *) 0xfb0006f8 = address;
-        *(volatile int32_t *) 0xfb0006fc = val;
-
-        udelay(30);
-
-        *(volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_write(struct pci_bus *bus, unsigned int devfn,
-        int offset, int size, u32 val)
-{
-        uint32_t val1, val2, mask;
-
-        titan_ht_config_read_dword(bus, devfn, offset, &val2);
-
-        val1 = val << ((offset & 3) << 3);
-        mask = ~(0xffffffffU >> ((4 - size) << 8));
-        val2 &= ~(mask << ((offset & 3) << 8));
-
-        titan_ht_config_write_dword(bus, devfn, offset, val1 | val2);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops titan_ht_pci_ops = {
-        .read   = titan_ht_config_read,
-        .write  = titan_ht_config_write,
-};
diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c
deleted file mode 100644
index ebf8fc40e9b2..000000000000
--- a/arch/mips/pci/ops-titan.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/pci.h>
-#include <asm/io.h>
-#include <asm/rm9k-ocd.h>
-
-/*
- * PCI specific defines
- */
-#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
-#define TITAN_PCI_0_CONFIG_DATA         0x784
-
-/*
- * Titan PCI Config Read Byte
- */
-static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
-        int size, u32 * val)
-{
-        uint32_t address, tmp;
-        int dev, busno, func;
-
-        busno = bus->number;
-        dev = PCI_SLOT(devfn);
-        func = PCI_FUNC(devfn);
-
-        address = (busno << 16) | (dev << 11) | (func << 8) |
-                  (reg & 0xfc) | 0x80000000;
-
-
-        /* start the configuration cycle */
-        ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
-        tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
-
-        switch (size) {
-        case 1:
-                tmp &= 0xff;
-        case 2:
-                tmp &= 0xffff;
-        }
-        *val = tmp;
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
-        int size, u32 val)
-{
-        uint32_t address;
-        int dev, busno, func;
-
-        busno = bus->number;
-        dev = PCI_SLOT(devfn);
-        func = PCI_FUNC(devfn);
-
-        address = (busno << 16) | (dev << 11) | (func << 8) |
-                (reg & 0xfc) | 0x80000000;
-
-        /* start the configuration cycle */
-        ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
-
-        /* write the data */
-        switch (size) {
-        case 1:
-                ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
-                break;
-
-        case 2:
-                ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
-                break;
-
-        case 4:
-                ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
-                break;
-        }
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-/*
- * Titan PCI structure
- */
-struct pci_ops titan_pci_ops = {
-        titan_read_config,
-        titan_write_config,
-};
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 4b0c347d7a82..5b5ed76c6f47 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -11,6 +11,7 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
 #include <linux/swiotlb.h>
 
 #include <asm/time.h>
@@ -704,6 +705,10 @@ static int __init octeon_pci_setup(void)
          */
         cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
 
+        if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
+                                                   -1, NULL, 0)))
+                pr_err("Registation of co_pci_edac failed!\n");
+
         octeon_pci_dma_init();
 
         return 0;
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
deleted file mode 100644
index cf5e1a25cb7d..000000000000
--- a/arch/mips/pci/pci-yosemite.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/titan_dep.h>
-
-extern struct pci_ops titan_pci_ops;
-
-static struct resource py_mem_resource = {
-        .start  = 0xe0000000UL,
-        .end    = 0xe3ffffffUL,
-        .name   = "Titan PCI MEM",
-        .flags  = IORESOURCE_MEM
-};
-
-/*
- * PMON really reserves 16MB of I/O port space but that's stupid, nothing
- * needs that much since allocations are limited to 256 bytes per device
- * anyway.  So we just claim 64kB here.
- */
-#define TITAN_IO_SIZE   0x0000ffffUL
-#define TITAN_IO_BASE   0xe8000000UL
-
-static struct resource py_io_resource = {
-        .start  = 0x00001000UL,
-        .end    = TITAN_IO_SIZE - 1,
-        .name   = "Titan IO MEM",
-        .flags  = IORESOURCE_IO,
-};
-
-static struct pci_controller py_controller = {
-        .pci_ops        = &titan_pci_ops,
-        .mem_resource   = &py_mem_resource,
-        .mem_offset     = 0x00000000UL,
-        .io_resource    = &py_io_resource,
-        .io_offset      = 0x00000000UL
-};
-
-static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
-
-static int __init pmc_yosemite_setup(void)
-{
-        unsigned long io_v_base;
-
-        io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
-        if (!io_v_base)
-                panic(ioremap_failed);
-
-        set_io_port_base(io_v_base);
-        py_controller.io_map_base = io_v_base;
-        TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
-
-        ioport_resource.end = TITAN_IO_SIZE - 1;
-
-        register_pci_controller(&py_controller);
-
-        return 0;
-}
-
-arch_initcall(pmc_yosemite_setup);
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index bbd76082fa8c..3482b8c8640c 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -34,10 +34,6 @@ config PMC_MSP7120_FPGA
 
 endchoice
 
-config HYPERTRANSPORT
-        bool "Hypertransport Support for PMC-Sierra Yosemite"
-        depends on PMC_YOSEMITE
-
 config MSP_HAS_USB
         boolean
         depends on PMC_MSP
diff --git a/arch/mips/pmc-sierra/Platform b/arch/mips/pmc-sierra/Platform
index f092f2524c5f..387fda6c28c6 100644
--- a/arch/mips/pmc-sierra/Platform
+++ b/arch/mips/pmc-sierra/Platform
@@ -5,10 +5,3 @@ platform-$(CONFIG_PMC_MSP)	+= pmc-sierra/msp71xx/
 cflags-$(CONFIG_PMC_MSP)        += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
                                         -mno-branch-likely
 load-$(CONFIG_PMC_MSP)          += 0xffffffff80100000
-
-#
-# PMC-Sierra Yosemite
-#
-platform-$(CONFIG_PMC_YOSEMITE) += pmc-sierra/yosemite/
-cflags-$(CONFIG_PMC_YOSEMITE)   += -I$(srctree)/arch/mips/include/asm/mach-yosemite
-load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
deleted file mode 100644
index 5af95ec3319d..000000000000
--- a/arch/mips/pmc-sierra/yosemite/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the PMC-Sierra Titan
-#
-
-obj-y    += irq.o prom.o py-console.o setup.o
-
-obj-$(CONFIG_SMP)               += smp.o
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
deleted file mode 100644
index d6f8bdff8cbb..000000000000
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Description:
- *
- * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
- * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
- * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
- * expected to have a connectivity from the EEPROM to the serial port. This program does
- * __not__ communicate using the I2C protocol
- */
-
-#include "atmel_read_eeprom.h"
-
-static void delay(int delay)
-{
-        while (delay--);
-}
-
-static void send_bit(unsigned char bit)
-{
-        scl_lo;
-        delay(TXX);
-        if (bit)
-                sda_hi;
-        else
-                sda_lo;
-
-        delay(TXX);
-        scl_hi;
-        delay(TXX);
-}
-
-static void send_ack(void)
-{
-        send_bit(0);
-}
-
-static void send_byte(unsigned char byte)
-{
-        int     i = 0;
-
-        for (i = 7; i >= 0; i--)
-                send_bit((byte >> i) & 0x01);
-}
-
-static void send_start(void)
-{
-        sda_hi;
-        delay(TXX);
-        scl_hi;
-        delay(TXX);
-        sda_lo;
-        delay(TXX);
-}
-
-static void send_stop(void)
-{
-        sda_lo;
-        delay(TXX);
-        scl_hi;
-        delay(TXX);
-        sda_hi;
-        delay(TXX);
-}
-
-static void do_idle(void)
-{
-        sda_hi;
-        scl_hi;
-        vcc_off;
-}
-
-static int recv_bit(void)
-{
-        int     status;
-
-        scl_lo;
-        delay(TXX);
-        sda_hi;
-        delay(TXX);
-        scl_hi;
-        delay(TXX);
-
-        return 1;
-}
-
-static unsigned char recv_byte(void) {
-        int i;
-        unsigned char byte=0;
-
-        for (i=7;i>=0;i--)
-                byte |= (recv_bit() << i);
-
-        return byte;
-}
-
-static int recv_ack(void)
-{
-        unsigned int    ack;
-
-        ack = (unsigned int)recv_bit();
-        scl_lo;
-
-        if (ack) {
-                do_idle();
-                printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM\n");
-                return -1;
-        }
-
-        return ack;
-}
-
-/*
- * This function does the actual read of the EEPROM. It needs the buffer into which the
- * read data is copied, the size of the EEPROM being read and the buffer size
- */
-int read_eeprom(char *buffer, int eeprom_size, int size)
-{
-        int     i = 0, err;
-
-        send_start();
-        send_byte(W_HEADER);
-        recv_ack();
-
-        /* EEPROM with size of more than 2K need two byte addressing */
-        if (eeprom_size > 2048) {
-                send_byte(0x00);
-                recv_ack();
-        }
-
-        send_start();
-        send_byte(R_HEADER);
-        err = recv_ack();
-        if (err == -1)
-                return err;
-
-        for (i = 0; i < size; i++) {
-                *buffer++ = recv_byte();
-                send_ack();
-        }
-
-        /* Note : We should do some check if the buffer contains correct information */
-
-        send_stop();
-}
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
deleted file mode 100644
index d6c7ec469fa8..000000000000
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
- *
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *  Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Header file for atmel_read_eeprom.c
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <asm/pci.h>
-#include <asm/io.h>
-#include <linux/init.h>
-#include <asm/termios.h>
-#include <asm/ioctls.h>
-#include <linux/ioctl.h>
-#include <linux/fcntl.h>
-
-#define DEFAULT_PORT    "/dev/ttyS0"    /* Port to open */
-#define TXX             0               /* Dummy loop for spinning */
-
-#define BLOCK_SEL       0x00
-#define SLAVE_ADDR      0xa0
-#define READ_BIT        0x01
-#define WRITE_BIT       0x00
-#define R_HEADER        SLAVE_ADDR + BLOCK_SEL + READ_BIT
-#define W_HEADER        SLAVE_ADDR + BLOCK_SEL + WRITE_BIT
-
-/*
- * Clock, Voltages and Data
- */
-#define vcc_off         (ioctl(fd, TIOCSBRK, 0))
-#define vcc_on          (ioctl(fd, TIOCCBRK, 0))
-#define sda_hi          (ioctl(fd, TIOCMBIS, &dtr))
-#define sda_lo          (ioctl(fd, TIOCMBIC, &dtr))
-#define scl_lo          (ioctl(fd, TIOCMBIC, &rts))
-#define scl_hi          (ioctl(fd, TIOCMBIS, &rts))
-
-const char rts = TIOCM_RTS;
-const char dtr = TIOCM_DTR;
-int fd;
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
deleted file mode 100644
index 62ead6601c69..000000000000
--- a/arch/mips/pmc-sierra/yosemite/ht-irq.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/pci.h>
-
-/*
- * HT Bus fixup for the Titan
- * XXX IRQ values need to change based on the board layout
- */
-void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
-{
-        /*
-         * PLX and SPKT related changes go here
-         */
-}
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
deleted file mode 100644
index 14dc9c8fff0e..000000000000
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <asm/pci.h>
-#include <asm/io.h>
-
-#include <linux/init.h>
-#include <asm/titan_dep.h>
-
-#ifdef CONFIG_HYPERTRANSPORT
-
-
-/*
- * This function check if the Hypertransport Link Initialization completed. If
- * it did, then proceed further with scanning bus #2
- */
-static __inline__ int check_titan_htlink(void)
-{
-        u32 val;
-
-        val = *(volatile uint32_t *)(RM9000x2_HTLINK_REG);
-        if (val & 0x00000020)
-                /* HT Link Initialization completed */
-                return 1;
-        else
-                return 0;
-}
-
-static int titan_ht_config_read_dword(struct pci_dev *device,
-                                             int offset, u32* val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-        /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                        0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_READ(data_reg, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int titan_ht_config_read_word(struct pci_dev *device,
-                                             int offset, u16* val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-        /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        if ((offset & 0x3) == 0)
-                offset = 0x2;
-        else
-                offset = 0x0;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_READ_16(data_reg + offset, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-u32 longswap(unsigned long l)
-{
-        unsigned char b1, b2, b3, b4;
-
-        b1 = l&255;
-        b2 = (l>>8)&255;
-        b3 = (l>>16)&255;
-        b4 = (l>>24)&255;
-
-        return ((b1<<24) + (b2<<16) + (b3<<8) + b4);
-}
-
-
-static int titan_ht_config_read_byte(struct pci_dev *device,
-                                             int offset, u8* val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-        int offset1;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-        /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                        0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-
-        if ((offset & 0x3) == 0) {
-                offset1 = 0x3;
-        }
-        if ((offset & 0x3) == 1) {
-                offset1 = 0x2;
-        }
-        if ((offset & 0x3) == 2) {
-                offset1 = 0x1;
-        }
-        if ((offset & 0x3) == 3) {
-                offset1 = 0x0;
-        }
-        RM9K_READ_8(data_reg + offset1, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int titan_ht_config_write_dword(struct pci_dev *device,
-                                             int offset, u8 val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-        /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                        0x80000000 | 0x1;
-        else
-              address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_WRITE(data_reg, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_write_word(struct pci_dev *device,
-                                             int offset, u8 val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-        /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        if ((offset & 0x3) == 0)
-                offset = 0x2;
-        else
-                offset = 0x0;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_WRITE_16(data_reg + offset, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_write_byte(struct pci_dev *device,
-                                             int offset, u8 val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-        int offset1;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-        /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-
-        if ((offset & 0x3) == 0) {
-             offset1 = 0x3;
-        }
-        if ((offset & 0x3) == 1) {
-             offset1 = 0x2;
-        }
-        if ((offset & 0x3) == 2) {
-             offset1 = 0x1;
-        }
-        if ((offset & 0x3) == 3) {
-            offset1 = 0x0;
-        }
-
-        RM9K_WRITE_8(data_reg + offset1, val);
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static void titan_pcibios_set_master(struct pci_dev *dev)
-{
-        u16 cmd;
-        int bus = dev->bus->number;
-
-        if (check_titan_htlink())
-            titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
-
-        cmd |= PCI_COMMAND_MASTER;
-
-        if (check_titan_htlink())
-            titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
-}
-
-
-int pcibios_enable_resources(struct pci_dev *dev)
-{
-        u16 cmd, old_cmd;
-        u8 tmp1;
-        int idx;
-        struct resource *r;
-        int bus = dev->bus->number;
-
-        if (check_titan_htlink())
-            titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
-
-        old_cmd = cmd;
-        for (idx = 0; idx < 6; idx++) {
-                r = &dev->resource[idx];
-                if (!r->start && r->end) {
-                        printk(KERN_ERR
-                               "PCI: Device %s not available because of "
-                               "resource collisions\n", pci_name(dev));
-                        return -EINVAL;
-                }
-                if (r->flags & IORESOURCE_IO)
-                        cmd |= PCI_COMMAND_IO;
-                if (r->flags & IORESOURCE_MEM)
-                        cmd |= PCI_COMMAND_MEMORY;
-        }
-        if (cmd != old_cmd) {
-                if (check_titan_htlink())
-                   titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
-        }
-
-        if (check_titan_htlink())
-                titan_ht_config_read_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
-
-        if (tmp1 != 8) {
-                printk(KERN_WARNING "PCI setting cache line size to 8 from "
-                       "%d\n", tmp1);
-        }
-
-        if (check_titan_htlink())
-                titan_ht_config_write_byte(dev, PCI_CACHE_LINE_SIZE, 8);
-
-        if (check_titan_htlink())
-                titan_ht_config_read_byte(dev, PCI_LATENCY_TIMER, &tmp1);
-
-        if (tmp1 < 32 || tmp1 == 0xff) {
-                printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
-                       tmp1);
-        }
-
-        if (check_titan_htlink())
-                titan_ht_config_write_byte(dev, PCI_LATENCY_TIMER, 32);
-
-        return 0;
-}
-
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pcibios_enable_resources(dev);
-}
-
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                                resource_size_t size, resource_size_t align)
-{
-        struct pci_dev *dev = data;
-        resource_size_t start = res->start;
-
-        if (res->flags & IORESOURCE_IO) {
-                /* We need to avoid collisions with `mirrored' VGA ports
-                   and other strange ISA hardware, so we always want the
-                   addresses kilobyte aligned.  */
-                if (size > 0x100) {
-                        printk(KERN_ERR "PCI: I/O Region %s/%d too large"
-                               " (%ld bytes)\n", pci_name(dev),
-                                dev->resource - res, size);
-                }
-
-                start = (start + 1024 - 1) & ~(1024 - 1);
-        }
-
-        return start;
-}
-
-struct pci_ops titan_pci_ops = {
-        titan_ht_config_read_byte,
-        titan_ht_config_read_word,
-        titan_ht_config_read_dword,
-        titan_ht_config_write_byte,
-        titan_ht_config_write_word,
-        titan_ht_config_write_dword
-};
-
-void __init pcibios_fixup_bus(struct pci_bus *c)
-{
-        titan_ht_pcibios_fixup_bus(c);
-}
-
-void __init pcibios_init(void)
-{
-
-        /* Reset PCI I/O and PCI MEM values */
-        /* XXX Need to add the proper values here */
-        ioport_resource.start = 0xe0000000;
-        ioport_resource.end   = 0xe0000000 + 0x20000000 - 1;
-        iomem_resource.start  = 0xc0000000;
-        iomem_resource.end    = 0xc0000000 + 0x20000000 - 1;
-
-        /* XXX Need to add bus values */
-        pci_scan_bus(2, &titan_pci_ops, NULL);
-        pci_scan_bus(3, &titan_pci_ops, NULL);
-}
-
-unsigned __init int pcibios_assign_all_busses(void)
-{
-        /* We want to use the PCI bus detection done by PMON */
-        return 0;
-}
-
-#endif /* CONFIG_HYPERTRANSPORT */
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
deleted file mode 100644
index 6590812daa56..000000000000
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (C) 2003 PMC-Sierra Inc.
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Second level Interrupt handlers for the PMC-Sierra Titan/Yosemite board
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/timex.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/titan_dep.h>
-
-/* Hypertransport specific */
-#define IRQ_ACK_BITS            0x00000000      /* Ack bits */
-
-#define HYPERTRANSPORT_INTA     0x78            /* INTA# */
-#define HYPERTRANSPORT_INTB     0x79            /* INTB# */
-#define HYPERTRANSPORT_INTC     0x7a            /* INTC# */
-#define HYPERTRANSPORT_INTD     0x7b            /* INTD# */
-
-extern void titan_mailbox_irq(void);
-
-#ifdef CONFIG_HYPERTRANSPORT
-/*
- * Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
- * For interprocessor interrupts, the best thing to do is to use the INTMSG
- * register. We use the same external interrupt line, i.e. INTB3 and monitor
- * another status bit
- */
-static void ll_ht_smp_irq_handler(int irq)
-{
-        u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
-
-        /* Ack all the bits that correspond to the interrupt sources */
-        if (status != 0)
-                OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
-
-        status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
-        if (status != 0)
-                OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
-
-#ifdef CONFIG_HT_LEVEL_TRIGGER
-        /*
-         * Level Trigger Mode only. Send the HT EOI message back to the source.
-         */
-        switch (status) {
-        case 0x1000000:
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
-                break;
-        case 0x2000000:
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
-                break;
-        case 0x4000000:
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
-                break;
-        case 0x8000000:
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
-                break;
-        case 0x0000001:
-                /* PLX */
-                OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
-                OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
-                break;
-        case 0xf000000:
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
-                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
-                break;
-        }
-#endif /* CONFIG_HT_LEVEL_TRIGGER */
-
-        do_IRQ(irq);
-}
-#endif
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        unsigned int cause = read_c0_cause();
-        unsigned int status = read_c0_status();
-        unsigned int pending = cause & status;
-
-        if (pending & STATUSF_IP7) {
-                do_IRQ(7);
-        } else if (pending & STATUSF_IP2) {
-#ifdef CONFIG_HYPERTRANSPORT
-                ll_ht_smp_irq_handler(2);
-#else
-                do_IRQ(2);
-#endif
-        } else if (pending & STATUSF_IP3) {
-                do_IRQ(3);
-        } else if (pending & STATUSF_IP4) {
-                do_IRQ(4);
-        } else if (pending & STATUSF_IP5) {
-#ifdef CONFIG_SMP
-                titan_mailbox_irq();
-#else
-                do_IRQ(5);
-#endif
-        } else if (pending & STATUSF_IP6) {
-                do_IRQ(4);
-        }
-}
-
-/*
- * Initialize the next level interrupt handler
- */
-void __init arch_init_irq(void)
-{
-        clear_c0_status(ST0_IM);
-
-        mips_cpu_irq_init();
-        rm7k_cpu_irq_init();
-        rm9k_cpu_irq_init();
-}
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
deleted file mode 100644
index 6a2754c4f106..000000000000
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Copyright (C) 2003, 2004 PMC-Sierra Inc.
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- * Copyright (C) 2004 Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/smp.h>
-
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/smp-ops.h>
-#include <asm/bootinfo.h>
-#include <asm/pmon.h>
-
-#ifdef CONFIG_SMP
-extern void prom_grab_secondary(void);
-#else
-#define prom_grab_secondary() do { } while (0)
-#endif
-
-#include "setup.h"
-
-struct callvectors *debug_vectors;
-
-extern unsigned long yosemite_base;
-extern unsigned long cpu_clock_freq;
-
-const char *get_system_type(void)
-{
-        return "PMC-Sierra Yosemite";
-}
-
-static void prom_cpu0_exit(void *arg)
-{
-        void *nvram = (void *) YOSEMITE_RTC_BASE;
-
-        /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
-        writeb(0x84, nvram + 0xff7);
-
-        /* wait for the watchdog to go off */
-        mdelay(100 + (1000 / 16));
-
-        /* if the watchdog fails for some reason, let people know */
-        printk(KERN_NOTICE "Watchdog reset failed\n");
-}
-
-/*
- * Reset the NVRAM over the local bus
- */
-static void prom_exit(void)
-{
-#ifdef CONFIG_SMP
-        if (smp_processor_id())
-                /* CPU 1 */
-                smp_call_function(prom_cpu0_exit, NULL, 1);
-#endif
-        prom_cpu0_exit(NULL);
-}
-
-/*
- * Halt the system
- */
-static void prom_halt(void)
-{
-        printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-        while (1)
-                __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
-}
-
-extern struct plat_smp_ops yos_smp_ops;
-
-/*
- * Init routine which accepts the variables from PMON
- */
-void __init prom_init(void)
-{
-        int argc = fw_arg0;
-        char **arg = (char **) fw_arg1;
-        char **env = (char **) fw_arg2;
-        struct callvectors *cv = (struct callvectors *) fw_arg3;
-        int i = 0;
-
-        /* Callbacks for halt, restart */
-        _machine_restart = (void (*)(char *)) prom_exit;
-        _machine_halt = prom_halt;
-        pm_power_off = prom_halt;
-
-        debug_vectors = cv;
-        arcs_cmdline[0] = '\0';
-
-        /* Get the boot parameters */
-        for (i = 1; i < argc; i++) {
-                if (strlen(arcs_cmdline) + strlen(arg[i]) + 1 >=
-                    sizeof(arcs_cmdline))
-                        break;
-
-                strcat(arcs_cmdline, arg[i]);
-                strcat(arcs_cmdline, " ");
-        }
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        if ((strstr(arcs_cmdline, "console=ttyS")) == NULL)
-                strcat(arcs_cmdline, "console=ttyS0,115200");
-#endif
-
-        while (*env) {
-                if (strncmp("ocd_base", *env, strlen("ocd_base")) == 0)
-                        yosemite_base =
-                            simple_strtol(*env + strlen("ocd_base="), NULL,
-                                          16);
-
-                if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0)
-                        cpu_clock_freq =
-                            simple_strtol(*env + strlen("cpuclock="), NULL,
-                                          10);
-
-                env++;
-        }
-
-        prom_grab_secondary();
-
-        register_smp_ops(&yos_smp_ops);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
-{
-}
diff --git a/arch/mips/pmc-sierra/yosemite/py-console.c b/arch/mips/pmc-sierra/yosemite/py-console.c
deleted file mode 100644
index b7f1d9c4a8a3..000000000000
--- a/arch/mips/pmc-sierra/yosemite/py-console.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001, 2002, 2004 Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/termios.h>
-#include <linux/sched.h>
-#include <linux/tty.h>
-
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <asm/serial.h>
-#include <asm/io.h>
-
-/* SUPERIO uart register map */
-struct yo_uartregs {
-        union {
-                volatile u8     rbr;    /* read only, DLAB == 0 */
-                volatile u8     thr;    /* write only, DLAB == 0 */
-                volatile u8     dll;    /* DLAB == 1 */
-        } u1;
-        union {
-                volatile u8     ier;    /* DLAB == 0 */
-                volatile u8     dlm;    /* DLAB == 1 */
-        } u2;
-        union {
-                volatile u8     iir;    /* read only */
-                volatile u8     fcr;    /* write only */
-        } u3;
-        volatile u8     iu_lcr;
-        volatile u8     iu_mcr;
-        volatile u8     iu_lsr;
-        volatile u8     iu_msr;
-        volatile u8     iu_scr;
-} yo_uregs_t;
-
-#define iu_rbr u1.rbr
-#define iu_thr u1.thr
-#define iu_dll u1.dll
-#define iu_ier u2.ier
-#define iu_dlm u2.dlm
-#define iu_iir u3.iir
-#define iu_fcr u3.fcr
-
-#define ssnop()         __asm__ __volatile__("sll       $0, $0, 1\n");
-#define ssnop_4()       do { ssnop(); ssnop(); ssnop(); ssnop(); } while (0)
-
-#define IO_BASE_64      0x9000000000000000ULL
-
-static unsigned char readb_outer_space(unsigned long long phys)
-{
-        unsigned long long vaddr = IO_BASE_64 | phys;
-        unsigned char res;
-        unsigned int sr;
-
-        sr = read_c0_status();
-        write_c0_status((sr | ST0_KX) & ~ ST0_IE);
-        ssnop_4();
-
-        __asm__ __volatile__ (
-        "       .set    mips3           \n"
-        "       ld      %0, %1          \n"
-        "       lbu     %0, (%0)        \n"
-        "       .set    mips0           \n"
-        : "=r" (res)
-        : "m" (vaddr));
-
-        write_c0_status(sr);
-        ssnop_4();
-
-        return res;
-}
-
-static void writeb_outer_space(unsigned long long phys, unsigned char c)
-{
-        unsigned long long vaddr = IO_BASE_64 | phys;
-        unsigned long tmp;
-        unsigned int sr;
-
-        sr = read_c0_status();
-        write_c0_status((sr | ST0_KX) & ~ ST0_IE);
-        ssnop_4();
-
-        __asm__ __volatile__ (
-        "       .set    mips3           \n"
-        "       ld      %0, %1          \n"
-        "       sb      %2, (%0)        \n"
-        "       .set    mips0           \n"
-        : "=&r" (tmp)
-        : "m" (vaddr), "r" (c));
-
-        write_c0_status(sr);
-        ssnop_4();
-}
-
-void prom_putchar(char c)
-{
-        unsigned long lsr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_lsr);
-        unsigned long thr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_thr);
-
-        while ((readb_outer_space(lsr) & 0x20) == 0);
-        writeb_outer_space(thr, c);
-}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
deleted file mode 100644
index b6472fc88a99..000000000000
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/bcd.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <linux/swap.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/termios.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/serial.h>
-#include <asm/titan_dep.h>
-#include <asm/m48t37.h>
-
-#include "setup.h"
-
-unsigned char titan_ge_mac_addr_base[6] = {
-        // 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
-        0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
-};
-
-unsigned long cpu_clock_freq;
-unsigned long yosemite_base;
-
-static struct m48t37_rtc *m48t37_base;
-
-void __init bus_error_init(void)
-{
-        /* Do nothing */
-}
-
-
-void read_persistent_clock(struct timespec *ts)
-{
-        unsigned int year, month, day, hour, min, sec;
-        unsigned long flags;
-
-        spin_lock_irqsave(&rtc_lock, flags);
-        /* Stop the update to the time */
-        m48t37_base->control = 0x40;
-
-        year = bcd2bin(m48t37_base->year);
-        year += bcd2bin(m48t37_base->century) * 100;
-
-        month = bcd2bin(m48t37_base->month);
-        day = bcd2bin(m48t37_base->date);
-        hour = bcd2bin(m48t37_base->hour);
-        min = bcd2bin(m48t37_base->min);
-        sec = bcd2bin(m48t37_base->sec);
-
-        /* Start the update to the time again */
-        m48t37_base->control = 0x00;
-        spin_unlock_irqrestore(&rtc_lock, flags);
-
-        ts->tv_sec = mktime(year, month, day, hour, min, sec);
-        ts->tv_nsec = 0;
-}
-
-int rtc_mips_set_time(unsigned long tim)
-{
-        struct rtc_time tm;
-        unsigned long flags;
-
-        /*
-         * Convert to a more useful format -- note months count from 0
-         * and years from 1900
-         */
-        rtc_time_to_tm(tim, &tm);
-        tm.tm_year += 1900;
-        tm.tm_mon += 1;
-
-        spin_lock_irqsave(&rtc_lock, flags);
-        /* enable writing */
-        m48t37_base->control = 0x80;
-
-        /* year */
-        m48t37_base->year = bin2bcd(tm.tm_year % 100);
-        m48t37_base->century = bin2bcd(tm.tm_year / 100);
-
-        /* month */
-        m48t37_base->month = bin2bcd(tm.tm_mon);
-
-        /* day */
-        m48t37_base->date = bin2bcd(tm.tm_mday);
-
-        /* hour/min/sec */
-        m48t37_base->hour = bin2bcd(tm.tm_hour);
-        m48t37_base->min = bin2bcd(tm.tm_min);
-        m48t37_base->sec = bin2bcd(tm.tm_sec);
-
-        /* day of week -- not really used, but let's keep it up-to-date */
-        m48t37_base->day = bin2bcd(tm.tm_wday + 1);
-
-        /* disable writing */
-        m48t37_base->control = 0x00;
-        spin_unlock_irqrestore(&rtc_lock, flags);
-
-        return 0;
-}
-
-void __init plat_time_init(void)
-{
-        mips_hpt_frequency = cpu_clock_freq / 2;
-mips_hpt_frequency = 33000000 * 3 * 5;
-}
-
-unsigned long ocd_base;
-
-EXPORT_SYMBOL(ocd_base);
-
-/*
- * Common setup before any secondaries are started
- */
-
-#define TITAN_UART_CLK          3686400
-#define TITAN_SERIAL_BASE_BAUD  (TITAN_UART_CLK / 16)
-#define TITAN_SERIAL_IRQ        4
-#define TITAN_SERIAL_BASE       0xfd000008UL
-
-static void __init py_map_ocd(void)
-{
-        ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
-        if (!ocd_base)
-                panic("Mapping OCD failed - game over.  Your score is 0.");
-
-        /* Kludge for PMON bug ... */
-        OCD_WRITE(0x0710, 0x0ffff029);
-}
-
-static void __init py_uart_setup(void)
-{
-#ifdef CONFIG_SERIAL_8250
-        struct uart_port up;
-
-        /*
-         * Register to interrupt zero because we share the interrupt with
-         * the serial driver which we don't properly support yet.
-         */
-        memset(&up, 0, sizeof(up));
-        up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
-        up.irq          = TITAN_SERIAL_IRQ;
-        up.uartclk      = TITAN_UART_CLK;
-        up.regshift     = 0;
-        up.iotype       = UPIO_MEM;
-        up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-        up.line         = 0;
-
-        if (early_serial_setup(&up))
-                printk(KERN_ERR "Early serial init of port 0 failed\n");
-#endif /* CONFIG_SERIAL_8250 */
-}
-
-static void __init py_rtc_setup(void)
-{
-        m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
-        if (!m48t37_base)
-                printk(KERN_ERR "Mapping the RTC failed\n");
-}
-
-/* Not only time init but that's what the hook it's called through is named */
-static void __init py_late_time_init(void)
-{
-        py_map_ocd();
-        py_uart_setup();
-        py_rtc_setup();
-}
-
-void __init plat_mem_setup(void)
-{
-        late_time_init = py_late_time_init;
-
-        /* Add memory regions */
-        add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
-
-#if 0 /* XXX Crash ...  */
-        OCD_WRITE(RM9000x2_OCD_HTSC,
-                  OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
-
-        /* Set the BAR. Shifted mode */
-        OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
-        OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
-#endif
-}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.h b/arch/mips/pmc-sierra/yosemite/setup.h
deleted file mode 100644
index 1a01abfc7d33..000000000000
--- a/arch/mips/pmc-sierra/yosemite/setup.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2003, 04 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
- *
- * Board specific definititions for the PMC-Sierra Yosemite
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __SETUP_H__
-#define __SETUP_H__
-
-/* M48T37 RTC + NVRAM */
-#define YOSEMITE_RTC_BASE               0xfc800000
-#define YOSEMITE_RTC_SIZE               0x00800000
-
-#define HYPERTRANSPORT_BAR0_ADDR        0x00000006
-#define HYPERTRANSPORT_SIZE0            0x0fffffff
-#define HYPERTRANSPORT_BAR0_ATTR        0x00002000
-
-#define HYPERTRANSPORT_ENABLE           0x6
-
-/*
- * EEPROM Size
- */
-#define TITAN_ATMEL_24C32_SIZE          32768
-#define TITAN_ATMEL_24C64_SIZE          65536
-
-#endif /* __SETUP_H__ */
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
deleted file mode 100644
index 5edab2bc6fc0..000000000000
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ /dev/null
@@ -1,185 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-
-#include <asm/pmon.h>
-#include <asm/titan_dep.h>
-#include <asm/time.h>
-
-#define LAUNCHSTACK_SIZE 256
-
-static __cpuinitdata arch_spinlock_t launch_lock = __ARCH_SPIN_LOCK_UNLOCKED;
-
-static unsigned long secondary_sp __cpuinitdata;
-static unsigned long secondary_gp __cpuinitdata;
-
-static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
-        __attribute__((aligned(2 * sizeof(long))));
-
-static void __init prom_smp_bootstrap(void)
-{
-        local_irq_disable();
-
-        while (arch_spin_is_locked(&launch_lock));
-
-        __asm__ __volatile__(
-        "       move    $sp, %0         \n"
-        "       move    $gp, %1         \n"
-        "       j       smp_bootstrap   \n"
-        :
-        : "r" (secondary_sp), "r" (secondary_gp));
-}
-
-/*
- * PMON is a fragile beast.  It'll blow up once the mappings it's littering
- * right into the middle of KSEG3 are blown away so we have to grab the slave
- * core early and keep it in a waiting loop.
- */
-void __init prom_grab_secondary(void)
-{
-        arch_spin_lock(&launch_lock);
-
-        pmon_cpustart(1, &prom_smp_bootstrap,
-                      launchstack + LAUNCHSTACK_SIZE, 0);
-}
-
-void titan_mailbox_irq(void)
-{
-        int cpu = smp_processor_id();
-        unsigned long status;
-
-        switch (cpu) {
-        case 0:
-                status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
-                OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
-
-                if (status & 0x2)
-                        smp_call_function_interrupt();
-                if (status & 0x4)
-                        scheduler_ipi();
-                break;
-
-        case 1:
-                status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
-                OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
-
-                if (status & 0x2)
-                        smp_call_function_interrupt();
-                if (status & 0x4)
-                        scheduler_ipi();
-                break;
-        }
-}
-
-/*
- * Send inter-processor interrupt
- */
-static void yos_send_ipi_single(int cpu, unsigned int action)
-{
-        /*
-         * Generate an INTMSG so that it can be sent over to the
-         * destination CPU. The INTMSG will put the STATUS bits
-         * based on the action desired. An alternative strategy
-         * is to write to the Interrupt Set register, read the
-         * Interrupt Status register and clear the Interrupt
-         * Clear register. The latter is preffered.
-         */
-        switch (action) {
-        case SMP_RESCHEDULE_YOURSELF:
-                if (cpu == 1)
-                        OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
-                else
-                        OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
-                break;
-
-        case SMP_CALL_FUNCTION:
-                if (cpu == 1)
-                        OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
-                else
-                        OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
-                break;
-        }
-}
-
-static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
-{
-        unsigned int i;
-
-        for_each_cpu(i, mask)
-                yos_send_ipi_single(i, action);
-}
-
-/*
- *  After we've done initial boot, this function is called to allow the
- *  board code to clean up state, if needed
- */
-static void __cpuinit yos_init_secondary(void)
-{
-}
-
-static void __cpuinit yos_smp_finish(void)
-{
-        set_c0_status(ST0_CO | ST0_IM | ST0_IE);
-}
-
-/* Hook for after all CPUs are online */
-static void yos_cpus_done(void)
-{
-}
-
-/*
- * Firmware CPU startup hook
- * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
- * It launches the next * available CPU and copies some information on the
- * stack so the first thing we do is throw away that stuff and load useful
- * values into the registers ...
- */
-static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
-{
-        unsigned long gp = (unsigned long) task_thread_info(idle);
-        unsigned long sp = __KSTK_TOS(idle);
-
-        secondary_sp = sp;
-        secondary_gp = gp;
-
-        arch_spin_unlock(&launch_lock);
-}
-
-/*
- * Detect available CPUs, populate cpu_possible_mask before smp_init
- *
- * We don't want to start the secondary CPU yet nor do we have a nice probing
- * feature in PMON so we just assume presence of the secondary core.
- */
-static void __init yos_smp_setup(void)
-{
-        int i;
-
-        init_cpu_possible(cpu_none_mask);
-
-        for (i = 0; i < 2; i++) {
-                set_cpu_possible(i, true);
-                __cpu_number_map[i]     = i;
-                __cpu_logical_map[i]    = i;
-        }
-}
-
-static void __init yos_prepare_cpus(unsigned int max_cpus)
-{
-        /*
-         * Be paranoid.  Enable the IPI only if we're really about to go SMP.
-         */
-        if (num_possible_cpus())
-                set_c0_status(STATUSF_IP5);
-}
-
-struct plat_smp_ops yos_smp_ops = {
-        .send_ipi_single        = yos_send_ipi_single,
-        .send_ipi_mask          = yos_send_ipi_mask,
-        .init_secondary         = yos_init_secondary,
-        .smp_finish             = yos_smp_finish,
-        .cpus_done              = yos_cpus_done,
-        .boot_secondary         = yos_boot_secondary,
-        .smp_setup              = yos_smp_setup,
-        .prepare_cpus           = yos_prepare_cpus,
-};
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index 1cf5abbef715..c6979353980b 100644
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -69,40 +69,6 @@ char *prom_getenv(char *envname)
         return result;
 }
 
-/* TODO: Verify on linux-mips mailing list that the following two  */
-/* functions are correct                                           */
-/* TODO: Copy NMI and EJTAG exception vectors to memory from the   */
-/* BootROM exception vectors. Flush their cache entries. test it.  */
-
-static void __init mips_nmi_setup(void)
-{
-        void *base;
-#if defined(CONFIG_CPU_MIPS32_R1)
-        base = cpu_has_veic ?
-                (void *)(CAC_BASE + 0xa80) :
-                (void *)(CAC_BASE + 0x380);
-#elif defined(CONFIG_CPU_MIPS32_R2)
-        base = (void *)0xbfc00000;
-#else
-#error NMI exception handler address not defined
-#endif
-}
-
-static void __init mips_ejtag_setup(void)
-{
-        void *base;
-
-#if defined(CONFIG_CPU_MIPS32_R1)
-        base = cpu_has_veic ?
-                (void *)(CAC_BASE + 0xa00) :
-                (void *)(CAC_BASE + 0x300);
-#elif defined(CONFIG_CPU_MIPS32_R2)
-        base = (void *)0xbfc00480;
-#else
-#error EJTAG exception handler address not defined
-#endif
-}
-
 void __init prom_init(void)
 {
         int prom_argc;
@@ -113,9 +79,6 @@ void __init prom_init(void)
         _prom_envp = (int *) fw_arg2;
         _prom_memsize = (unsigned long) fw_arg3;
 
-        board_nmi_handler_setup = mips_nmi_setup;
-        board_ejtag_handler_setup = mips_ejtag_setup;
-
         if (prom_argc == 1) {
                 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
                 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index d7c26d00cfef..a757ded437cd 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -72,12 +72,11 @@ void __init prom_setup_cmdline(void)
         static char cmd_line[COMMAND_LINE_SIZE] __initdata;
         char *cp, *board;
         int prom_argc;
-        char **prom_argv, **prom_envp;
+        char **prom_argv;
         int i;
 
         prom_argc = fw_arg0;
         prom_argv = (char **) fw_arg1;
-        prom_envp = (char **) fw_arg2;
 
         cp = cmd_line;
                 /* Note: it is common that parameters start
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index da44ccb20829..4a6057b35b9d 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -73,12 +73,10 @@ static char __init *decode_eisa_sig(unsigned long addr)
 
 static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
 {
-        u8 eisa_irq;
-        u8 dma1, dma2;
+        u8 eisa_irq = inb(EIU_INTRPT_ACK);
 
-        eisa_irq = inb(EIU_INTRPT_ACK);
-        dma1 = inb(EISA_DMA1_STATUS);
-        dma2 = inb(EISA_DMA2_STATUS);
+        inb(EISA_DMA1_STATUS);
+        inb(EISA_DMA2_STATUS);
 
         if (eisa_irq < EISA_MAX_IRQ) {
                 do_IRQ(eisa_irq);
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 3cd937e0e9a3..01cc1a749c73 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -74,7 +74,7 @@ config SIBYTE_SB1xxx_SOC
         select SWAP_IO_SPACE
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL
-        select CFE
+        select FW_CFE
         select SYS_HAS_EARLY_PRINTK
 
 choice
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 413f17f8e892..d6c7bd4b5ab0 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -15,12 +15,12 @@
 #include <linux/fb.h>
 #include <linux/screen_info.h>
 
-#ifdef CONFIG_ARC
+#ifdef CONFIG_FW_ARC
 #include <asm/fw/arc/types.h>
 #include <asm/sgialib.h>
 #endif
 
-#ifdef CONFIG_SNIPROM
+#ifdef CONFIG_FW_SNIPROM
 #include <asm/mipsprom.h>
 #endif
 
@@ -37,7 +37,7 @@ extern void sni_machine_power_off(void);
 
 static void __init sni_display_setup(void)
 {
-#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
+#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_FW_ARC)
         struct screen_info *si = &screen_info;
         DISPLAY_STATUS *di;
 
@@ -56,7 +56,7 @@ static void __init sni_display_setup(void)
 
 static void __init sni_console_setup(void)
 {
-#ifndef CONFIG_ARC
+#ifndef CONFIG_FW_ARC
         char *ctype;
         char *cdev;
         char *baud;
diff --git a/arch/mips/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
index d06192faeb7c..8b8a0e1a40ca 100644
--- a/arch/mips/wrppmc/pci.c
+++ b/arch/mips/wrppmc/pci.c
@@ -38,10 +38,8 @@ static struct pci_controller hose_0 = {
 
 static int __init gt64120_pci_init(void)
 {
-        u32 tmp;
-
-        tmp = GT_READ(GT_PCI0_CMD_OFS);         /* Huh??? -- Ralf  */
-        tmp = GT_READ(GT_PCI0_BARE_OFS);
+        (void) GT_READ(GT_PCI0_CMD_OFS);        /* Huh??? -- Ralf  */
+        (void) GT_READ(GT_PCI0_BARE_OFS);
 
         /* reset the whole PCI I/O space range */
         ioport_resource.start = GT_PCI_IO_BASE;
diff --git a/arch/parisc/kernel/signal32.c b/arch/parisc/kernel/signal32.c
index fd49aeda9eb8..5dede04f2f3e 100644
--- a/arch/parisc/kernel/signal32.c
+++ b/arch/parisc/kernel/signal32.c
@@ -65,7 +65,8 @@ put_sigset32(compat_sigset_t __user *up, sigset_t *set, size_t sz)
 {
         compat_sigset_t s;
 
-        if (sz != sizeof *set) panic("put_sigset32()");
+        if (sz != sizeof *set)
+                return -EINVAL;
         sigset_64to32(&s, set);
 
         return copy_to_user(up, &s, sizeof s);
@@ -77,7 +78,8 @@ get_sigset32(compat_sigset_t __user *up, sigset_t *set, size_t sz)
         compat_sigset_t s;
         int r;
 
-        if (sz != sizeof *set) panic("put_sigset32()");
+        if (sz != sizeof *set)
+                return -EINVAL;
 
         if ((r = copy_from_user(&s, up, sz)) == 0) {
                 sigset_32to64(set, &s);
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c
index 7426e40699bd..f76c10863c62 100644
--- a/arch/parisc/kernel/sys_parisc.c
+++ b/arch/parisc/kernel/sys_parisc.c
@@ -73,6 +73,8 @@ static unsigned long get_shared_area(struct address_space *mapping,
         struct vm_area_struct *vma;
         int offset = mapping ? get_offset(mapping) : 0;
 
+        offset = (offset + (pgoff << PAGE_SHIFT)) & 0x3FF000;
+
         addr = DCACHE_ALIGN(addr - offset) + offset;
 
         for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
index 7ab286ab5300..39ed65a44c5f 100644
--- a/arch/powerpc/boot/dts/mpc5200b.dtsi
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -231,6 +231,12 @@
                         interrupts = <2 7 0>;
                 };
 
+                sclpc@3c00 {
+                        compatible = "fsl,mpc5200-lpbfifo";
+                        reg = <0x3c00 0x60>;
+                        interrupts = <2 23 0>;
+                };
+
                 i2c@3d00 {
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/o2d.dtsi b/arch/powerpc/boot/dts/o2d.dtsi
index 3444eb8f0ade..24f668039295 100644
--- a/arch/powerpc/boot/dts/o2d.dtsi
+++ b/arch/powerpc/boot/dts/o2d.dtsi
@@ -86,12 +86,6 @@
                                 reg = <0>;
                         };
                 };
-
-                sclpc@3c00 {
-                        compatible = "fsl,mpc5200-lpbfifo";
-                        reg = <0x3c00 0x60>;
-                        interrupts = <3 23 0>;
-                };
         };
 
         localbus {
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 9e354997eb7e..96512c058033 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -59,7 +59,7 @@
                         #gpio-cells = <2>;
                 };
 
-                psc@2000 { /* PSC1 in ac97 mode */
+                audioplatform: psc@2000 { /* PSC1 in ac97 mode */
                         compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
                         cell-index = <0>;
                 };
@@ -134,4 +134,9 @@
         localbus {
                 status = "disabled";
         };
+
+        sound {
+                compatible = "phytec,pcm030-audio-fabric";
+                asoc-platform = <&audioplatform>;
+        };
 };
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 8520b58a5e9a..b89ef65392dc 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -372,10 +372,11 @@ static int mpc52xx_irqhost_map(struct irq_domain *h, unsigned int virq,
         case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
         case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
         case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
-        default:
-                pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
-                       __func__, virq, l1irq, l2irq);
-                return -EINVAL;
+        case MPC52xx_IRQ_L1_CRIT:
+                pr_warn("%s: Critical IRQ #%d is unsupported! Nopping it.\n",
+                        __func__, l2irq);
+                irq_set_chip(virq, &no_irq_chip);
+                return 0;
         }
 
         irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
diff --git a/arch/powerpc/platforms/pseries/eeh_pe.c b/arch/powerpc/platforms/pseries/eeh_pe.c
index 797cd181dc3f..d16c8ded1084 100644
--- a/arch/powerpc/platforms/pseries/eeh_pe.c
+++ b/arch/powerpc/platforms/pseries/eeh_pe.c
@@ -449,7 +449,7 @@ int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe)
                         if (list_empty(&pe->edevs)) {
                                 cnt = 0;
                                 list_for_each_entry(child, &pe->child_list, child) {
-                                        if (!(pe->type & EEH_PE_INVALID)) {
+                                        if (!(child->type & EEH_PE_INVALID)) {
                                                 cnt++;
                                                 break;
                                         }
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index d19f4977c834..e5b084723131 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -220,7 +220,8 @@ static struct device_node *find_pe_dn(struct pci_dev *dev, int *total)
 
         /* Get the top level device in the PE */
         edev = of_node_to_eeh_dev(dn);
-        edev = list_first_entry(&edev->pe->edevs, struct eeh_dev, list);
+        if (edev->pe)
+                edev = list_first_entry(&edev->pe->edevs, struct eeh_dev, list);
         dn = eeh_dev_to_of_node(edev);
         if (!dn)
                 return NULL;
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 5dba755a43e6..d385f396dfee 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -96,6 +96,7 @@ config S390
         select HAVE_MEMBLOCK_NODE_MAP
         select HAVE_CMPXCHG_LOCAL
         select HAVE_CMPXCHG_DOUBLE
+        select HAVE_ALIGNED_STRUCT_PAGE if SLUB
         select HAVE_VIRT_CPU_ACCOUNTING
         select VIRT_CPU_ACCOUNTING
         select ARCH_DISCARD_MEMBLOCK
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
index 55bde6035216..ad2b924167d7 100644
--- a/arch/s390/include/asm/cio.h
+++ b/arch/s390/include/asm/cio.h
@@ -9,6 +9,8 @@
 
 #define LPM_ANYPATH 0xff
 #define __MAX_CSSID 0
+#define __MAX_SUBCHANNEL 65535
+#define __MAX_SSID 3
 
 #include <asm/scsw.h>
 
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index a34a9d612fc0..18cd6b592650 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -20,7 +20,7 @@
 #define PSW32_MASK_CC           0x00003000UL
 #define PSW32_MASK_PM           0x00000f00UL
 
-#define PSW32_MASK_USER         0x00003F00UL
+#define PSW32_MASK_USER         0x0000FF00UL
 
 #define PSW32_ADDR_AMODE        0x80000000UL
 #define PSW32_ADDR_INSN         0x7FFFFFFFUL
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index dd647c919a66..2d3b7cb26005 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -506,12 +506,15 @@ static inline int pud_bad(pud_t pud)
 
 static inline int pmd_present(pmd_t pmd)
 {
-        return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
+        unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO;
+        return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE ||
+               !(pmd_val(pmd) & _SEGMENT_ENTRY_INV);
 }
 
 static inline int pmd_none(pmd_t pmd)
 {
-        return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
+        return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) &&
+               !(pmd_val(pmd) & _SEGMENT_ENTRY_RO);
 }
 
 static inline int pmd_large(pmd_t pmd)
@@ -1223,6 +1226,11 @@ static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
 }
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+#define SEGMENT_NONE    __pgprot(_HPAGE_TYPE_NONE)
+#define SEGMENT_RO      __pgprot(_HPAGE_TYPE_RO)
+#define SEGMENT_RW      __pgprot(_HPAGE_TYPE_RW)
+
 #define __HAVE_ARCH_PGTABLE_DEPOSIT
 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
 
@@ -1242,16 +1250,15 @@ static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
 
 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
 {
-        unsigned long pgprot_pmd = 0;
-
-        if (pgprot_val(pgprot) & _PAGE_INVALID) {
-                if (pgprot_val(pgprot) & _PAGE_SWT)
-                        pgprot_pmd |= _HPAGE_TYPE_NONE;
-                pgprot_pmd |= _SEGMENT_ENTRY_INV;
-        }
-        if (pgprot_val(pgprot) & _PAGE_RO)
-                pgprot_pmd |= _SEGMENT_ENTRY_RO;
-        return pgprot_pmd;
+        /*
+         * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx)
+         * Convert to segment table entry format.
+         */
+        if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
+                return pgprot_val(SEGMENT_NONE);
+        if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
+                return pgprot_val(SEGMENT_RO);
+        return pgprot_val(SEGMENT_RW);
 }
 
 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
@@ -1269,7 +1276,9 @@ static inline pmd_t pmd_mkhuge(pmd_t pmd)
 
 static inline pmd_t pmd_mkwrite(pmd_t pmd)
 {
-        pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
+        /* Do not clobber _HPAGE_TYPE_NONE pages! */
+        if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV))
+                pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
         return pmd;
 }
 
diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h
index 9ca305383760..9935cbd6a46f 100644
--- a/arch/s390/include/asm/topology.h
+++ b/arch/s390/include/asm/topology.h
@@ -8,6 +8,9 @@ struct cpu;
 
 #ifdef CONFIG_SCHED_BOOK
 
+extern unsigned char cpu_socket_id[NR_CPUS];
+#define topology_physical_package_id(cpu) (cpu_socket_id[cpu])
+
 extern unsigned char cpu_core_id[NR_CPUS];
 extern cpumask_t cpu_core_map[NR_CPUS];
 
diff --git a/arch/s390/include/uapi/asm/ptrace.h b/arch/s390/include/uapi/asm/ptrace.h
index 705588a16d70..a5ca214b34fd 100644
--- a/arch/s390/include/uapi/asm/ptrace.h
+++ b/arch/s390/include/uapi/asm/ptrace.h
@@ -239,7 +239,7 @@ typedef struct
 #define PSW_MASK_EA             0x00000000UL
 #define PSW_MASK_BA             0x00000000UL
 
-#define PSW_MASK_USER           0x00003F00UL
+#define PSW_MASK_USER           0x0000FF00UL
 
 #define PSW_ADDR_AMODE          0x80000000UL
 #define PSW_ADDR_INSN           0x7FFFFFFFUL
@@ -269,7 +269,7 @@ typedef struct
 #define PSW_MASK_EA             0x0000000100000000UL
 #define PSW_MASK_BA             0x0000000080000000UL
 
-#define PSW_MASK_USER           0x00003F8180000000UL
+#define PSW_MASK_USER           0x0000FF8180000000UL
 
 #define PSW_ADDR_AMODE          0x0000000000000000UL
 #define PSW_ADDR_INSN           0xFFFFFFFFFFFFFFFFUL
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index a1e8a8694bb7..593fcc9253fc 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -309,6 +309,10 @@ static int restore_sigregs32(struct pt_regs *regs,_sigregs32 __user *sregs)
         regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) |
                 (__u64)(regs32.psw.mask & PSW32_MASK_USER) << 32 |
                 (__u64)(regs32.psw.addr & PSW32_ADDR_AMODE);
+        /* Check for invalid user address space control. */
+        if ((regs->psw.mask & PSW_MASK_ASC) >= (psw_kernel_bits & PSW_MASK_ASC))
+                regs->psw.mask = (psw_user_bits & PSW_MASK_ASC) |
+                        (regs->psw.mask & ~PSW_MASK_ASC);
         regs->psw.addr = (__u64)(regs32.psw.addr & PSW32_ADDR_INSN);
         for (i = 0; i < NUM_GPRS; i++)
                 regs->gprs[i] = (__u64) regs32.gprs[i];
@@ -481,7 +485,10 @@ static int setup_frame32(int sig, struct k_sigaction *ka,
 
         /* Set up registers for signal handler */
         regs->gprs[15] = (__force __u64) frame;
-        regs->psw.mask |= PSW_MASK_BA;          /* force amode 31 */
+        /* Force 31 bit amode and default user address space control. */
+        regs->psw.mask = PSW_MASK_BA |
+                (psw_user_bits & PSW_MASK_ASC) |
+                (regs->psw.mask & ~PSW_MASK_ASC);
         regs->psw.addr = (__force __u64) ka->sa.sa_handler;
 
         regs->gprs[2] = map_signal(sig);
@@ -549,7 +556,10 @@ static int setup_rt_frame32(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* Set up registers for signal handler */
         regs->gprs[15] = (__force __u64) frame;
-        regs->psw.mask |= PSW_MASK_BA;          /* force amode 31 */
+        /* Force 31 bit amode and default user address space control. */
+        regs->psw.mask = PSW_MASK_BA |
+                (psw_user_bits & PSW_MASK_ASC) |
+                (regs->psw.mask & ~PSW_MASK_ASC);
         regs->psw.addr = (__u64) ka->sa.sa_handler;
 
         regs->gprs[2] = map_signal(sig);
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index bf053898630d..b6506ee32a36 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -44,6 +44,12 @@ _sclp_wait_int:
 #endif
         mvc     .LoldpswS1-.LbaseS1(16,%r13),0(%r8)
         mvc     0(16,%r8),0(%r9)
+#ifdef CONFIG_64BIT
+        epsw    %r6,%r7                         # set current addressing mode
+        nill    %r6,0x1                         # in new psw (31 or 64 bit mode)
+        nilh    %r7,0x8000
+        stm     %r6,%r7,0(%r8)
+#endif
         lhi     %r6,0x0200                      # cr mask for ext int (cr0.54)
         ltr     %r2,%r2
         jz      .LsetctS1
@@ -87,7 +93,7 @@ _sclp_wait_int:
         .long   0x00080000, 0x80000000+.LwaitS1 # PSW to handle ext int
 #ifdef CONFIG_64BIT
 .LextpswS1_64:
-        .quad   0x0000000180000000, .LwaitS1    # PSW to handle ext int, 64 bit
+        .quad   0, .LwaitS1                     # PSW to handle ext int, 64 bit
 #endif
 .LwaitpswS1:
         .long   0x010a0000, 0x00000000+.LloopS1 # PSW to wait for ext int
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index c13a2a37ef00..d1259d875074 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -136,6 +136,10 @@ static int restore_sigregs(struct pt_regs *regs, _sigregs __user *sregs)
         /* Use regs->psw.mask instead of psw_user_bits to preserve PER bit. */
         regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) |
                 (user_sregs.regs.psw.mask & PSW_MASK_USER);
+        /* Check for invalid user address space control. */
+        if ((regs->psw.mask & PSW_MASK_ASC) >= (psw_kernel_bits & PSW_MASK_ASC))
+                regs->psw.mask = (psw_user_bits & PSW_MASK_ASC) |
+                        (regs->psw.mask & ~PSW_MASK_ASC);
         /* Check for invalid amode */
         if (regs->psw.mask & PSW_MASK_EA)
                 regs->psw.mask |= PSW_MASK_BA;
@@ -273,7 +277,10 @@ static int setup_frame(int sig, struct k_sigaction *ka,
 
         /* Set up registers for signal handler */
         regs->gprs[15] = (unsigned long) frame;
-        regs->psw.mask |= PSW_MASK_EA | PSW_MASK_BA;    /* 64 bit amode */
+        /* Force default amode and default user address space control. */
+        regs->psw.mask = PSW_MASK_EA | PSW_MASK_BA |
+                (psw_user_bits & PSW_MASK_ASC) |
+                (regs->psw.mask & ~PSW_MASK_ASC);
         regs->psw.addr = (unsigned long) ka->sa.sa_handler | PSW_ADDR_AMODE;
 
         regs->gprs[2] = map_signal(sig);
@@ -346,7 +353,10 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* Set up registers for signal handler */
         regs->gprs[15] = (unsigned long) frame;
-        regs->psw.mask |= PSW_MASK_EA | PSW_MASK_BA;    /* 64 bit amode */
+        /* Force default amode and default user address space control. */
+        regs->psw.mask = PSW_MASK_EA | PSW_MASK_BA |
+                (psw_user_bits & PSW_MASK_ASC) |
+                (regs->psw.mask & ~PSW_MASK_ASC);
         regs->psw.addr = (unsigned long) ka->sa.sa_handler | PSW_ADDR_AMODE;
 
         regs->gprs[2] = map_signal(sig);
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 54d93f4b6818..dd55f7c20104 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -40,6 +40,7 @@ static DEFINE_SPINLOCK(topology_lock);
 static struct mask_info core_info;
 cpumask_t cpu_core_map[NR_CPUS];
 unsigned char cpu_core_id[NR_CPUS];
+unsigned char cpu_socket_id[NR_CPUS];
 
 static struct mask_info book_info;
 cpumask_t cpu_book_map[NR_CPUS];
@@ -83,11 +84,12 @@ static struct mask_info *add_cpus_to_mask(struct topology_cpu *tl_cpu,
                         cpumask_set_cpu(lcpu, &book->mask);
                         cpu_book_id[lcpu] = book->id;
                         cpumask_set_cpu(lcpu, &core->mask);
+                        cpu_core_id[lcpu] = rcpu;
                         if (one_core_per_cpu) {
-                                cpu_core_id[lcpu] = rcpu;
+                                cpu_socket_id[lcpu] = rcpu;
                                 core = core->next;
                         } else {
-                                cpu_core_id[lcpu] = core->id;
+                                cpu_socket_id[lcpu] = core->id;
                         }
                         smp_cpu_set_polarization(lcpu, tl_cpu->pp);
                 }
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index 2d37bb861faf..9017a63dda3d 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -39,7 +39,7 @@ static __always_inline unsigned long follow_table(struct mm_struct *mm,
         pmd = pmd_offset(pud, addr);
         if (pmd_none(*pmd))
                 return -0x10UL;
-        if (pmd_huge(*pmd)) {
+        if (pmd_large(*pmd)) {
                 if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO))
                         return -0x04UL;
                 return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK);
diff --git a/arch/s390/mm/gup.c b/arch/s390/mm/gup.c
index 60acb93a4680..1f5315d1215c 100644
--- a/arch/s390/mm/gup.c
+++ b/arch/s390/mm/gup.c
@@ -126,7 +126,7 @@ static inline int gup_pmd_range(pud_t *pudp, pud_t pud, unsigned long addr,
                  */
                 if (pmd_none(pmd) || pmd_trans_splitting(pmd))
                         return 0;
-                if (unlikely(pmd_huge(pmd))) {
+                if (unlikely(pmd_large(pmd))) {
                         if (!gup_huge_pmd(pmdp, pmd, addr, next,
                                           write, pages, nr))
                                 return 0;
@@ -180,8 +180,7 @@ int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
         addr = start;
         len = (unsigned long) nr_pages << PAGE_SHIFT;
         end = start + len;
-        if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
-                                        (void __user *)start, len)))
+        if ((end < start) || (end > TASK_SIZE))
                 return 0;
 
         local_irq_save(flags);
@@ -229,7 +228,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
         addr = start;
         len = (unsigned long) nr_pages << PAGE_SHIFT;
         end = start + len;
-        if (end < start)
+        if ((end < start) || (end > TASK_SIZE))
                 goto slow_irqon;
 
         /*
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index b6b442b0d793..9f2edb5c5551 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -20,6 +20,7 @@ config SPARC
         select HAVE_ARCH_TRACEHOOK
         select SYSCTL_EXCEPTION_TRACE
         select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select RTC_CLASS
         select RTC_DRV_M48T59
         select HAVE_IRQ_WORK
diff --git a/arch/sparc/crypto/Makefile b/arch/sparc/crypto/Makefile
index 6ae1ad5e502b..5d469d81761f 100644
--- a/arch/sparc/crypto/Makefile
+++ b/arch/sparc/crypto/Makefile
@@ -13,13 +13,13 @@ obj-$(CONFIG_CRYPTO_DES_SPARC64) += camellia-sparc64.o
 
 obj-$(CONFIG_CRYPTO_CRC32C_SPARC64) += crc32c-sparc64.o
 
-sha1-sparc64-y := sha1_asm.o sha1_glue.o crop_devid.o
-sha256-sparc64-y := sha256_asm.o sha256_glue.o crop_devid.o
-sha512-sparc64-y := sha512_asm.o sha512_glue.o crop_devid.o
-md5-sparc64-y := md5_asm.o md5_glue.o crop_devid.o
+sha1-sparc64-y := sha1_asm.o sha1_glue.o
+sha256-sparc64-y := sha256_asm.o sha256_glue.o
+sha512-sparc64-y := sha512_asm.o sha512_glue.o
+md5-sparc64-y := md5_asm.o md5_glue.o
 
-aes-sparc64-y := aes_asm.o aes_glue.o crop_devid.o
-des-sparc64-y := des_asm.o des_glue.o crop_devid.o
-camellia-sparc64-y := camellia_asm.o camellia_glue.o crop_devid.o
+aes-sparc64-y := aes_asm.o aes_glue.o
+des-sparc64-y := des_asm.o des_glue.o
+camellia-sparc64-y := camellia_asm.o camellia_glue.o
 
-crc32c-sparc64-y := crc32c_asm.o crc32c_glue.o crop_devid.o
+crc32c-sparc64-y := crc32c_asm.o crc32c_glue.o
diff --git a/arch/sparc/crypto/aes_glue.c b/arch/sparc/crypto/aes_glue.c
index 8f1c9980f637..3965d1d36dfa 100644
--- a/arch/sparc/crypto/aes_glue.c
+++ b/arch/sparc/crypto/aes_glue.c
@@ -475,3 +475,5 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("AES Secure Hash Algorithm, sparc64 aes opcode accelerated");
 
 MODULE_ALIAS("aes");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/camellia_glue.c b/arch/sparc/crypto/camellia_glue.c
index 42905c084299..62c89af3fd3f 100644
--- a/arch/sparc/crypto/camellia_glue.c
+++ b/arch/sparc/crypto/camellia_glue.c
@@ -320,3 +320,5 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Camellia Cipher Algorithm, sparc64 camellia opcode accelerated");
 
 MODULE_ALIAS("aes");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/crc32c_glue.c b/arch/sparc/crypto/crc32c_glue.c
index 0bd89cea8d8e..5162fad912ce 100644
--- a/arch/sparc/crypto/crc32c_glue.c
+++ b/arch/sparc/crypto/crc32c_glue.c
@@ -177,3 +177,5 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("CRC32c (Castagnoli), sparc64 crc32c opcode accelerated");
 
 MODULE_ALIAS("crc32c");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/des_glue.c b/arch/sparc/crypto/des_glue.c
index c4940c2d3073..41524cebcc49 100644
--- a/arch/sparc/crypto/des_glue.c
+++ b/arch/sparc/crypto/des_glue.c
@@ -527,3 +527,5 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms, sparc64 des opcode accelerated");
 
 MODULE_ALIAS("des");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/md5_glue.c b/arch/sparc/crypto/md5_glue.c
index 603d723038ce..09a9ea1dfb69 100644
--- a/arch/sparc/crypto/md5_glue.c
+++ b/arch/sparc/crypto/md5_glue.c
@@ -186,3 +186,5 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("MD5 Secure Hash Algorithm, sparc64 md5 opcode accelerated");
 
 MODULE_ALIAS("md5");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/sha1_glue.c b/arch/sparc/crypto/sha1_glue.c
index 2bbb20bee9f1..6cd5f29e1e0d 100644
--- a/arch/sparc/crypto/sha1_glue.c
+++ b/arch/sparc/crypto/sha1_glue.c
@@ -181,3 +181,5 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, sparc64 sha1 opcode accelerated");
 
 MODULE_ALIAS("sha1");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/sha256_glue.c b/arch/sparc/crypto/sha256_glue.c
index 591e656bd891..04f555ab2680 100644
--- a/arch/sparc/crypto/sha256_glue.c
+++ b/arch/sparc/crypto/sha256_glue.c
@@ -239,3 +239,5 @@ MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm, sparc64 sha256 op
 
 MODULE_ALIAS("sha224");
 MODULE_ALIAS("sha256");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/crypto/sha512_glue.c b/arch/sparc/crypto/sha512_glue.c
index 486f0a2b7001..f04d1994d19a 100644
--- a/arch/sparc/crypto/sha512_glue.c
+++ b/arch/sparc/crypto/sha512_glue.c
@@ -224,3 +224,5 @@ MODULE_DESCRIPTION("SHA-384 and SHA-512 Secure Hash Algorithm, sparc64 sha512 op
 
 MODULE_ALIAS("sha384");
 MODULE_ALIAS("sha512");
+
+#include "crop_devid.c"
diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h
index ce35a1cf1a20..be56a244c9cf 100644
--- a/arch/sparc/include/asm/atomic_64.h
+++ b/arch/sparc/include/asm/atomic_64.h
@@ -1,7 +1,7 @@
 /* atomic.h: Thankfully the V9 is at least reasonable for this
  *           stuff.
  *
- * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)
+ * Copyright (C) 1996, 1997, 2000, 2012 David S. Miller (davem@redhat.com)
  */
 
 #ifndef __ARCH_SPARC64_ATOMIC__
@@ -106,6 +106,8 @@ static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
 
 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
 
+extern long atomic64_dec_if_positive(atomic64_t *v);
+
 /* Atomic operations are already serializing */
 #define smp_mb__before_atomic_dec()     barrier()
 #define smp_mb__after_atomic_dec()      barrier()
diff --git a/arch/sparc/include/asm/backoff.h b/arch/sparc/include/asm/backoff.h
index db3af0d30fb1..4e02086b839c 100644
--- a/arch/sparc/include/asm/backoff.h
+++ b/arch/sparc/include/asm/backoff.h
@@ -1,6 +1,46 @@
 #ifndef _SPARC64_BACKOFF_H
 #define _SPARC64_BACKOFF_H
 
+/* The macros in this file implement an exponential backoff facility
+ * for atomic operations.
+ *
+ * When multiple threads compete on an atomic operation, it is
+ * possible for one thread to be continually denied a successful
+ * completion of the compare-and-swap instruction.  Heavily
+ * threaded cpu implementations like Niagara can compound this
+ * problem even further.
+ *
+ * When an atomic operation fails and needs to be retried, we spin a
+ * certain number of times.  At each subsequent failure of the same
+ * operation we double the spin count, realizing an exponential
+ * backoff.
+ *
+ * When we spin, we try to use an operation that will cause the
+ * current cpu strand to block, and therefore make the core fully
+ * available to any other other runnable strands.  There are two
+ * options, based upon cpu capabilities.
+ *
+ * On all cpus prior to SPARC-T4 we do three dummy reads of the
+ * condition code register.  Each read blocks the strand for something
+ * between 40 and 50 cpu cycles.
+ *
+ * For SPARC-T4 and later we have a special "pause" instruction
+ * available.  This is implemented using writes to register %asr27.
+ * The cpu will block the number of cycles written into the register,
+ * unless a disrupting trap happens first.  SPARC-T4 specifically
+ * implements pause with a granularity of 8 cycles.  Each strand has
+ * an internal pause counter which decrements every 8 cycles.  So the
+ * chip shifts the %asr27 value down by 3 bits, and writes the result
+ * into the pause counter.  If a value smaller than 8 is written, the
+ * chip blocks for 1 cycle.
+ *
+ * To achieve the same amount of backoff as the three %ccr reads give
+ * on earlier chips, we shift the backoff value up by 7 bits.  (Three
+ * %ccr reads block for about 128 cycles, 1 << 7 == 128) We write the
+ * whole amount we want to block into the pause register, rather than
+ * loop writing 128 each time.
+ */
+
 #define BACKOFF_LIMIT   (4 * 1024)
 
 #ifdef CONFIG_SMP
@@ -11,16 +51,25 @@
 #define BACKOFF_LABEL(spin_label, continue_label) \
         spin_label
 
-#define BACKOFF_SPIN(reg, tmp, label)   \
-        mov     reg, tmp; \
-88:     brnz,pt tmp, 88b; \
-         sub    tmp, 1, tmp; \
-        set     BACKOFF_LIMIT, tmp; \
-        cmp     reg, tmp; \
-        bg,pn   %xcc, label; \
-         nop; \
-        ba,pt   %xcc, label; \
-         sllx   reg, 1, reg;
+#define BACKOFF_SPIN(reg, tmp, label)           \
+        mov             reg, tmp;               \
+88:     rd              %ccr, %g0;              \
+        rd              %ccr, %g0;              \
+        rd              %ccr, %g0;              \
+        .section        .pause_3insn_patch,"ax";\
+        .word           88b;                    \
+        sllx            tmp, 7, tmp;            \
+        wr              tmp, 0, %asr27;         \
+        clr             tmp;                    \
+        .previous;                              \
+        brnz,pt         tmp, 88b;               \
+         sub            tmp, 1, tmp;            \
+        set             BACKOFF_LIMIT, tmp;     \
+        cmp             reg, tmp;               \
+        bg,pn           %xcc, label;            \
+         nop;                                   \
+        ba,pt           %xcc, label;            \
+         sllx           reg, 1, reg;
 
 #else
 
diff --git a/arch/sparc/include/asm/compat.h b/arch/sparc/include/asm/compat.h
index cef99fbc0a21..830502fe62b4 100644
--- a/arch/sparc/include/asm/compat.h
+++ b/arch/sparc/include/asm/compat.h
@@ -232,9 +232,10 @@ static inline void __user *arch_compat_alloc_user_space(long len)
         struct pt_regs *regs = current_thread_info()->kregs;
         unsigned long usp = regs->u_regs[UREG_I6];
 
-        if (!(test_thread_flag(TIF_32BIT)))
+        if (test_thread_64bit_stack(usp))
                 usp += STACK_BIAS;
-        else
+
+        if (test_thread_flag(TIF_32BIT))
                 usp &= 0xffffffffUL;
 
         usp -= len;
diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h
index 4e5a483122a0..721e25f0e2ea 100644
--- a/arch/sparc/include/asm/processor_64.h
+++ b/arch/sparc/include/asm/processor_64.h
@@ -196,7 +196,22 @@ extern unsigned long get_wchan(struct task_struct *task);
 #define KSTK_EIP(tsk)  (task_pt_regs(tsk)->tpc)
 #define KSTK_ESP(tsk)  (task_pt_regs(tsk)->u_regs[UREG_FP])
 
-#define cpu_relax()     barrier()
+/* Please see the commentary in asm/backoff.h for a description of
+ * what these instructions are doing and how they have been choosen.
+ * To make a long story short, we are trying to yield the current cpu
+ * strand during busy loops.
+ */
+#define cpu_relax()     asm volatile("\n99:\n\t"                        \
+                                     "rd        %%ccr, %%g0\n\t"        \
+                                     "rd        %%ccr, %%g0\n\t"        \
+                                     "rd        %%ccr, %%g0\n\t"        \
+                                     ".section  .pause_3insn_patch,\"ax\"\n\t"\
+                                     ".word     99b\n\t"                \
+                                     "wr        %%g0, 128, %%asr27\n\t" \
+                                     "nop\n\t"                          \
+                                     "nop\n\t"                          \
+                                     ".previous"                        \
+                                     ::: "memory")
 
 /* Prefetch support.  This is tuned for UltraSPARC-III and later.
  * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index c28765110706..67c62578d170 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -63,5 +63,13 @@ extern char *of_console_options;
 extern void irq_trans_init(struct device_node *dp);
 extern char *build_path_component(struct device_node *dp);
 
+/* SPARC has local implementations */
+extern int of_address_to_resource(struct device_node *dev, int index,
+                                  struct resource *r);
+#define of_address_to_resource of_address_to_resource
+
+void __iomem *of_iomap(struct device_node *node, int index);
+#define of_iomap of_iomap
+
 #endif /* __KERNEL__ */
 #endif /* _SPARC_PROM_H */
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
index 4e2276631081..a3fe4dcc0aa6 100644
--- a/arch/sparc/include/asm/thread_info_64.h
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -259,6 +259,11 @@ static inline bool test_and_clear_restore_sigmask(void)
 
 #define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
 
+#define thread32_stack_is_64bit(__SP) (((__SP) & 0x1) != 0)
+#define test_thread_64bit_stack(__SP) \
+        ((test_thread_flag(TIF_32BIT) && !thread32_stack_is_64bit(__SP)) ? \
+         false : true)
+
 #endif  /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/sparc/include/asm/ttable.h b/arch/sparc/include/asm/ttable.h
index 48f2807d3265..71b5a67522ab 100644
--- a/arch/sparc/include/asm/ttable.h
+++ b/arch/sparc/include/asm/ttable.h
@@ -372,7 +372,9 @@ etrap_spill_fixup_64bit:				\
 
 /* Normal 32bit spill */
 #define SPILL_2_GENERIC(ASI)                            \
-        srl     %sp, 0, %sp;                            \
+        and     %sp, 1, %g3;                            \
+        brnz,pn %g3, (. - (128 + 4));                   \
+         srl    %sp, 0, %sp;                            \
         stwa    %l0, [%sp + %g0] ASI;                   \
         mov     0x04, %g3;                              \
         stwa    %l1, [%sp + %g3] ASI;                   \
@@ -398,14 +400,16 @@ etrap_spill_fixup_64bit:				\
         stwa    %i6, [%g1 + %g0] ASI;                   \
         stwa    %i7, [%g1 + %g3] ASI;                   \
         saved;                                          \
-        retry; nop; nop;                                \
+        retry;                                          \
         b,a,pt  %xcc, spill_fixup_dax;                  \
         b,a,pt  %xcc, spill_fixup_mna;                  \
         b,a,pt  %xcc, spill_fixup;
 
 #define SPILL_2_GENERIC_ETRAP           \
 etrap_user_spill_32bit:                 \
-        srl     %sp, 0, %sp;            \
+        and     %sp, 1, %g3;            \
+        brnz,pn %g3, etrap_user_spill_64bit;    \
+         srl    %sp, 0, %sp;            \
         stwa    %l0, [%sp + 0x00] %asi; \
         stwa    %l1, [%sp + 0x04] %asi; \
         stwa    %l2, [%sp + 0x08] %asi; \
@@ -427,7 +431,7 @@ etrap_user_spill_32bit:			\
         ba,pt   %xcc, etrap_save;       \
          wrpr   %g1, %cwp;              \
         nop; nop; nop; nop;             \
-        nop; nop; nop; nop;             \
+        nop; nop;                       \
         ba,a,pt %xcc, etrap_spill_fixup_32bit; \
         ba,a,pt %xcc, etrap_spill_fixup_32bit; \
         ba,a,pt %xcc, etrap_spill_fixup_32bit;
@@ -592,7 +596,9 @@ user_rtt_fill_64bit:					\
 
 /* Normal 32bit fill */
 #define FILL_2_GENERIC(ASI)                             \
-        srl     %sp, 0, %sp;                            \
+        and     %sp, 1, %g3;                            \
+        brnz,pn %g3, (. - (128 + 4));                   \
+         srl    %sp, 0, %sp;                            \
         lduwa   [%sp + %g0] ASI, %l0;                   \
         mov     0x04, %g2;                              \
         mov     0x08, %g3;                              \
@@ -616,14 +622,16 @@ user_rtt_fill_64bit:					\
         lduwa   [%g1 + %g3] ASI, %i6;                   \
         lduwa   [%g1 + %g5] ASI, %i7;                   \
         restored;                                       \
-        retry; nop; nop; nop; nop;                      \
+        retry; nop; nop;                                \
         b,a,pt  %xcc, fill_fixup_dax;                   \
         b,a,pt  %xcc, fill_fixup_mna;                   \
         b,a,pt  %xcc, fill_fixup;
 
 #define FILL_2_GENERIC_RTRAP                            \
 user_rtt_fill_32bit:                                    \
-        srl     %sp, 0, %sp;                            \
+        and     %sp, 1, %g3;                            \
+        brnz,pn %g3, user_rtt_fill_64bit;               \
+         srl    %sp, 0, %sp;                            \
         lduwa   [%sp + 0x00] %asi, %l0;                 \
         lduwa   [%sp + 0x04] %asi, %l1;                 \
         lduwa   [%sp + 0x08] %asi, %l2;                 \
@@ -643,7 +651,7 @@ user_rtt_fill_32bit:					\
         ba,pt   %xcc, user_rtt_pre_restore;             \
          restored;                                      \
         nop; nop; nop; nop; nop;                        \
-        nop; nop; nop; nop; nop;                        \
+        nop; nop; nop;                                  \
         ba,a,pt %xcc, user_rtt_fill_fixup;              \
         ba,a,pt %xcc, user_rtt_fill_fixup;              \
         ba,a,pt %xcc, user_rtt_fill_fixup;
diff --git a/arch/sparc/include/uapi/asm/unistd.h b/arch/sparc/include/uapi/asm/unistd.h
index 8974ef7ae920..cac719d1bc5c 100644
--- a/arch/sparc/include/uapi/asm/unistd.h
+++ b/arch/sparc/include/uapi/asm/unistd.h
@@ -405,8 +405,13 @@
 #define __NR_setns              337
 #define __NR_process_vm_readv   338
 #define __NR_process_vm_writev  339
+#define __NR_kern_features      340
+#define __NR_kcmp               341
 
-#define NR_syscalls             340
+#define NR_syscalls             342
+
+/* Bitmask values returned from kern_features system call.  */
+#define KERN_FEATURE_MIXED_MODE_STACK   0x00000001
 
 #ifdef __32bit_syscall_numbers__
 /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
diff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h
index 0c218e4c0881..cc3c5cb47cda 100644
--- a/arch/sparc/kernel/entry.h
+++ b/arch/sparc/kernel/entry.h
@@ -59,6 +59,13 @@ struct popc_6insn_patch_entry {
 extern struct popc_6insn_patch_entry __popc_6insn_patch,
         __popc_6insn_patch_end;
 
+struct pause_patch_entry {
+        unsigned int    addr;
+        unsigned int    insns[3];
+};
+extern struct pause_patch_entry __pause_3insn_patch,
+        __pause_3insn_patch_end;
+
 extern void __init per_cpu_patch(void);
 extern void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *,
                                     struct sun4v_1insn_patch_entry *);
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index f8b6eee40bde..87f60ee65433 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -56,11 +56,13 @@ static inline unsigned int leon_eirq_get(int cpu)
 static void leon_handle_ext_irq(unsigned int irq, struct irq_desc *desc)
 {
         unsigned int eirq;
+        struct irq_bucket *p;
         int cpu = sparc_leon3_cpuid();
 
         eirq = leon_eirq_get(cpu);
-        if ((eirq & 0x10) && irq_map[eirq]->irq) /* bit4 tells if IRQ happened */
-                generic_handle_irq(irq_map[eirq]->irq);
+        p = irq_map[eirq];
+        if ((eirq & 0x10) && p && p->irq) /* bit4 tells if IRQ happened */
+                generic_handle_irq(p->irq);
 }
 
 /* The extended IRQ controller has been found, this function registers it */
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 885a8af74064..b5c38faa4ead 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1762,15 +1762,25 @@ static void perf_callchain_user_32(struct perf_callchain_entry *entry,
 
         ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
         do {
-                struct sparc_stackf32 *usf, sf;
                 unsigned long pc;
 
-                usf = (struct sparc_stackf32 *) ufp;
-                if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
-                        break;
+                if (thread32_stack_is_64bit(ufp)) {
+                        struct sparc_stackf *usf, sf;
 
-                pc = sf.callers_pc;
-                ufp = (unsigned long)sf.fp;
+                        ufp += STACK_BIAS;
+                        usf = (struct sparc_stackf *) ufp;
+                        if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
+                                break;
+                        pc = sf.callers_pc & 0xffffffff;
+                        ufp = ((unsigned long) sf.fp) & 0xffffffff;
+                } else {
+                        struct sparc_stackf32 *usf, sf;
+                        usf = (struct sparc_stackf32 *) ufp;
+                        if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
+                                break;
+                        pc = sf.callers_pc;
+                        ufp = (unsigned long)sf.fp;
+                }
                 perf_callchain_store(entry, pc);
         } while (entry->nr < PERF_MAX_STACK_DEPTH);
 }
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index d778248ef3f8..c6e0c2910043 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -452,13 +452,16 @@ void flush_thread(void)
 /* It's a bit more tricky when 64-bit tasks are involved... */
 static unsigned long clone_stackframe(unsigned long csp, unsigned long psp)
 {
+        bool stack_64bit = test_thread_64bit_stack(psp);
         unsigned long fp, distance, rval;
 
-        if (!(test_thread_flag(TIF_32BIT))) {
+        if (stack_64bit) {
                 csp += STACK_BIAS;
                 psp += STACK_BIAS;
                 __get_user(fp, &(((struct reg_window __user *)psp)->ins[6]));
                 fp += STACK_BIAS;
+                if (test_thread_flag(TIF_32BIT))
+                        fp &= 0xffffffff;
         } else
                 __get_user(fp, &(((struct reg_window32 __user *)psp)->ins[6]));
 
@@ -472,7 +475,7 @@ static unsigned long clone_stackframe(unsigned long csp, unsigned long psp)
         rval = (csp - distance);
         if (copy_in_user((void __user *) rval, (void __user *) psp, distance))
                 rval = 0;
-        else if (test_thread_flag(TIF_32BIT)) {
+        else if (!stack_64bit) {
                 if (put_user(((u32)csp),
                              &(((struct reg_window32 __user *)rval)->ins[6])))
                         rval = 0;
@@ -507,18 +510,18 @@ void synchronize_user_stack(void)
 
         flush_user_windows();
         if ((window = get_thread_wsaved()) != 0) {
-                int winsize = sizeof(struct reg_window);
-                int bias = 0;
-
-                if (test_thread_flag(TIF_32BIT))
-                        winsize = sizeof(struct reg_window32);
-                else
-                        bias = STACK_BIAS;
-
                 window -= 1;
                 do {
-                        unsigned long sp = (t->rwbuf_stkptrs[window] + bias);
                         struct reg_window *rwin = &t->reg_window[window];
+                        int winsize = sizeof(struct reg_window);
+                        unsigned long sp;
+
+                        sp = t->rwbuf_stkptrs[window];
+
+                        if (test_thread_64bit_stack(sp))
+                                sp += STACK_BIAS;
+                        else
+                                winsize = sizeof(struct reg_window32);
 
                         if (!copy_to_user((char __user *)sp, rwin, winsize)) {
                                 shift_window_buffer(window, get_thread_wsaved() - 1, t);
@@ -544,13 +547,6 @@ void fault_in_user_windows(void)
 {
         struct thread_info *t = current_thread_info();
         unsigned long window;
-        int winsize = sizeof(struct reg_window);
-        int bias = 0;
-
-        if (test_thread_flag(TIF_32BIT))
-                winsize = sizeof(struct reg_window32);
-        else
-                bias = STACK_BIAS;
 
         flush_user_windows();
         window = get_thread_wsaved();
@@ -558,8 +554,16 @@ void fault_in_user_windows(void)
         if (likely(window != 0)) {
                 window -= 1;
                 do {
-                        unsigned long sp = (t->rwbuf_stkptrs[window] + bias);
                         struct reg_window *rwin = &t->reg_window[window];
+                        int winsize = sizeof(struct reg_window);
+                        unsigned long sp;
+
+                        sp = t->rwbuf_stkptrs[window];
+
+                        if (test_thread_64bit_stack(sp))
+                                sp += STACK_BIAS;
+                        else
+                                winsize = sizeof(struct reg_window32);
 
                         if (unlikely(sp & 0x7UL))
                                 stack_unaligned(sp);
diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c
index 484dabac7045..7ff45e4ba681 100644
--- a/arch/sparc/kernel/ptrace_64.c
+++ b/arch/sparc/kernel/ptrace_64.c
@@ -151,7 +151,7 @@ static int regwindow64_get(struct task_struct *target,
 {
         unsigned long rw_addr = regs->u_regs[UREG_I6];
 
-        if (test_tsk_thread_flag(current, TIF_32BIT)) {
+        if (!test_thread_64bit_stack(rw_addr)) {
                 struct reg_window32 win32;
                 int i;
 
@@ -176,7 +176,7 @@ static int regwindow64_set(struct task_struct *target,
 {
         unsigned long rw_addr = regs->u_regs[UREG_I6];
 
-        if (test_tsk_thread_flag(current, TIF_32BIT)) {
+        if (!test_thread_64bit_stack(rw_addr)) {
                 struct reg_window32 win32;
                 int i;
 
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 0800e71d8a88..0eaf0059aaef 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -316,6 +316,25 @@ static void __init popc_patch(void)
         }
 }
 
+static void __init pause_patch(void)
+{
+        struct pause_patch_entry *p;
+
+        p = &__pause_3insn_patch;
+        while (p < &__pause_3insn_patch_end) {
+                unsigned long i, addr = p->addr;
+
+                for (i = 0; i < 3; i++) {
+                        *(unsigned int *) (addr +  (i * 4)) = p->insns[i];
+                        wmb();
+                        __asm__ __volatile__("flush     %0"
+                                             : : "r" (addr +  (i * 4)));
+                }
+
+                p++;
+        }
+}
+
 #ifdef CONFIG_SMP
 void __init boot_cpu_id_too_large(int cpu)
 {
@@ -528,6 +547,8 @@ static void __init init_sparc64_elf_hwcap(void)
 
         if (sparc64_elf_hwcap & AV_SPARC_POPC)
                 popc_patch();
+        if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
+                pause_patch();
 }
 
 void __init setup_arch(char **cmdline_p)
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index 867de2f8189c..689e1ba62809 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -295,9 +295,7 @@ void do_rt_sigreturn(struct pt_regs *regs)
                 err |= restore_fpu_state(regs, fpu_save);
 
         err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t));
-        err |= do_sigaltstack(&sf->stack, NULL, (unsigned long)sf);
-
-        if (err)
+        if (err || do_sigaltstack(&sf->stack, NULL, (unsigned long)sf) == -EFAULT)
                 goto segv;
 
         err |= __get_user(rwin_save, &sf->rwin_save);
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 11c6c9603e71..878ef3d5fec5 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -751,3 +751,8 @@ int kernel_execve(const char *filename,
                       : "cc");
         return __res;
 }
+
+asmlinkage long sys_kern_features(void)
+{
+        return KERN_FEATURE_MIXED_MODE_STACK;
+}
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 63402f9e9f51..5147f574f125 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -85,3 +85,4 @@ sys_call_table:
 /*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
 /*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
 /*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
+/*340*/ .long sys_ni_syscall, sys_kcmp
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 3a58e0d66f51..1c9af9fa38e9 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -86,6 +86,7 @@ sys_call_table32:
         .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init
 /*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime
         .word sys_syncfs, compat_sys_sendmmsg, sys_setns, compat_sys_process_vm_readv, compat_sys_process_vm_writev
+/*340*/ .word sys_kern_features, sys_kcmp
 
 #endif /* CONFIG_COMPAT */
 
@@ -163,3 +164,4 @@ sys_call_table:
         .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
 /*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
         .word sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
+/*340*/ .word sys_kern_features, sys_kcmp
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index f81d038f7340..8201c25e7669 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -113,21 +113,24 @@ static inline long sign_extend_imm13(long imm)
 
 static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
 {
-        unsigned long value;
+        unsigned long value, fp;
         
         if (reg < 16)
                 return (!reg ? 0 : regs->u_regs[reg]);
+
+        fp = regs->u_regs[UREG_FP];
+
         if (regs->tstate & TSTATE_PRIV) {
                 struct reg_window *win;
-                win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window *)(fp + STACK_BIAS);
                 value = win->locals[reg - 16];
-        } else if (test_thread_flag(TIF_32BIT)) {
+        } else if (!test_thread_64bit_stack(fp)) {
                 struct reg_window32 __user *win32;
-                win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
+                win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
                 get_user(value, &win32->locals[reg - 16]);
         } else {
                 struct reg_window __user *win;
-                win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window __user *)(fp + STACK_BIAS);
                 get_user(value, &win->locals[reg - 16]);
         }
         return value;
@@ -135,19 +138,24 @@ static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
 
 static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs)
 {
+        unsigned long fp;
+
         if (reg < 16)
                 return &regs->u_regs[reg];
+
+        fp = regs->u_regs[UREG_FP];
+
         if (regs->tstate & TSTATE_PRIV) {
                 struct reg_window *win;
-                win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window *)(fp + STACK_BIAS);
                 return &win->locals[reg - 16];
-        } else if (test_thread_flag(TIF_32BIT)) {
+        } else if (!test_thread_64bit_stack(fp)) {
                 struct reg_window32 *win32;
-                win32 = (struct reg_window32 *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
+                win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
                 return (unsigned long *)&win32->locals[reg - 16];
         } else {
                 struct reg_window *win;
-                win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window *)(fp + STACK_BIAS);
                 return &win->locals[reg - 16];
         }
 }
@@ -392,13 +400,15 @@ int handle_popc(u32 insn, struct pt_regs *regs)
                 if (rd)
                         regs->u_regs[rd] = ret;
         } else {
-                if (test_thread_flag(TIF_32BIT)) {
+                unsigned long fp = regs->u_regs[UREG_FP];
+
+                if (!test_thread_64bit_stack(fp)) {
                         struct reg_window32 __user *win32;
-                        win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
+                        win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
                         put_user(ret, &win32->locals[rd - 16]);
                 } else {
                         struct reg_window __user *win;
-                        win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                        win = (struct reg_window __user *)(fp + STACK_BIAS);
                         put_user(ret, &win->locals[rd - 16]);
                 }
         }
@@ -554,7 +564,7 @@ void handle_ld_nf(u32 insn, struct pt_regs *regs)
                 reg[0] = 0;
                 if ((insn & 0x780000) == 0x180000)
                         reg[1] = 0;
-        } else if (test_thread_flag(TIF_32BIT)) {
+        } else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
                 put_user(0, (int __user *) reg);
                 if ((insn & 0x780000) == 0x180000)
                         put_user(0, ((int __user *) reg) + 1);
diff --git a/arch/sparc/kernel/visemul.c b/arch/sparc/kernel/visemul.c
index 08e074b7eb6a..c096c624ac4d 100644
--- a/arch/sparc/kernel/visemul.c
+++ b/arch/sparc/kernel/visemul.c
@@ -149,21 +149,24 @@ static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
 
 static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
 {
-        unsigned long value;
+        unsigned long value, fp;
         
         if (reg < 16)
                 return (!reg ? 0 : regs->u_regs[reg]);
+
+        fp = regs->u_regs[UREG_FP];
+
         if (regs->tstate & TSTATE_PRIV) {
                 struct reg_window *win;
-                win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window *)(fp + STACK_BIAS);
                 value = win->locals[reg - 16];
-        } else if (test_thread_flag(TIF_32BIT)) {
+        } else if (!test_thread_64bit_stack(fp)) {
                 struct reg_window32 __user *win32;
-                win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
+                win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
                 get_user(value, &win32->locals[reg - 16]);
         } else {
                 struct reg_window __user *win;
-                win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window __user *)(fp + STACK_BIAS);
                 get_user(value, &win->locals[reg - 16]);
         }
         return value;
@@ -172,16 +175,18 @@ static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
 static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg,
                                                           struct pt_regs *regs)
 {
+        unsigned long fp = regs->u_regs[UREG_FP];
+
         BUG_ON(reg < 16);
         BUG_ON(regs->tstate & TSTATE_PRIV);
 
-        if (test_thread_flag(TIF_32BIT)) {
+        if (!test_thread_64bit_stack(fp)) {
                 struct reg_window32 __user *win32;
-                win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
+                win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
                 return (unsigned long __user *)&win32->locals[reg - 16];
         } else {
                 struct reg_window __user *win;
-                win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
+                win = (struct reg_window __user *)(fp + STACK_BIAS);
                 return &win->locals[reg - 16];
         }
 }
@@ -204,7 +209,7 @@ static void store_reg(struct pt_regs *regs, unsigned long val, unsigned long rd)
         } else {
                 unsigned long __user *rd_user = __fetch_reg_addr_user(rd, regs);
 
-                if (test_thread_flag(TIF_32BIT))
+                if (!test_thread_64bit_stack(regs->u_regs[UREG_FP]))
                         __put_user((u32)val, (u32 __user *)rd_user);
                 else
                         __put_user(val, rd_user);
diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S
index 89c2c29f154b..0bacceb19150 100644
--- a/arch/sparc/kernel/vmlinux.lds.S
+++ b/arch/sparc/kernel/vmlinux.lds.S
@@ -132,6 +132,11 @@ SECTIONS
                 *(.popc_6insn_patch)
                 __popc_6insn_patch_end = .;
         }
+        .pause_3insn_patch : {
+                __pause_3insn_patch = .;
+                *(.pause_3insn_patch)
+                __pause_3insn_patch_end = .;
+        }
         PERCPU_SECTION(SMP_CACHE_BYTES)
 
         . = ALIGN(PAGE_SIZE);
diff --git a/arch/sparc/kernel/winfixup.S b/arch/sparc/kernel/winfixup.S
index a6b0863c27df..1e67ce958369 100644
--- a/arch/sparc/kernel/winfixup.S
+++ b/arch/sparc/kernel/winfixup.S
@@ -43,6 +43,8 @@ spill_fixup_mna:
 spill_fixup_dax:
         TRAP_LOAD_THREAD_REG(%g6, %g1)
         ldx     [%g6 + TI_FLAGS], %g1
+        andcc   %sp, 0x1, %g0
+        movne   %icc, 0, %g1
         andcc   %g1, _TIF_32BIT, %g0
         ldub    [%g6 + TI_WSAVED], %g1
         sll     %g1, 3, %g3
diff --git a/arch/sparc/lib/atomic_64.S b/arch/sparc/lib/atomic_64.S
index 4d502da3de78..85c233d0a340 100644
--- a/arch/sparc/lib/atomic_64.S
+++ b/arch/sparc/lib/atomic_64.S
@@ -1,6 +1,6 @@
 /* atomic.S: These things are too big to do inline.
  *
- * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1999, 2007 2012 David S. Miller (davem@davemloft.net)
  */
 
 #include <linux/linkage.h>
@@ -117,3 +117,17 @@ ENTRY(atomic64_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */
          sub    %g1, %o0, %o0
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
 ENDPROC(atomic64_sub_ret)
+
+ENTRY(atomic64_dec_if_positive) /* %o0 = atomic_ptr */
+        BACKOFF_SETUP(%o2)
+1:      ldx     [%o0], %g1
+        brlez,pn %g1, 3f
+         sub    %g1, 1, %g7
+        casx    [%o0], %g1, %g7
+        cmp     %g1, %g7
+        bne,pn  %xcc, BACKOFF_LABEL(2f, 1b)
+         nop
+3:      retl
+         sub    %g1, 1, %o0
+2:      BACKOFF_SPIN(%o2, %o3, 1b)
+ENDPROC(atomic64_dec_if_positive)
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c
index ee31b884c61b..0c4e35e522fa 100644
--- a/arch/sparc/lib/ksyms.c
+++ b/arch/sparc/lib/ksyms.c
@@ -116,6 +116,7 @@ EXPORT_SYMBOL(atomic64_add);
 EXPORT_SYMBOL(atomic64_add_ret);
 EXPORT_SYMBOL(atomic64_sub);
 EXPORT_SYMBOL(atomic64_sub_ret);
+EXPORT_SYMBOL(atomic64_dec_if_positive);
 
 /* Atomic bit operations. */
 EXPORT_SYMBOL(test_and_set_bit);
diff --git a/arch/sparc/math-emu/math_64.c b/arch/sparc/math-emu/math_64.c
index 1704068da928..034aadbff036 100644
--- a/arch/sparc/math-emu/math_64.c
+++ b/arch/sparc/math-emu/math_64.c
@@ -320,7 +320,7 @@ int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap)
                                         XR = 0;
                                 else if (freg < 16)
                                         XR = regs->u_regs[freg];
-                                else if (test_thread_flag(TIF_32BIT)) {
+                                else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
                                         struct reg_window32 __user *win32;
                                         flushw_user ();
                                         win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index e5c5473e69ce..c4fbb21e802b 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -16,6 +16,8 @@ config UNICORE32
         select ARCH_WANT_FRAME_POINTERS
         select GENERIC_IOMAP
         select MODULES_USE_ELF_REL
+        select GENERIC_KERNEL_THREAD
+        select GENERIC_KERNEL_EXECVE
         help
           UniCore-32 is 32-bit Instruction Set Architecture,
           including a series of low-power-consumption RISC chip
@@ -64,6 +66,9 @@ config GENERIC_CALIBRATE_DELAY
 config ARCH_MAY_HAVE_PC_FDC
         bool
 
+config ZONE_DMA
+        def_bool y
+
 config NEED_DMA_MAP_STATE
        def_bool y
 
@@ -216,7 +221,7 @@ config PUV3_GPIO
         bool
         depends on !ARCH_FPGA
         select GENERIC_GPIO
-        select GPIO_SYSFS if EXPERIMENTAL
+        select GPIO_SYSFS
         default y
 
 if PUV3_NB0916
diff --git a/arch/unicore32/include/asm/Kbuild b/arch/unicore32/include/asm/Kbuild
index c910c9857e11..601e92f18af6 100644
--- a/arch/unicore32/include/asm/Kbuild
+++ b/arch/unicore32/include/asm/Kbuild
@@ -1,4 +1,3 @@
-include include/asm-generic/Kbuild.asm
 
 generic-y += atomic.h
 generic-y += auxvec.h
diff --git a/arch/unicore32/include/asm/bug.h b/arch/unicore32/include/asm/bug.h
index b1ff8cadb086..93a56f3e2344 100644
--- a/arch/unicore32/include/asm/bug.h
+++ b/arch/unicore32/include/asm/bug.h
@@ -19,9 +19,4 @@ extern void die(const char *msg, struct pt_regs *regs, int err);
 extern void uc32_notify_die(const char *str, struct pt_regs *regs,
                 struct siginfo *info, unsigned long err, unsigned long trap);
 
-extern asmlinkage void __backtrace(void);
-extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
-
-extern void __show_regs(struct pt_regs *);
-
 #endif /* __UNICORE_BUG_H__ */
diff --git a/arch/unicore32/include/asm/cmpxchg.h b/arch/unicore32/include/asm/cmpxchg.h
index df4d5acfd19f..8e797ad4fa24 100644
--- a/arch/unicore32/include/asm/cmpxchg.h
+++ b/arch/unicore32/include/asm/cmpxchg.h
@@ -35,7 +35,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
                         : "memory", "cc");
                 break;
         default:
-                ret = __xchg_bad_pointer();
+                __xchg_bad_pointer();
         }
 
         return ret;
diff --git a/arch/unicore32/include/asm/kvm_para.h b/arch/unicore32/include/asm/kvm_para.h
deleted file mode 100644
index 14fab8f0b957..000000000000
--- a/arch/unicore32/include/asm/kvm_para.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kvm_para.h>
diff --git a/arch/unicore32/include/asm/processor.h b/arch/unicore32/include/asm/processor.h
index 14382cb09657..4eaa42167667 100644
--- a/arch/unicore32/include/asm/processor.h
+++ b/arch/unicore32/include/asm/processor.h
@@ -72,11 +72,6 @@ unsigned long get_wchan(struct task_struct *p);
 
 #define cpu_relax()                     barrier()
 
-/*
- * Create a new kernel thread
- */
-extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
 #define task_pt_regs(p) \
         ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
 
diff --git a/arch/unicore32/include/asm/ptrace.h b/arch/unicore32/include/asm/ptrace.h
index b9caf9b0997b..726749dab52f 100644
--- a/arch/unicore32/include/asm/ptrace.h
+++ b/arch/unicore32/include/asm/ptrace.h
@@ -12,80 +12,10 @@
 #ifndef __UNICORE_PTRACE_H__
 #define __UNICORE_PTRACE_H__
 
-#define PTRACE_GET_THREAD_AREA  22
-
-/*
- * PSR bits
- */
-#define USER_MODE       0x00000010
-#define REAL_MODE       0x00000011
-#define INTR_MODE       0x00000012
-#define PRIV_MODE       0x00000013
-#define ABRT_MODE       0x00000017
-#define EXTN_MODE       0x0000001b
-#define SUSR_MODE       0x0000001f
-#define MODE_MASK       0x0000001f
-#define PSR_R_BIT       0x00000040
-#define PSR_I_BIT       0x00000080
-#define PSR_V_BIT       0x10000000
-#define PSR_C_BIT       0x20000000
-#define PSR_Z_BIT       0x40000000
-#define PSR_S_BIT       0x80000000
-
-/*
- * Groups of PSR bits
- */
-#define PSR_f           0xff000000      /* Flags                */
-#define PSR_c           0x000000ff      /* Control              */
+#include <uapi/asm/ptrace.h>
 
 #ifndef __ASSEMBLY__
 
-/*
- * This struct defines the way the registers are stored on the
- * stack during a system call.  Note that sizeof(struct pt_regs)
- * has to be a multiple of 8.
- */
-struct pt_regs {
-        unsigned long uregs[34];
-};
-
-#define UCreg_asr               uregs[32]
-#define UCreg_pc                uregs[31]
-#define UCreg_lr                uregs[30]
-#define UCreg_sp                uregs[29]
-#define UCreg_ip                uregs[28]
-#define UCreg_fp                uregs[27]
-#define UCreg_26                uregs[26]
-#define UCreg_25                uregs[25]
-#define UCreg_24                uregs[24]
-#define UCreg_23                uregs[23]
-#define UCreg_22                uregs[22]
-#define UCreg_21                uregs[21]
-#define UCreg_20                uregs[20]
-#define UCreg_19                uregs[19]
-#define UCreg_18                uregs[18]
-#define UCreg_17                uregs[17]
-#define UCreg_16                uregs[16]
-#define UCreg_15                uregs[15]
-#define UCreg_14                uregs[14]
-#define UCreg_13                uregs[13]
-#define UCreg_12                uregs[12]
-#define UCreg_11                uregs[11]
-#define UCreg_10                uregs[10]
-#define UCreg_09                uregs[9]
-#define UCreg_08                uregs[8]
-#define UCreg_07                uregs[7]
-#define UCreg_06                uregs[6]
-#define UCreg_05                uregs[5]
-#define UCreg_04                uregs[4]
-#define UCreg_03                uregs[3]
-#define UCreg_02                uregs[2]
-#define UCreg_01                uregs[1]
-#define UCreg_00                uregs[0]
-#define UCreg_ORIG_00           uregs[33]
-
-#ifdef __KERNEL__
-
 #define user_mode(regs) \
         (processor_mode(regs) == USER_MODE)
 
@@ -125,9 +55,5 @@ static inline int valid_user_regs(struct pt_regs *regs)
 
 #define instruction_pointer(regs)       ((regs)->UCreg_pc)
 
-#endif /* __KERNEL__ */
-
 #endif /* __ASSEMBLY__ */
-
 #endif
-
diff --git a/arch/unicore32/include/uapi/asm/Kbuild b/arch/unicore32/include/uapi/asm/Kbuild
index baebb3da1d44..0514d7ad6855 100644
--- a/arch/unicore32/include/uapi/asm/Kbuild
+++ b/arch/unicore32/include/uapi/asm/Kbuild
@@ -1,3 +1,10 @@
 # UAPI Header export list
 include include/uapi/asm-generic/Kbuild.asm
 
+header-y += byteorder.h
+header-y += kvm_para.h
+header-y += ptrace.h
+header-y += sigcontext.h
+header-y += unistd.h
+
+generic-y += kvm_para.h
diff --git a/arch/unicore32/include/asm/byteorder.h b/arch/unicore32/include/uapi/asm/byteorder.h
index ebe1b3fef3e3..ebe1b3fef3e3 100644
--- a/arch/unicore32/include/asm/byteorder.h
+++ b/arch/unicore32/include/uapi/asm/byteorder.h
diff --git a/arch/unicore32/include/uapi/asm/ptrace.h b/arch/unicore32/include/uapi/asm/ptrace.h
new file mode 100644
index 000000000000..187aa2e98a53
--- /dev/null
+++ b/arch/unicore32/include/uapi/asm/ptrace.h
@@ -0,0 +1,90 @@
+/*
+ * linux/arch/unicore32/include/asm/ptrace.h
+ *
+ * Code specific to PKUnity SoC and UniCore ISA
+ *
+ * Copyright (C) 2001-2010 GUAN Xue-tao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _UAPI__UNICORE_PTRACE_H__
+#define _UAPI__UNICORE_PTRACE_H__
+
+#define PTRACE_GET_THREAD_AREA  22
+
+/*
+ * PSR bits
+ */
+#define USER_MODE       0x00000010
+#define REAL_MODE       0x00000011
+#define INTR_MODE       0x00000012
+#define PRIV_MODE       0x00000013
+#define ABRT_MODE       0x00000017
+#define EXTN_MODE       0x0000001b
+#define SUSR_MODE       0x0000001f
+#define MODE_MASK       0x0000001f
+#define PSR_R_BIT       0x00000040
+#define PSR_I_BIT       0x00000080
+#define PSR_V_BIT       0x10000000
+#define PSR_C_BIT       0x20000000
+#define PSR_Z_BIT       0x40000000
+#define PSR_S_BIT       0x80000000
+
+/*
+ * Groups of PSR bits
+ */
+#define PSR_f           0xff000000      /* Flags                */
+#define PSR_c           0x000000ff      /* Control              */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored on the
+ * stack during a system call.  Note that sizeof(struct pt_regs)
+ * has to be a multiple of 8.
+ */
+struct pt_regs {
+        unsigned long uregs[34];
+};
+
+#define UCreg_asr               uregs[32]
+#define UCreg_pc                uregs[31]
+#define UCreg_lr                uregs[30]
+#define UCreg_sp                uregs[29]
+#define UCreg_ip                uregs[28]
+#define UCreg_fp                uregs[27]
+#define UCreg_26                uregs[26]
+#define UCreg_25                uregs[25]
+#define UCreg_24                uregs[24]
+#define UCreg_23                uregs[23]
+#define UCreg_22                uregs[22]
+#define UCreg_21                uregs[21]
+#define UCreg_20                uregs[20]
+#define UCreg_19                uregs[19]
+#define UCreg_18                uregs[18]
+#define UCreg_17                uregs[17]
+#define UCreg_16                uregs[16]
+#define UCreg_15                uregs[15]
+#define UCreg_14                uregs[14]
+#define UCreg_13                uregs[13]
+#define UCreg_12                uregs[12]
+#define UCreg_11                uregs[11]
+#define UCreg_10                uregs[10]
+#define UCreg_09                uregs[9]
+#define UCreg_08                uregs[8]
+#define UCreg_07                uregs[7]
+#define UCreg_06                uregs[6]
+#define UCreg_05                uregs[5]
+#define UCreg_04                uregs[4]
+#define UCreg_03                uregs[3]
+#define UCreg_02                uregs[2]
+#define UCreg_01                uregs[1]
+#define UCreg_00                uregs[0]
+#define UCreg_ORIG_00           uregs[33]
+
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _UAPI__UNICORE_PTRACE_H__ */
diff --git a/arch/unicore32/include/asm/sigcontext.h b/arch/unicore32/include/uapi/asm/sigcontext.h
index 6a2d7671c052..6a2d7671c052 100644
--- a/arch/unicore32/include/asm/sigcontext.h
+++ b/arch/unicore32/include/uapi/asm/sigcontext.h
diff --git a/arch/unicore32/include/asm/unistd.h b/arch/unicore32/include/uapi/asm/unistd.h
index 2abcf61c615d..d18a3be89b38 100644
--- a/arch/unicore32/include/asm/unistd.h
+++ b/arch/unicore32/include/uapi/asm/unistd.h
@@ -12,3 +12,4 @@
 
 /* Use the standard ABI for syscalls. */
 #include <asm-generic/unistd.h>
+#define __ARCH_WANT_SYS_EXECVE
diff --git a/arch/unicore32/kernel/entry.S b/arch/unicore32/kernel/entry.S
index dcb87ab19ddd..7049350c790f 100644
--- a/arch/unicore32/kernel/entry.S
+++ b/arch/unicore32/kernel/entry.S
@@ -573,17 +573,16 @@ ENDPROC(ret_to_user)
  */
 ENTRY(ret_from_fork)
         b.l     schedule_tail
-        get_thread_info tsk
-        ldw     r1, [tsk+], #TI_FLAGS           @ check for syscall tracing
-        mov     why, #1
-        cand.a  r1, #_TIF_SYSCALL_TRACE         @ are we tracing syscalls?
-        beq     ret_slow_syscall
-        mov     r1, sp
-        mov     r0, #1                          @ trace exit [IP = 1]
-        b.l     syscall_trace
         b       ret_slow_syscall
 ENDPROC(ret_from_fork)
 
+ENTRY(ret_from_kernel_thread)
+        b.l     schedule_tail
+        mov     r0, r5
+        adr     lr, ret_slow_syscall
+        mov     pc, r4
+ENDPROC(ret_from_kernel_thread)
+
 /*=============================================================================
  * SWI handler
  *-----------------------------------------------------------------------------
@@ -669,11 +668,6 @@ __cr_alignment:
 #endif
         .ltorg
 
-ENTRY(sys_execve)
-                add     r3, sp, #S_OFF
-                b       __sys_execve
-ENDPROC(sys_execve)
-
 ENTRY(sys_clone)
                 add     ip, sp, #S_OFF
                 stw     ip, [sp+], #4
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index b008586dad75..a8fe265ce2c0 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -258,6 +258,7 @@ void release_thread(struct task_struct *dead_task)
 }
 
 asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
+asmlinkage void ret_from_kernel_thread(void) __asm__("ret_from_kernel_thread");
 
 int
 copy_thread(unsigned long clone_flags, unsigned long stack_start,
@@ -266,17 +267,22 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
         struct thread_info *thread = task_thread_info(p);
         struct pt_regs *childregs = task_pt_regs(p);
 
-        *childregs = *regs;
-        childregs->UCreg_00 = 0;
-        childregs->UCreg_sp = stack_start;
-
         memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save));
         thread->cpu_context.sp = (unsigned long)childregs;
-        thread->cpu_context.pc = (unsigned long)ret_from_fork;
-
-        if (clone_flags & CLONE_SETTLS)
-                childregs->UCreg_16 = regs->UCreg_03;
+        if (unlikely(!regs)) {
+                thread->cpu_context.pc = (unsigned long)ret_from_kernel_thread;
+                thread->cpu_context.r4 = stack_start;
+                thread->cpu_context.r5 = stk_sz;
+                memset(childregs, 0, sizeof(struct pt_regs));
+        } else {
+                thread->cpu_context.pc = (unsigned long)ret_from_fork;
+                *childregs = *regs;
+                childregs->UCreg_00 = 0;
+                childregs->UCreg_sp = stack_start;
 
+                if (clone_flags & CLONE_SETTLS)
+                        childregs->UCreg_16 = regs->UCreg_03;
+        }
         return 0;
 }
 
@@ -305,42 +311,6 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fp)
 }
 EXPORT_SYMBOL(dump_fpu);
 
-/*
- * Shuffle the argument into the correct register before calling the
- * thread function.  r1 is the thread argument, r2 is the pointer to
- * the thread function, and r3 points to the exit function.
- */
-asm(".pushsection .text\n"
-"       .align\n"
-"       .type   kernel_thread_helper, #function\n"
-"kernel_thread_helper:\n"
-"       mov.a   asr, r7\n"
-"       mov     r0, r4\n"
-"       mov     lr, r6\n"
-"       mov     pc, r5\n"
-"       .size   kernel_thread_helper, . - kernel_thread_helper\n"
-"       .popsection");
-
-/*
- * Create a kernel thread.
- */
-pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
-{
-        struct pt_regs regs;
-
-        memset(&regs, 0, sizeof(regs));
-
-        regs.UCreg_04 = (unsigned long)arg;
-        regs.UCreg_05 = (unsigned long)fn;
-        regs.UCreg_06 = (unsigned long)do_exit;
-        regs.UCreg_07 = PRIV_MODE;
-        regs.UCreg_pc = (unsigned long)kernel_thread_helper;
-        regs.UCreg_asr = regs.UCreg_07 | PSR_I_BIT;
-
-        return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
-}
-EXPORT_SYMBOL(kernel_thread);
-
 unsigned long get_wchan(struct task_struct *p)
 {
         struct stackframe frame;
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index f23955028a18..30f749da8f73 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -30,4 +30,10 @@ extern char __vectors_start[], __vectors_end[];
 extern void kernel_thread_helper(void);
 
 extern void __init early_signal_init(void);
+
+extern asmlinkage void __backtrace(void);
+extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
+
+extern void __show_regs(struct pt_regs *);
+
 #endif
diff --git a/arch/unicore32/kernel/sys.c b/arch/unicore32/kernel/sys.c
index fabdee96110b..9680134b31f0 100644
--- a/arch/unicore32/kernel/sys.c
+++ b/arch/unicore32/kernel/sys.c
@@ -42,69 +42,6 @@ asmlinkage long __sys_clone(unsigned long clone_flags, unsigned long newsp,
                         parent_tid, child_tid);
 }
 
-/* sys_execve() executes a new program.
- * This is called indirectly via a small wrapper
- */
-asmlinkage long __sys_execve(const char __user *filename,
-                          const char __user *const __user *argv,
-                          const char __user *const __user *envp,
-                          struct pt_regs *regs)
-{
-        int error;
-        struct filename *fn;
-
-        fn = getname(filename);
-        error = PTR_ERR(fn);
-        if (IS_ERR(fn))
-                goto out;
-        error = do_execve(fn->name, argv, envp, regs);
-        putname(fn);
-out:
-        return error;
-}
-
-int kernel_execve(const char *filename,
-                  const char *const argv[],
-                  const char *const envp[])
-{
-        struct pt_regs regs;
-        int ret;
-
-        memset(&regs, 0, sizeof(struct pt_regs));
-        ret = do_execve(filename,
-                        (const char __user *const __user *)argv,
-                        (const char __user *const __user *)envp, &regs);
-        if (ret < 0)
-                goto out;
-
-        /*
-         * Save argc to the register structure for userspace.
-         */
-        regs.UCreg_00 = ret;
-
-        /*
-         * We were successful.  We won't be returning to our caller, but
-         * instead to user space by manipulating the kernel stack.
-         */
-        asm("add        r0, %0, %1\n\t"
-                "mov    r1, %2\n\t"
-                "mov    r2, %3\n\t"
-                "mov    r22, #0\n\t"    /* not a syscall */
-                "mov    r23, %0\n\t"    /* thread structure */
-                "b.l    memmove\n\t"    /* copy regs to top of stack */
-                "mov    sp, r0\n\t"     /* reposition stack pointer */
-                "b      ret_to_user"
-                :
-                : "r" (current_thread_info()),
-                  "Ir" (THREAD_START_SP - sizeof(regs)),
-                  "r" (&regs),
-                  "Ir" (sizeof(regs))
-                : "r0", "r1", "r2", "r3", "ip", "lr", "memory");
-
- out:
-        return ret;
-}
-
 /* Note: used by the compat code even in 64-bit Linux. */
 SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
                 unsigned long, prot, unsigned long, flags,
diff --git a/arch/unicore32/mm/fault.c b/arch/unicore32/mm/fault.c
index 2eeb9c04cab0..f9b5c10bccee 100644
--- a/arch/unicore32/mm/fault.c
+++ b/arch/unicore32/mm/fault.c
@@ -168,7 +168,7 @@ static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma)
 }
 
 static int __do_pf(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
-                struct task_struct *tsk)
+                unsigned int flags, struct task_struct *tsk)
 {
         struct vm_area_struct *vma;
         int fault;
@@ -194,14 +194,7 @@ good_area:
          * If for any reason at all we couldn't handle the fault, make
          * sure we exit gracefully rather than endlessly redo the fault.
          */
-        fault = handle_mm_fault(mm, vma, addr & PAGE_MASK,
-                            (!(fsr ^ 0x12)) ? FAULT_FLAG_WRITE : 0);
-        if (unlikely(fault & VM_FAULT_ERROR))
-                return fault;
-        if (fault & VM_FAULT_MAJOR)
-                tsk->maj_flt++;
-        else
-                tsk->min_flt++;
+        fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, flags);
         return fault;
 
 check_stack:
@@ -216,6 +209,8 @@ static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         struct task_struct *tsk;
         struct mm_struct *mm;
         int fault, sig, code;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
+                                 ((!(fsr ^ 0x12)) ? FAULT_FLAG_WRITE : 0);
 
         tsk = current;
         mm = tsk->mm;
@@ -236,6 +231,7 @@ static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 if (!user_mode(regs)
                     && !search_exception_tables(regs->UCreg_pc))
                         goto no_context;
+retry:
                 down_read(&mm->mmap_sem);
         } else {
                 /*
@@ -251,7 +247,28 @@ static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 #endif
         }
 
-        fault = __do_pf(mm, addr, fsr, tsk);
+        fault = __do_pf(mm, addr, fsr, flags, tsk);
+
+        /* If we need to retry but a fatal signal is pending, handle the
+         * signal first. We do not need to release the mmap_sem because
+         * it would already be released in __lock_page_or_retry in
+         * mm/filemap.c. */
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return 0;
+
+        if (!(fault & VM_FAULT_ERROR) && (flags & FAULT_FLAG_ALLOW_RETRY)) {
+                if (fault & VM_FAULT_MAJOR)
+                        tsk->maj_flt++;
+                else
+                        tsk->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
+                        * of starvation. */
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        goto retry;
+                }
+        }
+
         up_read(&mm->mmap_sem);
 
         /*
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index c760e073963e..e87b0cac14b5 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -12,6 +12,8 @@
 #include <asm/setup.h>
 #include <asm/desc.h>
 
+#undef memcpy                   /* Use memcpy from misc.c */
+
 #include "eboot.h"
 
 static efi_system_table_t *sys_table;
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index 2a017441b8b2..8c132a625b94 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -476,6 +476,3 @@ die:
 setup_corrupt:
         .byte   7
         .string "No setup signature found...\n"
-
-        .data
-dummy:  .long   0
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index dcfde52979c3..19f16ebaf4fa 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -205,21 +205,14 @@ static inline bool user_64bit_mode(struct pt_regs *regs)
 }
 #endif
 
-/*
- * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode
- * when it traps.  The previous stack will be directly underneath the saved
- * registers, and 'sp/ss' won't even have been saved. Thus the '&regs->sp'.
- *
- * This is valid only for kernel mode traps.
- */
-static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
-{
 #ifdef CONFIG_X86_32
-        return (unsigned long)(&regs->sp);
+extern unsigned long kernel_stack_pointer(struct pt_regs *regs);
 #else
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
         return regs->sp;
-#endif
 }
+#endif
 
 #define GET_IP(regs) ((regs)->ip)
 #define GET_FP(regs) ((regs)->bp)
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 59c226d120cd..c20d1ce62dc6 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -359,18 +359,14 @@ HYPERVISOR_update_va_mapping(unsigned long va, pte_t new_val,
                 return _hypercall4(int, update_va_mapping, va,
                                    new_val.pte, new_val.pte >> 32, flags);
 }
+extern int __must_check xen_event_channel_op_compat(int, void *);
 
 static inline int
 HYPERVISOR_event_channel_op(int cmd, void *arg)
 {
         int rc = _hypercall2(int, event_channel_op, cmd, arg);
-        if (unlikely(rc == -ENOSYS)) {
-                struct evtchn_op op;
-                op.cmd = cmd;
-                memcpy(&op.u, arg, sizeof(op.u));
-                rc = _hypercall1(int, event_channel_op_compat, &op);
-                memcpy(arg, &op.u, sizeof(op.u));
-        }
+        if (unlikely(rc == -ENOSYS))
+                rc = xen_event_channel_op_compat(cmd, arg);
         return rc;
 }
 
@@ -386,17 +382,14 @@ HYPERVISOR_console_io(int cmd, int count, char *str)
         return _hypercall3(int, console_io, cmd, count, str);
 }
 
+extern int __must_check HYPERVISOR_physdev_op_compat(int, void *);
+
 static inline int
 HYPERVISOR_physdev_op(int cmd, void *arg)
 {
         int rc = _hypercall2(int, physdev_op, cmd, arg);
-        if (unlikely(rc == -ENOSYS)) {
-                struct physdev_op op;
-                op.cmd = cmd;
-                memcpy(&op.u, arg, sizeof(op.u));
-                rc = _hypercall1(int, physdev_op_compat, &op);
-                memcpy(arg, &op.u, sizeof(op.u));
-        }
+        if (unlikely(rc == -ENOSYS))
+                rc = HYPERVISOR_physdev_op_compat(cmd, arg);
         return rc;
 }
 
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f7e98a2c0d12..1b7d1656a042 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 }
         }
 
+        /*
+         * The way access filter has a performance penalty on some workloads.
+         * Disable it on the affected CPUs.
+         */
+        if ((c->x86 == 0x15) &&
+            (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
+                u64 val;
+
+                if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
+                        val |= 0x1E;
+                        wrmsrl_safe(0xc0011021, val);
+                }
+        }
+
         cpu_detect_cache_sizes(c);
 
         /* Multi core CPU? */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 698b6ec12e0f..1ac581f38dfa 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -6,7 +6,7 @@
  *
  *  Written by Jacob Shin - AMD, Inc.
  *
- *  Support: borislav.petkov@amd.com
+ *  Maintained by: Borislav Petkov <bp@alien8.de>
  *
  *  April 2006
  *     - added support for AMD Family 0x10 processors
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 5f88abf07e9c..4f9a3cbfc4a3 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -285,34 +285,39 @@ void cmci_clear(void)
         raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
 }
 
+static long cmci_rediscover_work_func(void *arg)
+{
+        int banks;
+
+        /* Recheck banks in case CPUs don't all have the same */
+        if (cmci_supported(&banks))
+                cmci_discover(banks);
+
+        return 0;
+}
+
 /*
  * After a CPU went down cycle through all the others and rediscover
  * Must run in process context.
  */
 void cmci_rediscover(int dying)
 {
-        int banks;
-        int cpu;
-        cpumask_var_t old;
+        int cpu, banks;
 
         if (!cmci_supported(&banks))
                 return;
-        if (!alloc_cpumask_var(&old, GFP_KERNEL))
-                return;
-        cpumask_copy(old, &current->cpus_allowed);
 
         for_each_online_cpu(cpu) {
                 if (cpu == dying)
                         continue;
-                if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
+
+                if (cpu == smp_processor_id()) {
+                        cmci_rediscover_work_func(NULL);
                         continue;
-                /* Recheck banks in case CPUs don't all have the same */
-                if (cmci_supported(&banks))
-                        cmci_discover(banks);
-        }
+                }
 
-        set_cpus_allowed_ptr(current, old);
-        free_cpumask_var(old);
+                work_on_cpu(cpu, cmci_rediscover_work_func, NULL);
+        }
 }
 
 /*
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index b51b2c7ee51f..1328fe49a3f1 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -995,8 +995,8 @@ END(interrupt)
          */
         .p2align CONFIG_X86_L1_CACHE_SHIFT
 common_interrupt:
-        ASM_CLAC
         XCPT_FRAME
+        ASM_CLAC
         addq $-0x80,(%rsp)              /* Adjust vector to [-256,-1] range */
         interrupt do_IRQ
         /* 0(%rsp): old_rsp-ARGOFFSET */
@@ -1135,8 +1135,8 @@ END(common_interrupt)
  */
 .macro apicinterrupt num sym do_sym
 ENTRY(\sym)
-        ASM_CLAC
         INTR_FRAME
+        ASM_CLAC
         pushq_cfi $~(\num)
 .Lcommon_\sym:
         interrupt \do_sym
@@ -1190,8 +1190,8 @@ apicinterrupt IRQ_WORK_VECTOR \
  */
 .macro zeroentry sym do_sym
 ENTRY(\sym)
-        ASM_CLAC
         INTR_FRAME
+        ASM_CLAC
         PARAVIRT_ADJUST_EXCEPTION_FRAME
         pushq_cfi $-1           /* ORIG_RAX: no syscall to restart */
         subq $ORIG_RAX-R15, %rsp
@@ -1208,8 +1208,8 @@ END(\sym)
 
 .macro paranoidzeroentry sym do_sym
 ENTRY(\sym)
-        ASM_CLAC
         INTR_FRAME
+        ASM_CLAC
         PARAVIRT_ADJUST_EXCEPTION_FRAME
         pushq_cfi $-1           /* ORIG_RAX: no syscall to restart */
         subq $ORIG_RAX-R15, %rsp
@@ -1227,8 +1227,8 @@ END(\sym)
 #define INIT_TSS_IST(x) PER_CPU_VAR(init_tss) + (TSS_ist + ((x) - 1) * 8)
 .macro paranoidzeroentry_ist sym do_sym ist
 ENTRY(\sym)
-        ASM_CLAC
         INTR_FRAME
+        ASM_CLAC
         PARAVIRT_ADJUST_EXCEPTION_FRAME
         pushq_cfi $-1           /* ORIG_RAX: no syscall to restart */
         subq $ORIG_RAX-R15, %rsp
@@ -1247,8 +1247,8 @@ END(\sym)
 
 .macro errorentry sym do_sym
 ENTRY(\sym)
-        ASM_CLAC
         XCPT_FRAME
+        ASM_CLAC
         PARAVIRT_ADJUST_EXCEPTION_FRAME
         subq $ORIG_RAX-R15, %rsp
         CFI_ADJUST_CFA_OFFSET ORIG_RAX-R15
@@ -1266,8 +1266,8 @@ END(\sym)
         /* error code is on the stack already */
 .macro paranoiderrorentry sym do_sym
 ENTRY(\sym)
-        ASM_CLAC
         XCPT_FRAME
+        ASM_CLAC
         PARAVIRT_ADJUST_EXCEPTION_FRAME
         subq $ORIG_RAX-R15, %rsp
         CFI_ADJUST_CFA_OFFSET ORIG_RAX-R15
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 7720ff5a9ee2..efdec7cd8e01 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -8,8 +8,8 @@
  *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
  *
  *  Maintainers:
- *  Andreas Herrmann <andreas.herrmann3@amd.com>
- *  Borislav Petkov <borislav.petkov@amd.com>
+ *  Andreas Herrmann <herrmann.der.user@googlemail.com>
+ *  Borislav Petkov <bp@alien8.de>
  *
  *  This driver allows to upgrade microcode on F10h AMD
  *  CPUs and later.
@@ -190,6 +190,7 @@ static unsigned int verify_patch_size(int cpu, u32 patch_size,
 #define F1XH_MPB_MAX_SIZE 2048
 #define F14H_MPB_MAX_SIZE 1824
 #define F15H_MPB_MAX_SIZE 4096
+#define F16H_MPB_MAX_SIZE 3458
 
         switch (c->x86) {
         case 0x14:
@@ -198,6 +199,9 @@ static unsigned int verify_patch_size(int cpu, u32 patch_size,
         case 0x15:
                 max_size = F15H_MPB_MAX_SIZE;
                 break;
+        case 0x16:
+                max_size = F16H_MPB_MAX_SIZE;
+                break;
         default:
                 max_size = F1XH_MPB_MAX_SIZE;
                 break;
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index b00b33a18390..5e0596b0632e 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -22,6 +22,7 @@
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/rcupdate.h>
+#include <linux/module.h>
 
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -166,6 +167,35 @@ static inline bool invalid_selector(u16 value)
 
 #define FLAG_MASK               FLAG_MASK_32
 
+/*
+ * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode
+ * when it traps.  The previous stack will be directly underneath the saved
+ * registers, and 'sp/ss' won't even have been saved. Thus the '&regs->sp'.
+ *
+ * Now, if the stack is empty, '&regs->sp' is out of range. In this
+ * case we try to take the previous stack. To always return a non-null
+ * stack pointer we fall back to regs as stack if no previous stack
+ * exists.
+ *
+ * This is valid only for kernel mode traps.
+ */
+unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+        unsigned long context = (unsigned long)regs & ~(THREAD_SIZE - 1);
+        unsigned long sp = (unsigned long)&regs->sp;
+        struct thread_info *tinfo;
+
+        if (context == (sp & ~(THREAD_SIZE - 1)))
+                return sp;
+
+        tinfo = (struct thread_info *)context;
+        if (tinfo->previous_esp)
+                return tinfo->previous_esp;
+
+        return (unsigned long)regs;
+}
+EXPORT_SYMBOL_GPL(kernel_stack_pointer);
+
 static unsigned long *pt_regs_access(struct pt_regs *regs, unsigned long regno)
 {
         BUILD_BUG_ON(offsetof(struct pt_regs, bx) != 0);
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index a10e46016851..58fc51488828 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -24,6 +24,9 @@ static inline bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
 {
         struct kvm_cpuid_entry2 *best;
 
+        if (!static_cpu_has(X86_FEATURE_XSAVE))
+                return 0;
+
         best = kvm_find_cpuid_entry(vcpu, 1, 0);
         return best && (best->ecx & bit(X86_FEATURE_XSAVE));
 }
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ad6b1dd06f8b..f85815945fc6 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -6549,19 +6549,22 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
                 }
         }
 
-        exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
         /* Exposing INVPCID only when PCID is exposed */
         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
         if (vmx_invpcid_supported() &&
             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
             guest_cpuid_has_pcid(vcpu)) {
+                exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
                              exec_control);
         } else {
-                exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
-                vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
-                             exec_control);
+                if (cpu_has_secondary_exec_ctrls()) {
+                        exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+                        exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
+                        vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
+                                     exec_control);
+                }
                 if (best)
                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
         }
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 224a7e78cb6c..4f7641756be2 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5781,6 +5781,9 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         int pending_vec, max_bits, idx;
         struct desc_ptr dt;
 
+        if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
+                return -EINVAL;
+
         dt.size = sregs->idt.limit;
         dt.address = sregs->idt.base;
         kvm_x86_ops->set_idt(vcpu, &dt);
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 0777f042e400..60f926cd8b0e 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -197,7 +197,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
         }
 
         if (end == TLB_FLUSH_ALL || tlb_flushall_shift == -1
-                                        || vmflag == VM_HUGETLB) {
+                                        || vmflag & VM_HUGETLB) {
                 local_flush_tlb();
                 goto flush_all;
         }
diff --git a/arch/x86/pci/ce4100.c b/arch/x86/pci/ce4100.c
index 41bd2a2d2c50..b914e20b5a00 100644
--- a/arch/x86/pci/ce4100.c
+++ b/arch/x86/pci/ce4100.c
@@ -115,6 +115,16 @@ static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
         reg_read(reg, value);
 }
 
+static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
+        /* force interrupt pin value to 0 */
+        *value = reg->sim_reg.value & 0xfff00ff;
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+}
+
 static struct sim_dev_reg bus1_fixups[] = {
         DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
         DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
@@ -144,6 +154,7 @@ static struct sim_dev_reg bus1_fixups[] = {
         DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
         DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
         DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
         DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
         DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
         DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
@@ -161,8 +172,10 @@ static struct sim_dev_reg bus1_fixups[] = {
         DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
         DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
         DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
         DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
         DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
 };
 
 static void __init init_sim_regs(void)
diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
index 4c61b52191eb..92525cb8e54c 100644
--- a/arch/x86/platform/ce4100/ce4100.c
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -21,12 +21,25 @@
 #include <asm/i8259.h>
 #include <asm/io.h>
 #include <asm/io_apic.h>
+#include <asm/emergency-restart.h>
 
 static int ce4100_i8042_detect(void)
 {
         return 0;
 }
 
+/*
+ * The CE4100 platform has an internal 8051 Microcontroller which is
+ * responsible for signaling to the external Power Management Unit the
+ * intention to reset, reboot or power off the system. This 8051 device has
+ * its command register mapped at I/O port 0xcf9 and the value 0x4 is used
+ * to power off the system.
+ */
+static void ce4100_power_off(void)
+{
+        outb(0x4, 0xcf9);
+}
+
 #ifdef CONFIG_SERIAL_8250
 
 static unsigned int mem_serial_in(struct uart_port *p, int offset)
@@ -139,8 +152,19 @@ void __init x86_ce4100_early_setup(void)
         x86_init.mpparse.find_smp_config = x86_init_noop;
         x86_init.pci.init = ce4100_pci_init;
 
+        /*
+         * By default, the reboot method is ACPI which is supported by the
+         * CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue
+         * the bootloader will however issue a system power off instead of
+         * reboot. By using BOOT_KBD we ensure proper system reboot as
+         * expected.
+         */
+        reboot_type = BOOT_KBD;
+
 #ifdef CONFIG_X86_IO_APIC
         x86_init.pci.init_irq = sdv_pci_init;
         x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
 #endif
+
+        pm_power_off = ce4100_power_off;
 }