diff options
Diffstat (limited to 'arch')
25 files changed, 679 insertions, 1467 deletions
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 61691cdbdcf2..9173d112ea01 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -16,6 +16,7 @@ | |||
16 | */ | 16 | */ |
17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/irq.h> | ||
19 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
20 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
21 | #include <linux/errno.h> | 22 | #include <linux/errno.h> |
@@ -28,9 +29,8 @@ | |||
28 | #include <linux/io.h> | 29 | #include <linux/io.h> |
29 | 30 | ||
30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
31 | #include <asm/mach-types.h> | ||
32 | #include <asm/irq.h> | ||
33 | #include <asm/mach/irq.h> | 32 | #include <asm/mach/irq.h> |
33 | #include <asm/mach-types.h> | ||
34 | #include <asm/sizes.h> | 34 | #include <asm/sizes.h> |
35 | 35 | ||
36 | #include <asm/hardware/sa1111.h> | 36 | #include <asm/hardware/sa1111.h> |
@@ -86,8 +86,10 @@ | |||
86 | #define IRQ_S1_CD_VALID (52) | 86 | #define IRQ_S1_CD_VALID (52) |
87 | #define IRQ_S0_BVD1_STSCHG (53) | 87 | #define IRQ_S0_BVD1_STSCHG (53) |
88 | #define IRQ_S1_BVD1_STSCHG (54) | 88 | #define IRQ_S1_BVD1_STSCHG (54) |
89 | #define SA1111_IRQ_NR (55) | ||
89 | 90 | ||
90 | extern void __init sa1110_mb_enable(void); | 91 | extern void sa1110_mb_enable(void); |
92 | extern void sa1110_mb_disable(void); | ||
91 | 93 | ||
92 | /* | 94 | /* |
93 | * We keep the following data for the overall SA1111. Note that the | 95 | * We keep the following data for the overall SA1111. Note that the |
@@ -104,6 +106,7 @@ struct sa1111 { | |||
104 | int irq_base; /* base for cascaded on-chip IRQs */ | 106 | int irq_base; /* base for cascaded on-chip IRQs */ |
105 | spinlock_t lock; | 107 | spinlock_t lock; |
106 | void __iomem *base; | 108 | void __iomem *base; |
109 | struct sa1111_platform_data *pdata; | ||
107 | #ifdef CONFIG_PM | 110 | #ifdef CONFIG_PM |
108 | void *saved_state; | 111 | void *saved_state; |
109 | #endif | 112 | #endif |
@@ -118,6 +121,7 @@ static struct sa1111 *g_sa1111; | |||
118 | struct sa1111_dev_info { | 121 | struct sa1111_dev_info { |
119 | unsigned long offset; | 122 | unsigned long offset; |
120 | unsigned long skpcr_mask; | 123 | unsigned long skpcr_mask; |
124 | bool dma; | ||
121 | unsigned int devid; | 125 | unsigned int devid; |
122 | unsigned int irq[6]; | 126 | unsigned int irq[6]; |
123 | }; | 127 | }; |
@@ -126,6 +130,7 @@ static struct sa1111_dev_info sa1111_devices[] = { | |||
126 | { | 130 | { |
127 | .offset = SA1111_USB, | 131 | .offset = SA1111_USB, |
128 | .skpcr_mask = SKPCR_UCLKEN, | 132 | .skpcr_mask = SKPCR_UCLKEN, |
133 | .dma = true, | ||
129 | .devid = SA1111_DEVID_USB, | 134 | .devid = SA1111_DEVID_USB, |
130 | .irq = { | 135 | .irq = { |
131 | IRQ_USBPWR, | 136 | IRQ_USBPWR, |
@@ -139,6 +144,7 @@ static struct sa1111_dev_info sa1111_devices[] = { | |||
139 | { | 144 | { |
140 | .offset = 0x0600, | 145 | .offset = 0x0600, |
141 | .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, | 146 | .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, |
147 | .dma = true, | ||
142 | .devid = SA1111_DEVID_SAC, | 148 | .devid = SA1111_DEVID_SAC, |
143 | .irq = { | 149 | .irq = { |
144 | AUDXMTDMADONEA, | 150 | AUDXMTDMADONEA, |
@@ -155,7 +161,7 @@ static struct sa1111_dev_info sa1111_devices[] = { | |||
155 | { | 161 | { |
156 | .offset = SA1111_KBD, | 162 | .offset = SA1111_KBD, |
157 | .skpcr_mask = SKPCR_PTCLKEN, | 163 | .skpcr_mask = SKPCR_PTCLKEN, |
158 | .devid = SA1111_DEVID_PS2, | 164 | .devid = SA1111_DEVID_PS2_KBD, |
159 | .irq = { | 165 | .irq = { |
160 | IRQ_TPRXINT, | 166 | IRQ_TPRXINT, |
161 | IRQ_TPTXINT | 167 | IRQ_TPTXINT |
@@ -164,7 +170,7 @@ static struct sa1111_dev_info sa1111_devices[] = { | |||
164 | { | 170 | { |
165 | .offset = SA1111_MSE, | 171 | .offset = SA1111_MSE, |
166 | .skpcr_mask = SKPCR_PMCLKEN, | 172 | .skpcr_mask = SKPCR_PMCLKEN, |
167 | .devid = SA1111_DEVID_PS2, | 173 | .devid = SA1111_DEVID_PS2_MSE, |
168 | .irq = { | 174 | .irq = { |
169 | IRQ_MSRXINT, | 175 | IRQ_MSRXINT, |
170 | IRQ_MSTXINT | 176 | IRQ_MSTXINT |
@@ -434,16 +440,28 @@ static struct irq_chip sa1111_high_chip = { | |||
434 | .irq_set_wake = sa1111_wake_highirq, | 440 | .irq_set_wake = sa1111_wake_highirq, |
435 | }; | 441 | }; |
436 | 442 | ||
437 | static void sa1111_setup_irq(struct sa1111 *sachip) | 443 | static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) |
438 | { | 444 | { |
439 | void __iomem *irqbase = sachip->base + SA1111_INTC; | 445 | void __iomem *irqbase = sachip->base + SA1111_INTC; |
440 | unsigned int irq; | 446 | unsigned i, irq; |
447 | int ret; | ||
441 | 448 | ||
442 | /* | 449 | /* |
443 | * We're guaranteed that this region hasn't been taken. | 450 | * We're guaranteed that this region hasn't been taken. |
444 | */ | 451 | */ |
445 | request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); | 452 | request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); |
446 | 453 | ||
454 | ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); | ||
455 | if (ret <= 0) { | ||
456 | dev_err(sachip->dev, "unable to allocate %u irqs: %d\n", | ||
457 | SA1111_IRQ_NR, ret); | ||
458 | if (ret == 0) | ||
459 | ret = -EINVAL; | ||
460 | return ret; | ||
461 | } | ||
462 | |||
463 | sachip->irq_base = ret; | ||
464 | |||
447 | /* disable all IRQs */ | 465 | /* disable all IRQs */ |
448 | sa1111_writel(0, irqbase + SA1111_INTEN0); | 466 | sa1111_writel(0, irqbase + SA1111_INTEN0); |
449 | sa1111_writel(0, irqbase + SA1111_INTEN1); | 467 | sa1111_writel(0, irqbase + SA1111_INTEN1); |
@@ -463,14 +481,16 @@ static void sa1111_setup_irq(struct sa1111 *sachip) | |||
463 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); | 481 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); |
464 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); | 482 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); |
465 | 483 | ||
466 | for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { | 484 | for (i = IRQ_GPAIN0; i <= SSPROR; i++) { |
485 | irq = sachip->irq_base + i; | ||
467 | irq_set_chip_and_handler(irq, &sa1111_low_chip, | 486 | irq_set_chip_and_handler(irq, &sa1111_low_chip, |
468 | handle_edge_irq); | 487 | handle_edge_irq); |
469 | irq_set_chip_data(irq, sachip); | 488 | irq_set_chip_data(irq, sachip); |
470 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 489 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
471 | } | 490 | } |
472 | 491 | ||
473 | for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { | 492 | for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) { |
493 | irq = sachip->irq_base + i; | ||
474 | irq_set_chip_and_handler(irq, &sa1111_high_chip, | 494 | irq_set_chip_and_handler(irq, &sa1111_high_chip, |
475 | handle_edge_irq); | 495 | handle_edge_irq); |
476 | irq_set_chip_data(irq, sachip); | 496 | irq_set_chip_data(irq, sachip); |
@@ -483,6 +503,11 @@ static void sa1111_setup_irq(struct sa1111 *sachip) | |||
483 | irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); | 503 | irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); |
484 | irq_set_handler_data(sachip->irq, sachip); | 504 | irq_set_handler_data(sachip->irq, sachip); |
485 | irq_set_chained_handler(sachip->irq, sa1111_irq_handler); | 505 | irq_set_chained_handler(sachip->irq, sa1111_irq_handler); |
506 | |||
507 | dev_info(sachip->dev, "Providing IRQ%u-%u\n", | ||
508 | sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); | ||
509 | |||
510 | return 0; | ||
486 | } | 511 | } |
487 | 512 | ||
488 | /* | 513 | /* |
@@ -581,41 +606,10 @@ sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, | |||
581 | } | 606 | } |
582 | #endif | 607 | #endif |
583 | 608 | ||
584 | #ifdef CONFIG_DMABOUNCE | ||
585 | /* | ||
586 | * According to the "Intel StrongARM SA-1111 Microprocessor Companion | ||
587 | * Chip Specification Update" (June 2000), erratum #7, there is a | ||
588 | * significant bug in the SA1111 SDRAM shared memory controller. If | ||
589 | * an access to a region of memory above 1MB relative to the bank base, | ||
590 | * it is important that address bit 10 _NOT_ be asserted. Depending | ||
591 | * on the configuration of the RAM, bit 10 may correspond to one | ||
592 | * of several different (processor-relative) address bits. | ||
593 | * | ||
594 | * This routine only identifies whether or not a given DMA address | ||
595 | * is susceptible to the bug. | ||
596 | * | ||
597 | * This should only get called for sa1111_device types due to the | ||
598 | * way we configure our device dma_masks. | ||
599 | */ | ||
600 | static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) | ||
601 | { | ||
602 | /* | ||
603 | * Section 4.6 of the "Intel StrongARM SA-1111 Development Module | ||
604 | * User's Guide" mentions that jumpers R51 and R52 control the | ||
605 | * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or | ||
606 | * SDRAM bank 1 on Neponset). The default configuration selects | ||
607 | * Assabet, so any address in bank 1 is necessarily invalid. | ||
608 | */ | ||
609 | return (machine_is_assabet() || machine_is_pfs168()) && | ||
610 | (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); | ||
611 | } | ||
612 | #endif | ||
613 | |||
614 | static void sa1111_dev_release(struct device *_dev) | 609 | static void sa1111_dev_release(struct device *_dev) |
615 | { | 610 | { |
616 | struct sa1111_dev *dev = SA1111_DEV(_dev); | 611 | struct sa1111_dev *dev = SA1111_DEV(_dev); |
617 | 612 | ||
618 | release_resource(&dev->res); | ||
619 | kfree(dev); | 613 | kfree(dev); |
620 | } | 614 | } |
621 | 615 | ||
@@ -624,67 +618,58 @@ sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, | |||
624 | struct sa1111_dev_info *info) | 618 | struct sa1111_dev_info *info) |
625 | { | 619 | { |
626 | struct sa1111_dev *dev; | 620 | struct sa1111_dev *dev; |
621 | unsigned i; | ||
627 | int ret; | 622 | int ret; |
628 | 623 | ||
629 | dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); | 624 | dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); |
630 | if (!dev) { | 625 | if (!dev) { |
631 | ret = -ENOMEM; | 626 | ret = -ENOMEM; |
632 | goto out; | 627 | goto err_alloc; |
633 | } | 628 | } |
634 | 629 | ||
630 | device_initialize(&dev->dev); | ||
635 | dev_set_name(&dev->dev, "%4.4lx", info->offset); | 631 | dev_set_name(&dev->dev, "%4.4lx", info->offset); |
636 | dev->devid = info->devid; | 632 | dev->devid = info->devid; |
637 | dev->dev.parent = sachip->dev; | 633 | dev->dev.parent = sachip->dev; |
638 | dev->dev.bus = &sa1111_bus_type; | 634 | dev->dev.bus = &sa1111_bus_type; |
639 | dev->dev.release = sa1111_dev_release; | 635 | dev->dev.release = sa1111_dev_release; |
640 | dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; | ||
641 | dev->res.start = sachip->phys + info->offset; | 636 | dev->res.start = sachip->phys + info->offset; |
642 | dev->res.end = dev->res.start + 511; | 637 | dev->res.end = dev->res.start + 511; |
643 | dev->res.name = dev_name(&dev->dev); | 638 | dev->res.name = dev_name(&dev->dev); |
644 | dev->res.flags = IORESOURCE_MEM; | 639 | dev->res.flags = IORESOURCE_MEM; |
645 | dev->mapbase = sachip->base + info->offset; | 640 | dev->mapbase = sachip->base + info->offset; |
646 | dev->skpcr_mask = info->skpcr_mask; | 641 | dev->skpcr_mask = info->skpcr_mask; |
647 | memmove(dev->irq, info->irq, sizeof(dev->irq)); | ||
648 | |||
649 | ret = request_resource(parent, &dev->res); | ||
650 | if (ret) { | ||
651 | printk("SA1111: failed to allocate resource for %s\n", | ||
652 | dev->res.name); | ||
653 | dev_set_name(&dev->dev, NULL); | ||
654 | kfree(dev); | ||
655 | goto out; | ||
656 | } | ||
657 | |||
658 | 642 | ||
659 | ret = device_register(&dev->dev); | 643 | for (i = 0; i < ARRAY_SIZE(info->irq); i++) |
660 | if (ret) { | 644 | dev->irq[i] = sachip->irq_base + info->irq[i]; |
661 | release_resource(&dev->res); | ||
662 | kfree(dev); | ||
663 | goto out; | ||
664 | } | ||
665 | 645 | ||
666 | #ifdef CONFIG_DMABOUNCE | ||
667 | /* | 646 | /* |
668 | * If the parent device has a DMA mask associated with it, | 647 | * If the parent device has a DMA mask associated with it, and |
669 | * propagate it down to the children. | 648 | * this child supports DMA, propagate it down to the children. |
670 | */ | 649 | */ |
671 | if (sachip->dev->dma_mask) { | 650 | if (info->dma && sachip->dev->dma_mask) { |
672 | dev->dma_mask = *sachip->dev->dma_mask; | 651 | dev->dma_mask = *sachip->dev->dma_mask; |
673 | dev->dev.dma_mask = &dev->dma_mask; | 652 | dev->dev.dma_mask = &dev->dma_mask; |
653 | dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; | ||
654 | } | ||
674 | 655 | ||
675 | if (dev->dma_mask != 0xffffffffUL) { | 656 | ret = request_resource(parent, &dev->res); |
676 | ret = dmabounce_register_dev(&dev->dev, 1024, 4096, | 657 | if (ret) { |
677 | sa1111_needs_bounce); | 658 | dev_err(sachip->dev, "failed to allocate resource for %s\n", |
678 | if (ret) { | 659 | dev->res.name); |
679 | dev_err(&dev->dev, "SA1111: Failed to register" | 660 | goto err_resource; |
680 | " with dmabounce\n"); | ||
681 | device_unregister(&dev->dev); | ||
682 | } | ||
683 | } | ||
684 | } | 661 | } |
685 | #endif | ||
686 | 662 | ||
687 | out: | 663 | ret = device_add(&dev->dev); |
664 | if (ret) | ||
665 | goto err_add; | ||
666 | return 0; | ||
667 | |||
668 | err_add: | ||
669 | release_resource(&dev->res); | ||
670 | err_resource: | ||
671 | put_device(&dev->dev); | ||
672 | err_alloc: | ||
688 | return ret; | 673 | return ret; |
689 | } | 674 | } |
690 | 675 | ||
@@ -698,16 +683,21 @@ out: | |||
698 | * Returns: | 683 | * Returns: |
699 | * %-ENODEV device not found. | 684 | * %-ENODEV device not found. |
700 | * %-EBUSY physical address already marked in-use. | 685 | * %-EBUSY physical address already marked in-use. |
686 | * %-EINVAL no platform data passed | ||
701 | * %0 successful. | 687 | * %0 successful. |
702 | */ | 688 | */ |
703 | static int __devinit | 689 | static int __devinit |
704 | __sa1111_probe(struct device *me, struct resource *mem, int irq) | 690 | __sa1111_probe(struct device *me, struct resource *mem, int irq) |
705 | { | 691 | { |
692 | struct sa1111_platform_data *pd = me->platform_data; | ||
706 | struct sa1111 *sachip; | 693 | struct sa1111 *sachip; |
707 | unsigned long id; | 694 | unsigned long id; |
708 | unsigned int has_devs; | 695 | unsigned int has_devs; |
709 | int i, ret = -ENODEV; | 696 | int i, ret = -ENODEV; |
710 | 697 | ||
698 | if (!pd) | ||
699 | return -EINVAL; | ||
700 | |||
711 | sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); | 701 | sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); |
712 | if (!sachip) | 702 | if (!sachip) |
713 | return -ENOMEM; | 703 | return -ENOMEM; |
@@ -727,6 +717,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
727 | sachip->dev = me; | 717 | sachip->dev = me; |
728 | dev_set_drvdata(sachip->dev, sachip); | 718 | dev_set_drvdata(sachip->dev, sachip); |
729 | 719 | ||
720 | sachip->pdata = pd; | ||
730 | sachip->phys = mem->start; | 721 | sachip->phys = mem->start; |
731 | sachip->irq = irq; | 722 | sachip->irq = irq; |
732 | 723 | ||
@@ -759,6 +750,16 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
759 | */ | 750 | */ |
760 | sa1111_wake(sachip); | 751 | sa1111_wake(sachip); |
761 | 752 | ||
753 | /* | ||
754 | * The interrupt controller must be initialised before any | ||
755 | * other device to ensure that the interrupts are available. | ||
756 | */ | ||
757 | if (sachip->irq != NO_IRQ) { | ||
758 | ret = sa1111_setup_irq(sachip, pd->irq_base); | ||
759 | if (ret) | ||
760 | goto err_unmap; | ||
761 | } | ||
762 | |||
762 | #ifdef CONFIG_ARCH_SA1100 | 763 | #ifdef CONFIG_ARCH_SA1100 |
763 | { | 764 | { |
764 | unsigned int val; | 765 | unsigned int val; |
@@ -789,24 +790,14 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
789 | } | 790 | } |
790 | #endif | 791 | #endif |
791 | 792 | ||
792 | /* | ||
793 | * The interrupt controller must be initialised before any | ||
794 | * other device to ensure that the interrupts are available. | ||
795 | */ | ||
796 | if (sachip->irq != NO_IRQ) | ||
797 | sa1111_setup_irq(sachip); | ||
798 | |||
799 | g_sa1111 = sachip; | 793 | g_sa1111 = sachip; |
800 | 794 | ||
801 | has_devs = ~0; | 795 | has_devs = ~0; |
802 | if (machine_is_assabet() || machine_is_jornada720() || | 796 | if (pd) |
803 | machine_is_badge4()) | 797 | has_devs &= ~pd->disable_devs; |
804 | has_devs &= ~(1 << 4); | ||
805 | else | ||
806 | has_devs &= ~(1 << 1); | ||
807 | 798 | ||
808 | for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) | 799 | for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) |
809 | if (has_devs & (1 << i)) | 800 | if (sa1111_devices[i].devid & has_devs) |
810 | sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); | 801 | sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); |
811 | 802 | ||
812 | return 0; | 803 | return 0; |
@@ -824,7 +815,10 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
824 | 815 | ||
825 | static int sa1111_remove_one(struct device *dev, void *data) | 816 | static int sa1111_remove_one(struct device *dev, void *data) |
826 | { | 817 | { |
827 | device_unregister(dev); | 818 | struct sa1111_dev *sadev = SA1111_DEV(dev); |
819 | device_del(&sadev->dev); | ||
820 | release_resource(&sadev->res); | ||
821 | put_device(&sadev->dev); | ||
828 | return 0; | 822 | return 0; |
829 | } | 823 | } |
830 | 824 | ||
@@ -846,6 +840,7 @@ static void __sa1111_remove(struct sa1111 *sachip) | |||
846 | if (sachip->irq != NO_IRQ) { | 840 | if (sachip->irq != NO_IRQ) { |
847 | irq_set_chained_handler(sachip->irq, NULL); | 841 | irq_set_chained_handler(sachip->irq, NULL); |
848 | irq_set_handler_data(sachip->irq, NULL); | 842 | irq_set_handler_data(sachip->irq, NULL); |
843 | irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); | ||
849 | 844 | ||
850 | release_mem_region(sachip->phys + SA1111_INTC, 512); | 845 | release_mem_region(sachip->phys + SA1111_INTC, 512); |
851 | } | 846 | } |
@@ -904,6 +899,9 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state) | |||
904 | save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0); | 899 | save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0); |
905 | save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1); | 900 | save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1); |
906 | 901 | ||
902 | sa1111_writel(0, sachip->base + SA1111_SKPWM0); | ||
903 | sa1111_writel(0, sachip->base + SA1111_SKPWM1); | ||
904 | |||
907 | base = sachip->base + SA1111_INTC; | 905 | base = sachip->base + SA1111_INTC; |
908 | save->intpol0 = sa1111_readl(base + SA1111_INTPOL0); | 906 | save->intpol0 = sa1111_readl(base + SA1111_INTPOL0); |
909 | save->intpol1 = sa1111_readl(base + SA1111_INTPOL1); | 907 | save->intpol1 = sa1111_readl(base + SA1111_INTPOL1); |
@@ -919,13 +917,15 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state) | |||
919 | */ | 917 | */ |
920 | val = sa1111_readl(sachip->base + SA1111_SKCR); | 918 | val = sa1111_readl(sachip->base + SA1111_SKCR); |
921 | sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); | 919 | sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); |
922 | sa1111_writel(0, sachip->base + SA1111_SKPWM0); | ||
923 | sa1111_writel(0, sachip->base + SA1111_SKPWM1); | ||
924 | 920 | ||
925 | clk_disable(sachip->clk); | 921 | clk_disable(sachip->clk); |
926 | 922 | ||
927 | spin_unlock_irqrestore(&sachip->lock, flags); | 923 | spin_unlock_irqrestore(&sachip->lock, flags); |
928 | 924 | ||
925 | #ifdef CONFIG_ARCH_SA1100 | ||
926 | sa1110_mb_disable(); | ||
927 | #endif | ||
928 | |||
929 | return 0; | 929 | return 0; |
930 | } | 930 | } |
931 | 931 | ||
@@ -966,6 +966,11 @@ static int sa1111_resume(struct platform_device *dev) | |||
966 | */ | 966 | */ |
967 | sa1111_wake(sachip); | 967 | sa1111_wake(sachip); |
968 | 968 | ||
969 | #ifdef CONFIG_ARCH_SA1100 | ||
970 | /* Enable the memory bus request/grant signals */ | ||
971 | sa1110_mb_enable(); | ||
972 | #endif | ||
973 | |||
969 | /* | 974 | /* |
970 | * Only lock for write ops. Also, sa1111_wake must be called with | 975 | * Only lock for write ops. Also, sa1111_wake must be called with |
971 | * released spinlock! | 976 | * released spinlock! |
@@ -1053,6 +1058,7 @@ static struct platform_driver sa1111_device_driver = { | |||
1053 | .resume = sa1111_resume, | 1058 | .resume = sa1111_resume, |
1054 | .driver = { | 1059 | .driver = { |
1055 | .name = "sa1111", | 1060 | .name = "sa1111", |
1061 | .owner = THIS_MODULE, | ||
1056 | }, | 1062 | }, |
1057 | }; | 1063 | }; |
1058 | 1064 | ||
@@ -1238,16 +1244,23 @@ EXPORT_SYMBOL(sa1111_set_sleep_io); | |||
1238 | * sa1111_enable_device - enable an on-chip SA1111 function block | 1244 | * sa1111_enable_device - enable an on-chip SA1111 function block |
1239 | * @sadev: SA1111 function block device to enable | 1245 | * @sadev: SA1111 function block device to enable |
1240 | */ | 1246 | */ |
1241 | void sa1111_enable_device(struct sa1111_dev *sadev) | 1247 | int sa1111_enable_device(struct sa1111_dev *sadev) |
1242 | { | 1248 | { |
1243 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | 1249 | struct sa1111 *sachip = sa1111_chip_driver(sadev); |
1244 | unsigned long flags; | 1250 | unsigned long flags; |
1245 | unsigned int val; | 1251 | unsigned int val; |
1252 | int ret = 0; | ||
1246 | 1253 | ||
1247 | spin_lock_irqsave(&sachip->lock, flags); | 1254 | if (sachip->pdata && sachip->pdata->enable) |
1248 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | 1255 | ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid); |
1249 | sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | 1256 | |
1250 | spin_unlock_irqrestore(&sachip->lock, flags); | 1257 | if (ret == 0) { |
1258 | spin_lock_irqsave(&sachip->lock, flags); | ||
1259 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | ||
1260 | sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | ||
1261 | spin_unlock_irqrestore(&sachip->lock, flags); | ||
1262 | } | ||
1263 | return ret; | ||
1251 | } | 1264 | } |
1252 | EXPORT_SYMBOL(sa1111_enable_device); | 1265 | EXPORT_SYMBOL(sa1111_enable_device); |
1253 | 1266 | ||
@@ -1265,6 +1278,9 @@ void sa1111_disable_device(struct sa1111_dev *sadev) | |||
1265 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | 1278 | val = sa1111_readl(sachip->base + SA1111_SKPCR); |
1266 | sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | 1279 | sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); |
1267 | spin_unlock_irqrestore(&sachip->lock, flags); | 1280 | spin_unlock_irqrestore(&sachip->lock, flags); |
1281 | |||
1282 | if (sachip->pdata && sachip->pdata->disable) | ||
1283 | sachip->pdata->disable(sachip->pdata->data, sadev->devid); | ||
1268 | } | 1284 | } |
1269 | EXPORT_SYMBOL(sa1111_disable_device); | 1285 | EXPORT_SYMBOL(sa1111_disable_device); |
1270 | 1286 | ||
@@ -1279,7 +1295,7 @@ static int sa1111_match(struct device *_dev, struct device_driver *_drv) | |||
1279 | struct sa1111_dev *dev = SA1111_DEV(_dev); | 1295 | struct sa1111_dev *dev = SA1111_DEV(_dev); |
1280 | struct sa1111_driver *drv = SA1111_DRV(_drv); | 1296 | struct sa1111_driver *drv = SA1111_DRV(_drv); |
1281 | 1297 | ||
1282 | return dev->devid == drv->devid; | 1298 | return dev->devid & drv->devid; |
1283 | } | 1299 | } |
1284 | 1300 | ||
1285 | static int sa1111_bus_suspend(struct device *dev, pm_message_t state) | 1301 | static int sa1111_bus_suspend(struct device *dev, pm_message_t state) |
@@ -1304,6 +1320,14 @@ static int sa1111_bus_resume(struct device *dev) | |||
1304 | return ret; | 1320 | return ret; |
1305 | } | 1321 | } |
1306 | 1322 | ||
1323 | static void sa1111_bus_shutdown(struct device *dev) | ||
1324 | { | ||
1325 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | ||
1326 | |||
1327 | if (drv && drv->shutdown) | ||
1328 | drv->shutdown(SA1111_DEV(dev)); | ||
1329 | } | ||
1330 | |||
1307 | static int sa1111_bus_probe(struct device *dev) | 1331 | static int sa1111_bus_probe(struct device *dev) |
1308 | { | 1332 | { |
1309 | struct sa1111_dev *sadev = SA1111_DEV(dev); | 1333 | struct sa1111_dev *sadev = SA1111_DEV(dev); |
@@ -1333,6 +1357,7 @@ struct bus_type sa1111_bus_type = { | |||
1333 | .remove = sa1111_bus_remove, | 1357 | .remove = sa1111_bus_remove, |
1334 | .suspend = sa1111_bus_suspend, | 1358 | .suspend = sa1111_bus_suspend, |
1335 | .resume = sa1111_bus_resume, | 1359 | .resume = sa1111_bus_resume, |
1360 | .shutdown = sa1111_bus_shutdown, | ||
1336 | }; | 1361 | }; |
1337 | EXPORT_SYMBOL(sa1111_bus_type); | 1362 | EXPORT_SYMBOL(sa1111_bus_type); |
1338 | 1363 | ||
@@ -1349,9 +1374,70 @@ void sa1111_driver_unregister(struct sa1111_driver *driver) | |||
1349 | } | 1374 | } |
1350 | EXPORT_SYMBOL(sa1111_driver_unregister); | 1375 | EXPORT_SYMBOL(sa1111_driver_unregister); |
1351 | 1376 | ||
1377 | #ifdef CONFIG_DMABOUNCE | ||
1378 | /* | ||
1379 | * According to the "Intel StrongARM SA-1111 Microprocessor Companion | ||
1380 | * Chip Specification Update" (June 2000), erratum #7, there is a | ||
1381 | * significant bug in the SA1111 SDRAM shared memory controller. If | ||
1382 | * an access to a region of memory above 1MB relative to the bank base, | ||
1383 | * it is important that address bit 10 _NOT_ be asserted. Depending | ||
1384 | * on the configuration of the RAM, bit 10 may correspond to one | ||
1385 | * of several different (processor-relative) address bits. | ||
1386 | * | ||
1387 | * This routine only identifies whether or not a given DMA address | ||
1388 | * is susceptible to the bug. | ||
1389 | * | ||
1390 | * This should only get called for sa1111_device types due to the | ||
1391 | * way we configure our device dma_masks. | ||
1392 | */ | ||
1393 | static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) | ||
1394 | { | ||
1395 | /* | ||
1396 | * Section 4.6 of the "Intel StrongARM SA-1111 Development Module | ||
1397 | * User's Guide" mentions that jumpers R51 and R52 control the | ||
1398 | * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or | ||
1399 | * SDRAM bank 1 on Neponset). The default configuration selects | ||
1400 | * Assabet, so any address in bank 1 is necessarily invalid. | ||
1401 | */ | ||
1402 | return (machine_is_assabet() || machine_is_pfs168()) && | ||
1403 | (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); | ||
1404 | } | ||
1405 | |||
1406 | static int sa1111_notifier_call(struct notifier_block *n, unsigned long action, | ||
1407 | void *data) | ||
1408 | { | ||
1409 | struct sa1111_dev *dev = SA1111_DEV(data); | ||
1410 | |||
1411 | switch (action) { | ||
1412 | case BUS_NOTIFY_ADD_DEVICE: | ||
1413 | if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) { | ||
1414 | int ret = dmabounce_register_dev(&dev->dev, 1024, 4096, | ||
1415 | sa1111_needs_bounce); | ||
1416 | if (ret) | ||
1417 | dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret); | ||
1418 | } | ||
1419 | break; | ||
1420 | |||
1421 | case BUS_NOTIFY_DEL_DEVICE: | ||
1422 | if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) | ||
1423 | dmabounce_unregister_dev(&dev->dev); | ||
1424 | break; | ||
1425 | } | ||
1426 | return NOTIFY_OK; | ||
1427 | } | ||
1428 | |||
1429 | static struct notifier_block sa1111_bus_notifier = { | ||
1430 | .notifier_call = sa1111_notifier_call, | ||
1431 | }; | ||
1432 | #endif | ||
1433 | |||
1352 | static int __init sa1111_init(void) | 1434 | static int __init sa1111_init(void) |
1353 | { | 1435 | { |
1354 | int ret = bus_register(&sa1111_bus_type); | 1436 | int ret = bus_register(&sa1111_bus_type); |
1437 | #ifdef CONFIG_DMABOUNCE | ||
1438 | if (ret == 0) | ||
1439 | bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier); | ||
1440 | #endif | ||
1355 | if (ret == 0) | 1441 | if (ret == 0) |
1356 | platform_driver_register(&sa1111_device_driver); | 1442 | platform_driver_register(&sa1111_device_driver); |
1357 | return ret; | 1443 | return ret; |
@@ -1360,6 +1446,9 @@ static int __init sa1111_init(void) | |||
1360 | static void __exit sa1111_exit(void) | 1446 | static void __exit sa1111_exit(void) |
1361 | { | 1447 | { |
1362 | platform_driver_unregister(&sa1111_device_driver); | 1448 | platform_driver_unregister(&sa1111_device_driver); |
1449 | #ifdef CONFIG_DMABOUNCE | ||
1450 | bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier); | ||
1451 | #endif | ||
1363 | bus_unregister(&sa1111_bus_type); | 1452 | bus_unregister(&sa1111_bus_type); |
1364 | } | 1453 | } |
1365 | 1454 | ||
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h index 92ed254c175b..7c2bbc7f0be1 100644 --- a/arch/arm/include/asm/hardware/sa1111.h +++ b/arch/arm/include/asm/hardware/sa1111.h | |||
@@ -132,34 +132,10 @@ | |||
132 | #define SKPCR_DCLKEN (1<<7) | 132 | #define SKPCR_DCLKEN (1<<7) |
133 | #define SKPCR_PWMCLKEN (1<<8) | 133 | #define SKPCR_PWMCLKEN (1<<8) |
134 | 134 | ||
135 | /* | 135 | /* USB Host controller */ |
136 | * USB Host controller | ||
137 | */ | ||
138 | #define SA1111_USB 0x0400 | 136 | #define SA1111_USB 0x0400 |
139 | 137 | ||
140 | /* | 138 | /* |
141 | * Offsets from SA1111_USB_BASE | ||
142 | */ | ||
143 | #define SA1111_USB_STATUS 0x0118 | ||
144 | #define SA1111_USB_RESET 0x011c | ||
145 | #define SA1111_USB_IRQTEST 0x0120 | ||
146 | |||
147 | #define USB_RESET_FORCEIFRESET (1 << 0) | ||
148 | #define USB_RESET_FORCEHCRESET (1 << 1) | ||
149 | #define USB_RESET_CLKGENRESET (1 << 2) | ||
150 | #define USB_RESET_SIMSCALEDOWN (1 << 3) | ||
151 | #define USB_RESET_USBINTTEST (1 << 4) | ||
152 | #define USB_RESET_SLEEPSTBYEN (1 << 5) | ||
153 | #define USB_RESET_PWRSENSELOW (1 << 6) | ||
154 | #define USB_RESET_PWRCTRLLOW (1 << 7) | ||
155 | |||
156 | #define USB_STATUS_IRQHCIRMTWKUP (1 << 7) | ||
157 | #define USB_STATUS_IRQHCIBUFFACC (1 << 8) | ||
158 | #define USB_STATUS_NIRQHCIM (1 << 9) | ||
159 | #define USB_STATUS_NHCIMFCLR (1 << 10) | ||
160 | #define USB_STATUS_USBPWRSENSE (1 << 11) | ||
161 | |||
162 | /* | ||
163 | * Serial Audio Controller | 139 | * Serial Audio Controller |
164 | * | 140 | * |
165 | * Registers | 141 | * Registers |
@@ -327,22 +303,6 @@ | |||
327 | * PC_SSR GPIO Block C Sleep State | 303 | * PC_SSR GPIO Block C Sleep State |
328 | */ | 304 | */ |
329 | 305 | ||
330 | #define _PA_DDR _SA1111( 0x1000 ) | ||
331 | #define _PA_DRR _SA1111( 0x1004 ) | ||
332 | #define _PA_DWR _SA1111( 0x1004 ) | ||
333 | #define _PA_SDR _SA1111( 0x1008 ) | ||
334 | #define _PA_SSR _SA1111( 0x100c ) | ||
335 | #define _PB_DDR _SA1111( 0x1010 ) | ||
336 | #define _PB_DRR _SA1111( 0x1014 ) | ||
337 | #define _PB_DWR _SA1111( 0x1014 ) | ||
338 | #define _PB_SDR _SA1111( 0x1018 ) | ||
339 | #define _PB_SSR _SA1111( 0x101c ) | ||
340 | #define _PC_DDR _SA1111( 0x1020 ) | ||
341 | #define _PC_DRR _SA1111( 0x1024 ) | ||
342 | #define _PC_DWR _SA1111( 0x1024 ) | ||
343 | #define _PC_SDR _SA1111( 0x1028 ) | ||
344 | #define _PC_SSR _SA1111( 0x102c ) | ||
345 | |||
346 | #define SA1111_GPIO 0x1000 | 306 | #define SA1111_GPIO 0x1000 |
347 | 307 | ||
348 | #define SA1111_GPIO_PADDR (0x000) | 308 | #define SA1111_GPIO_PADDR (0x000) |
@@ -425,106 +385,30 @@ | |||
425 | #define SA1111_WAKEPOL0 0x0034 | 385 | #define SA1111_WAKEPOL0 0x0034 |
426 | #define SA1111_WAKEPOL1 0x0038 | 386 | #define SA1111_WAKEPOL1 0x0038 |
427 | 387 | ||
428 | /* | 388 | /* PS/2 Trackpad and Mouse Interfaces */ |
429 | * PS/2 Trackpad and Mouse Interfaces | ||
430 | * | ||
431 | * Registers | ||
432 | * PS2CR Control Register | ||
433 | * PS2STAT Status Register | ||
434 | * PS2DATA Transmit/Receive Data register | ||
435 | * PS2CLKDIV Clock Division Register | ||
436 | * PS2PRECNT Clock Precount Register | ||
437 | * PS2TEST1 Test register 1 | ||
438 | * PS2TEST2 Test register 2 | ||
439 | * PS2TEST3 Test register 3 | ||
440 | * PS2TEST4 Test register 4 | ||
441 | */ | ||
442 | |||
443 | #define SA1111_KBD 0x0a00 | 389 | #define SA1111_KBD 0x0a00 |
444 | #define SA1111_MSE 0x0c00 | 390 | #define SA1111_MSE 0x0c00 |
445 | 391 | ||
446 | /* | 392 | /* PCMCIA Interface */ |
447 | * These are offsets from the above bases. | 393 | #define SA1111_PCMCIA 0x1600 |
448 | */ | ||
449 | #define SA1111_PS2CR 0x0000 | ||
450 | #define SA1111_PS2STAT 0x0004 | ||
451 | #define SA1111_PS2DATA 0x0008 | ||
452 | #define SA1111_PS2CLKDIV 0x000c | ||
453 | #define SA1111_PS2PRECNT 0x0010 | ||
454 | |||
455 | #define PS2CR_ENA 0x08 | ||
456 | #define PS2CR_FKD 0x02 | ||
457 | #define PS2CR_FKC 0x01 | ||
458 | |||
459 | #define PS2STAT_STP 0x0100 | ||
460 | #define PS2STAT_TXE 0x0080 | ||
461 | #define PS2STAT_TXB 0x0040 | ||
462 | #define PS2STAT_RXF 0x0020 | ||
463 | #define PS2STAT_RXB 0x0010 | ||
464 | #define PS2STAT_ENA 0x0008 | ||
465 | #define PS2STAT_RXP 0x0004 | ||
466 | #define PS2STAT_KBD 0x0002 | ||
467 | #define PS2STAT_KBC 0x0001 | ||
468 | 394 | ||
469 | /* | ||
470 | * PCMCIA Interface | ||
471 | * | ||
472 | * Registers | ||
473 | * PCSR Status Register | ||
474 | * PCCR Control Register | ||
475 | * PCSSR Sleep State Register | ||
476 | */ | ||
477 | |||
478 | #define SA1111_PCMCIA 0x1600 | ||
479 | |||
480 | /* | ||
481 | * These are offsets from the above base. | ||
482 | */ | ||
483 | #define SA1111_PCCR 0x0000 | ||
484 | #define SA1111_PCSSR 0x0004 | ||
485 | #define SA1111_PCSR 0x0008 | ||
486 | |||
487 | #define PCSR_S0_READY (1<<0) | ||
488 | #define PCSR_S1_READY (1<<1) | ||
489 | #define PCSR_S0_DETECT (1<<2) | ||
490 | #define PCSR_S1_DETECT (1<<3) | ||
491 | #define PCSR_S0_VS1 (1<<4) | ||
492 | #define PCSR_S0_VS2 (1<<5) | ||
493 | #define PCSR_S1_VS1 (1<<6) | ||
494 | #define PCSR_S1_VS2 (1<<7) | ||
495 | #define PCSR_S0_WP (1<<8) | ||
496 | #define PCSR_S1_WP (1<<9) | ||
497 | #define PCSR_S0_BVD1 (1<<10) | ||
498 | #define PCSR_S0_BVD2 (1<<11) | ||
499 | #define PCSR_S1_BVD1 (1<<12) | ||
500 | #define PCSR_S1_BVD2 (1<<13) | ||
501 | |||
502 | #define PCCR_S0_RST (1<<0) | ||
503 | #define PCCR_S1_RST (1<<1) | ||
504 | #define PCCR_S0_FLT (1<<2) | ||
505 | #define PCCR_S1_FLT (1<<3) | ||
506 | #define PCCR_S0_PWAITEN (1<<4) | ||
507 | #define PCCR_S1_PWAITEN (1<<5) | ||
508 | #define PCCR_S0_PSE (1<<6) | ||
509 | #define PCCR_S1_PSE (1<<7) | ||
510 | |||
511 | #define PCSSR_S0_SLEEP (1<<0) | ||
512 | #define PCSSR_S1_SLEEP (1<<1) | ||
513 | 395 | ||
514 | 396 | ||
515 | 397 | ||
516 | 398 | ||
517 | extern struct bus_type sa1111_bus_type; | 399 | extern struct bus_type sa1111_bus_type; |
518 | 400 | ||
519 | #define SA1111_DEVID_SBI 0 | 401 | #define SA1111_DEVID_SBI (1 << 0) |
520 | #define SA1111_DEVID_SK 1 | 402 | #define SA1111_DEVID_SK (1 << 1) |
521 | #define SA1111_DEVID_USB 2 | 403 | #define SA1111_DEVID_USB (1 << 2) |
522 | #define SA1111_DEVID_SAC 3 | 404 | #define SA1111_DEVID_SAC (1 << 3) |
523 | #define SA1111_DEVID_SSP 4 | 405 | #define SA1111_DEVID_SSP (1 << 4) |
524 | #define SA1111_DEVID_PS2 5 | 406 | #define SA1111_DEVID_PS2 (3 << 5) |
525 | #define SA1111_DEVID_GPIO 6 | 407 | #define SA1111_DEVID_PS2_KBD (1 << 5) |
526 | #define SA1111_DEVID_INT 7 | 408 | #define SA1111_DEVID_PS2_MSE (1 << 6) |
527 | #define SA1111_DEVID_PCMCIA 8 | 409 | #define SA1111_DEVID_GPIO (1 << 7) |
410 | #define SA1111_DEVID_INT (1 << 8) | ||
411 | #define SA1111_DEVID_PCMCIA (1 << 9) | ||
528 | 412 | ||
529 | struct sa1111_dev { | 413 | struct sa1111_dev { |
530 | struct device dev; | 414 | struct device dev; |
@@ -548,6 +432,7 @@ struct sa1111_driver { | |||
548 | int (*remove)(struct sa1111_dev *); | 432 | int (*remove)(struct sa1111_dev *); |
549 | int (*suspend)(struct sa1111_dev *, pm_message_t); | 433 | int (*suspend)(struct sa1111_dev *, pm_message_t); |
550 | int (*resume)(struct sa1111_dev *); | 434 | int (*resume)(struct sa1111_dev *); |
435 | void (*shutdown)(struct sa1111_dev *); | ||
551 | }; | 436 | }; |
552 | 437 | ||
553 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) | 438 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) |
@@ -555,9 +440,10 @@ struct sa1111_driver { | |||
555 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) | 440 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) |
556 | 441 | ||
557 | /* | 442 | /* |
558 | * These frob the SKPCR register. | 443 | * These frob the SKPCR register, and call platform specific |
444 | * enable/disable functions. | ||
559 | */ | 445 | */ |
560 | void sa1111_enable_device(struct sa1111_dev *); | 446 | int sa1111_enable_device(struct sa1111_dev *); |
561 | void sa1111_disable_device(struct sa1111_dev *); | 447 | void sa1111_disable_device(struct sa1111_dev *); |
562 | 448 | ||
563 | unsigned int sa1111_pll_clock(struct sa1111_dev *); | 449 | unsigned int sa1111_pll_clock(struct sa1111_dev *); |
@@ -580,6 +466,10 @@ void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned i | |||
580 | 466 | ||
581 | struct sa1111_platform_data { | 467 | struct sa1111_platform_data { |
582 | int irq_base; /* base for cascaded on-chip IRQs */ | 468 | int irq_base; /* base for cascaded on-chip IRQs */ |
469 | unsigned disable_devs; | ||
470 | void *data; | ||
471 | int (*enable)(void *, unsigned); | ||
472 | void (*disable)(void *, unsigned); | ||
583 | }; | 473 | }; |
584 | 474 | ||
585 | #endif /* _ASM_ARCH_SA1111 */ | 475 | #endif /* _ASM_ARCH_SA1111 */ |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 6ebd276aebeb..6bb3f47b1f14 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
@@ -223,6 +223,7 @@ static struct resource sa1111_resources[] = { | |||
223 | 223 | ||
224 | static struct sa1111_platform_data sa1111_info = { | 224 | static struct sa1111_platform_data sa1111_info = { |
225 | .irq_base = LUBBOCK_SA1111_IRQ_BASE, | 225 | .irq_base = LUBBOCK_SA1111_IRQ_BASE, |
226 | .disable_devs = SA1111_DEVID_SAC, | ||
226 | }; | 227 | }; |
227 | 228 | ||
228 | static struct platform_device sa1111_device = { | 229 | static struct platform_device sa1111_device = { |
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index ed7408d3216c..60b97ec01676 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile | |||
@@ -3,7 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o | 6 | obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o |
7 | obj-m := | 7 | obj-m := |
8 | obj-n := | 8 | obj-n := |
9 | obj- := | 9 | obj- := |
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index 65b0a9a3fb9c..c3f5064df4bf 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c | |||
@@ -42,13 +42,13 @@ | |||
42 | #include "generic.h" | 42 | #include "generic.h" |
43 | 43 | ||
44 | #define ASSABET_BCR_DB1110 \ | 44 | #define ASSABET_BCR_DB1110 \ |
45 | (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ | 45 | (ASSABET_BCR_SPK_OFF | \ |
46 | ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ | 46 | ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ |
47 | ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ | 47 | ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ |
48 | ASSABET_BCR_IRDA_MD0) | 48 | ASSABET_BCR_IRDA_MD0) |
49 | 49 | ||
50 | #define ASSABET_BCR_DB1111 \ | 50 | #define ASSABET_BCR_DB1111 \ |
51 | (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ | 51 | (ASSABET_BCR_SPK_OFF | \ |
52 | ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ | 52 | ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ |
53 | ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ | 53 | ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ |
54 | ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ | 54 | ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ |
@@ -127,15 +127,8 @@ static struct flash_platform_data assabet_flash_data = { | |||
127 | }; | 127 | }; |
128 | 128 | ||
129 | static struct resource assabet_flash_resources[] = { | 129 | static struct resource assabet_flash_resources[] = { |
130 | { | 130 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), |
131 | .start = SA1100_CS0_PHYS, | 131 | DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), |
132 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
133 | .flags = IORESOURCE_MEM, | ||
134 | }, { | ||
135 | .start = SA1100_CS1_PHYS, | ||
136 | .end = SA1100_CS1_PHYS + SZ_32M - 1, | ||
137 | .flags = IORESOURCE_MEM, | ||
138 | } | ||
139 | }; | 132 | }; |
140 | 133 | ||
141 | 134 | ||
@@ -272,13 +265,22 @@ static struct sa1100fb_mach_info pal_info = { | |||
272 | }; | 265 | }; |
273 | #endif | 266 | #endif |
274 | 267 | ||
268 | #ifdef CONFIG_ASSABET_NEPONSET | ||
269 | static struct resource neponset_resources[] = { | ||
270 | DEFINE_RES_MEM(0x10000000, 0x08000000), | ||
271 | DEFINE_RES_MEM(0x18000000, 0x04000000), | ||
272 | DEFINE_RES_MEM(0x40000000, SZ_8K), | ||
273 | DEFINE_RES_IRQ(IRQ_GPIO25), | ||
274 | }; | ||
275 | #endif | ||
276 | |||
275 | static void __init assabet_init(void) | 277 | static void __init assabet_init(void) |
276 | { | 278 | { |
277 | /* | 279 | /* |
278 | * Ensure that the power supply is in "high power" mode. | 280 | * Ensure that the power supply is in "high power" mode. |
279 | */ | 281 | */ |
280 | GPDR |= GPIO_GPIO16; | ||
281 | GPSR = GPIO_GPIO16; | 282 | GPSR = GPIO_GPIO16; |
283 | GPDR |= GPIO_GPIO16; | ||
282 | 284 | ||
283 | /* | 285 | /* |
284 | * Ensure that these pins are set as outputs and are driving | 286 | * Ensure that these pins are set as outputs and are driving |
@@ -286,8 +288,16 @@ static void __init assabet_init(void) | |||
286 | * the WS latch in the CPLD, and we don't float causing | 288 | * the WS latch in the CPLD, and we don't float causing |
287 | * excessive power drain. --rmk | 289 | * excessive power drain. --rmk |
288 | */ | 290 | */ |
289 | GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; | ||
290 | GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; | 291 | GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; |
292 | GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; | ||
293 | |||
294 | /* | ||
295 | * Also set GPIO27 as an output; this is used to clock UART3 | ||
296 | * via the FPGA and as otherwise has no pullups or pulldowns, | ||
297 | * so stop it floating. | ||
298 | */ | ||
299 | GPCR = GPIO_GPIO27; | ||
300 | GPDR |= GPIO_GPIO27; | ||
291 | 301 | ||
292 | /* | 302 | /* |
293 | * Set up registers for sleep mode. | 303 | * Set up registers for sleep mode. |
@@ -311,6 +321,9 @@ static void __init assabet_init(void) | |||
311 | #ifndef CONFIG_ASSABET_NEPONSET | 321 | #ifndef CONFIG_ASSABET_NEPONSET |
312 | printk( "Warning: Neponset detected but full support " | 322 | printk( "Warning: Neponset detected but full support " |
313 | "hasn't been configured in the kernel\n" ); | 323 | "hasn't been configured in the kernel\n" ); |
324 | #else | ||
325 | platform_device_register_simple("neponset", 0, | ||
326 | neponset_resources, ARRAY_SIZE(neponset_resources)); | ||
314 | #endif | 327 | #endif |
315 | } | 328 | } |
316 | 329 | ||
@@ -482,21 +495,8 @@ static void __init assabet_map_io(void) | |||
482 | */ | 495 | */ |
483 | Ser1SDCR0 |= SDCR0_SUS; | 496 | Ser1SDCR0 |= SDCR0_SUS; |
484 | 497 | ||
485 | if (machine_has_neponset()) { | 498 | if (!machine_has_neponset()) |
486 | #ifdef CONFIG_ASSABET_NEPONSET | ||
487 | extern void neponset_map_io(void); | ||
488 | |||
489 | /* | ||
490 | * We map Neponset registers even if it isn't present since | ||
491 | * many drivers will try to probe their stuff (and fail). | ||
492 | * This is still more friendly than a kernel paging request | ||
493 | * crash. | ||
494 | */ | ||
495 | neponset_map_io(); | ||
496 | #endif | ||
497 | } else { | ||
498 | sa1100_register_uart_fns(&assabet_port_fns); | 499 | sa1100_register_uart_fns(&assabet_port_fns); |
499 | } | ||
500 | 500 | ||
501 | /* | 501 | /* |
502 | * When Neponset is attached, the first UART should be | 502 | * When Neponset is attached, the first UART should be |
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index b07a2c024cb7..5839c9d8bb92 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c | |||
@@ -39,20 +39,28 @@ | |||
39 | #include "generic.h" | 39 | #include "generic.h" |
40 | 40 | ||
41 | static struct resource sa1111_resources[] = { | 41 | static struct resource sa1111_resources[] = { |
42 | [0] = { | 42 | [0] = DEFINE_RES_MEM(BADGE4_SA1111_BASE, 0x2000), |
43 | .start = BADGE4_SA1111_BASE, | 43 | [1] = DEFINE_RES_IRQ(BADGE4_IRQ_GPIO_SA1111), |
44 | .end = BADGE4_SA1111_BASE + 0x00001fff, | ||
45 | .flags = IORESOURCE_MEM, | ||
46 | }, | ||
47 | [1] = { | ||
48 | .start = BADGE4_IRQ_GPIO_SA1111, | ||
49 | .end = BADGE4_IRQ_GPIO_SA1111, | ||
50 | .flags = IORESOURCE_IRQ, | ||
51 | }, | ||
52 | }; | 44 | }; |
53 | 45 | ||
46 | static int badge4_sa1111_enable(void *data, unsigned devid) | ||
47 | { | ||
48 | if (devid == SA1111_DEVID_USB) | ||
49 | badge4_set_5V(BADGE4_5V_USB, 1); | ||
50 | return 0; | ||
51 | } | ||
52 | |||
53 | static void badge4_sa1111_disable(void *data, unsigned devid) | ||
54 | { | ||
55 | if (devid == SA1111_DEVID_USB) | ||
56 | badge4_set_5V(BADGE4_5V_USB, 0); | ||
57 | } | ||
58 | |||
54 | static struct sa1111_platform_data sa1111_info = { | 59 | static struct sa1111_platform_data sa1111_info = { |
55 | .irq_base = IRQ_BOARD_END, | 60 | .irq_base = IRQ_BOARD_END, |
61 | .disable_devs = SA1111_DEVID_PS2_MSE, | ||
62 | .enable = badge4_sa1111_enable, | ||
63 | .disable = badge4_sa1111_disable, | ||
56 | }; | 64 | }; |
57 | 65 | ||
58 | static u64 sa1111_dmamask = 0xffffffffUL; | 66 | static u64 sa1111_dmamask = 0xffffffffUL; |
@@ -121,11 +129,8 @@ static struct flash_platform_data badge4_flash_data = { | |||
121 | .nr_parts = ARRAY_SIZE(badge4_partitions), | 129 | .nr_parts = ARRAY_SIZE(badge4_partitions), |
122 | }; | 130 | }; |
123 | 131 | ||
124 | static struct resource badge4_flash_resource = { | 132 | static struct resource badge4_flash_resource = |
125 | .start = SA1100_CS0_PHYS, | 133 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_64M); |
126 | .end = SA1100_CS0_PHYS + SZ_64M - 1, | ||
127 | .flags = IORESOURCE_MEM, | ||
128 | }; | ||
129 | 134 | ||
130 | static int five_v_on __initdata = 0; | 135 | static int five_v_on __initdata = 0; |
131 | 136 | ||
@@ -269,11 +274,6 @@ static struct map_desc badge4_io_desc[] __initdata = { | |||
269 | .pfn = __phys_to_pfn(0x10000000), | 274 | .pfn = __phys_to_pfn(0x10000000), |
270 | .length = 0x00100000, | 275 | .length = 0x00100000, |
271 | .type = MT_DEVICE | 276 | .type = MT_DEVICE |
272 | }, { /* SA-1111 */ | ||
273 | .virtual = 0xf4000000, | ||
274 | .pfn = __phys_to_pfn(0x48000000), | ||
275 | .length = 0x00100000, | ||
276 | .type = MT_DEVICE | ||
277 | } | 277 | } |
278 | }; | 278 | }; |
279 | 279 | ||
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 11bb6d0b9be3..c2f9ba3a9578 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c | |||
@@ -33,11 +33,7 @@ | |||
33 | #include "generic.h" | 33 | #include "generic.h" |
34 | 34 | ||
35 | static struct resource cerfuart2_resources[] = { | 35 | static struct resource cerfuart2_resources[] = { |
36 | [0] = { | 36 | [0] = DEFINE_RES_MEM(0x80030000, SZ_64K), |
37 | .start = 0x80030000, | ||
38 | .end = 0x8003ffff, | ||
39 | .flags = IORESOURCE_MEM, | ||
40 | }, | ||
41 | }; | 37 | }; |
42 | 38 | ||
43 | static struct platform_device cerfuart2_device = { | 39 | static struct platform_device cerfuart2_device = { |
@@ -87,11 +83,8 @@ static struct flash_platform_data cerf_flash_data = { | |||
87 | .nr_parts = ARRAY_SIZE(cerf_partitions), | 83 | .nr_parts = ARRAY_SIZE(cerf_partitions), |
88 | }; | 84 | }; |
89 | 85 | ||
90 | static struct resource cerf_flash_resource = { | 86 | static struct resource cerf_flash_resource = |
91 | .start = SA1100_CS0_PHYS, | 87 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); |
92 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
93 | .flags = IORESOURCE_MEM, | ||
94 | }; | ||
95 | 88 | ||
96 | static void __init cerf_init_irq(void) | 89 | static void __init cerf_init_irq(void) |
97 | { | 90 | { |
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 70f6cdc9e63d..841041e11815 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c | |||
@@ -50,11 +50,7 @@ | |||
50 | #include "generic.h" | 50 | #include "generic.h" |
51 | 51 | ||
52 | static struct resource collie_scoop_resources[] = { | 52 | static struct resource collie_scoop_resources[] = { |
53 | [0] = { | 53 | [0] = DEFINE_RES_MEM(0x40800000, SZ_4K), |
54 | .start = 0x40800000, | ||
55 | .end = 0x40800fff, | ||
56 | .flags = IORESOURCE_MEM, | ||
57 | }, | ||
58 | }; | 54 | }; |
59 | 55 | ||
60 | static struct scoop_config collie_scoop_setup = { | 56 | static struct scoop_config collie_scoop_setup = { |
@@ -223,16 +219,8 @@ device_initcall(collie_uart_init); | |||
223 | 219 | ||
224 | 220 | ||
225 | static struct resource locomo_resources[] = { | 221 | static struct resource locomo_resources[] = { |
226 | [0] = { | 222 | [0] = DEFINE_RES_MEM(0x40000000, SZ_8K), |
227 | .start = 0x40000000, | 223 | [1] = DEFINE_RES_IRQ(IRQ_GPIO25), |
228 | .end = 0x40001fff, | ||
229 | .flags = IORESOURCE_MEM, | ||
230 | }, | ||
231 | [1] = { | ||
232 | .start = IRQ_GPIO25, | ||
233 | .end = IRQ_GPIO25, | ||
234 | .flags = IORESOURCE_IRQ, | ||
235 | }, | ||
236 | }; | 224 | }; |
237 | 225 | ||
238 | static struct locomo_platform_data locomo_info = { | 226 | static struct locomo_platform_data locomo_info = { |
@@ -305,11 +293,7 @@ static struct flash_platform_data collie_flash_data = { | |||
305 | }; | 293 | }; |
306 | 294 | ||
307 | static struct resource collie_flash_resources[] = { | 295 | static struct resource collie_flash_resources[] = { |
308 | { | 296 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), |
309 | .start = SA1100_CS0_PHYS, | ||
310 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
311 | .flags = IORESOURCE_MEM, | ||
312 | } | ||
313 | }; | 297 | }; |
314 | 298 | ||
315 | static struct sa1100fb_mach_info collie_lcd_info = { | 299 | static struct sa1100fb_mach_info collie_lcd_info = { |
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c deleted file mode 100644 index ad660350c296..000000000000 --- a/arch/arm/mach-sa1100/dma.c +++ /dev/null | |||
@@ -1,348 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-sa1100/dma.c | ||
3 | * | ||
4 | * Support functions for the SA11x0 internal DMA channels. | ||
5 | * | ||
6 | * Copyright (C) 2000, 2001 by Nicolas Pitre | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/spinlock.h> | ||
17 | #include <linux/errno.h> | ||
18 | |||
19 | #include <asm/system.h> | ||
20 | #include <asm/irq.h> | ||
21 | #include <mach/hardware.h> | ||
22 | #include <mach/dma.h> | ||
23 | |||
24 | |||
25 | #undef DEBUG | ||
26 | #ifdef DEBUG | ||
27 | #define DPRINTK( s, arg... ) printk( "dma<%p>: " s, regs , ##arg ) | ||
28 | #else | ||
29 | #define DPRINTK( x... ) | ||
30 | #endif | ||
31 | |||
32 | |||
33 | typedef struct { | ||
34 | const char *device_id; /* device name */ | ||
35 | u_long device; /* this channel device, 0 if unused*/ | ||
36 | dma_callback_t callback; /* to call when DMA completes */ | ||
37 | void *data; /* ... with private data ptr */ | ||
38 | } sa1100_dma_t; | ||
39 | |||
40 | static sa1100_dma_t dma_chan[SA1100_DMA_CHANNELS]; | ||
41 | |||
42 | static DEFINE_SPINLOCK(dma_list_lock); | ||
43 | |||
44 | |||
45 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) | ||
46 | { | ||
47 | dma_regs_t *dma_regs = dev_id; | ||
48 | sa1100_dma_t *dma = dma_chan + (((u_int)dma_regs >> 5) & 7); | ||
49 | int status = dma_regs->RdDCSR; | ||
50 | |||
51 | if (status & (DCSR_ERROR)) { | ||
52 | printk(KERN_CRIT "DMA on \"%s\" caused an error\n", dma->device_id); | ||
53 | dma_regs->ClrDCSR = DCSR_ERROR; | ||
54 | } | ||
55 | |||
56 | dma_regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB); | ||
57 | if (dma->callback) { | ||
58 | if (status & DCSR_DONEA) | ||
59 | dma->callback(dma->data); | ||
60 | if (status & DCSR_DONEB) | ||
61 | dma->callback(dma->data); | ||
62 | } | ||
63 | return IRQ_HANDLED; | ||
64 | } | ||
65 | |||
66 | |||
67 | /** | ||
68 | * sa1100_request_dma - allocate one of the SA11x0's DMA channels | ||
69 | * @device: The SA11x0 peripheral targeted by this request | ||
70 | * @device_id: An ascii name for the claiming device | ||
71 | * @callback: Function to be called when the DMA completes | ||
72 | * @data: A cookie passed back to the callback function | ||
73 | * @dma_regs: Pointer to the location of the allocated channel's identifier | ||
74 | * | ||
75 | * This function will search for a free DMA channel and returns the | ||
76 | * address of the hardware registers for that channel as the channel | ||
77 | * identifier. This identifier is written to the location pointed by | ||
78 | * @dma_regs. The list of possible values for @device are listed into | ||
79 | * arch/arm/mach-sa1100/include/mach/dma.h as a dma_device_t enum. | ||
80 | * | ||
81 | * Note that reading from a port and writing to the same port are | ||
82 | * actually considered as two different streams requiring separate | ||
83 | * DMA registrations. | ||
84 | * | ||
85 | * The @callback function is called from interrupt context when one | ||
86 | * of the two possible DMA buffers in flight has terminated. That | ||
87 | * function has to be small and efficient while posponing more complex | ||
88 | * processing to a lower priority execution context. | ||
89 | * | ||
90 | * If no channels are available, or if the desired @device is already in | ||
91 | * use by another DMA channel, then an error code is returned. This | ||
92 | * function must be called before any other DMA calls. | ||
93 | **/ | ||
94 | |||
95 | int sa1100_request_dma (dma_device_t device, const char *device_id, | ||
96 | dma_callback_t callback, void *data, | ||
97 | dma_regs_t **dma_regs) | ||
98 | { | ||
99 | sa1100_dma_t *dma = NULL; | ||
100 | dma_regs_t *regs; | ||
101 | int i, err; | ||
102 | |||
103 | *dma_regs = NULL; | ||
104 | |||
105 | err = 0; | ||
106 | spin_lock(&dma_list_lock); | ||
107 | for (i = 0; i < SA1100_DMA_CHANNELS; i++) { | ||
108 | if (dma_chan[i].device == device) { | ||
109 | err = -EBUSY; | ||
110 | break; | ||
111 | } else if (!dma_chan[i].device && !dma) { | ||
112 | dma = &dma_chan[i]; | ||
113 | } | ||
114 | } | ||
115 | if (!err) { | ||
116 | if (dma) | ||
117 | dma->device = device; | ||
118 | else | ||
119 | err = -ENOSR; | ||
120 | } | ||
121 | spin_unlock(&dma_list_lock); | ||
122 | if (err) | ||
123 | return err; | ||
124 | |||
125 | i = dma - dma_chan; | ||
126 | regs = (dma_regs_t *)&DDAR(i); | ||
127 | err = request_irq(IRQ_DMA0 + i, dma_irq_handler, IRQF_DISABLED, | ||
128 | device_id, regs); | ||
129 | if (err) { | ||
130 | printk(KERN_ERR | ||
131 | "%s: unable to request IRQ %d for %s\n", | ||
132 | __func__, IRQ_DMA0 + i, device_id); | ||
133 | dma->device = 0; | ||
134 | return err; | ||
135 | } | ||
136 | |||
137 | *dma_regs = regs; | ||
138 | dma->device_id = device_id; | ||
139 | dma->callback = callback; | ||
140 | dma->data = data; | ||
141 | |||
142 | regs->ClrDCSR = | ||
143 | (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | | ||
144 | DCSR_IE | DCSR_ERROR | DCSR_RUN); | ||
145 | regs->DDAR = device; | ||
146 | |||
147 | return 0; | ||
148 | } | ||
149 | |||
150 | |||
151 | /** | ||
152 | * sa1100_free_dma - free a SA11x0 DMA channel | ||
153 | * @regs: identifier for the channel to free | ||
154 | * | ||
155 | * This clears all activities on a given DMA channel and releases it | ||
156 | * for future requests. The @regs identifier is provided by a | ||
157 | * successful call to sa1100_request_dma(). | ||
158 | **/ | ||
159 | |||
160 | void sa1100_free_dma(dma_regs_t *regs) | ||
161 | { | ||
162 | int i; | ||
163 | |||
164 | for (i = 0; i < SA1100_DMA_CHANNELS; i++) | ||
165 | if (regs == (dma_regs_t *)&DDAR(i)) | ||
166 | break; | ||
167 | if (i >= SA1100_DMA_CHANNELS) { | ||
168 | printk(KERN_ERR "%s: bad DMA identifier\n", __func__); | ||
169 | return; | ||
170 | } | ||
171 | |||
172 | if (!dma_chan[i].device) { | ||
173 | printk(KERN_ERR "%s: Trying to free free DMA\n", __func__); | ||
174 | return; | ||
175 | } | ||
176 | |||
177 | regs->ClrDCSR = | ||
178 | (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | | ||
179 | DCSR_IE | DCSR_ERROR | DCSR_RUN); | ||
180 | free_irq(IRQ_DMA0 + i, regs); | ||
181 | dma_chan[i].device = 0; | ||
182 | } | ||
183 | |||
184 | |||
185 | /** | ||
186 | * sa1100_start_dma - submit a data buffer for DMA | ||
187 | * @regs: identifier for the channel to use | ||
188 | * @dma_ptr: buffer physical (or bus) start address | ||
189 | * @size: buffer size | ||
190 | * | ||
191 | * This function hands the given data buffer to the hardware for DMA | ||
192 | * access. If another buffer is already in flight then this buffer | ||
193 | * will be queued so the DMA engine will switch to it automatically | ||
194 | * when the previous one is done. The DMA engine is actually toggling | ||
195 | * between two buffers so at most 2 successful calls can be made before | ||
196 | * one of them terminates and the callback function is called. | ||
197 | * | ||
198 | * The @regs identifier is provided by a successful call to | ||
199 | * sa1100_request_dma(). | ||
200 | * | ||
201 | * The @size must not be larger than %MAX_DMA_SIZE. If a given buffer | ||
202 | * is larger than that then it's the caller's responsibility to split | ||
203 | * it into smaller chunks and submit them separately. If this is the | ||
204 | * case then a @size of %CUT_DMA_SIZE is recommended to avoid ending | ||
205 | * up with too small chunks. The callback function can be used to chain | ||
206 | * submissions of buffer chunks. | ||
207 | * | ||
208 | * Error return values: | ||
209 | * %-EOVERFLOW: Given buffer size is too big. | ||
210 | * %-EBUSY: Both DMA buffers are already in use. | ||
211 | * %-EAGAIN: Both buffers were busy but one of them just completed | ||
212 | * but the interrupt handler has to execute first. | ||
213 | * | ||
214 | * This function returs 0 on success. | ||
215 | **/ | ||
216 | |||
217 | int sa1100_start_dma(dma_regs_t *regs, dma_addr_t dma_ptr, u_int size) | ||
218 | { | ||
219 | unsigned long flags; | ||
220 | u_long status; | ||
221 | int ret; | ||
222 | |||
223 | if (dma_ptr & 3) | ||
224 | printk(KERN_WARNING "DMA: unaligned start address (0x%08lx)\n", | ||
225 | (unsigned long)dma_ptr); | ||
226 | |||
227 | if (size > MAX_DMA_SIZE) | ||
228 | return -EOVERFLOW; | ||
229 | |||
230 | local_irq_save(flags); | ||
231 | status = regs->RdDCSR; | ||
232 | |||
233 | /* If both DMA buffers are started, there's nothing else we can do. */ | ||
234 | if ((status & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB)) { | ||
235 | DPRINTK("start: st %#x busy\n", status); | ||
236 | ret = -EBUSY; | ||
237 | goto out; | ||
238 | } | ||
239 | |||
240 | if (((status & DCSR_BIU) && (status & DCSR_STRTB)) || | ||
241 | (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) { | ||
242 | if (status & DCSR_DONEA) { | ||
243 | /* give a chance for the interrupt to be processed */ | ||
244 | ret = -EAGAIN; | ||
245 | goto out; | ||
246 | } | ||
247 | regs->DBSA = dma_ptr; | ||
248 | regs->DBTA = size; | ||
249 | regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN; | ||
250 | DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size); | ||
251 | } else { | ||
252 | if (status & DCSR_DONEB) { | ||
253 | /* give a chance for the interrupt to be processed */ | ||
254 | ret = -EAGAIN; | ||
255 | goto out; | ||
256 | } | ||
257 | regs->DBSB = dma_ptr; | ||
258 | regs->DBTB = size; | ||
259 | regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN; | ||
260 | DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size); | ||
261 | } | ||
262 | ret = 0; | ||
263 | |||
264 | out: | ||
265 | local_irq_restore(flags); | ||
266 | return ret; | ||
267 | } | ||
268 | |||
269 | |||
270 | /** | ||
271 | * sa1100_get_dma_pos - return current DMA position | ||
272 | * @regs: identifier for the channel to use | ||
273 | * | ||
274 | * This function returns the current physical (or bus) address for the | ||
275 | * given DMA channel. If the channel is running i.e. not in a stopped | ||
276 | * state then the caller must disable interrupts prior calling this | ||
277 | * function and process the returned value before re-enabling them to | ||
278 | * prevent races with the completion interrupt handler and the callback | ||
279 | * function. The validation of the returned value is the caller's | ||
280 | * responsibility as well -- the hardware seems to return out of range | ||
281 | * values when the DMA engine completes a buffer. | ||
282 | * | ||
283 | * The @regs identifier is provided by a successful call to | ||
284 | * sa1100_request_dma(). | ||
285 | **/ | ||
286 | |||
287 | dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs) | ||
288 | { | ||
289 | int status; | ||
290 | |||
291 | /* | ||
292 | * We must determine whether buffer A or B is active. | ||
293 | * Two possibilities: either we are in the middle of | ||
294 | * a buffer, or the DMA controller just switched to the | ||
295 | * next toggle but the interrupt hasn't been serviced yet. | ||
296 | * The former case is straight forward. In the later case, | ||
297 | * we'll do like if DMA is just at the end of the previous | ||
298 | * toggle since all registers haven't been reset yet. | ||
299 | * This goes around the edge case and since we're always | ||
300 | * a little behind anyways it shouldn't make a big difference. | ||
301 | * If DMA has been stopped prior calling this then the | ||
302 | * position is exact. | ||
303 | */ | ||
304 | status = regs->RdDCSR; | ||
305 | if ((!(status & DCSR_BIU) && (status & DCSR_STRTA)) || | ||
306 | ( (status & DCSR_BIU) && !(status & DCSR_STRTB))) | ||
307 | return regs->DBSA; | ||
308 | else | ||
309 | return regs->DBSB; | ||
310 | } | ||
311 | |||
312 | |||
313 | /** | ||
314 | * sa1100_reset_dma - reset a DMA channel | ||
315 | * @regs: identifier for the channel to use | ||
316 | * | ||
317 | * This function resets and reconfigure the given DMA channel. This is | ||
318 | * particularly useful after a sleep/wakeup event. | ||
319 | * | ||
320 | * The @regs identifier is provided by a successful call to | ||
321 | * sa1100_request_dma(). | ||
322 | **/ | ||
323 | |||
324 | void sa1100_reset_dma(dma_regs_t *regs) | ||
325 | { | ||
326 | int i; | ||
327 | |||
328 | for (i = 0; i < SA1100_DMA_CHANNELS; i++) | ||
329 | if (regs == (dma_regs_t *)&DDAR(i)) | ||
330 | break; | ||
331 | if (i >= SA1100_DMA_CHANNELS) { | ||
332 | printk(KERN_ERR "%s: bad DMA identifier\n", __func__); | ||
333 | return; | ||
334 | } | ||
335 | |||
336 | regs->ClrDCSR = | ||
337 | (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | | ||
338 | DCSR_IE | DCSR_ERROR | DCSR_RUN); | ||
339 | regs->DDAR = dma_chan[i].device; | ||
340 | } | ||
341 | |||
342 | |||
343 | EXPORT_SYMBOL(sa1100_request_dma); | ||
344 | EXPORT_SYMBOL(sa1100_free_dma); | ||
345 | EXPORT_SYMBOL(sa1100_start_dma); | ||
346 | EXPORT_SYMBOL(sa1100_get_dma_pos); | ||
347 | EXPORT_SYMBOL(sa1100_reset_dma); | ||
348 | |||
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 9cb4062b1e9b..0296d69622ac 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/delay.h> | 16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | ||
17 | #include <linux/pm.h> | 18 | #include <linux/pm.h> |
18 | #include <linux/cpufreq.h> | 19 | #include <linux/cpufreq.h> |
19 | #include <linux/ioport.h> | 20 | #include <linux/ioport.h> |
@@ -151,16 +152,8 @@ static void sa11x0_register_device(struct platform_device *dev, void *data) | |||
151 | 152 | ||
152 | 153 | ||
153 | static struct resource sa11x0udc_resources[] = { | 154 | static struct resource sa11x0udc_resources[] = { |
154 | [0] = { | 155 | [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K), |
155 | .start = __PREG(Ser0UDCCR), | 156 | [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC), |
156 | .end = __PREG(Ser0UDCCR) + 0xffff, | ||
157 | .flags = IORESOURCE_MEM, | ||
158 | }, | ||
159 | [1] = { | ||
160 | .start = IRQ_Ser0UDC, | ||
161 | .end = IRQ_Ser0UDC, | ||
162 | .flags = IORESOURCE_IRQ, | ||
163 | }, | ||
164 | }; | 157 | }; |
165 | 158 | ||
166 | static u64 sa11x0udc_dma_mask = 0xffffffffUL; | 159 | static u64 sa11x0udc_dma_mask = 0xffffffffUL; |
@@ -177,16 +170,8 @@ static struct platform_device sa11x0udc_device = { | |||
177 | }; | 170 | }; |
178 | 171 | ||
179 | static struct resource sa11x0uart1_resources[] = { | 172 | static struct resource sa11x0uart1_resources[] = { |
180 | [0] = { | 173 | [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K), |
181 | .start = __PREG(Ser1UTCR0), | 174 | [1] = DEFINE_RES_IRQ(IRQ_Ser1UART), |
182 | .end = __PREG(Ser1UTCR0) + 0xffff, | ||
183 | .flags = IORESOURCE_MEM, | ||
184 | }, | ||
185 | [1] = { | ||
186 | .start = IRQ_Ser1UART, | ||
187 | .end = IRQ_Ser1UART, | ||
188 | .flags = IORESOURCE_IRQ, | ||
189 | }, | ||
190 | }; | 175 | }; |
191 | 176 | ||
192 | static struct platform_device sa11x0uart1_device = { | 177 | static struct platform_device sa11x0uart1_device = { |
@@ -197,16 +182,8 @@ static struct platform_device sa11x0uart1_device = { | |||
197 | }; | 182 | }; |
198 | 183 | ||
199 | static struct resource sa11x0uart3_resources[] = { | 184 | static struct resource sa11x0uart3_resources[] = { |
200 | [0] = { | 185 | [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K), |
201 | .start = __PREG(Ser3UTCR0), | 186 | [1] = DEFINE_RES_IRQ(IRQ_Ser3UART), |
202 | .end = __PREG(Ser3UTCR0) + 0xffff, | ||
203 | .flags = IORESOURCE_MEM, | ||
204 | }, | ||
205 | [1] = { | ||
206 | .start = IRQ_Ser3UART, | ||
207 | .end = IRQ_Ser3UART, | ||
208 | .flags = IORESOURCE_IRQ, | ||
209 | }, | ||
210 | }; | 187 | }; |
211 | 188 | ||
212 | static struct platform_device sa11x0uart3_device = { | 189 | static struct platform_device sa11x0uart3_device = { |
@@ -217,16 +194,8 @@ static struct platform_device sa11x0uart3_device = { | |||
217 | }; | 194 | }; |
218 | 195 | ||
219 | static struct resource sa11x0mcp_resources[] = { | 196 | static struct resource sa11x0mcp_resources[] = { |
220 | [0] = { | 197 | [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K), |
221 | .start = __PREG(Ser4MCCR0), | 198 | [1] = DEFINE_RES_IRQ(IRQ_Ser4MCP), |
222 | .end = __PREG(Ser4MCCR0) + 0xffff, | ||
223 | .flags = IORESOURCE_MEM, | ||
224 | }, | ||
225 | [1] = { | ||
226 | .start = IRQ_Ser4MCP, | ||
227 | .end = IRQ_Ser4MCP, | ||
228 | .flags = IORESOURCE_IRQ, | ||
229 | }, | ||
230 | }; | 199 | }; |
231 | 200 | ||
232 | static u64 sa11x0mcp_dma_mask = 0xffffffffUL; | 201 | static u64 sa11x0mcp_dma_mask = 0xffffffffUL; |
@@ -248,16 +217,8 @@ void sa11x0_register_mcp(struct mcp_plat_data *data) | |||
248 | } | 217 | } |
249 | 218 | ||
250 | static struct resource sa11x0ssp_resources[] = { | 219 | static struct resource sa11x0ssp_resources[] = { |
251 | [0] = { | 220 | [0] = DEFINE_RES_MEM(0x80070000, SZ_64K), |
252 | .start = 0x80070000, | 221 | [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP), |
253 | .end = 0x8007ffff, | ||
254 | .flags = IORESOURCE_MEM, | ||
255 | }, | ||
256 | [1] = { | ||
257 | .start = IRQ_Ser4SSP, | ||
258 | .end = IRQ_Ser4SSP, | ||
259 | .flags = IORESOURCE_IRQ, | ||
260 | }, | ||
261 | }; | 222 | }; |
262 | 223 | ||
263 | static u64 sa11x0ssp_dma_mask = 0xffffffffUL; | 224 | static u64 sa11x0ssp_dma_mask = 0xffffffffUL; |
@@ -274,16 +235,8 @@ static struct platform_device sa11x0ssp_device = { | |||
274 | }; | 235 | }; |
275 | 236 | ||
276 | static struct resource sa11x0fb_resources[] = { | 237 | static struct resource sa11x0fb_resources[] = { |
277 | [0] = { | 238 | [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K), |
278 | .start = 0xb0100000, | 239 | [1] = DEFINE_RES_IRQ(IRQ_LCD), |
279 | .end = 0xb010ffff, | ||
280 | .flags = IORESOURCE_MEM, | ||
281 | }, | ||
282 | [1] = { | ||
283 | .start = IRQ_LCD, | ||
284 | .end = IRQ_LCD, | ||
285 | .flags = IORESOURCE_IRQ, | ||
286 | }, | ||
287 | }; | 240 | }; |
288 | 241 | ||
289 | static struct platform_device sa11x0fb_device = { | 242 | static struct platform_device sa11x0fb_device = { |
@@ -321,23 +274,10 @@ void sa11x0_register_mtd(struct flash_platform_data *flash, | |||
321 | } | 274 | } |
322 | 275 | ||
323 | static struct resource sa11x0ir_resources[] = { | 276 | static struct resource sa11x0ir_resources[] = { |
324 | { | 277 | DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24), |
325 | .start = __PREG(Ser2UTCR0), | 278 | DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c), |
326 | .end = __PREG(Ser2UTCR0) + 0x24 - 1, | 279 | DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04), |
327 | .flags = IORESOURCE_MEM, | 280 | DEFINE_RES_IRQ(IRQ_Ser2ICP), |
328 | }, { | ||
329 | .start = __PREG(Ser2HSCR0), | ||
330 | .end = __PREG(Ser2HSCR0) + 0x1c - 1, | ||
331 | .flags = IORESOURCE_MEM, | ||
332 | }, { | ||
333 | .start = __PREG(Ser2HSCR2), | ||
334 | .end = __PREG(Ser2HSCR2) + 0x04 - 1, | ||
335 | .flags = IORESOURCE_MEM, | ||
336 | }, { | ||
337 | .start = IRQ_Ser2ICP, | ||
338 | .end = IRQ_Ser2ICP, | ||
339 | .flags = IORESOURCE_IRQ, | ||
340 | } | ||
341 | }; | 281 | }; |
342 | 282 | ||
343 | static struct platform_device sa11x0ir_device = { | 283 | static struct platform_device sa11x0ir_device = { |
@@ -357,6 +297,29 @@ static struct platform_device sa11x0rtc_device = { | |||
357 | .id = -1, | 297 | .id = -1, |
358 | }; | 298 | }; |
359 | 299 | ||
300 | static struct resource sa11x0dma_resources[] = { | ||
301 | DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE), | ||
302 | DEFINE_RES_IRQ(IRQ_DMA0), | ||
303 | DEFINE_RES_IRQ(IRQ_DMA1), | ||
304 | DEFINE_RES_IRQ(IRQ_DMA2), | ||
305 | DEFINE_RES_IRQ(IRQ_DMA3), | ||
306 | DEFINE_RES_IRQ(IRQ_DMA4), | ||
307 | DEFINE_RES_IRQ(IRQ_DMA5), | ||
308 | }; | ||
309 | |||
310 | static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32); | ||
311 | |||
312 | static struct platform_device sa11x0dma_device = { | ||
313 | .name = "sa11x0-dma", | ||
314 | .id = -1, | ||
315 | .dev = { | ||
316 | .dma_mask = &sa11x0dma_dma_mask, | ||
317 | .coherent_dma_mask = 0xffffffff, | ||
318 | }, | ||
319 | .num_resources = ARRAY_SIZE(sa11x0dma_resources), | ||
320 | .resource = sa11x0dma_resources, | ||
321 | }; | ||
322 | |||
360 | static struct platform_device *sa11x0_devices[] __initdata = { | 323 | static struct platform_device *sa11x0_devices[] __initdata = { |
361 | &sa11x0udc_device, | 324 | &sa11x0udc_device, |
362 | &sa11x0uart1_device, | 325 | &sa11x0uart1_device, |
@@ -364,6 +327,7 @@ static struct platform_device *sa11x0_devices[] __initdata = { | |||
364 | &sa11x0ssp_device, | 327 | &sa11x0ssp_device, |
365 | &sa11x0pcmcia_device, | 328 | &sa11x0pcmcia_device, |
366 | &sa11x0rtc_device, | 329 | &sa11x0rtc_device, |
330 | &sa11x0dma_device, | ||
367 | }; | 331 | }; |
368 | 332 | ||
369 | static int __init sa1100_init(void) | 333 | static int __init sa1100_init(void) |
@@ -428,7 +392,7 @@ void __init sa1100_map_io(void) | |||
428 | * the MBGNT signal false to ensure the SA1111 doesn't own the | 392 | * the MBGNT signal false to ensure the SA1111 doesn't own the |
429 | * SDRAM bus. | 393 | * SDRAM bus. |
430 | */ | 394 | */ |
431 | void __init sa1110_mb_disable(void) | 395 | void sa1110_mb_disable(void) |
432 | { | 396 | { |
433 | unsigned long flags; | 397 | unsigned long flags; |
434 | 398 | ||
@@ -447,7 +411,7 @@ void __init sa1110_mb_disable(void) | |||
447 | * If the system is going to use the SA-1111 DMA engines, set up | 411 | * If the system is going to use the SA-1111 DMA engines, set up |
448 | * the memory bus request/grant pins. | 412 | * the memory bus request/grant pins. |
449 | */ | 413 | */ |
450 | void __devinit sa1110_mb_enable(void) | 414 | void sa1110_mb_enable(void) |
451 | { | 415 | { |
452 | unsigned long flags; | 416 | unsigned long flags; |
453 | 417 | ||
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c index b0784c974c2d..63150e1ffe9e 100644 --- a/arch/arm/mach-sa1100/h3xxx.c +++ b/arch/arm/mach-sa1100/h3xxx.c | |||
@@ -109,11 +109,8 @@ static struct flash_platform_data h3xxx_flash_data = { | |||
109 | .nr_parts = ARRAY_SIZE(h3xxx_partitions), | 109 | .nr_parts = ARRAY_SIZE(h3xxx_partitions), |
110 | }; | 110 | }; |
111 | 111 | ||
112 | static struct resource h3xxx_flash_resource = { | 112 | static struct resource h3xxx_flash_resource = |
113 | .start = SA1100_CS0_PHYS, | 113 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); |
114 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
115 | .flags = IORESOURCE_MEM, | ||
116 | }; | ||
117 | 114 | ||
118 | 115 | ||
119 | /* | 116 | /* |
@@ -186,11 +183,7 @@ static struct sa1100_port_fns h3xxx_port_fns __initdata = { | |||
186 | */ | 183 | */ |
187 | 184 | ||
188 | static struct resource egpio_resources[] = { | 185 | static struct resource egpio_resources[] = { |
189 | [0] = { | 186 | [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4), |
190 | .start = H3600_EGPIO_PHYS, | ||
191 | .end = H3600_EGPIO_PHYS + 0x4 - 1, | ||
192 | .flags = IORESOURCE_MEM, | ||
193 | }, | ||
194 | }; | 187 | }; |
195 | 188 | ||
196 | static struct htc_egpio_chip egpio_chips[] = { | 189 | static struct htc_egpio_chip egpio_chips[] = { |
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c index c01bb36db940..37d381ad5464 100644 --- a/arch/arm/mach-sa1100/hackkit.c +++ b/arch/arm/mach-sa1100/hackkit.c | |||
@@ -179,11 +179,8 @@ static struct flash_platform_data hackkit_flash_data = { | |||
179 | .nr_parts = ARRAY_SIZE(hackkit_partitions), | 179 | .nr_parts = ARRAY_SIZE(hackkit_partitions), |
180 | }; | 180 | }; |
181 | 181 | ||
182 | static struct resource hackkit_flash_resource = { | 182 | static struct resource hackkit_flash_resource = |
183 | .start = SA1100_CS0_PHYS, | 183 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); |
184 | .end = SA1100_CS0_PHYS + SZ_32M, | ||
185 | .flags = IORESOURCE_MEM, | ||
186 | }; | ||
187 | 184 | ||
188 | static void __init hackkit_init(void) | 185 | static void __init hackkit_init(void) |
189 | { | 186 | { |
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h index 3a4d4e067ed8..3f2d1b60188c 100644 --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h | |||
@@ -1590,224 +1590,9 @@ | |||
1590 | 1590 | ||
1591 | /* | 1591 | /* |
1592 | * Direct Memory Access (DMA) control registers | 1592 | * Direct Memory Access (DMA) control registers |
1593 | * | ||
1594 | * Registers | ||
1595 | * DDAR0 Direct Memory Access (DMA) Device Address Register | ||
1596 | * channel 0 (read/write). | ||
1597 | * DCSR0 Direct Memory Access (DMA) Control and Status | ||
1598 | * Register channel 0 (read/write). | ||
1599 | * DBSA0 Direct Memory Access (DMA) Buffer Start address | ||
1600 | * register A channel 0 (read/write). | ||
1601 | * DBTA0 Direct Memory Access (DMA) Buffer Transfer count | ||
1602 | * register A channel 0 (read/write). | ||
1603 | * DBSB0 Direct Memory Access (DMA) Buffer Start address | ||
1604 | * register B channel 0 (read/write). | ||
1605 | * DBTB0 Direct Memory Access (DMA) Buffer Transfer count | ||
1606 | * register B channel 0 (read/write). | ||
1607 | * | ||
1608 | * DDAR1 Direct Memory Access (DMA) Device Address Register | ||
1609 | * channel 1 (read/write). | ||
1610 | * DCSR1 Direct Memory Access (DMA) Control and Status | ||
1611 | * Register channel 1 (read/write). | ||
1612 | * DBSA1 Direct Memory Access (DMA) Buffer Start address | ||
1613 | * register A channel 1 (read/write). | ||
1614 | * DBTA1 Direct Memory Access (DMA) Buffer Transfer count | ||
1615 | * register A channel 1 (read/write). | ||
1616 | * DBSB1 Direct Memory Access (DMA) Buffer Start address | ||
1617 | * register B channel 1 (read/write). | ||
1618 | * DBTB1 Direct Memory Access (DMA) Buffer Transfer count | ||
1619 | * register B channel 1 (read/write). | ||
1620 | * | ||
1621 | * DDAR2 Direct Memory Access (DMA) Device Address Register | ||
1622 | * channel 2 (read/write). | ||
1623 | * DCSR2 Direct Memory Access (DMA) Control and Status | ||
1624 | * Register channel 2 (read/write). | ||
1625 | * DBSA2 Direct Memory Access (DMA) Buffer Start address | ||
1626 | * register A channel 2 (read/write). | ||
1627 | * DBTA2 Direct Memory Access (DMA) Buffer Transfer count | ||
1628 | * register A channel 2 (read/write). | ||
1629 | * DBSB2 Direct Memory Access (DMA) Buffer Start address | ||
1630 | * register B channel 2 (read/write). | ||
1631 | * DBTB2 Direct Memory Access (DMA) Buffer Transfer count | ||
1632 | * register B channel 2 (read/write). | ||
1633 | * | ||
1634 | * DDAR3 Direct Memory Access (DMA) Device Address Register | ||
1635 | * channel 3 (read/write). | ||
1636 | * DCSR3 Direct Memory Access (DMA) Control and Status | ||
1637 | * Register channel 3 (read/write). | ||
1638 | * DBSA3 Direct Memory Access (DMA) Buffer Start address | ||
1639 | * register A channel 3 (read/write). | ||
1640 | * DBTA3 Direct Memory Access (DMA) Buffer Transfer count | ||
1641 | * register A channel 3 (read/write). | ||
1642 | * DBSB3 Direct Memory Access (DMA) Buffer Start address | ||
1643 | * register B channel 3 (read/write). | ||
1644 | * DBTB3 Direct Memory Access (DMA) Buffer Transfer count | ||
1645 | * register B channel 3 (read/write). | ||
1646 | * | ||
1647 | * DDAR4 Direct Memory Access (DMA) Device Address Register | ||
1648 | * channel 4 (read/write). | ||
1649 | * DCSR4 Direct Memory Access (DMA) Control and Status | ||
1650 | * Register channel 4 (read/write). | ||
1651 | * DBSA4 Direct Memory Access (DMA) Buffer Start address | ||
1652 | * register A channel 4 (read/write). | ||
1653 | * DBTA4 Direct Memory Access (DMA) Buffer Transfer count | ||
1654 | * register A channel 4 (read/write). | ||
1655 | * DBSB4 Direct Memory Access (DMA) Buffer Start address | ||
1656 | * register B channel 4 (read/write). | ||
1657 | * DBTB4 Direct Memory Access (DMA) Buffer Transfer count | ||
1658 | * register B channel 4 (read/write). | ||
1659 | * | ||
1660 | * DDAR5 Direct Memory Access (DMA) Device Address Register | ||
1661 | * channel 5 (read/write). | ||
1662 | * DCSR5 Direct Memory Access (DMA) Control and Status | ||
1663 | * Register channel 5 (read/write). | ||
1664 | * DBSA5 Direct Memory Access (DMA) Buffer Start address | ||
1665 | * register A channel 5 (read/write). | ||
1666 | * DBTA5 Direct Memory Access (DMA) Buffer Transfer count | ||
1667 | * register A channel 5 (read/write). | ||
1668 | * DBSB5 Direct Memory Access (DMA) Buffer Start address | ||
1669 | * register B channel 5 (read/write). | ||
1670 | * DBTB5 Direct Memory Access (DMA) Buffer Transfer count | ||
1671 | * register B channel 5 (read/write). | ||
1672 | */ | 1593 | */ |
1673 | 1594 | #define DMA_SIZE (6 * 0x20) | |
1674 | #define DMASp 0x00000020 /* DMA control reg. Space [byte] */ | 1595 | #define DMA_PHYS 0xb0000000 |
1675 | |||
1676 | #define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */ | ||
1677 | #define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */ | ||
1678 | #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */ | ||
1679 | #define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */ | ||
1680 | #define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */ | ||
1681 | #define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */ | ||
1682 | #define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */ | ||
1683 | #define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */ | ||
1684 | |||
1685 | #define DDAR_RW 0x00000001 /* device data Read/Write */ | ||
1686 | #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ | ||
1687 | /* (memory -> device) */ | ||
1688 | #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ | ||
1689 | /* (device -> memory) */ | ||
1690 | #define DDAR_E 0x00000002 /* big/little Endian device */ | ||
1691 | #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ | ||
1692 | #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ | ||
1693 | #define DDAR_BS 0x00000004 /* device Burst Size */ | ||
1694 | #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ | ||
1695 | #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ | ||
1696 | #define DDAR_DW 0x00000008 /* device Data Width */ | ||
1697 | #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ | ||
1698 | #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ | ||
1699 | #define DDAR_DS Fld (4, 4) /* Device Select */ | ||
1700 | #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ | ||
1701 | (0x0 << FShft (DDAR_DS)) | ||
1702 | #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ | ||
1703 | (0x1 << FShft (DDAR_DS)) | ||
1704 | #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ | ||
1705 | (0x2 << FShft (DDAR_DS)) | ||
1706 | #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ | ||
1707 | (0x3 << FShft (DDAR_DS)) | ||
1708 | #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ | ||
1709 | (0x4 << FShft (DDAR_DS)) | ||
1710 | #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ | ||
1711 | (0x5 << FShft (DDAR_DS)) | ||
1712 | #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ | ||
1713 | (0x6 << FShft (DDAR_DS)) | ||
1714 | #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ | ||
1715 | (0x7 << FShft (DDAR_DS)) | ||
1716 | #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ | ||
1717 | (0x8 << FShft (DDAR_DS)) | ||
1718 | #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ | ||
1719 | (0x9 << FShft (DDAR_DS)) | ||
1720 | #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ | ||
1721 | /* (audio) */ \ | ||
1722 | (0xA << FShft (DDAR_DS)) | ||
1723 | #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ | ||
1724 | /* (audio) */ \ | ||
1725 | (0xB << FShft (DDAR_DS)) | ||
1726 | #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ | ||
1727 | /* (telecom) */ \ | ||
1728 | (0xC << FShft (DDAR_DS)) | ||
1729 | #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ | ||
1730 | /* (telecom) */ \ | ||
1731 | (0xD << FShft (DDAR_DS)) | ||
1732 | #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ | ||
1733 | (0xE << FShft (DDAR_DS)) | ||
1734 | #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ | ||
1735 | (0xF << FShft (DDAR_DS)) | ||
1736 | #define DDAR_DA Fld (24, 8) /* Device Address */ | ||
1737 | #define DDAR_DevAdd(Add) /* Device Address */ \ | ||
1738 | (((Add) & 0xF0000000) | \ | ||
1739 | (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) | ||
1740 | #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ | ||
1741 | (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ | ||
1742 | DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR))) | ||
1743 | #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ | ||
1744 | (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ | ||
1745 | DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR))) | ||
1746 | #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ | ||
1747 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1748 | DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR))) | ||
1749 | #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ | ||
1750 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1751 | DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR))) | ||
1752 | #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ | ||
1753 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1754 | DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR))) | ||
1755 | #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ | ||
1756 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1757 | DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR))) | ||
1758 | #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ | ||
1759 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1760 | DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR))) | ||
1761 | #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ | ||
1762 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1763 | DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR))) | ||
1764 | #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ | ||
1765 | (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ | ||
1766 | DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR))) | ||
1767 | #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ | ||
1768 | (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ | ||
1769 | DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR))) | ||
1770 | #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ | ||
1771 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1772 | DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR))) | ||
1773 | #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ | ||
1774 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
1775 | DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR))) | ||
1776 | #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ | ||
1777 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
1778 | DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0))) | ||
1779 | #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ | ||
1780 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
1781 | DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0))) | ||
1782 | #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ | ||
1783 | /* (telecom) */ \ | ||
1784 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
1785 | DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1))) | ||
1786 | #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ | ||
1787 | /* (telecom) */ \ | ||
1788 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
1789 | DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1))) | ||
1790 | #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ | ||
1791 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
1792 | DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR))) | ||
1793 | #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ | ||
1794 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
1795 | DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) | ||
1796 | |||
1797 | #define DCSR_RUN 0x00000001 /* DMA running */ | ||
1798 | #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ | ||
1799 | #define DCSR_ERROR 0x00000004 /* DMA ERROR */ | ||
1800 | #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ | ||
1801 | #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ | ||
1802 | #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ | ||
1803 | #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ | ||
1804 | #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ | ||
1805 | #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ | ||
1806 | #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ | ||
1807 | |||
1808 | #define DBT_TC Fld (13, 0) /* Transfer Count */ | ||
1809 | #define DBTA_TCA DBT_TC /* Transfer Count buffer A */ | ||
1810 | #define DBTB_TCB DBT_TC /* Transfer Count buffer B */ | ||
1811 | 1596 | ||
1812 | 1597 | ||
1813 | /* | 1598 | /* |
diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h deleted file mode 100644 index dda1b351310d..000000000000 --- a/arch/arm/mach-sa1100/include/mach/dma.h +++ /dev/null | |||
@@ -1,117 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-sa1100/include/mach/dma.h | ||
3 | * | ||
4 | * Generic SA1100 DMA support | ||
5 | * | ||
6 | * Copyright (C) 2000 Nicolas Pitre | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASM_ARCH_DMA_H | ||
11 | #define __ASM_ARCH_DMA_H | ||
12 | |||
13 | #include "hardware.h" | ||
14 | |||
15 | |||
16 | /* | ||
17 | * The SA1100 has six internal DMA channels. | ||
18 | */ | ||
19 | #define SA1100_DMA_CHANNELS 6 | ||
20 | |||
21 | /* | ||
22 | * Maximum physical DMA buffer size | ||
23 | */ | ||
24 | #define MAX_DMA_SIZE 0x1fff | ||
25 | #define CUT_DMA_SIZE 0x1000 | ||
26 | |||
27 | /* | ||
28 | * All possible SA1100 devices a DMA channel can be attached to. | ||
29 | */ | ||
30 | typedef enum { | ||
31 | DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */ | ||
32 | DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */ | ||
33 | DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */ | ||
34 | DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */ | ||
35 | DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */ | ||
36 | DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */ | ||
37 | DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */ | ||
38 | DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */ | ||
39 | DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */ | ||
40 | DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */ | ||
41 | DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */ | ||
42 | DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */ | ||
43 | DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */ | ||
44 | DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */ | ||
45 | DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */ | ||
46 | DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */ | ||
47 | DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */ | ||
48 | DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ | ||
49 | } dma_device_t; | ||
50 | |||
51 | typedef struct { | ||
52 | volatile u_long DDAR; | ||
53 | volatile u_long SetDCSR; | ||
54 | volatile u_long ClrDCSR; | ||
55 | volatile u_long RdDCSR; | ||
56 | volatile dma_addr_t DBSA; | ||
57 | volatile u_long DBTA; | ||
58 | volatile dma_addr_t DBSB; | ||
59 | volatile u_long DBTB; | ||
60 | } dma_regs_t; | ||
61 | |||
62 | typedef void (*dma_callback_t)(void *data); | ||
63 | |||
64 | /* | ||
65 | * DMA function prototypes | ||
66 | */ | ||
67 | |||
68 | extern int sa1100_request_dma( dma_device_t device, const char *device_id, | ||
69 | dma_callback_t callback, void *data, | ||
70 | dma_regs_t **regs ); | ||
71 | extern void sa1100_free_dma( dma_regs_t *regs ); | ||
72 | extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); | ||
73 | extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); | ||
74 | extern void sa1100_reset_dma(dma_regs_t *regs); | ||
75 | |||
76 | /** | ||
77 | * sa1100_stop_dma - stop DMA in progress | ||
78 | * @regs: identifier for the channel to use | ||
79 | * | ||
80 | * This stops DMA without clearing buffer pointers. Unlike | ||
81 | * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() | ||
82 | * or sa1100_get_dma_pos(). | ||
83 | * | ||
84 | * The @regs identifier is provided by a successful call to | ||
85 | * sa1100_request_dma(). | ||
86 | **/ | ||
87 | |||
88 | #define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) | ||
89 | |||
90 | /** | ||
91 | * sa1100_resume_dma - resume DMA on a stopped channel | ||
92 | * @regs: identifier for the channel to use | ||
93 | * | ||
94 | * This resumes DMA on a channel previously stopped with | ||
95 | * sa1100_stop_dma(). | ||
96 | * | ||
97 | * The @regs identifier is provided by a successful call to | ||
98 | * sa1100_request_dma(). | ||
99 | **/ | ||
100 | |||
101 | #define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) | ||
102 | |||
103 | /** | ||
104 | * sa1100_clear_dma - clear DMA pointers | ||
105 | * @regs: identifier for the channel to use | ||
106 | * | ||
107 | * This clear any DMA state so the DMA engine is ready to restart | ||
108 | * with new buffers through sa1100_start_dma(). Any buffers in flight | ||
109 | * are discarded. | ||
110 | * | ||
111 | * The @regs identifier is provided by a successful call to | ||
112 | * sa1100_request_dma(). | ||
113 | **/ | ||
114 | |||
115 | #define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) | ||
116 | |||
117 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index d18f21abef80..9e07634a4670 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h | |||
@@ -82,11 +82,3 @@ | |||
82 | #else | 82 | #else |
83 | #define NR_IRQS (IRQ_BOARD_START) | 83 | #define NR_IRQS (IRQ_BOARD_START) |
84 | #endif | 84 | #endif |
85 | |||
86 | /* | ||
87 | * Board specific IRQs. Define them here. | ||
88 | * Do not surround them with ifdefs. | ||
89 | */ | ||
90 | #define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) | ||
91 | #define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) | ||
92 | #define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) | ||
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h index ffe2bc45eed0..5516a52a329d 100644 --- a/arch/arm/mach-sa1100/include/mach/neponset.h +++ b/arch/arm/mach-sa1100/include/mach/neponset.h | |||
@@ -15,54 +15,6 @@ | |||
15 | /* | 15 | /* |
16 | * Neponset definitions: | 16 | * Neponset definitions: |
17 | */ | 17 | */ |
18 | |||
19 | #define NEPONSET_CPLD_BASE (0x10000000) | ||
20 | #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) | ||
21 | #define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE) | ||
22 | |||
23 | #define _IRR 0x10000024 /* Interrupt Reason Register */ | ||
24 | #define _AUD_CTL 0x100000c0 /* Audio controls (RW) */ | ||
25 | #define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */ | ||
26 | #define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */ | ||
27 | #define _NCR_0 0x100000a0 /* Control Register (RW) */ | ||
28 | #define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */ | ||
29 | #define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */ | ||
30 | #define _SWPK 0x10000020 /* Switch pack (RO) */ | ||
31 | #define _WHOAMI 0x10000000 /* System ID Register (RO) */ | ||
32 | |||
33 | #define _LEDS 0x10000010 /* LEDs [31:0] (WO) */ | ||
34 | |||
35 | #define IRR (*((volatile u_char *) Nep_p2v(_IRR))) | ||
36 | #define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL))) | ||
37 | #define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0))) | ||
38 | #define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1))) | ||
39 | #define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0))) | ||
40 | #define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT))) | ||
41 | #define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN))) | ||
42 | #define SWPK (*((volatile u_char *) Nep_p2v(_SWPK))) | ||
43 | #define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI))) | ||
44 | |||
45 | #define LEDS (*((volatile Word *) Nep_p2v(_LEDS))) | ||
46 | |||
47 | #define IRR_ETHERNET (1<<0) | ||
48 | #define IRR_USAR (1<<1) | ||
49 | #define IRR_SA1111 (1<<2) | ||
50 | |||
51 | #define AUD_SEL_1341 (1<<0) | ||
52 | #define AUD_MUTE_1341 (1<<1) | ||
53 | |||
54 | #define MDM_CTL0_RTS1 (1 << 0) | ||
55 | #define MDM_CTL0_DTR1 (1 << 1) | ||
56 | #define MDM_CTL0_RTS2 (1 << 2) | ||
57 | #define MDM_CTL0_DTR2 (1 << 3) | ||
58 | |||
59 | #define MDM_CTL1_CTS1 (1 << 0) | ||
60 | #define MDM_CTL1_DSR1 (1 << 1) | ||
61 | #define MDM_CTL1_DCD1 (1 << 2) | ||
62 | #define MDM_CTL1_CTS2 (1 << 3) | ||
63 | #define MDM_CTL1_DSR2 (1 << 4) | ||
64 | #define MDM_CTL1_DCD2 (1 << 5) | ||
65 | |||
66 | #define NCR_GP01_OFF (1<<0) | 18 | #define NCR_GP01_OFF (1<<0) |
67 | #define NCR_TP_PWR_EN (1<<1) | 19 | #define NCR_TP_PWR_EN (1<<1) |
68 | #define NCR_MS_PWR_EN (1<<2) | 20 | #define NCR_MS_PWR_EN (1<<2) |
@@ -71,4 +23,8 @@ | |||
71 | #define NCR_A0VPP (1<<5) | 23 | #define NCR_A0VPP (1<<5) |
72 | #define NCR_A1VPP (1<<6) | 24 | #define NCR_A1VPP (1<<6) |
73 | 25 | ||
26 | void neponset_ncr_frob(unsigned int, unsigned int); | ||
27 | #define neponset_ncr_set(v) neponset_ncr_frob(0, v) | ||
28 | #define neponset_ncr_clear(v) neponset_ncr_frob(v, 0) | ||
29 | |||
74 | #endif | 30 | #endif |
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index dfbf824a69fa..5d12a305f53e 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c | |||
@@ -221,11 +221,8 @@ static struct irq_chip sa1100_normal_chip = { | |||
221 | .irq_set_wake = sa1100_set_wake, | 221 | .irq_set_wake = sa1100_set_wake, |
222 | }; | 222 | }; |
223 | 223 | ||
224 | static struct resource irq_resource = { | 224 | static struct resource irq_resource = |
225 | .name = "irqs", | 225 | DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); |
226 | .start = 0x90050000, | ||
227 | .end = 0x9005ffff, | ||
228 | }; | ||
229 | 226 | ||
230 | static struct sa1100irq_state { | 227 | static struct sa1100irq_state { |
231 | unsigned int saved; | 228 | unsigned int saved; |
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index ee121d6f0480..8be8130baf63 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c | |||
@@ -46,7 +46,7 @@ | |||
46 | 46 | ||
47 | /* memory space (line 52 of HP's doc) */ | 47 | /* memory space (line 52 of HP's doc) */ |
48 | #define SA1111REGSTART 0x40000000 | 48 | #define SA1111REGSTART 0x40000000 |
49 | #define SA1111REGLEN 0x00001fff | 49 | #define SA1111REGLEN 0x00002000 |
50 | #define EPSONREGSTART 0x48000000 | 50 | #define EPSONREGSTART 0x48000000 |
51 | #define EPSONREGLEN 0x00100000 | 51 | #define EPSONREGLEN 0x00100000 |
52 | #define EPSONFBSTART 0x48200000 | 52 | #define EPSONFBSTART 0x48200000 |
@@ -174,16 +174,8 @@ static struct s1d13xxxfb_pdata s1d13xxxfb_data = { | |||
174 | }; | 174 | }; |
175 | 175 | ||
176 | static struct resource s1d13xxxfb_resources[] = { | 176 | static struct resource s1d13xxxfb_resources[] = { |
177 | [0] = { | 177 | [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN), |
178 | .start = EPSONFBSTART, | 178 | [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN), |
179 | .end = EPSONFBSTART + EPSONFBLEN, | ||
180 | .flags = IORESOURCE_MEM, | ||
181 | }, | ||
182 | [1] = { | ||
183 | .start = EPSONREGSTART, | ||
184 | .end = EPSONREGSTART + EPSONREGLEN, | ||
185 | .flags = IORESOURCE_MEM, | ||
186 | } | ||
187 | }; | 179 | }; |
188 | 180 | ||
189 | static struct platform_device s1d13xxxfb_device = { | 181 | static struct platform_device s1d13xxxfb_device = { |
@@ -197,20 +189,13 @@ static struct platform_device s1d13xxxfb_device = { | |||
197 | }; | 189 | }; |
198 | 190 | ||
199 | static struct resource sa1111_resources[] = { | 191 | static struct resource sa1111_resources[] = { |
200 | [0] = { | 192 | [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN), |
201 | .start = SA1111REGSTART, | 193 | [1] = DEFINE_RES_IRQ(IRQ_GPIO1), |
202 | .end = SA1111REGSTART + SA1111REGLEN, | ||
203 | .flags = IORESOURCE_MEM, | ||
204 | }, | ||
205 | [1] = { | ||
206 | .start = IRQ_GPIO1, | ||
207 | .end = IRQ_GPIO1, | ||
208 | .flags = IORESOURCE_IRQ, | ||
209 | }, | ||
210 | }; | 194 | }; |
211 | 195 | ||
212 | static struct sa1111_platform_data sa1111_info = { | 196 | static struct sa1111_platform_data sa1111_info = { |
213 | .irq_base = IRQ_BOARD_END, | 197 | .irq_base = IRQ_BOARD_END, |
198 | .disable_devs = SA1111_DEVID_PS2_MSE, | ||
214 | }; | 199 | }; |
215 | 200 | ||
216 | static u64 sa1111_dmamask = 0xffffffffUL; | 201 | static u64 sa1111_dmamask = 0xffffffffUL; |
@@ -284,11 +269,6 @@ static struct map_desc jornada720_io_desc[] __initdata = { | |||
284 | .pfn = __phys_to_pfn(EPSONFBSTART), | 269 | .pfn = __phys_to_pfn(EPSONFBSTART), |
285 | .length = EPSONFBLEN, | 270 | .length = EPSONFBLEN, |
286 | .type = MT_DEVICE | 271 | .type = MT_DEVICE |
287 | }, { /* SA-1111 */ | ||
288 | .virtual = 0xf4000000, | ||
289 | .pfn = __phys_to_pfn(SA1111REGSTART), | ||
290 | .length = SA1111REGLEN, | ||
291 | .type = MT_DEVICE | ||
292 | } | 272 | } |
293 | }; | 273 | }; |
294 | 274 | ||
@@ -352,11 +332,8 @@ static struct flash_platform_data jornada720_flash_data = { | |||
352 | .nr_parts = ARRAY_SIZE(jornada720_partitions), | 332 | .nr_parts = ARRAY_SIZE(jornada720_partitions), |
353 | }; | 333 | }; |
354 | 334 | ||
355 | static struct resource jornada720_flash_resource = { | 335 | static struct resource jornada720_flash_resource = |
356 | .start = SA1100_CS0_PHYS, | 336 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); |
357 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
358 | .flags = IORESOURCE_MEM, | ||
359 | }; | ||
360 | 337 | ||
361 | static void __init jornada720_mach_init(void) | 338 | static void __init jornada720_mach_init(void) |
362 | { | 339 | { |
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c index 85f6ee672225..3923911000de 100644 --- a/arch/arm/mach-sa1100/nanoengine.c +++ b/arch/arm/mach-sa1100/nanoengine.c | |||
@@ -58,15 +58,8 @@ static struct flash_platform_data nanoengine_flash_data = { | |||
58 | }; | 58 | }; |
59 | 59 | ||
60 | static struct resource nanoengine_flash_resources[] = { | 60 | static struct resource nanoengine_flash_resources[] = { |
61 | { | 61 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), |
62 | .start = SA1100_CS0_PHYS, | 62 | DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), |
63 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
64 | .flags = IORESOURCE_MEM, | ||
65 | }, { | ||
66 | .start = SA1100_CS1_PHYS, | ||
67 | .end = SA1100_CS1_PHYS + SZ_32M - 1, | ||
68 | .flags = IORESOURCE_MEM, | ||
69 | } | ||
70 | }; | 63 | }; |
71 | 64 | ||
72 | static struct map_desc nanoengine_io_desc[] __initdata = { | 65 | static struct map_desc nanoengine_io_desc[] __initdata = { |
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index b4fa53a1427e..3297aa22cd77 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c | |||
@@ -1,89 +1,103 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-sa1100/neponset.c | 2 | * linux/arch/arm/mach-sa1100/neponset.c |
3 | * | ||
4 | */ | 3 | */ |
5 | #include <linux/kernel.h> | 4 | #include <linux/err.h> |
6 | #include <linux/init.h> | 5 | #include <linux/init.h> |
7 | #include <linux/tty.h> | ||
8 | #include <linux/ioport.h> | 6 | #include <linux/ioport.h> |
9 | #include <linux/serial_core.h> | 7 | #include <linux/irq.h> |
8 | #include <linux/kernel.h> | ||
9 | #include <linux/module.h> | ||
10 | #include <linux/platform_device.h> | 10 | #include <linux/platform_device.h> |
11 | #include <linux/pm.h> | ||
12 | #include <linux/serial_core.h> | ||
13 | #include <linux/slab.h> | ||
11 | 14 | ||
12 | #include <mach/hardware.h> | ||
13 | #include <asm/mach-types.h> | 15 | #include <asm/mach-types.h> |
14 | #include <asm/irq.h> | ||
15 | #include <asm/mach/map.h> | 16 | #include <asm/mach/map.h> |
16 | #include <asm/mach/irq.h> | ||
17 | #include <asm/mach/serial_sa1100.h> | 17 | #include <asm/mach/serial_sa1100.h> |
18 | #include <mach/assabet.h> | ||
19 | #include <mach/neponset.h> | ||
20 | #include <asm/hardware/sa1111.h> | 18 | #include <asm/hardware/sa1111.h> |
21 | #include <asm/sizes.h> | 19 | #include <asm/sizes.h> |
22 | 20 | ||
23 | /* | 21 | #include <mach/hardware.h> |
24 | * Install handler for Neponset IRQ. Note that we have to loop here | 22 | #include <mach/assabet.h> |
25 | * since the ETHERNET and USAR IRQs are level based, and we need to | 23 | #include <mach/neponset.h> |
26 | * ensure that the IRQ signal is deasserted before returning. This | ||
27 | * is rather unfortunate. | ||
28 | */ | ||
29 | static void | ||
30 | neponset_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
31 | { | ||
32 | unsigned int irr; | ||
33 | |||
34 | while (1) { | ||
35 | /* | ||
36 | * Acknowledge the parent IRQ. | ||
37 | */ | ||
38 | desc->irq_data.chip->irq_ack(&desc->irq_data); | ||
39 | |||
40 | /* | ||
41 | * Read the interrupt reason register. Let's have all | ||
42 | * active IRQ bits high. Note: there is a typo in the | ||
43 | * Neponset user's guide for the SA1111 IRR level. | ||
44 | */ | ||
45 | irr = IRR ^ (IRR_ETHERNET | IRR_USAR); | ||
46 | |||
47 | if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) | ||
48 | break; | ||
49 | |||
50 | /* | ||
51 | * Since there is no individual mask, we have to | ||
52 | * mask the parent IRQ. This is safe, since we'll | ||
53 | * recheck the register for any pending IRQs. | ||
54 | */ | ||
55 | if (irr & (IRR_ETHERNET | IRR_USAR)) { | ||
56 | desc->irq_data.chip->irq_mask(&desc->irq_data); | ||
57 | 24 | ||
58 | /* | 25 | #define NEP_IRQ_SMC91X 0 |
59 | * Ack the interrupt now to prevent re-entering | 26 | #define NEP_IRQ_USAR 1 |
60 | * this neponset handler. Again, this is safe | 27 | #define NEP_IRQ_SA1111 2 |
61 | * since we'll check the IRR register prior to | 28 | #define NEP_IRQ_NR 3 |
62 | * leaving. | 29 | |
63 | */ | 30 | #define WHOAMI 0x00 |
64 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 31 | #define LEDS 0x10 |
32 | #define SWPK 0x20 | ||
33 | #define IRR 0x24 | ||
34 | #define KP_Y_IN 0x80 | ||
35 | #define KP_X_OUT 0x90 | ||
36 | #define NCR_0 0xa0 | ||
37 | #define MDM_CTL_0 0xb0 | ||
38 | #define MDM_CTL_1 0xb4 | ||
39 | #define AUD_CTL 0xc0 | ||
40 | |||
41 | #define IRR_ETHERNET (1 << 0) | ||
42 | #define IRR_USAR (1 << 1) | ||
43 | #define IRR_SA1111 (1 << 2) | ||
44 | |||
45 | #define MDM_CTL0_RTS1 (1 << 0) | ||
46 | #define MDM_CTL0_DTR1 (1 << 1) | ||
47 | #define MDM_CTL0_RTS2 (1 << 2) | ||
48 | #define MDM_CTL0_DTR2 (1 << 3) | ||
49 | |||
50 | #define MDM_CTL1_CTS1 (1 << 0) | ||
51 | #define MDM_CTL1_DSR1 (1 << 1) | ||
52 | #define MDM_CTL1_DCD1 (1 << 2) | ||
53 | #define MDM_CTL1_CTS2 (1 << 3) | ||
54 | #define MDM_CTL1_DSR2 (1 << 4) | ||
55 | #define MDM_CTL1_DCD2 (1 << 5) | ||
56 | |||
57 | #define AUD_SEL_1341 (1 << 0) | ||
58 | #define AUD_MUTE_1341 (1 << 1) | ||
65 | 59 | ||
66 | if (irr & IRR_ETHERNET) { | 60 | extern void sa1110_mb_disable(void); |
67 | generic_handle_irq(IRQ_NEPONSET_SMC9196); | ||
68 | } | ||
69 | 61 | ||
70 | if (irr & IRR_USAR) { | 62 | struct neponset_drvdata { |
71 | generic_handle_irq(IRQ_NEPONSET_USAR); | 63 | void __iomem *base; |
72 | } | 64 | struct platform_device *sa1111; |
65 | struct platform_device *smc91x; | ||
66 | unsigned irq_base; | ||
67 | #ifdef CONFIG_PM_SLEEP | ||
68 | u32 ncr0; | ||
69 | u32 mdm_ctl_0; | ||
70 | #endif | ||
71 | }; | ||
73 | 72 | ||
74 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | 73 | static void __iomem *nep_base; |
75 | } | ||
76 | 74 | ||
77 | if (irr & IRR_SA1111) { | 75 | void neponset_ncr_frob(unsigned int mask, unsigned int val) |
78 | generic_handle_irq(IRQ_NEPONSET_SA1111); | 76 | { |
79 | } | 77 | void __iomem *base = nep_base; |
78 | |||
79 | if (base) { | ||
80 | unsigned long flags; | ||
81 | unsigned v; | ||
82 | |||
83 | local_irq_save(flags); | ||
84 | v = readb_relaxed(base + NCR_0); | ||
85 | writeb_relaxed((v & ~mask) | val, base + NCR_0); | ||
86 | local_irq_restore(flags); | ||
87 | } else { | ||
88 | WARN(1, "nep_base unset\n"); | ||
80 | } | 89 | } |
81 | } | 90 | } |
82 | 91 | ||
83 | static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) | 92 | static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) |
84 | { | 93 | { |
85 | u_int mdm_ctl0 = MDM_CTL_0; | 94 | void __iomem *base = nep_base; |
95 | u_int mdm_ctl0; | ||
96 | |||
97 | if (!base) | ||
98 | return; | ||
86 | 99 | ||
100 | mdm_ctl0 = readb_relaxed(base + MDM_CTL_0); | ||
87 | if (port->mapbase == _Ser1UTCR0) { | 101 | if (port->mapbase == _Ser1UTCR0) { |
88 | if (mctrl & TIOCM_RTS) | 102 | if (mctrl & TIOCM_RTS) |
89 | mdm_ctl0 &= ~MDM_CTL0_RTS2; | 103 | mdm_ctl0 &= ~MDM_CTL0_RTS2; |
@@ -106,14 +120,19 @@ static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) | |||
106 | mdm_ctl0 |= MDM_CTL0_DTR1; | 120 | mdm_ctl0 |= MDM_CTL0_DTR1; |
107 | } | 121 | } |
108 | 122 | ||
109 | MDM_CTL_0 = mdm_ctl0; | 123 | writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); |
110 | } | 124 | } |
111 | 125 | ||
112 | static u_int neponset_get_mctrl(struct uart_port *port) | 126 | static u_int neponset_get_mctrl(struct uart_port *port) |
113 | { | 127 | { |
128 | void __iomem *base = nep_base; | ||
114 | u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; | 129 | u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; |
115 | u_int mdm_ctl1 = MDM_CTL_1; | 130 | u_int mdm_ctl1; |
116 | 131 | ||
132 | if (!base) | ||
133 | return ret; | ||
134 | |||
135 | mdm_ctl1 = readb_relaxed(base + MDM_CTL_1); | ||
117 | if (port->mapbase == _Ser1UTCR0) { | 136 | if (port->mapbase == _Ser1UTCR0) { |
118 | if (mdm_ctl1 & MDM_CTL1_DCD2) | 137 | if (mdm_ctl1 & MDM_CTL1_DCD2) |
119 | ret &= ~TIOCM_CD; | 138 | ret &= ~TIOCM_CD; |
@@ -138,209 +157,279 @@ static struct sa1100_port_fns neponset_port_fns __devinitdata = { | |||
138 | .get_mctrl = neponset_get_mctrl, | 157 | .get_mctrl = neponset_get_mctrl, |
139 | }; | 158 | }; |
140 | 159 | ||
141 | static int __devinit neponset_probe(struct platform_device *dev) | 160 | /* |
161 | * Install handler for Neponset IRQ. Note that we have to loop here | ||
162 | * since the ETHERNET and USAR IRQs are level based, and we need to | ||
163 | * ensure that the IRQ signal is deasserted before returning. This | ||
164 | * is rather unfortunate. | ||
165 | */ | ||
166 | static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
142 | { | 167 | { |
143 | sa1100_register_uart_fns(&neponset_port_fns); | 168 | struct neponset_drvdata *d = irq_desc_get_handler_data(desc); |
169 | unsigned int irr; | ||
144 | 170 | ||
145 | /* | 171 | while (1) { |
146 | * Install handler for GPIO25. | 172 | /* |
147 | */ | 173 | * Acknowledge the parent IRQ. |
148 | irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); | 174 | */ |
149 | irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); | 175 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
150 | 176 | ||
151 | /* | 177 | /* |
152 | * We would set IRQ_GPIO25 to be a wake-up IRQ, but | 178 | * Read the interrupt reason register. Let's have all |
153 | * unfortunately something on the Neponset activates | 179 | * active IRQ bits high. Note: there is a typo in the |
154 | * this IRQ on sleep (ethernet?) | 180 | * Neponset user's guide for the SA1111 IRR level. |
155 | */ | 181 | */ |
156 | #if 0 | 182 | irr = readb_relaxed(d->base + IRR); |
157 | enable_irq_wake(IRQ_GPIO25); | 183 | irr ^= IRR_ETHERNET | IRR_USAR; |
158 | #endif | ||
159 | 184 | ||
160 | /* | 185 | if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) |
161 | * Setup other Neponset IRQs. SA1111 will be done by the | 186 | break; |
162 | * generic SA1111 code. | ||
163 | */ | ||
164 | irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); | ||
165 | set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); | ||
166 | irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq); | ||
167 | set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); | ||
168 | 187 | ||
169 | /* | 188 | /* |
170 | * Disable GPIO 0/1 drivers so the buttons work on the module. | 189 | * Since there is no individual mask, we have to |
171 | */ | 190 | * mask the parent IRQ. This is safe, since we'll |
172 | NCR_0 = NCR_GP01_OFF; | 191 | * recheck the register for any pending IRQs. |
192 | */ | ||
193 | if (irr & (IRR_ETHERNET | IRR_USAR)) { | ||
194 | desc->irq_data.chip->irq_mask(&desc->irq_data); | ||
173 | 195 | ||
174 | return 0; | 196 | /* |
175 | } | 197 | * Ack the interrupt now to prevent re-entering |
198 | * this neponset handler. Again, this is safe | ||
199 | * since we'll check the IRR register prior to | ||
200 | * leaving. | ||
201 | */ | ||
202 | desc->irq_data.chip->irq_ack(&desc->irq_data); | ||
176 | 203 | ||
177 | #ifdef CONFIG_PM | 204 | if (irr & IRR_ETHERNET) |
205 | generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); | ||
178 | 206 | ||
179 | /* | 207 | if (irr & IRR_USAR) |
180 | * LDM power management. | 208 | generic_handle_irq(d->irq_base + NEP_IRQ_USAR); |
181 | */ | ||
182 | static unsigned int neponset_saved_state; | ||
183 | 209 | ||
184 | static int neponset_suspend(struct platform_device *dev, pm_message_t state) | 210 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
185 | { | 211 | } |
186 | /* | ||
187 | * Save state. | ||
188 | */ | ||
189 | neponset_saved_state = NCR_0; | ||
190 | 212 | ||
191 | return 0; | 213 | if (irr & IRR_SA1111) |
214 | generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); | ||
215 | } | ||
192 | } | 216 | } |
193 | 217 | ||
194 | static int neponset_resume(struct platform_device *dev) | 218 | /* Yes, we really do not have any kind of masking or unmasking */ |
219 | static void nochip_noop(struct irq_data *irq) | ||
195 | { | 220 | { |
196 | NCR_0 = neponset_saved_state; | ||
197 | |||
198 | return 0; | ||
199 | } | 221 | } |
200 | 222 | ||
201 | #else | 223 | static struct irq_chip nochip = { |
202 | #define neponset_suspend NULL | 224 | .name = "neponset", |
203 | #define neponset_resume NULL | 225 | .irq_ack = nochip_noop, |
204 | #endif | 226 | .irq_mask = nochip_noop, |
205 | 227 | .irq_unmask = nochip_noop, | |
206 | static struct platform_driver neponset_device_driver = { | ||
207 | .probe = neponset_probe, | ||
208 | .suspend = neponset_suspend, | ||
209 | .resume = neponset_resume, | ||
210 | .driver = { | ||
211 | .name = "neponset", | ||
212 | }, | ||
213 | }; | ||
214 | |||
215 | static struct resource neponset_resources[] = { | ||
216 | [0] = { | ||
217 | .start = 0x10000000, | ||
218 | .end = 0x17ffffff, | ||
219 | .flags = IORESOURCE_MEM, | ||
220 | }, | ||
221 | }; | ||
222 | |||
223 | static struct platform_device neponset_device = { | ||
224 | .name = "neponset", | ||
225 | .id = 0, | ||
226 | .num_resources = ARRAY_SIZE(neponset_resources), | ||
227 | .resource = neponset_resources, | ||
228 | }; | ||
229 | |||
230 | static struct resource sa1111_resources[] = { | ||
231 | [0] = { | ||
232 | .start = 0x40000000, | ||
233 | .end = 0x40001fff, | ||
234 | .flags = IORESOURCE_MEM, | ||
235 | }, | ||
236 | [1] = { | ||
237 | .start = IRQ_NEPONSET_SA1111, | ||
238 | .end = IRQ_NEPONSET_SA1111, | ||
239 | .flags = IORESOURCE_IRQ, | ||
240 | }, | ||
241 | }; | 228 | }; |
242 | 229 | ||
243 | static struct sa1111_platform_data sa1111_info = { | 230 | static struct sa1111_platform_data sa1111_info = { |
244 | .irq_base = IRQ_BOARD_END, | 231 | .irq_base = IRQ_BOARD_END, |
232 | .disable_devs = SA1111_DEVID_PS2_MSE, | ||
245 | }; | 233 | }; |
246 | 234 | ||
247 | static u64 sa1111_dmamask = 0xffffffffUL; | 235 | static int __devinit neponset_probe(struct platform_device *dev) |
236 | { | ||
237 | struct neponset_drvdata *d; | ||
238 | struct resource *nep_res, *sa1111_res, *smc91x_res; | ||
239 | struct resource sa1111_resources[] = { | ||
240 | DEFINE_RES_MEM(0x40000000, SZ_8K), | ||
241 | { .flags = IORESOURCE_IRQ }, | ||
242 | }; | ||
243 | struct platform_device_info sa1111_devinfo = { | ||
244 | .parent = &dev->dev, | ||
245 | .name = "sa1111", | ||
246 | .id = 0, | ||
247 | .res = sa1111_resources, | ||
248 | .num_res = ARRAY_SIZE(sa1111_resources), | ||
249 | .data = &sa1111_info, | ||
250 | .size_data = sizeof(sa1111_info), | ||
251 | .dma_mask = 0xffffffffUL, | ||
252 | }; | ||
253 | struct resource smc91x_resources[] = { | ||
254 | DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS, | ||
255 | 0x02000000, "smc91x-regs"), | ||
256 | DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000, | ||
257 | 0x02000000, "smc91x-attrib"), | ||
258 | { .flags = IORESOURCE_IRQ }, | ||
259 | }; | ||
260 | struct platform_device_info smc91x_devinfo = { | ||
261 | .parent = &dev->dev, | ||
262 | .name = "smc91x", | ||
263 | .id = 0, | ||
264 | .res = smc91x_resources, | ||
265 | .num_res = ARRAY_SIZE(smc91x_resources), | ||
266 | }; | ||
267 | int ret, irq; | ||
268 | |||
269 | if (nep_base) | ||
270 | return -EBUSY; | ||
271 | |||
272 | irq = ret = platform_get_irq(dev, 0); | ||
273 | if (ret < 0) | ||
274 | goto err_alloc; | ||
275 | |||
276 | nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0); | ||
277 | smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1); | ||
278 | sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2); | ||
279 | if (!nep_res || !smc91x_res || !sa1111_res) { | ||
280 | ret = -ENXIO; | ||
281 | goto err_alloc; | ||
282 | } | ||
248 | 283 | ||
249 | static struct platform_device sa1111_device = { | 284 | d = kzalloc(sizeof(*d), GFP_KERNEL); |
250 | .name = "sa1111", | 285 | if (!d) { |
251 | .id = 0, | 286 | ret = -ENOMEM; |
252 | .dev = { | 287 | goto err_alloc; |
253 | .dma_mask = &sa1111_dmamask, | 288 | } |
254 | .coherent_dma_mask = 0xffffffff, | ||
255 | .platform_data = &sa1111_info, | ||
256 | }, | ||
257 | .num_resources = ARRAY_SIZE(sa1111_resources), | ||
258 | .resource = sa1111_resources, | ||
259 | }; | ||
260 | 289 | ||
261 | static struct resource smc91x_resources[] = { | 290 | d->base = ioremap(nep_res->start, SZ_4K); |
262 | [0] = { | 291 | if (!d->base) { |
263 | .name = "smc91x-regs", | 292 | ret = -ENOMEM; |
264 | .start = SA1100_CS3_PHYS, | 293 | goto err_ioremap; |
265 | .end = SA1100_CS3_PHYS + 0x01ffffff, | 294 | } |
266 | .flags = IORESOURCE_MEM, | ||
267 | }, | ||
268 | [1] = { | ||
269 | .start = IRQ_NEPONSET_SMC9196, | ||
270 | .end = IRQ_NEPONSET_SMC9196, | ||
271 | .flags = IORESOURCE_IRQ, | ||
272 | }, | ||
273 | [2] = { | ||
274 | .name = "smc91x-attrib", | ||
275 | .start = SA1100_CS3_PHYS + 0x02000000, | ||
276 | .end = SA1100_CS3_PHYS + 0x03ffffff, | ||
277 | .flags = IORESOURCE_MEM, | ||
278 | }, | ||
279 | }; | ||
280 | 295 | ||
281 | static struct platform_device smc91x_device = { | 296 | if (readb_relaxed(d->base + WHOAMI) != 0x11) { |
282 | .name = "smc91x", | 297 | dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n", |
283 | .id = 0, | 298 | readb_relaxed(d->base + WHOAMI)); |
284 | .num_resources = ARRAY_SIZE(smc91x_resources), | 299 | ret = -ENODEV; |
285 | .resource = smc91x_resources, | 300 | goto err_id; |
286 | }; | 301 | } |
287 | 302 | ||
288 | static struct platform_device *devices[] __initdata = { | 303 | ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1); |
289 | &neponset_device, | 304 | if (ret <= 0) { |
290 | &sa1111_device, | 305 | dev_err(&dev->dev, "unable to allocate %u irqs: %d\n", |
291 | &smc91x_device, | 306 | NEP_IRQ_NR, ret); |
292 | }; | 307 | if (ret == 0) |
308 | ret = -ENOMEM; | ||
309 | goto err_irq_alloc; | ||
310 | } | ||
293 | 311 | ||
294 | extern void sa1110_mb_disable(void); | 312 | d->irq_base = ret; |
295 | 313 | ||
296 | static int __init neponset_init(void) | 314 | irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, |
297 | { | 315 | handle_simple_irq); |
298 | platform_driver_register(&neponset_device_driver); | 316 | set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); |
317 | irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, | ||
318 | handle_simple_irq); | ||
319 | set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); | ||
320 | irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); | ||
299 | 321 | ||
300 | /* | 322 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
301 | * The Neponset is only present on the Assabet machine type. | 323 | irq_set_handler_data(irq, d); |
302 | */ | 324 | irq_set_chained_handler(irq, neponset_irq_handler); |
303 | if (!machine_is_assabet()) | ||
304 | return -ENODEV; | ||
305 | 325 | ||
306 | /* | 326 | /* |
307 | * Ensure that the memory bus request/grant signals are setup, | 327 | * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately |
308 | * and the grant is held in its inactive state, whether or not | 328 | * something on the Neponset activates this IRQ on sleep (eth?) |
309 | * we actually have a Neponset attached. | ||
310 | */ | 329 | */ |
330 | #if 0 | ||
331 | enable_irq_wake(irq); | ||
332 | #endif | ||
333 | |||
334 | dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n", | ||
335 | d->irq_base, d->irq_base + NEP_IRQ_NR - 1); | ||
336 | nep_base = d->base; | ||
337 | |||
338 | sa1100_register_uart_fns(&neponset_port_fns); | ||
339 | |||
340 | /* Ensure that the memory bus request/grant signals are setup */ | ||
311 | sa1110_mb_disable(); | 341 | sa1110_mb_disable(); |
312 | 342 | ||
313 | if (!machine_has_neponset()) { | 343 | /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */ |
314 | printk(KERN_DEBUG "Neponset expansion board not present\n"); | 344 | writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); |
315 | return -ENODEV; | ||
316 | } | ||
317 | 345 | ||
318 | if (WHOAMI != 0x11) { | 346 | sa1111_resources[0].parent = sa1111_res; |
319 | printk(KERN_WARNING "Neponset board detected, but " | 347 | sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111; |
320 | "wrong ID: %02x\n", WHOAMI); | 348 | sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111; |
321 | return -ENODEV; | 349 | d->sa1111 = platform_device_register_full(&sa1111_devinfo); |
322 | } | 350 | |
351 | smc91x_resources[0].parent = smc91x_res; | ||
352 | smc91x_resources[1].parent = smc91x_res; | ||
353 | smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X; | ||
354 | smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X; | ||
355 | d->smc91x = platform_device_register_full(&smc91x_devinfo); | ||
356 | |||
357 | platform_set_drvdata(dev, d); | ||
323 | 358 | ||
324 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | 359 | return 0; |
360 | |||
361 | err_irq_alloc: | ||
362 | err_id: | ||
363 | iounmap(d->base); | ||
364 | err_ioremap: | ||
365 | kfree(d); | ||
366 | err_alloc: | ||
367 | return ret; | ||
325 | } | 368 | } |
326 | 369 | ||
327 | subsys_initcall(neponset_init); | 370 | static int __devexit neponset_remove(struct platform_device *dev) |
371 | { | ||
372 | struct neponset_drvdata *d = platform_get_drvdata(dev); | ||
373 | int irq = platform_get_irq(dev, 0); | ||
374 | |||
375 | if (!IS_ERR(d->sa1111)) | ||
376 | platform_device_unregister(d->sa1111); | ||
377 | if (!IS_ERR(d->smc91x)) | ||
378 | platform_device_unregister(d->smc91x); | ||
379 | irq_set_chained_handler(irq, NULL); | ||
380 | irq_free_descs(d->irq_base, NEP_IRQ_NR); | ||
381 | nep_base = NULL; | ||
382 | iounmap(d->base); | ||
383 | kfree(d); | ||
328 | 384 | ||
329 | static struct map_desc neponset_io_desc[] __initdata = { | 385 | return 0; |
330 | { /* System Registers */ | 386 | } |
331 | .virtual = 0xf3000000, | 387 | |
332 | .pfn = __phys_to_pfn(0x10000000), | 388 | #ifdef CONFIG_PM_SLEEP |
333 | .length = SZ_1M, | 389 | static int neponset_suspend(struct device *dev) |
334 | .type = MT_DEVICE | 390 | { |
335 | }, { /* SA-1111 */ | 391 | struct neponset_drvdata *d = dev_get_drvdata(dev); |
336 | .virtual = 0xf4000000, | 392 | |
337 | .pfn = __phys_to_pfn(0x40000000), | 393 | d->ncr0 = readb_relaxed(d->base + NCR_0); |
338 | .length = SZ_1M, | 394 | d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0); |
339 | .type = MT_DEVICE | 395 | |
340 | } | 396 | return 0; |
397 | } | ||
398 | |||
399 | static int neponset_resume(struct device *dev) | ||
400 | { | ||
401 | struct neponset_drvdata *d = dev_get_drvdata(dev); | ||
402 | |||
403 | writeb_relaxed(d->ncr0, d->base + NCR_0); | ||
404 | writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0); | ||
405 | |||
406 | return 0; | ||
407 | } | ||
408 | |||
409 | static const struct dev_pm_ops neponset_pm_ops = { | ||
410 | .suspend_noirq = neponset_suspend, | ||
411 | .resume_noirq = neponset_resume, | ||
412 | .freeze_noirq = neponset_suspend, | ||
413 | .restore_noirq = neponset_resume, | ||
414 | }; | ||
415 | #define PM_OPS &neponset_pm_ops | ||
416 | #else | ||
417 | #define PM_OPS NULL | ||
418 | #endif | ||
419 | |||
420 | static struct platform_driver neponset_device_driver = { | ||
421 | .probe = neponset_probe, | ||
422 | .remove = __devexit_p(neponset_remove), | ||
423 | .driver = { | ||
424 | .name = "neponset", | ||
425 | .owner = THIS_MODULE, | ||
426 | .pm = PM_OPS, | ||
427 | }, | ||
341 | }; | 428 | }; |
342 | 429 | ||
343 | void __init neponset_map_io(void) | 430 | static int __init neponset_init(void) |
344 | { | 431 | { |
345 | iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc)); | 432 | return platform_driver_register(&neponset_device_driver); |
346 | } | 433 | } |
434 | |||
435 | subsys_initcall(neponset_init); | ||
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c index 0d01ca788922..41bb018b3103 100644 --- a/arch/arm/mach-sa1100/pci-nanoengine.c +++ b/arch/arm/mach-sa1100/pci-nanoengine.c | |||
@@ -135,12 +135,8 @@ struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys | |||
135 | &sys->resources); | 135 | &sys->resources); |
136 | } | 136 | } |
137 | 137 | ||
138 | static struct resource pci_io_ports = { | 138 | static struct resource pci_io_ports = |
139 | .name = "PCI IO", | 139 | DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); |
140 | .start = 0x400, | ||
141 | .end = 0x7FF, | ||
142 | .flags = IORESOURCE_IO, | ||
143 | }; | ||
144 | 140 | ||
145 | static struct resource pci_non_prefetchable_memory = { | 141 | static struct resource pci_non_prefetchable_memory = { |
146 | .name = "PCI non-prefetchable", | 142 | .name = "PCI non-prefetchable", |
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index 9307df053533..ca5d33b6041a 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c | |||
@@ -37,17 +37,9 @@ | |||
37 | #define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21 | 37 | #define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21 |
38 | 38 | ||
39 | static struct resource smc91x_resources[] = { | 39 | static struct resource smc91x_resources[] = { |
40 | [0] = { | 40 | [0] = DEFINE_RES_MEM(PLEB_ETH0_P, 0x04000000), |
41 | .start = PLEB_ETH0_P, | ||
42 | .end = PLEB_ETH0_P | 0x03ffffff, | ||
43 | .flags = IORESOURCE_MEM, | ||
44 | }, | ||
45 | #if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */ | 41 | #if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */ |
46 | [1] = { | 42 | [1] = DEFINE_RES_IRQ(IRQ_GPIO_ETH0_IRQ), |
47 | .start = IRQ_GPIO_ETH0_IRQ, | ||
48 | .end = IRQ_GPIO_ETH0_IRQ, | ||
49 | .flags = IORESOURCE_IRQ, | ||
50 | }, | ||
51 | #endif | 43 | #endif |
52 | }; | 44 | }; |
53 | 45 | ||
@@ -70,16 +62,8 @@ static struct platform_device *devices[] __initdata = { | |||
70 | * the two SA1100 lowest chip select outputs. | 62 | * the two SA1100 lowest chip select outputs. |
71 | */ | 63 | */ |
72 | static struct resource pleb_flash_resources[] = { | 64 | static struct resource pleb_flash_resources[] = { |
73 | [0] = { | 65 | [0] = DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_8M), |
74 | .start = SA1100_CS0_PHYS, | 66 | [1] = DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_8M), |
75 | .end = SA1100_CS0_PHYS + SZ_8M - 1, | ||
76 | .flags = IORESOURCE_MEM, | ||
77 | }, | ||
78 | [1] = { | ||
79 | .start = SA1100_CS1_PHYS, | ||
80 | .end = SA1100_CS1_PHYS + SZ_8M - 1, | ||
81 | .flags = IORESOURCE_MEM, | ||
82 | } | ||
83 | }; | 67 | }; |
84 | 68 | ||
85 | 69 | ||
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index c695b730bd69..77b2b9b522ac 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c | |||
@@ -48,11 +48,8 @@ static struct flash_platform_data shannon_flash_data = { | |||
48 | .nr_parts = ARRAY_SIZE(shannon_partitions), | 48 | .nr_parts = ARRAY_SIZE(shannon_partitions), |
49 | }; | 49 | }; |
50 | 50 | ||
51 | static struct resource shannon_flash_resource = { | 51 | static struct resource shannon_flash_resource = |
52 | .start = SA1100_CS0_PHYS, | 52 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_4M); |
53 | .end = SA1100_CS0_PHYS + SZ_4M - 1, | ||
54 | .flags = IORESOURCE_MEM, | ||
55 | }; | ||
56 | 53 | ||
57 | static struct mcp_plat_data shannon_mcp_data = { | 54 | static struct mcp_plat_data shannon_mcp_data = { |
58 | .mccr0 = MCCR0_ADM, | 55 | .mccr0 = MCCR0_ADM, |
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index e17c04d6e324..cdb9d197c092 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c | |||
@@ -176,15 +176,8 @@ static struct flash_platform_data simpad_flash_data = { | |||
176 | 176 | ||
177 | 177 | ||
178 | static struct resource simpad_flash_resources [] = { | 178 | static struct resource simpad_flash_resources [] = { |
179 | { | 179 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M), |
180 | .start = SA1100_CS0_PHYS, | 180 | DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M), |
181 | .end = SA1100_CS0_PHYS + SZ_16M -1, | ||
182 | .flags = IORESOURCE_MEM, | ||
183 | }, { | ||
184 | .start = SA1100_CS1_PHYS, | ||
185 | .end = SA1100_CS1_PHYS + SZ_16M -1, | ||
186 | .flags = IORESOURCE_MEM, | ||
187 | } | ||
188 | }; | 181 | }; |
189 | 182 | ||
190 | static struct mcp_plat_data simpad_mcp_data = { | 183 | static struct mcp_plat_data simpad_mcp_data = { |
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S index e8223315b442..30cc6721665b 100644 --- a/arch/arm/mach-sa1100/sleep.S +++ b/arch/arm/mach-sa1100/sleep.S | |||
@@ -26,27 +26,36 @@ | |||
26 | * | 26 | * |
27 | * Causes sa11x0 to enter sleep state | 27 | * Causes sa11x0 to enter sleep state |
28 | * | 28 | * |
29 | * Must be aligned to a cacheline. | ||
29 | */ | 30 | */ |
30 | 31 | .balign 32 | |
31 | ENTRY(sa1100_finish_suspend) | 32 | ENTRY(sa1100_finish_suspend) |
32 | @ disable clock switching | 33 | @ disable clock switching |
33 | mcr p15, 0, r1, c15, c2, 2 | 34 | mcr p15, 0, r1, c15, c2, 2 |
34 | 35 | ||
35 | @ Adjust memory timing before lowering CPU clock | 36 | ldr r6, =MDREFR |
36 | @ Clock speed adjustment without changing memory timing makes | 37 | ldr r4, [r6] |
37 | @ CPU hang in some cases | 38 | orr r4, r4, #MDREFR_K1DB2 |
38 | ldr r0, =MDREFR | 39 | ldr r5, =PPCR |
39 | ldr r1, [r0] | 40 | |
40 | orr r1, r1, #MDREFR_K1DB2 | 41 | @ Pre-load __udelay into the I-cache |
41 | str r1, [r0] | 42 | mov r0, #1 |
43 | bl __udelay | ||
44 | mov r0, r0 | ||
45 | |||
46 | @ The following must all exist in a single cache line to | ||
47 | @ avoid accessing memory until this sequence is complete, | ||
48 | @ otherwise we occasionally hang. | ||
49 | |||
50 | @ Adjust memory timing before lowering CPU clock | ||
51 | str r4, [r6] | ||
42 | 52 | ||
43 | @ delay 90us and set CPU PLL to lowest speed | 53 | @ delay 90us and set CPU PLL to lowest speed |
44 | @ fixes resume problem on high speed SA1110 | 54 | @ fixes resume problem on high speed SA1110 |
45 | mov r0, #90 | 55 | mov r0, #90 |
46 | bl __udelay | 56 | bl __udelay |
47 | ldr r0, =PPCR | ||
48 | mov r1, #0 | 57 | mov r1, #0 |
49 | str r1, [r0] | 58 | str r1, [r5] |
50 | mov r0, #90 | 59 | mov r0, #90 |
51 | bl __udelay | 60 | bl __udelay |
52 | 61 | ||
@@ -85,12 +94,10 @@ ENTRY(sa1100_finish_suspend) | |||
85 | bic r5, r5, #FMsk(MSC_RT) | 94 | bic r5, r5, #FMsk(MSC_RT) |
86 | bic r5, r5, #FMsk(MSC_RT)<<16 | 95 | bic r5, r5, #FMsk(MSC_RT)<<16 |
87 | 96 | ||
88 | ldr r6, =MDREFR | ||
89 | |||
90 | ldr r7, [r6] | 97 | ldr r7, [r6] |
91 | bic r7, r7, #0x0000FF00 | 98 | bic r7, r7, #0x0000FF00 |
92 | bic r7, r7, #0x000000F0 | 99 | bic r7, r7, #0x000000F0 |
93 | orr r8, r7, #MDREFR_SLFRSH | 100 | orr r8, r7, #MDREFR_SLFRSH |
94 | 101 | ||
95 | ldr r9, =MDCNFG | 102 | ldr r9, =MDCNFG |
96 | ldr r10, [r9] | 103 | ldr r10, [r9] |