2 files changed, 2 insertions, 4 deletions

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0816562725f6..d54cfc54b9fe 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -104,7 +104,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "clk_m",      NULL,           0,              true },
-        { "pll_p",      "clk_m",        408000000,      true },
+        { "pll_p",      "pll_ref",      408000000,      true },
         { "pll_p_out1", "pll_p",        9600000,        true },
         { "pll_p_out4", "pll_p",        102000000,      true },
         { "sclk",       "pll_p_out4",   102000000,      true },
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index efc000e32e1c..d7147779f8ea 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2045,9 +2045,7 @@ struct clk_ops tegra30_periph_clk_ops = {
 static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
 {
         struct clk *d = clk_get_sys(NULL, "pll_d");
-        /* The DSIB parent selection bit is in PLLD base
-           register - can not do direct r-m-w, must be
-           protected by PLLD lock */
+        /* The DSIB parent selection bit is in PLLD base register */
         tegra_clk_cfg_ex(
                 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);