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-rw-r--r--arch/powerpc/include/asm/reg.h15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6136515c7f2..8f6a94b2dc99 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -113,14 +113,15 @@
113 113
114/* Reason codes describing kernel causes for transaction aborts. By 114/* Reason codes describing kernel causes for transaction aborts. By
115 convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if 115 convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
116 the failure is persistent. 116 the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor.
117*/ 117*/
118#define TM_CAUSE_RESCHED 0xfe 118#define TM_CAUSE_PERSISTENT 0x01
119#define TM_CAUSE_TLBI 0xfc 119#define TM_CAUSE_RESCHED 0xde
120#define TM_CAUSE_FAC_UNAV 0xfa 120#define TM_CAUSE_TLBI 0xdc
121#define TM_CAUSE_SYSCALL 0xf9 /* Persistent */ 121#define TM_CAUSE_FAC_UNAV 0xda
122#define TM_CAUSE_MISC 0xf6 122#define TM_CAUSE_SYSCALL 0xd8 /* future use */
123#define TM_CAUSE_SIGNAL 0xf4 123#define TM_CAUSE_MISC 0xd6 /* future use */
124#define TM_CAUSE_SIGNAL 0xd4
124 125
125#if defined(CONFIG_PPC_BOOK3S_64) 126#if defined(CONFIG_PPC_BOOK3S_64)
126#define MSR_64BIT MSR_SF 127#define MSR_64BIT MSR_SF