1 files changed, 100 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index d4dbc4950936..8bc479634643 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -9,9 +9,63 @@ enum pnv_phb_type {
        PNV_PHB_IODA2,
 };
+/* Precise PHB model for error management */
+enum pnv_phb_model {
+        PNV_PHB_MODEL_UNKNOWN,
+        PNV_PHB_MODEL_P5IOC2,
+        PNV_PHB_MODEL_P7IOC,
+};
+#define PNV_PCI_DIAG_BUF_SIZE   4096
+/* Data associated with a PE, including IOMMU tracking etc.. */
+struct pnv_ioda_pe {
+        /* A PE can be associated with a single device or an
+         * entire bus (& children). In the former case, pdev
+         * is populated, in the later case, pbus is.
+         */
+        struct pci_dev          *pdev;
+        struct pci_bus          *pbus;
+        /* Effective RID (device RID for a device PE and base bus
+         * RID with devfn 0 for a bus PE)
+         */
+        unsigned int            rid;
+        /* PE number */
+        unsigned int            pe_number;
+        /* "Weight" assigned to the PE for the sake of DMA resource
+         * allocations
+         */
+        unsigned int            dma_weight;
+        /* This is a PCI-E -> PCI-X bridge, this points to the
+         * corresponding bus PE
+         */
+        struct pnv_ioda_pe      *bus_pe;
+        /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
+        int                     tce32_seg;
+        int                     tce32_segcount;
+        struct iommu_table      tce32_table;
+        /* XXX TODO: Add support for additional 64-bit iommus */
+        /* MSIs. MVE index is identical for for 32 and 64 bit MSI
+         * and -1 if not supported. (It's actually identical to the
+         * PE number)
+         */
+        int                     mve_number;
+        /* Link in list of PE#s */
+        struct list_head        link;
+};
 struct pnv_phb {
        struct pci_controller   *hose;
        enum pnv_phb_type       type;
+        enum pnv_phb_model      model;
        u64                     opal_id;
        void __iomem            *regs;
        spinlock_t              lock;
@@ -34,7 +88,52 @@ struct pnv_phb {
                struct {
                        struct iommu_table iommu_table;
                } p5ioc2;
+                struct {
+                        /* Global bridge info */
+                        unsigned int            total_pe;
+                        unsigned int            m32_size;
+                        unsigned int            m32_segsize;
+                        unsigned int            m32_pci_base;
+                        unsigned int            io_size;
+                        unsigned int            io_segsize;
+                        unsigned int            io_pci_base;
+                        /* PE allocation bitmap */
+                        unsigned long           *pe_alloc;
+                        /* M32 & IO segment maps */
+                        unsigned int            *m32_segmap;
+                        unsigned int            *io_segmap;
+                        struct pnv_ioda_pe      *pe_array;
+                        /* Reverse map of PEs, will have to extend if
+                         * we are to support more than 256 PEs, indexed
+                         * bus { bus, devfn }
+                         */
+                        unsigned char           pe_rmap[0x10000];
+                        /* 32-bit TCE tables allocation */
+                        unsigned long           tce32_count;
+                        /* Total "weight" for the sake of DMA resources
+                         * allocation
+                         */
+                        unsigned int            dma_weight;
+                        unsigned int            dma_pe_count;
+                        /* Sorted list of used PE's, sorted at
+                         * boot for resource allocation purposes
+                         */
+                        struct list_head        pe_list;
+                } ioda;
        };
+        /* PHB status structure */
+        union {
+                unsigned char                   blob[PNV_PCI_DIAG_BUF_SIZE];
+                struct OpalIoP7IOCPhbErrorData  p7ioc;
+        } diag;
 };
 extern struct pci_ops pnv_pci_ops;
@@ -43,6 +142,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                      void *tce_mem, u64 tce_size,
                                      u64 dma_offset);
 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
+extern void pnv_pci_init_ioda_hub(struct device_node *np);
 #endif /* __POWERNV_PCI_H */

diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index d4dbc4950936..8bc479634643 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h
@@ -9,9 +9,63 @@ enum pnv_phb_type {
9	PNV_PHB_IODA2,	9	PNV_PHB_IODA2,
10	};	10	};
11		11
		12	/* Precise PHB model for error management */
		13	enum pnv_phb_model {
		14	PNV_PHB_MODEL_UNKNOWN,
		15	PNV_PHB_MODEL_P5IOC2,
		16	PNV_PHB_MODEL_P7IOC,
		17	};
		18
		19	#define PNV_PCI_DIAG_BUF_SIZE 4096
		20
		21	/* Data associated with a PE, including IOMMU tracking etc.. */
		22	struct pnv_ioda_pe {
		23	/* A PE can be associated with a single device or an
		24	* entire bus (& children). In the former case, pdev
		25	* is populated, in the later case, pbus is.
		26	*/
		27	struct pci_dev *pdev;
		28	struct pci_bus *pbus;
		29
		30	/* Effective RID (device RID for a device PE and base bus
		31	* RID with devfn 0 for a bus PE)
		32	*/
		33	unsigned int rid;
		34
		35	/* PE number */
		36	unsigned int pe_number;
		37
		38	/* "Weight" assigned to the PE for the sake of DMA resource
		39	* allocations
		40	*/
		41	unsigned int dma_weight;
		42
		43	/* This is a PCI-E -> PCI-X bridge, this points to the
		44	* corresponding bus PE
		45	*/
		46	struct pnv_ioda_pe *bus_pe;
		47
		48	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
		49	int tce32_seg;
		50	int tce32_segcount;
		51	struct iommu_table tce32_table;
		52
		53	/* XXX TODO: Add support for additional 64-bit iommus */
		54
		55	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
		56	* and -1 if not supported. (It's actually identical to the
		57	* PE number)
		58	*/
		59	int mve_number;
		60
		61	/* Link in list of PE#s */
		62	struct list_head link;
		63	};
		64
12	struct pnv_phb {	65	struct pnv_phb {
13	struct pci_controller *hose;	66	struct pci_controller *hose;
14	enum pnv_phb_type type;	67	enum pnv_phb_type type;
		68	enum pnv_phb_model model;
15	u64 opal_id;	69	u64 opal_id;
16	void __iomem *regs;	70	void __iomem *regs;
17	spinlock_t lock;	71	spinlock_t lock;
@@ -34,7 +88,52 @@ struct pnv_phb {
34	struct {	88	struct {
35	struct iommu_table iommu_table;	89	struct iommu_table iommu_table;
36	} p5ioc2;	90	} p5ioc2;
		91
		92	struct {
		93	/* Global bridge info */
		94	unsigned int total_pe;
		95	unsigned int m32_size;
		96	unsigned int m32_segsize;
		97	unsigned int m32_pci_base;
		98	unsigned int io_size;
		99	unsigned int io_segsize;
		100	unsigned int io_pci_base;
		101
		102	/* PE allocation bitmap */
		103	unsigned long *pe_alloc;
		104
		105	/* M32 & IO segment maps */
		106	unsigned int *m32_segmap;
		107	unsigned int *io_segmap;
		108	struct pnv_ioda_pe *pe_array;
		109
		110	/* Reverse map of PEs, will have to extend if
		111	* we are to support more than 256 PEs, indexed
		112	* bus { bus, devfn }
		113	*/
		114	unsigned char pe_rmap[0x10000];
		115
		116	/* 32-bit TCE tables allocation */
		117	unsigned long tce32_count;
		118
		119	/* Total "weight" for the sake of DMA resources
		120	* allocation
		121	*/
		122	unsigned int dma_weight;
		123	unsigned int dma_pe_count;
		124
		125	/* Sorted list of used PE's, sorted at
		126	* boot for resource allocation purposes
		127	*/
		128	struct list_head pe_list;
		129	} ioda;
37	};	130	};
		131
		132	/* PHB status structure */
		133	union {
		134	unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
		135	struct OpalIoP7IOCPhbErrorData p7ioc;
		136	} diag;
38	};	137	};
39		138
40	extern struct pci_ops pnv_pci_ops;	139	extern struct pci_ops pnv_pci_ops;
@@ -43,6 +142,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
43	void *tce_mem, u64 tce_size,	142	void *tce_mem, u64 tce_size,
44	u64 dma_offset);	143	u64 dma_offset);
45	extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);	144	extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
		145	extern void pnv_pci_init_ioda_hub(struct device_node *np);
46		146
47		147
48	#endif /* __POWERNV_PCI_H */	148	#endif /* __POWERNV_PCI_H */