21 files changed, 778 insertions, 113 deletions

diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d7946be298b6..f000d81c4e31 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -6,6 +6,7 @@ menuconfig FSL_SOC_BOOKE
         select MPIC
         select PPC_PCI_CHOICE
         select FSL_PCI if PCI
+        select SERIAL_8250_EXTENDED if SERIAL_8250
         select SERIAL_8250_SHARE_IRQ if SERIAL_8250
         default y
 
@@ -13,6 +14,15 @@ if FSL_SOC_BOOKE
 
 if PPC32
 
+config FSL_85XX_CACHE_SRAM
+        bool
+        select PPC_LIB_RHEAP
+        help
+          When selected, this option enables cache-sram support
+          for memory allocation on P1/P2 QorIQ platforms.
+          cache-sram-size and cache-sram-offset kernel boot
+          parameters should be passed when this option is enabled.
+
 config MPC8540_ADS
         bool "Freescale MPC8540 ADS"
         select DEFAULT_UIMAGE
@@ -30,6 +40,7 @@ config MPC85xx_CDS
         bool "Freescale MPC85xx CDS"
         select DEFAULT_UIMAGE
         select PPC_I8259
+        select HAS_RAPIDIO
         help
           This option enables support for the MPC85xx CDS board
 
@@ -80,7 +91,6 @@ config P1010_RDB
 config P1022_DS
         bool "Freescale P1022 DS"
         select DEFAULT_UIMAGE
-        select PHYS_64BIT       # The DTS has 36-bit addresses
         select SWIOTLB
         help
           This option enables support for the Freescale P1022DS reference board.
@@ -171,6 +181,21 @@ config SBC8560
         help
           This option enables support for the Wind River SBC8560 board
 
+config GE_IMP3A
+        bool "GE Intelligent Platforms IMP3A"
+        select DEFAULT_UIMAGE
+        select SWIOTLB
+        select MMIO_NVRAM
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select GE_FPGA
+        help
+          This option enables support for the GE Intelligent Platforms IMP3A
+          board.
+
+          This board is a 3U CompactPCI Single Board Computer with a Freescale
+          P2020 processor.
+
 config P2041_RDB
         bool "Freescale P2041 RDB"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9cb2d4320dcc..2125d4ca068a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_SBC8548)     += sbc8548.o
 obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 obj-$(CONFIG_KSI8560)     += ksi8560.o
 obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
+obj-$(CONFIG_GE_IMP3A)    += ge_imp3a.o
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 07e3e6c47371..df69e99e511c 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -36,8 +36,8 @@
 void __init corenet_ds_pic_init(void)
 {
         struct mpic *mpic;
-        unsigned int flags = MPIC_BIG_ENDIAN |
-                                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
+        unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
+                MPIC_NO_RESET;
 
         if (ppc_md.get_irq == mpic_get_coreint_irq)
                 flags |= MPIC_ENABLE_COREINT;
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
new file mode 100644
index 000000000000..d50056f424f6
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -0,0 +1,246 @@
+/*
+ * GE IMP3A Board Setup
+ *
+ * Author Martyn Welch <martyn.welch@ge.com>
+ *
+ * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
+ * Copyright 2007 Freescale Semiconductor Inc.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/memblock.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+#include <asm/nvram.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+#include <sysdev/ge/ge_pic.h>
+
+void __iomem *imp3a_regs;
+
+void __init ge_imp3a_pic_init(void)
+{
+        struct mpic *mpic;
+        struct device_node *np;
+        struct device_node *cascade_node = NULL;
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
+                mpic = mpic_alloc(NULL, 0,
+                        MPIC_NO_RESET |
+                        MPIC_BIG_ENDIAN |
+                        MPIC_SINGLE_DEST_CPU,
+                        0, 256, " OpenPIC  ");
+        } else {
+                mpic = mpic_alloc(NULL, 0,
+                          MPIC_BIG_ENDIAN |
+                          MPIC_SINGLE_DEST_CPU,
+                        0, 256, " OpenPIC  ");
+        }
+
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+        /*
+         * There is a simple interrupt handler in the main FPGA, this needs
+         * to be cascaded into the MPIC
+         */
+        for_each_node_by_type(np, "interrupt-controller")
+                if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
+                        cascade_node = np;
+                        break;
+                }
+
+        if (cascade_node == NULL) {
+                printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
+                return;
+        }
+
+        gef_pic_init(cascade_node);
+        of_node_put(cascade_node);
+}
+
+#ifdef CONFIG_PCI
+static int primary_phb_addr;
+#endif  /* CONFIG_PCI */
+
+/*
+ * Setup the architecture
+ */
+static void __init ge_imp3a_setup_arch(void)
+{
+        struct device_node *regs;
+#ifdef CONFIG_PCI
+        struct device_node *np;
+        struct pci_controller *hose;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("ge_imp3a_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_node_by_type(np, "pci") {
+                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
+                    of_device_is_compatible(np, "fsl,p2020-pcie")) {
+                        struct resource rsrc;
+                        of_address_to_resource(np, 0, &rsrc);
+                        if ((rsrc.start & 0xfffff) == primary_phb_addr)
+                                fsl_add_bridge(np, 1);
+                        else
+                                fsl_add_bridge(np, 0);
+
+                        hose = pci_find_hose_for_OF_device(np);
+                        max = min(max, hose->dma_window_base_cur +
+                                        hose->dma_window_size);
+                }
+        }
+#endif
+
+        mpc85xx_smp_init();
+
+#ifdef CONFIG_SWIOTLB
+        if (memblock_end_of_DRAM() > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+
+        /* Remap basic board registers */
+        regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
+        if (regs) {
+                imp3a_regs = of_iomap(regs, 0);
+                if (imp3a_regs == NULL)
+                        printk(KERN_WARNING "Unable to map board registers\n");
+                of_node_put(regs);
+        }
+
+#if defined(CONFIG_MMIO_NVRAM)
+        mmio_nvram_init();
+#endif
+
+        printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
+}
+
+/* Return the PCB revision */
+static unsigned int ge_imp3a_get_pcb_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs);
+        return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int ge_imp3a_get_board_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x2);
+        return reg & 0xff;
+}
+
+/* Return the FPGA revision */
+static unsigned int ge_imp3a_get_fpga_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x2);
+        return (reg >> 8) & 0xff;
+}
+
+/* Return compactPCI Geographical Address */
+static unsigned int ge_imp3a_get_cpci_geo_addr(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x6);
+        return (reg & 0x0f00) >> 8;
+}
+
+/* Return compactPCI System Controller Status */
+static unsigned int ge_imp3a_get_cpci_is_syscon(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x6);
+        return reg & (1 << 12);
+}
+
+static void ge_imp3a_show_cpuinfo(struct seq_file *m)
+{
+        seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
+
+        seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
+                ('A' + ge_imp3a_get_board_rev() - 1));
+
+        seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
+
+        seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
+
+        seq_printf(m, "cPCI syscon\t: %s\n",
+                ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ge_imp3a_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
+#ifdef CONFIG_PCI
+                primary_phb_addr = 0x9000;
+#endif
+                return 1;
+        }
+
+        return 0;
+}
+
+machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
+
+machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
+
+define_machine(ge_imp3a) {
+        .name                   = "GE_IMP3A",
+        .probe                  = ge_imp3a_probe,
+        .setup_arch             = ge_imp3a_setup_arch,
+        .init_IRQ               = ge_imp3a_pic_init,
+        .show_cpuinfo           = ge_imp3a_show_cpuinfo,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index 20f75d7819c6..60120e55da41 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -57,8 +57,7 @@ static void machine_restart(char *cmd)
 
 static void __init ksi8560_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index cf266826682e..f58872688d8f 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -36,9 +36,7 @@
 
 void __init mpc8536_ds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                          MPIC_WANTS_RESET |
-                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 3bebb5173bfc..d19f675cb369 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -50,8 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
 
 static void __init mpc85xx_ads_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 40f03da616a9..ab5f0bf19454 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -3,7 +3,7 @@
  *
  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  *
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -48,17 +48,24 @@
 
 #include "mpc85xx.h"
 
-/* CADMUS info */
-/* xxx - galak, move into device tree */
-#define CADMUS_BASE (0xf8004000)
-#define CADMUS_SIZE (256)
-#define CM_VER  (0)
-#define CM_CSR  (1)
-#define CM_RST  (2)
-
+/*
+ * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
+ * various logic and performs system control functions.
+ * Here is the FPGA/CPLD register map.
+ */
+struct cadmus_reg {
+        u8 cm_ver;              /* Board version */
+        u8 cm_csr;              /* General control/status */
+        u8 cm_rst;              /* Reset control */
+        u8 cm_hsclk;    /* High speed clock */
+        u8 cm_hsxclk;   /* High speed clock extended */
+        u8 cm_led;              /* LED data */
+        u8 cm_pci;              /* PCI control/status */
+        u8 cm_dma;              /* DMA control */
+        u8 res[248];    /* Total 256 bytes */
+};
 
-static int cds_pci_slot = 2;
-static volatile u8 *cadmus;
+static struct cadmus_reg *cadmus;
 
 #ifdef CONFIG_PCI
 
@@ -158,6 +165,33 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 
+#define PCI_DEVICE_ID_IDT_TSI310        0x01a7
+
+/*
+ * Fix Tsi310 PCI-X bridge resource.
+ * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
+ * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
+ */
+void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
+{
+        struct pci_dev *dev = bus->self;
+        struct resource *res = bus->resource[0];
+
+        if (dev != NULL &&
+            dev->vendor == PCI_VENDOR_ID_IBM &&
+            dev->device == PCI_DEVICE_ID_IDT_TSI310) {
+                if (res) {
+                        res->start = 0;
+                        res->end   = 0x1fff;
+                        res->flags = IORESOURCE_IO;
+                        pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
+                        pr_info("mpc85xx_cds: %pR\n", res);
+                }
+        }
+
+        fsl_pcibios_fixup_bus(bus);
+}
+
 #ifdef CONFIG_PPC_I8259
 static void mpc85xx_8259_cascade_handler(unsigned int irq,
                                          struct irq_desc *desc)
@@ -188,8 +222,7 @@ static struct irqaction mpc85xxcds_8259_irqaction = {
 static void __init mpc85xx_cds_pic_init(void)
 {
         struct mpic *mpic;
-        mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
@@ -249,20 +282,30 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
  */
 static void __init mpc85xx_cds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
         struct device_node *np;
-#endif
+        int cds_pci_slot;
 
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 
-        cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
-        cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
+        if (!np) {
+                pr_err("Could not find FPGA node.\n");
+                return;
+        }
+
+        cadmus = of_iomap(np, 0);
+        of_node_put(np);
+        if (!cadmus) {
+                pr_err("Fail to map FPGA area.\n");
+                return;
+        }
 
         if (ppc_md.progress) {
                 char buf[40];
+                cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
-                                cadmus[CM_VER], cds_pci_slot);
+                                in_8(&cadmus->cm_ver), cds_pci_slot);
                 ppc_md.progress(buf, 0);
         }
 
@@ -292,7 +335,8 @@ static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
         svid = mfspr(SPRN_SVR);
 
         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
-        seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
+        seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
+                        in_8(&cadmus->cm_ver));
         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 
@@ -323,7 +367,7 @@ define_machine(mpc85xx_cds) {
         .get_irq        = mpic_get_irq,
 #ifdef CONFIG_PCI
         .restart        = mpc85xx_cds_restart,
-        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_bus      = mpc85xx_cds_fixup_bus,
 #else
         .restart        = fsl_rstcr_restart,
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index eefbb91e1d61..6e23e3e34bd9 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -72,13 +72,13 @@ void __init mpc85xx_ds_pic_init(void)
 
         if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
                 mpic = mpic_alloc(NULL, 0,
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                        MPIC_NO_RESET |
+                        MPIC_BIG_ENDIAN |
                         MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         } else {
                 mpic = mpic_alloc(NULL, 0,
-                          MPIC_WANTS_RESET |
-                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                          MPIC_BIG_ENDIAN |
                           MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0cd2c82..f33662b46b8d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
+ * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
+ * All rights reserved.
  *
  * Author: Andy Fleming <afleming@freescale.com>
  *
@@ -51,6 +52,7 @@
 #include <asm/qe_ic.h>
 #include <asm/mpic.h>
 #include <asm/swiotlb.h>
+#include <asm/fsl_guts.h>
 #include "smp.h"
 
 #include "mpc85xx.h"
@@ -268,34 +270,27 @@ static void __init mpc85xx_mds_qe_init(void)
         mpc85xx_mds_reset_ucc_phys();
 
         if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET           0x60
-#define MPC85xx_PMUXCR_QE0              0x00008000
-#define MPC85xx_PMUXCR_QE3              0x00001000
-#define MPC85xx_PMUXCR_QE9              0x00000040
-#define MPC85xx_PMUXCR_QE12             0x00000008
-                static __be32 __iomem *pmuxcr;
 
-                np = of_find_node_by_name(NULL, "global-utilities");
+                struct ccsr_guts_85xx __iomem *guts;
 
+                np = of_find_node_by_name(NULL, "global-utilities");
                 if (np) {
-                        pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
-
-                        if (!pmuxcr)
-                                printk(KERN_EMERG "Error: Alternate function"
-                                        " signal multiplex control register not"
-                                        " mapped!\n");
-                        else
+                        guts = of_iomap(np, 0);
+                        if (!guts)
+                                pr_err("mpc85xx-rdb: could not map global utilities register\n");
+                        else{
                         /* P1021 has pins muxed for QE and other functions. To
                          * enable QE UEC mode, we need to set bit QE0 for UCC1
                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
                          * and QE12 for QE MII management signals in PMUXCR
                          * register.
                          */
-                                setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
-                                                  MPC85xx_PMUXCR_QE3 |
-                                                  MPC85xx_PMUXCR_QE9 |
-                                                  MPC85xx_PMUXCR_QE12);
-
+                                setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+                                                  MPC85xx_PMUXCR_QE(3) |
+                                                  MPC85xx_PMUXCR_QE(9) |
+                                                  MPC85xx_PMUXCR_QE(12));
+                                iounmap(guts);
+                        }
                         of_node_put(np);
                 }
 
@@ -434,9 +429,8 @@ machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 
 static void __init mpc85xx_mds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                        MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                        MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e890be..db214cd4c822 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
 /*
  * MPC85xx RDB Board Setup
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -26,6 +26,9 @@
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/mpic.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+#include <asm/fsl_guts.h>
 
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
@@ -47,21 +50,36 @@ void __init mpc85xx_rdb_pic_init(void)
         struct mpic *mpic;
         unsigned long root = of_get_flat_dt_root();
 
+#ifdef CONFIG_QUICC_ENGINE
+        struct device_node *np;
+#endif
+
         if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
-                mpic = mpic_alloc(NULL, 0,
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
+                        MPIC_BIG_ENDIAN |
                         MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         } else {
                 mpic = mpic_alloc(NULL, 0,
-                  MPIC_WANTS_RESET |
-                  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                  MPIC_BIG_ENDIAN |
                   MPIC_SINGLE_DEST_CPU,
                   0, 256, " OpenPIC  ");
         }
 
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (np) {
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+                of_node_put(np);
+
+        } else
+                pr_err("%s: Could not find qe-ic node\n", __func__);
+#endif
+
 }
 
 /*
@@ -69,7 +87,7 @@ void __init mpc85xx_rdb_pic_init(void)
  */
 static void __init mpc85xx_rdb_setup_arch(void)
 {
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
         struct device_node *np;
 #endif
 
@@ -85,11 +103,73 @@ static void __init mpc85xx_rdb_setup_arch(void)
 #endif
 
         mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!np) {
+                pr_err("%s: Could not find Quicc Engine node\n", __func__);
+                goto qe_fail;
+        }
+
+        qe_reset();
+        of_node_put(np);
+
+        np = of_find_node_by_name(NULL, "par_io");
+        if (np) {
+                struct device_node *ucc;
+
+                par_io_init(np);
+                of_node_put(np);
+
+                for_each_node_by_name(ucc, "ucc")
+                        par_io_of_config(ucc);
+
+        }
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+        if (machine_is(p1025_rdb)) {
+
+                struct ccsr_guts_85xx __iomem *guts;
+
+                np = of_find_node_by_name(NULL, "global-utilities");
+                if (np) {
+                        guts = of_iomap(np, 0);
+                        if (!guts) {
+
+                                pr_err("mpc85xx-rdb: could not map global utilities register\n");
+
+                        } else {
+                        /* P1025 has pins muxed for QE and other functions. To
+                        * enable QE UEC mode, we need to set bit QE0 for UCC1
+                        * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+                        * and QE12 for QE MII management singals in PMUXCR
+                        * register.
+                        */
+                                setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+                                                MPC85xx_PMUXCR_QE(3) |
+                                                MPC85xx_PMUXCR_QE(9) |
+                                                MPC85xx_PMUXCR_QE(12));
+                                iounmap(guts);
+                        }
+                        of_node_put(np);
+                }
+
+        }
+#endif
+
+qe_fail:
+#endif  /* CONFIG_QUICC_ENGINE */
+
         printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
 }
 
 machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
 machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
@@ -112,6 +192,52 @@ static int __init p1020_rdb_probe(void)
         return 0;
 }
 
+static int __init p1020_rdb_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
+}
+
+static int __init p1021_rdb_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC"))
+                return 1;
+        return 0;
+}
+
+static int __init p2020_rdb_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC"))
+                return 1;
+        return 0;
+}
+
+static int __init p1025_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1025RDB");
+}
+
+static int __init p1020_mbg_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC");
+}
+
+static int __init p1020_utm_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
+}
+
 define_machine(p2020_rdb) {
         .name                   = "P2020 RDB",
         .probe                  = p2020_rdb_probe,
@@ -139,3 +265,87 @@ define_machine(p1020_rdb) {
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
 };
+
+define_machine(p1021_rdb_pc) {
+        .name                   = "P1021 RDB-PC",
+        .probe                  = p1021_rdb_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p2020_rdb_pc) {
+        .name                   = "P2020RDB-PC",
+        .probe                  = p2020_rdb_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1025_rdb) {
+        .name                   = "P1025 RDB",
+        .probe                  = p1025_rdb_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1020_mbg_pc) {
+        .name                   = "P1020 MBG-PC",
+        .probe                  = p1020_mbg_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1020_utm_pc) {
+        .name                   = "P1020 UTM-PC",
+        .probe                  = p1020_utm_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1020_rdb_pc) {
+        .name                   = "P1020RDB-PC",
+        .probe                  = p1020_rdb_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index 538bc3f57e9d..d8bd6563d9ca 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -32,9 +32,8 @@
 
 void __init p1010_rdb_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-          MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-          MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+          MPIC_SINGLE_DEST_CPU,
           0, 256, " OpenPIC  ");
 
         BUG_ON(mpic == NULL);
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index bb3d84f4046f..0fe88e39945e 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -25,6 +25,7 @@
 
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include <asm/udbg.h>
 #include <asm/fsl_guts.h>
 #include "smp.h"
 
@@ -32,6 +33,10 @@
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 
+#define PMUXCR_ELBCDIU_MASK     0xc0000000
+#define PMUXCR_ELBCDIU_NOR16    0x80000000
+#define PMUXCR_ELBCDIU_DIU      0x40000000
+
 /*
  * Board-specific initialization of the DIU.  This code should probably be
  * executed when the DIU is opened, rather than in arch code, but the DIU
@@ -49,11 +54,22 @@
 #define CLKDVDR_PXCLK_MASK      0x00FF0000
 
 /* Some ngPIXIS register definitions */
+#define PX_CTL          3
+#define PX_BRDCFG0      8
+#define PX_BRDCFG1      9
+
+#define PX_BRDCFG0_ELBC_SPI_MASK        0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC        0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL        0xc0
+#define PX_BRDCFG0_ELBC_DIU             0x02
+
 #define PX_BRDCFG1_DVIEN        0x80
 #define PX_BRDCFG1_DFPEN        0x40
 #define PX_BRDCFG1_BACKLIGHT    0x20
 #define PX_BRDCFG1_DDCEN        0x10
 
+#define PX_CTL_ALTACC           0x80
+
 /*
  * DIU Area Descriptor
  *
@@ -132,44 +148,117 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
  */
 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
 {
-        struct device_node *np;
-        void __iomem *pixis;
-        u8 __iomem *brdcfg1;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
-        if (!np)
-                /* older device trees used "fsl,p1022ds-pixis" */
-                np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
-        if (!np) {
-                pr_err("p1022ds: missing ngPIXIS node\n");
+        struct device_node *guts_node;
+        struct device_node *indirect_node = NULL;
+        struct ccsr_guts_85xx __iomem *guts;
+        u8 __iomem *lbc_lcs0_ba = NULL;
+        u8 __iomem *lbc_lcs1_ba = NULL;
+        u8 b;
+
+        /* Map the global utilities registers. */
+        guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
+        if (!guts_node) {
+                pr_err("p1022ds: missing global utilties device node\n");
                 return;
         }
 
-        pixis = of_iomap(np, 0);
-        if (!pixis) {
-                pr_err("p1022ds: could not map ngPIXIS registers\n");
-                return;
+        guts = of_iomap(guts_node, 0);
+        if (!guts) {
+                pr_err("p1022ds: could not map global utilties device\n");
+                goto exit;
         }
-        brdcfg1 = pixis + 9;    /* BRDCFG1 is at offset 9 in the ngPIXIS */
+
+        indirect_node = of_find_compatible_node(NULL, NULL,
+                                             "fsl,p1022ds-indirect-pixis");
+        if (!indirect_node) {
+                pr_err("p1022ds: missing pixis indirect mode node\n");
+                goto exit;
+        }
+
+        lbc_lcs0_ba = of_iomap(indirect_node, 0);
+        if (!lbc_lcs0_ba) {
+                pr_err("p1022ds: could not map localbus chip select 0\n");
+                goto exit;
+        }
+
+        lbc_lcs1_ba = of_iomap(indirect_node, 1);
+        if (!lbc_lcs1_ba) {
+                pr_err("p1022ds: could not map localbus chip select 1\n");
+                goto exit;
+        }
+
+        /* Make sure we're in indirect mode first. */
+        if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+            PMUXCR_ELBCDIU_DIU) {
+                struct device_node *pixis_node;
+                void __iomem *pixis;
+
+                pixis_node =
+                        of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
+                if (!pixis_node) {
+                        pr_err("p1022ds: missing pixis node\n");
+                        goto exit;
+                }
+
+                pixis = of_iomap(pixis_node, 0);
+                of_node_put(pixis_node);
+                if (!pixis) {
+                        pr_err("p1022ds: could not map pixis registers\n");
+                        goto exit;
+                }
+
+                /* Enable indirect PIXIS mode.  */
+                setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
+                iounmap(pixis);
+
+                /* Switch the board mux to the DIU */
+                out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
+                b = in_8(lbc_lcs1_ba);
+                b |= PX_BRDCFG0_ELBC_DIU;
+                out_8(lbc_lcs1_ba, b);
+
+                /* Set the chip mux to DIU mode. */
+                clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
+                                PMUXCR_ELBCDIU_DIU);
+                in_be32(&guts->pmuxcr);
+        }
+
 
         switch (port) {
         case FSL_DIU_PORT_DVI:
-                printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
                 /* Enable the DVI port, disable the DFP and the backlight */
-                clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
-                             PX_BRDCFG1_DVIEN);
+                out_8(lbc_lcs0_ba, PX_BRDCFG1);
+                b = in_8(lbc_lcs1_ba);
+                b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+                b |= PX_BRDCFG1_DVIEN;
+                out_8(lbc_lcs1_ba, b);
                 break;
         case FSL_DIU_PORT_LVDS:
-                printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
+                /*
+                 * LVDS also needs backlight enabled, otherwise the display
+                 * will be blank.
+                 */
                 /* Enable the DFP port, disable the DVI and the backlight */
-                clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
-                             PX_BRDCFG1_DFPEN);
+                out_8(lbc_lcs0_ba, PX_BRDCFG1);
+                b = in_8(lbc_lcs1_ba);
+                b &= ~PX_BRDCFG1_DVIEN;
+                b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
+                out_8(lbc_lcs1_ba, b);
                 break;
         default:
                 pr_err("p1022ds: unsupported monitor port %i\n", port);
         }
 
-        iounmap(pixis);
+exit:
+        if (lbc_lcs1_ba)
+                iounmap(lbc_lcs1_ba);
+        if (lbc_lcs0_ba)
+                iounmap(lbc_lcs0_ba);
+        if (guts)
+                iounmap(guts);
+
+        of_node_put(indirect_node);
+        of_node_put(guts_node);
 }
 
 /**
@@ -241,15 +330,56 @@ p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
 
 void __init p1022_ds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                MPIC_WANTS_RESET |
-                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
                 MPIC_SINGLE_DEST_CPU,
                 0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
 }
 
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+/*
+ * Disables a node in the device tree.
+ *
+ * This function is called before kmalloc() is available, so the 'new' object
+ * should be allocated in the global area.  The easiest way is to do that is
+ * to allocate one static local variable for each call to this function.
+ */
+static void __init disable_one_node(struct device_node *np, struct property *new)
+{
+        struct property *old;
+
+        old = of_find_property(np, new->name, NULL);
+        if (old)
+                prom_update_property(np, new, old);
+        else
+                prom_add_property(np, new);
+}
+
+/* TRUE if there is a "video=fslfb" command-line parameter. */
+static bool fslfb;
+
+/*
+ * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
+ * true if we find it.
+ *
+ * We need to use early_param() instead of __setup() because the normal
+ * __setup() gets called to late.  However, early_param() gets called very
+ * early, before the device tree is unflattened, so all we can do now is set a
+ * global variable.  Later on, p1022_ds_setup_arch() will use that variable
+ * to determine if we need to update the device tree.
+ */
+static int __init early_video_setup(char *options)
+{
+        fslfb = (strncmp(options, "fslfb:", 6) == 0);
+
+        return 0;
+}
+early_param("video", early_video_setup);
+
+#endif
+
 /*
  * Setup the architecture
  */
@@ -287,6 +417,34 @@ static void __init p1022_ds_setup_arch(void)
         diu_ops.set_monitor_port        = p1022ds_set_monitor_port;
         diu_ops.set_pixel_clock         = p1022ds_set_pixel_clock;
         diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
+
+        /*
+         * Disable the NOR flash node if there is video=fslfb... command-line
+         * parameter.  When the DIU is active, NOR flash is unavailable, so we
+         * have to disable the node before the MTD driver loads.
+         */
+        if (fslfb) {
+                struct device_node *np =
+                        of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
+
+                if (np) {
+                        np = of_find_compatible_node(np, NULL, "cfi-flash");
+                        if (np) {
+                                static struct property nor_status = {
+                                        .name = "status",
+                                        .value = "disabled",
+                                        .length = sizeof("disabled"),
+                                };
+
+                                pr_info("p1022ds: disabling %s node",
+                                        np->full_name);
+                                disable_one_node(np, &nor_status);
+                                of_node_put(np);
+                        }
+                }
+
+        }
+
 #endif
 
         mpc85xx_smp_init();
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index d951e7027bb6..6b07398e4369 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -93,9 +93,8 @@ machine_device_initcall(p1023_rds, mpc85xx_common_publish_devices);
 
 static void __init mpc85xx_rds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                MPIC_SINGLE_DEST_CPU,
                 0, 256, " OpenPIC  ");
 
         BUG_ON(mpic == NULL);
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index 184a50784617..1677b8a22677 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -54,8 +54,7 @@ static int sbc_rev;
 
 static void __init sbc8548_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index 940752e93051..3c3bbcc27566 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -41,8 +41,7 @@
 
 static void __init sbc8560_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index 18f635906b27..b71919217756 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -48,8 +48,7 @@ static void __init socrates_pic_init(void)
 {
         struct device_node *np;
 
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
index 12cb9bb2cc68..3bbbf7489487 100644
--- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
@@ -51,7 +51,7 @@ static struct socrates_fpga_irq_info fpga_irqs[SOCRATES_FPGA_NUM_IRQS] = {
 static DEFINE_RAW_SPINLOCK(socrates_fpga_pic_lock);
 
 static void __iomem *socrates_fpga_pic_iobase;
-static struct irq_host *socrates_fpga_pic_irq_host;
+static struct irq_domain *socrates_fpga_pic_irq_host;
 static unsigned int socrates_fpga_irqs[3];
 
 static inline uint32_t socrates_fpga_pic_read(int reg)
@@ -227,7 +227,7 @@ static struct irq_chip socrates_fpga_pic_chip = {
         .irq_set_type   = socrates_fpga_pic_set_type,
 };
 
-static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
+static int socrates_fpga_pic_host_map(struct irq_domain *h, unsigned int virq,
                 irq_hw_number_t hwirq)
 {
         /* All interrupts are LEVEL sensitive */
@@ -238,7 +238,7 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
         return 0;
 }
 
-static int socrates_fpga_pic_host_xlate(struct irq_host *h,
+static int socrates_fpga_pic_host_xlate(struct irq_domain *h,
                 struct device_node *ct, const u32 *intspec, unsigned int intsize,
                 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
@@ -269,7 +269,7 @@ static int socrates_fpga_pic_host_xlate(struct irq_host *h,
         return 0;
 }
 
-static struct irq_host_ops socrates_fpga_pic_host_ops = {
+static const struct irq_domain_ops socrates_fpga_pic_host_ops = {
         .map    = socrates_fpga_pic_host_map,
         .xlate  = socrates_fpga_pic_host_xlate,
 };
@@ -279,10 +279,9 @@ void socrates_fpga_pic_init(struct device_node *pic)
         unsigned long flags;
         int i;
 
-        /* Setup an irq_host structure */
-        socrates_fpga_pic_irq_host = irq_alloc_host(pic, IRQ_HOST_MAP_LINEAR,
-                        SOCRATES_FPGA_NUM_IRQS, &socrates_fpga_pic_host_ops,
-                        SOCRATES_FPGA_NUM_IRQS);
+        /* Setup an irq_domain structure */
+        socrates_fpga_pic_irq_host = irq_domain_add_linear(pic,
+                    SOCRATES_FPGA_NUM_IRQS, &socrates_fpga_pic_host_ops, NULL);
         if (socrates_fpga_pic_irq_host == NULL) {
                 pr_err("FPGA PIC: Unable to allocate host\n");
                 return;
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index e9e5234b4e76..27ca3a7b04ab 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -48,8 +48,7 @@
 
 static void __init stx_gp3_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index bf7c89fb75bb..d7504cefe016 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -47,7 +47,7 @@
 static void __init tqm85xx_pic_init(void)
 {
         struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index 3a69f8b77de6..503c21596c63 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -43,9 +43,7 @@
 
 void __init xes_mpc85xx_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                          MPIC_WANTS_RESET |
-                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);