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-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts482
1 files changed, 65 insertions, 417 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 647daf8e7291..09598bb5d443 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -9,60 +9,25 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8568si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8568EMDS"; 15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS"; 16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 17
20 aliases { 18 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0; 19 pci0 = &pci0;
28 pci1 = &pci1; 20 pci1 = &pci1;
29 rapidio0 = &rio0; 21 rapidio0 = &rio;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8568@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 sleep = <&pmc 0x00008000 // core
44 &pmc 0x00004000>; // timebase
45 timebase-frequency = <0>;
46 bus-frequency = <0>;
47 clock-frequency = <0>;
48 next-level-cache = <&L2>;
49 };
50 }; 22 };
51 23
52 memory { 24 memory {
53 device_type = "memory"; 25 device_type = "memory";
54 reg = <0x0 0x10000000>; 26 reg = <0x0 0x0 0x0 0x0>;
55 }; 27 };
56 28
57 localbus@e0005000 { 29 lbc: localbus@e0005000 {
58 #address-cells = <2>; 30 reg = <0x0 0xe0005000 0x0 0x1000>;
59 #size-cells = <1>;
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus";
62 reg = <0xe0005000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <19 2>;
65
66 ranges = <0x0 0x0 0xfe000000 0x02000000 31 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000 32 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000 33 0x2 0x0 0xf0000000 0x04000000
@@ -104,288 +69,65 @@
104 }; 69 };
105 }; 70 };
106 71
107 soc8568@e0000000 { 72 soc: soc8568@e0000000 {
108 #address-cells = <1>; 73 ranges = <0x0 0x0 0xe0000000 0x100000>;
109 #size-cells = <1>;
110 device_type = "soc";
111 compatible = "simple-bus";
112 ranges = <0x0 0xe0000000 0x100000>;
113 bus-frequency = <0>;
114
115 ecm-law@0 {
116 compatible = "fsl,ecm-law";
117 reg = <0x0 0x1000>;
118 fsl,num-laws = <10>;
119 };
120
121 ecm@1000 {
122 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
123 reg = <0x1000 0x1000>;
124 interrupts = <17 2>;
125 interrupt-parent = <&mpic>;
126 };
127
128 memory-controller@2000 {
129 compatible = "fsl,mpc8568-memory-controller";
130 reg = <0x2000 0x1000>;
131 interrupt-parent = <&mpic>;
132 interrupts = <18 2>;
133 };
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,mpc8568-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x80000>; // L2, 512K
140 interrupt-parent = <&mpic>;
141 interrupts = <16 2>;
142 };
143 74
144 i2c-sleep-nexus { 75 i2c-sleep-nexus {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "simple-bus";
148 sleep = <&pmc 0x00000004>;
149 ranges;
150
151 i2c@3000 { 76 i2c@3000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 cell-index = <0>;
155 compatible = "fsl-i2c";
156 reg = <0x3000 0x100>;
157 interrupts = <43 2>;
158 interrupt-parent = <&mpic>;
159 dfsrr;
160
161 rtc@68 { 77 rtc@68 {
162 compatible = "dallas,ds1374"; 78 compatible = "dallas,ds1374";
163 reg = <0x68>; 79 reg = <0x68>;
164 interrupts = <3 1>; 80 interrupts = <3 1 0 0>;
165 interrupt-parent = <&mpic>;
166 }; 81 };
167 }; 82 };
83 };
168 84
169 i2c@3100 { 85 enet0: ethernet@24000 {
170 #address-cells = <1>; 86 tbi-handle = <&tbi0>;
171 #size-cells = <0>; 87 phy-handle = <&phy2>;
172 cell-index = <1>;
173 compatible = "fsl-i2c";
174 reg = <0x3100 0x100>;
175 interrupts = <43 2>;
176 interrupt-parent = <&mpic>;
177 dfsrr;
178 };
179 }; 88 };
180 89
181 dma@21300 { 90 mdio@24520 {
182 #address-cells = <1>; 91 phy0: ethernet-phy@7 {
183 #size-cells = <1>; 92 interrupts = <1 1 0 0>;
184 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma"; 93 reg = <0x7>;
185 reg = <0x21300 0x4>; 94 device_type = "ethernet-phy";
186 ranges = <0x0 0x21100 0x200>;
187 cell-index = <0>;
188 sleep = <&pmc 0x00000400>;
189
190 dma-channel@0 {
191 compatible = "fsl,mpc8568-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x0 0x80>;
194 cell-index = <0>;
195 interrupt-parent = <&mpic>;
196 interrupts = <20 2>;
197 }; 95 };
198 dma-channel@80 { 96 phy1: ethernet-phy@1 {
199 compatible = "fsl,mpc8568-dma-channel", 97 interrupts = <2 1 0 0>;
200 "fsl,eloplus-dma-channel"; 98 reg = <0x1>;
201 reg = <0x80 0x80>; 99 device_type = "ethernet-phy";
202 cell-index = <1>;
203 interrupt-parent = <&mpic>;
204 interrupts = <21 2>;
205 }; 100 };
206 dma-channel@100 { 101 phy2: ethernet-phy@2 {
207 compatible = "fsl,mpc8568-dma-channel", 102 interrupts = <1 1 0 0>;
208 "fsl,eloplus-dma-channel"; 103 reg = <0x2>;
209 reg = <0x100 0x80>; 104 device_type = "ethernet-phy";
210 cell-index = <2>;
211 interrupt-parent = <&mpic>;
212 interrupts = <22 2>;
213 }; 105 };
214 dma-channel@180 { 106 phy3: ethernet-phy@3 {
215 compatible = "fsl,mpc8568-dma-channel", 107 interrupts = <2 1 0 0>;
216 "fsl,eloplus-dma-channel"; 108 reg = <0x3>;
217 reg = <0x180 0x80>; 109 device_type = "ethernet-phy";
218 cell-index = <3>;
219 interrupt-parent = <&mpic>;
220 interrupts = <23 2>;
221 }; 110 };
222 }; 111 tbi0: tbi-phy@11 {
223 112 reg = <0x11>;
224 enet0: ethernet@24000 { 113 device_type = "tbi-phy";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy2>;
238 sleep = <&pmc 0x00000080>;
239
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
245
246 phy0: ethernet-phy@7 {
247 interrupt-parent = <&mpic>;
248 interrupts = <1 1>;
249 reg = <0x7>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <2 1>;
255 reg = <0x1>;
256 device_type = "ethernet-phy";
257 };
258 phy2: ethernet-phy@2 {
259 interrupt-parent = <&mpic>;
260 interrupts = <1 1>;
261 reg = <0x2>;
262 device_type = "ethernet-phy";
263 };
264 phy3: ethernet-phy@3 {
265 interrupt-parent = <&mpic>;
266 interrupts = <2 1>;
267 reg = <0x3>;
268 device_type = "ethernet-phy";
269 };
270 tbi0: tbi-phy@11 {
271 reg = <0x11>;
272 device_type = "tbi-phy";
273 };
274 }; 114 };
275 }; 115 };
276 116
277 enet1: ethernet@25000 { 117 enet1: ethernet@25000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <1>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x25000 0x1000>;
285 ranges = <0x0 0x25000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <35 2 36 2 40 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi1>; 118 tbi-handle = <&tbi1>;
290 phy-handle = <&phy3>; 119 phy-handle = <&phy3>;
291 sleep = <&pmc 0x00000040>; 120 sleep = <&pmc 0x00000040>;
292
293 mdio@520 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,gianfar-tbi";
297 reg = <0x520 0x20>;
298
299 tbi1: tbi-phy@11 {
300 reg = <0x11>;
301 device_type = "tbi-phy";
302 };
303 };
304 }; 121 };
305 122
306 duart-sleep-nexus { 123 mdio@25520 {
307 #address-cells = <1>; 124 tbi1: tbi-phy@11 {
308 #size-cells = <1>; 125 reg = <0x11>;
309 compatible = "simple-bus"; 126 device_type = "tbi-phy";
310 sleep = <&pmc 0x00000002>;
311 ranges;
312
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 2>;
320 interrupt-parent = <&mpic>;
321 };
322
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 2>;
330 interrupt-parent = <&mpic>;
331 }; 127 };
332 }; 128 };
333 129
334 global-utilities@e0000 {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
338 reg = <0xe0000 0x1000>;
339 ranges = <0 0xe0000 0x1000>;
340 fsl,has-rstcr;
341
342 pmc: power@70 {
343 compatible = "fsl,mpc8568-pmc",
344 "fsl,mpc8548-pmc";
345 reg = <0x70 0x20>;
346 };
347 };
348
349 crypto@30000 {
350 compatible = "fsl,sec2.1", "fsl,sec2.0";
351 reg = <0x30000 0x10000>;
352 interrupts = <45 2>;
353 interrupt-parent = <&mpic>;
354 fsl,num-channels = <4>;
355 fsl,channel-fifo-len = <24>;
356 fsl,exec-units-mask = <0xfe>;
357 fsl,descriptor-types-mask = <0x12b0ebf>;
358 sleep = <&pmc 0x01000000>;
359 };
360
361 mpic: pic@40000 {
362 interrupt-controller;
363 #address-cells = <0>;
364 #interrupt-cells = <2>;
365 reg = <0x40000 0x40000>;
366 compatible = "chrp,open-pic";
367 device_type = "open-pic";
368 };
369
370 msi@41600 {
371 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
372 reg = <0x41600 0x80>;
373 msi-available-ranges = <0 0x100>;
374 interrupts = <
375 0xe0 0
376 0xe1 0
377 0xe2 0
378 0xe3 0
379 0xe4 0
380 0xe5 0
381 0xe6 0
382 0xe7 0>;
383 interrupt-parent = <&mpic>;
384 };
385
386 par_io@e0100 { 130 par_io@e0100 {
387 reg = <0xe0100 0x100>;
388 device_type = "par_io";
389 num-ports = <7>; 131 num-ports = <7>;
390 132
391 pio1: ucc_pin@01 { 133 pio1: ucc_pin@01 {
@@ -448,57 +190,21 @@
448 }; 190 };
449 }; 191 };
450 192
451 qe@e0080000 { 193 qe: qe@e0080000 {
452 #address-cells = <1>; 194 ranges = <0x0 0x0 0xe0080000 0x40000>;
453 #size-cells = <1>; 195 reg = <0x0 0xe0080000 0x0 0x480>;
454 device_type = "qe";
455 compatible = "fsl,qe";
456 ranges = <0x0 0xe0080000 0x40000>;
457 reg = <0xe0080000 0x480>;
458 sleep = <&pmc 0x00000800>;
459 brg-frequency = <0>;
460 bus-frequency = <396000000>;
461 fsl,qe-num-riscs = <2>;
462 fsl,qe-num-snums = <28>;
463
464 muram@10000 {
465 #address-cells = <1>;
466 #size-cells = <1>;
467 compatible = "fsl,qe-muram", "fsl,cpm-muram";
468 ranges = <0x0 0x10000 0x10000>;
469
470 data-only@0 {
471 compatible = "fsl,qe-muram-data",
472 "fsl,cpm-muram-data";
473 reg = <0x0 0x10000>;
474 };
475 };
476 196
477 spi@4c0 { 197 spi@4c0 {
478 cell-index = <0>;
479 compatible = "fsl,spi";
480 reg = <0x4c0 0x40>;
481 interrupts = <2>;
482 interrupt-parent = <&qeic>;
483 mode = "cpu"; 198 mode = "cpu";
484 }; 199 };
485 200
486 spi@500 { 201 spi@500 {
487 cell-index = <1>;
488 compatible = "fsl,spi";
489 reg = <0x500 0x40>;
490 interrupts = <1>;
491 interrupt-parent = <&qeic>;
492 mode = "cpu"; 202 mode = "cpu";
493 }; 203 };
494 204
495 enet2: ucc@2000 { 205 enet2: ucc@2000 {
496 device_type = "network"; 206 device_type = "network";
497 compatible = "ucc_geth"; 207 compatible = "ucc_geth";
498 cell-index = <1>;
499 reg = <0x2000 0x200>;
500 interrupts = <32>;
501 interrupt-parent = <&qeic>;
502 local-mac-address = [ 00 00 00 00 00 00 ]; 208 local-mac-address = [ 00 00 00 00 00 00 ];
503 rx-clock-name = "none"; 209 rx-clock-name = "none";
504 tx-clock-name = "clk16"; 210 tx-clock-name = "clk16";
@@ -510,10 +216,6 @@
510 enet3: ucc@3000 { 216 enet3: ucc@3000 {
511 device_type = "network"; 217 device_type = "network";
512 compatible = "ucc_geth"; 218 compatible = "ucc_geth";
513 cell-index = <2>;
514 reg = <0x3000 0x200>;
515 interrupts = <33>;
516 interrupt-parent = <&qeic>;
517 local-mac-address = [ 00 00 00 00 00 00 ]; 219 local-mac-address = [ 00 00 00 00 00 00 ];
518 rx-clock-name = "none"; 220 rx-clock-name = "none";
519 tx-clock-name = "clk16"; 221 tx-clock-name = "clk16";
@@ -532,102 +234,57 @@
532 * gianfar's MDIO bus */ 234 * gianfar's MDIO bus */
533 qe_phy0: ethernet-phy@07 { 235 qe_phy0: ethernet-phy@07 {
534 interrupt-parent = <&mpic>; 236 interrupt-parent = <&mpic>;
535 interrupts = <1 1>; 237 interrupts = <1 1 0 0>;
536 reg = <0x7>; 238 reg = <0x7>;
537 device_type = "ethernet-phy"; 239 device_type = "ethernet-phy";
538 }; 240 };
539 qe_phy1: ethernet-phy@01 { 241 qe_phy1: ethernet-phy@01 {
540 interrupt-parent = <&mpic>; 242 interrupt-parent = <&mpic>;
541 interrupts = <2 1>; 243 interrupts = <2 1 0 0>;
542 reg = <0x1>; 244 reg = <0x1>;
543 device_type = "ethernet-phy"; 245 device_type = "ethernet-phy";
544 }; 246 };
545 qe_phy2: ethernet-phy@02 { 247 qe_phy2: ethernet-phy@02 {
546 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
547 interrupts = <1 1>; 249 interrupts = <1 1 0 0>;
548 reg = <0x2>; 250 reg = <0x2>;
549 device_type = "ethernet-phy"; 251 device_type = "ethernet-phy";
550 }; 252 };
551 qe_phy3: ethernet-phy@03 { 253 qe_phy3: ethernet-phy@03 {
552 interrupt-parent = <&mpic>; 254 interrupt-parent = <&mpic>;
553 interrupts = <2 1>; 255 interrupts = <2 1 0 0>;
554 reg = <0x3>; 256 reg = <0x3>;
555 device_type = "ethernet-phy"; 257 device_type = "ethernet-phy";
556 }; 258 };
557 }; 259 };
558
559 qeic: interrupt-controller@80 {
560 interrupt-controller;
561 compatible = "fsl,qe-ic";
562 #address-cells = <0>;
563 #interrupt-cells = <1>;
564 reg = <0x80 0x80>;
565 big-endian;
566 interrupts = <46 2 46 2>; //high:30 low:30
567 interrupt-parent = <&mpic>;
568 };
569
570 }; 260 };
571 261
572 pci0: pci@e0008000 { 262 pci0: pci@e0008000 {
263 reg = <0x0 0xe0008000 0x0 0x1000>;
264 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
265 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
266 clock-frequency = <66666666>;
573 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 267 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
574 interrupt-map = < 268 interrupt-map = <
575 /* IDSEL 0x12 AD18 */ 269 /* IDSEL 0x12 AD18 */
576 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 270 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
577 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 271 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
578 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 272 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
579 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 273 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
580 274
581 /* IDSEL 0x13 AD19 */ 275 /* IDSEL 0x13 AD19 */
582 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 276 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
583 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 277 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
584 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 278 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
585 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>; 279 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
586
587 interrupt-parent = <&mpic>;
588 interrupts = <24 2>;
589 bus-range = <0 255>;
590 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
591 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
592 sleep = <&pmc 0x80000000>;
593 clock-frequency = <66666666>;
594 #interrupt-cells = <1>;
595 #size-cells = <2>;
596 #address-cells = <3>;
597 reg = <0xe0008000 0x1000>;
598 compatible = "fsl,mpc8540-pci";
599 device_type = "pci";
600 }; 280 };
601 281
602 /* PCI Express */ 282 /* PCI Express */
603 pci1: pcie@e000a000 { 283 pci1: pcie@e000a000 {
604 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 284 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
605 interrupt-map = < 285 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
606 286 reg = <0x0 0xe000a000 0x0 0x1000>;
607 /* IDSEL 0x0 (PEX) */
608 00000 0x0 0x0 0x1 &mpic 0x0 0x1
609 00000 0x0 0x0 0x2 &mpic 0x1 0x1
610 00000 0x0 0x0 0x3 &mpic 0x2 0x1
611 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
612
613 interrupt-parent = <&mpic>;
614 interrupts = <26 2>;
615 bus-range = <0 255>;
616 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
617 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
618 sleep = <&pmc 0x20000000>;
619 clock-frequency = <33333333>;
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 reg = <0xe000a000 0x1000>;
624 compatible = "fsl,mpc8548-pcie";
625 device_type = "pci";
626 pcie@0 { 287 pcie@0 {
627 reg = <0x0 0x0 0x0 0x0 0x0>;
628 #size-cells = <2>;
629 #address-cells = <3>;
630 device_type = "pci";
631 ranges = <0x2000000 0x0 0xa0000000 288 ranges = <0x2000000 0x0 0xa0000000
632 0x2000000 0x0 0xa0000000 289 0x2000000 0x0 0xa0000000
633 0x0 0x10000000 290 0x0 0x10000000
@@ -638,22 +295,11 @@
638 }; 295 };
639 }; 296 };
640 297
641 rio0: rapidio@e00c00000 { 298 rio: rapidio@e00c00000 {
642 #address-cells = <2>; 299 reg = <0x0 0xe00c0000 0x0 0x20000>;
643 #size-cells = <2>; 300 port1 {
644 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta"; 301 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
645 reg = <0xe00c0000 0x20000>; 302 };
646 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
647 interrupts = <48 2 /* error */
648 49 2 /* bell_outb */
649 50 2 /* bell_inb */
650 53 2 /* msg1_tx */
651 54 2 /* msg1_rx */
652 55 2 /* msg2_tx */
653 56 2 /* msg2_rx */>;
654 interrupt-parent = <&mpic>;
655 sleep = <&pmc 0x00080000 /* controller */
656 &pmc 0x00040000>; /* message unit */
657 }; 303 };
658 304
659 leds { 305 leds {
@@ -672,3 +318,5 @@
672 }; 318 };
673 }; 319 };
674}; 320};
321
322/include/ "fsl/mpc8568si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 21:07:03 -0500