2 files changed, 22 insertions, 3 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d053bf4759e4..8d79b8774b30 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -29,6 +29,7 @@
 #include <linux/notifier.h>
 #include <linux/kdb.h>
 #include <linux/irq.h>
+#include <linux/perf_event.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
@@ -576,10 +577,16 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
  */
 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 {
-        if ((opcode & OPCODE) == LL)
+        if ((opcode & OPCODE) == LL) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return simulate_ll(regs, opcode);
-        if ((opcode & OPCODE) == SC)
+        }
+        if ((opcode & OPCODE) == SC) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return simulate_sc(regs, opcode);
+        }
 
         return -1;                      /* Must be something else ... */
 }
@@ -595,6 +602,8 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
                 int rd = (opcode & RD) >> 11;
                 int rt = (opcode & RT) >> 16;
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 switch (rd) {
                 case 0:         /* CPU number */
                         regs->regs[rt] = smp_processor_id();
@@ -630,8 +639,11 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 
 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 {
-        if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
+        if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return 0;
+        }
 
         return -1;                      /* Must be something else ... */
 }
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 33d5a5ce4a29..cfea1adfa153 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -78,6 +78,8 @@
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
+
 #include <asm/asm.h>
 #include <asm/branch.h>
 #include <asm/byteorder.h>
@@ -109,6 +111,9 @@ static void emulate_load_store_insn(struct pt_regs *regs,
         unsigned long value;
         unsigned int res;
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                      1, 0, regs, 0);
+
         /*
          * This load never faults.
          */
@@ -511,6 +516,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
         unsigned int __user *pc;
         mm_segment_t seg;
 
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
+                        1, 0, regs, regs->cp0_badvaddr);
         /*
          * Did we catch a fault trying to load an instruction?
          * Or are we running in MIPS16 mode?