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Diffstat (limited to 'arch/mips/ddb5xxx/ddb5074/nile4_pic.c')
-rw-r--r--arch/mips/ddb5xxx/ddb5074/nile4_pic.c286
1 files changed, 0 insertions, 286 deletions
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
deleted file mode 100644
index 8743ffce8653..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17
18#include <asm/addrspace.h>
19
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22static int irq_base;
23
24/*
25 * Interrupt Programming
26 */
27void nile4_map_irq(int nile4_irq, int cpu_irq)
28{
29 u32 offset, t;
30
31 offset = DDB_INTCTRL;
32 if (nile4_irq >= 8) {
33 offset += 4;
34 nile4_irq -= 8;
35 }
36 t = ddb_in32(offset);
37 t &= ~(7 << (nile4_irq * 4));
38 t |= cpu_irq << (nile4_irq * 4);
39 ddb_out32(offset, t);
40}
41
42void nile4_map_irq_all(int cpu_irq)
43{
44 u32 all, t;
45
46 all = cpu_irq;
47 all |= all << 4;
48 all |= all << 8;
49 all |= all << 16;
50 t = ddb_in32(DDB_INTCTRL);
51 t &= 0x88888888;
52 t |= all;
53 ddb_out32(DDB_INTCTRL, t);
54 t = ddb_in32(DDB_INTCTRL + 4);
55 t &= 0x88888888;
56 t |= all;
57 ddb_out32(DDB_INTCTRL + 4, t);
58}
59
60void nile4_enable_irq(unsigned int nile4_irq)
61{
62 u32 offset, t;
63
64 nile4_irq-=irq_base;
65
66 ddb5074_led_hex(8);
67
68 offset = DDB_INTCTRL;
69 if (nile4_irq >= 8) {
70 offset += 4;
71 nile4_irq -= 8;
72 }
73 ddb5074_led_hex(9);
74 t = ddb_in32(offset);
75 ddb5074_led_hex(0xa);
76 t |= 8 << (nile4_irq * 4);
77 ddb_out32(offset, t);
78 ddb5074_led_hex(0xb);
79}
80
81void nile4_disable_irq(unsigned int nile4_irq)
82{
83 u32 offset, t;
84
85 nile4_irq-=irq_base;
86
87 offset = DDB_INTCTRL;
88 if (nile4_irq >= 8) {
89 offset += 4;
90 nile4_irq -= 8;
91 }
92 t = ddb_in32(offset);
93 t &= ~(8 << (nile4_irq * 4));
94 ddb_out32(offset, t);
95}
96
97void nile4_disable_irq_all(void)
98{
99 ddb_out32(DDB_INTCTRL, 0);
100 ddb_out32(DDB_INTCTRL + 4, 0);
101}
102
103u16 nile4_get_irq_stat(int cpu_irq)
104{
105 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
106}
107
108void nile4_enable_irq_output(int cpu_irq)
109{
110 u32 t;
111
112 t = ddb_in32(DDB_INTSTAT1 + 4);
113 t |= 1 << (16 + cpu_irq);
114 ddb_out32(DDB_INTSTAT1, t);
115}
116
117void nile4_disable_irq_output(int cpu_irq)
118{
119 u32 t;
120
121 t = ddb_in32(DDB_INTSTAT1 + 4);
122 t &= ~(1 << (16 + cpu_irq));
123 ddb_out32(DDB_INTSTAT1, t);
124}
125
126void nile4_set_pci_irq_polarity(int pci_irq, int high)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (high)
132 t &= ~(1 << (pci_irq * 2));
133 else
134 t |= 1 << (pci_irq * 2);
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
139{
140 u32 t;
141
142 t = ddb_in32(DDB_INTPPES);
143 if (level)
144 t |= 2 << (pci_irq * 2);
145 else
146 t &= ~(2 << (pci_irq * 2));
147 ddb_out32(DDB_INTPPES, t);
148}
149
150void nile4_clear_irq(int nile4_irq)
151{
152 nile4_irq-=irq_base;
153 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
154}
155
156void nile4_clear_irq_mask(u32 mask)
157{
158 ddb_out32(DDB_INTCLR, mask);
159}
160
161u8 nile4_i8259_iack(void)
162{
163 u8 irq;
164 u32 reg;
165
166 /* Set window 0 for interrupt acknowledge */
167 reg = ddb_in32(DDB_PCIINIT0);
168
169 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
170 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
171 /* restore window 0 for PCI I/O space */
172 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
173 ddb_out32(DDB_PCIINIT0, reg);
174
175 /* i8269.c set the base vector to be 0x0 */
176 return irq ;
177}
178
179static unsigned int nile4_irq_startup(unsigned int irq) {
180
181 nile4_enable_irq(irq);
182 return 0;
183
184}
185
186static void nile4_ack_irq(unsigned int irq) {
187
188 ddb5074_led_hex(4);
189
190 nile4_clear_irq(irq);
191 ddb5074_led_hex(2);
192 nile4_disable_irq(irq);
193
194 ddb5074_led_hex(0);
195}
196
197static void nile4_irq_end(unsigned int irq) {
198
199 ddb5074_led_hex(3);
200 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
201 ddb5074_led_hex(5);
202 nile4_enable_irq(irq);
203 ddb5074_led_hex(7);
204 }
205
206 ddb5074_led_hex(1);
207}
208
209#define nile4_irq_shutdown nile4_disable_irq
210
211static hw_irq_controller nile4_irq_controller = {
212 .typename = "nile4",
213 .startup = nile4_irq_startup,
214 .shutdown = nile4_irq_shutdown,
215 .enable = nile4_enable_irq,
216 .disable = nile4_disable_irq,
217 .ack = nile4_ack_irq,
218 .end = nile4_irq_end,
219};
220
221void nile4_irq_setup(u32 base) {
222
223 int i;
224
225 irq_base=base;
226
227 /* Map all interrupts to CPU int #0 */
228 nile4_map_irq_all(0);
229
230 /* PCI INTA#-E# must be level triggered */
231 nile4_set_pci_irq_level_or_edge(0, 1);
232 nile4_set_pci_irq_level_or_edge(1, 1);
233 nile4_set_pci_irq_level_or_edge(2, 1);
234 nile4_set_pci_irq_level_or_edge(3, 1);
235 nile4_set_pci_irq_level_or_edge(4, 1);
236
237 /* PCI INTA#-D# must be active low, INTE# must be active high */
238 nile4_set_pci_irq_polarity(0, 0);
239 nile4_set_pci_irq_polarity(1, 0);
240 nile4_set_pci_irq_polarity(2, 0);
241 nile4_set_pci_irq_polarity(3, 0);
242 nile4_set_pci_irq_polarity(4, 1);
243
244
245 for (i = 0; i < 16; i++) {
246 nile4_clear_irq(i);
247 nile4_disable_irq(i);
248 }
249
250 /* Enable CPU int #0 */
251 nile4_enable_irq_output(0);
252
253 for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
254 irq_desc[i].status = IRQ_DISABLED;
255 irq_desc[i].action = NULL;
256 irq_desc[i].depth = 1;
257 irq_desc[i].handler = &nile4_irq_controller;
258 }
259}
260
261#if defined(CONFIG_RUNTIME_DEBUG)
262void nile4_dump_irq_status(void)
263{
264 printk(KERN_DEBUG "
265 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
266 (void *) ddb_in32(DDB_CPUSTAT));
267 printk(KERN_DEBUG "
268 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
269 (void *) ddb_in32(DDB_INTCTRL));
270 printk(KERN_DEBUG
271 "INTSTAT0 = %p:%p\n",
272 (void *) ddb_in32(DDB_INTSTAT0 + 4),
273 (void *) ddb_in32(DDB_INTSTAT0));
274 printk(KERN_DEBUG
275 "INTSTAT1 = %p:%p\n",
276 (void *) ddb_in32(DDB_INTSTAT1 + 4),
277 (void *) ddb_in32(DDB_INTSTAT1));
278 printk(KERN_DEBUG
279 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
280 (void *) ddb_in32(DDB_INTCLR));
281 printk(KERN_DEBUG
282 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
283 (void *) ddb_in32(DDB_INTPPES));
284}
285
286#endif
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