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-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c10
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c20
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c91
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c26
-rw-r--r--arch/arm/mach-omap2/clock.c11
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c48
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c6
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h5
10 files changed, 135 insertions, 86 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7234ae..c2d15212d64d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
60 60
61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask, 61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
62 OMAP24XX_CM_IDLEST_VAL, clk->name); 62 OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
63 63
64 /* 64 /*
65 * REVISIT: Should we return an error code if omap2_wait_clock_ready() 65 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index cabcfdba5246..3524f0e7b6d5 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
68long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) 68long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
69{ 69{
70 const struct prcm_config *ptr; 70 const struct prcm_config *ptr;
71 long highest_rate; 71 long highest_rate, sys_clk_rate;
72 72
73 highest_rate = -EINVAL; 73 highest_rate = -EINVAL;
74 sys_clk_rate = __clk_get_rate(sclk);
74 75
75 for (ptr = rate_table; ptr->mpu_speed; ptr++) { 76 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
76 if (!(ptr->flags & cpu_mask)) 77 if (!(ptr->flags & cpu_mask))
77 continue; 78 continue;
78 if (ptr->xtal_speed != sclk->rate) 79 if (ptr->xtal_speed != sys_clk_rate)
79 continue; 80 continue;
80 81
81 highest_rate = ptr->mpu_speed; 82 highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
94 const struct prcm_config *prcm; 95 const struct prcm_config *prcm;
95 unsigned long found_speed = 0; 96 unsigned long found_speed = 0;
96 unsigned long flags; 97 unsigned long flags;
98 long sys_clk_rate;
99
100 sys_clk_rate = __clk_get_rate(sclk);
97 101
98 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 102 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
99 if (!(prcm->flags & cpu_mask)) 103 if (!(prcm->flags & cpu_mask))
100 continue; 104 continue;
101 105
102 if (prcm->xtal_speed != sclk->rate) 106 if (prcm->xtal_speed != sys_clk_rate)
103 continue; 107 continue;
104 108
105 if (prcm->mpu_speed <= rate) { 109 if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd9e7e7..0fd8b70201e4 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
56 struct omap_sdrc_params *sdrc_cs0; 56 struct omap_sdrc_params *sdrc_cs0;
57 struct omap_sdrc_params *sdrc_cs1; 57 struct omap_sdrc_params *sdrc_cs1;
58 int ret; 58 int ret;
59 unsigned long clkrate;
59 60
60 if (!clk || !rate) 61 if (!clk || !rate)
61 return -EINVAL; 62 return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
64 if (validrate != rate) 65 if (validrate != rate)
65 return -EINVAL; 66 return -EINVAL;
66 67
67 sdrcrate = sdrc_ick_p->rate; 68 sdrcrate = __clk_get_rate(sdrc_ick_p);
68 if (rate > clk->rate) 69 clkrate = __clk_get_rate(clk);
69 sdrcrate <<= ((rate / clk->rate) >> 1); 70 if (rate > clkrate)
71 sdrcrate <<= ((rate / clkrate) >> 1);
70 else 72 else
71 sdrcrate >>= ((clk->rate / rate) >> 1); 73 sdrcrate >>= ((clkrate / rate) >> 1);
72 74
73 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); 75 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
74 if (ret) 76 if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
82 /* 84 /*
83 * XXX This only needs to be done when the CPU frequency changes 85 * XXX This only needs to be done when the CPU frequency changes
84 */ 86 */
85 _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; 87 _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
86 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; 88 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
87 c += 1; /* for safety */ 89 c += 1; /* for safety */
88 c *= SDRC_MPURATE_LOOPS; 90 c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
90 if (c == 0) 92 if (c == 0)
91 c = 1; 93 c = 1;
92 94
93 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, 95 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
94 validrate); 96 clkrate, validrate);
95 pr_debug("clock: SDRC CS0 timing params used:" 97 pr_debug("clock: SDRC CS0 timing params used:"
96 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", 98 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
97 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 99 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
104 106
105 if (sdrc_cs1) 107 if (sdrc_cs1)
106 omap3_configure_core_dpll( 108 omap3_configure_core_dpll(
107 new_div, unlock_dll, c, rate > clk->rate, 109 new_div, unlock_dll, c, rate > clkrate,
108 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 110 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
109 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 111 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
110 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, 112 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
111 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); 113 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
112 else 114 else
113 omap3_configure_core_dpll( 115 omap3_configure_core_dpll(
114 new_div, unlock_dll, c, rate > clk->rate, 116 new_div, unlock_dll, c, rate > clkrate,
115 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 117 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
116 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 118 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
117 0, 0, 0, 0); 119 0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b1f7f7..33382fb46cc1 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
71 71
72 if (!clks->parent) { 72 if (!clks->parent) {
73 /* This indicates a data problem */ 73 /* This indicates a data problem */
74 WARN(1, "clock: Could not find parent clock %s in clksel array " 74 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
75 "of clock %s\n", src_clk->name, clk->name); 75 __clk_get_name(clk), __clk_get_name(src_clk));
76 return NULL; 76 return NULL;
77 } 77 }
78 78
@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
126 126
127 if (max_div == 0) { 127 if (max_div == 0) {
128 /* This indicates an error in the clksel data */ 128 /* This indicates an error in the clksel data */
129 WARN(1, "clock: Could not find divisor for clock %s parent %s" 129 WARN(1, "clock: %s: could not find divisor for parent %s\n",
130 "\n", clk->name, src_clk->parent->name); 130 __clk_get_name(clk),
131 __clk_get_name(__clk_get_parent(src_clk)));
131 return 0; 132 return 0;
132 } 133 }
133 134
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
176{ 177{
177 const struct clksel *clks; 178 const struct clksel *clks;
178 const struct clksel_rate *clkr; 179 const struct clksel_rate *clkr;
180 struct clk *parent;
179 181
180 clks = _get_clksel_by_parent(clk, clk->parent); 182 parent = __clk_get_parent(clk);
183 clks = _get_clksel_by_parent(clk, parent);
181 if (!clks) 184 if (!clks)
182 return 0; 185 return 0;
183 186
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
191 194
192 if (!clkr->div) { 195 if (!clkr->div) {
193 /* This indicates a data error */ 196 /* This indicates a data error */
194 WARN(1, "clock: Could not find fieldval %d for clock %s parent " 197 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
195 "%s\n", field_val, clk->name, clk->parent->name); 198 __clk_get_name(clk), field_val, __clk_get_name(parent));
196 return 0; 199 return 0;
197 } 200 }
198 201
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
213{ 216{
214 const struct clksel *clks; 217 const struct clksel *clks;
215 const struct clksel_rate *clkr; 218 const struct clksel_rate *clkr;
219 struct clk *parent;
216 220
217 /* should never happen */ 221 /* should never happen */
218 WARN_ON(div == 0); 222 WARN_ON(div == 0);
219 223
220 clks = _get_clksel_by_parent(clk, clk->parent); 224 parent = __clk_get_parent(clk);
225 clks = _get_clksel_by_parent(clk, parent);
221 if (!clks) 226 if (!clks)
222 return ~0; 227 return ~0;
223 228
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
230 } 235 }
231 236
232 if (!clkr->div) { 237 if (!clkr->div) {
233 pr_err("clock: Could not find divisor %d for clock %s parent " 238 pr_err("clock: %s: could not find divisor %d for parent %s\n",
234 "%s\n", div, clk->name, clk->parent->name); 239 __clk_get_name(clk), div, __clk_get_name(parent));
235 return ~0; 240 return ~0;
236 } 241 }
237 242
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
281 const struct clksel *clks; 286 const struct clksel *clks;
282 const struct clksel_rate *clkr; 287 const struct clksel_rate *clkr;
283 u32 last_div = 0; 288 u32 last_div = 0;
289 struct clk *parent;
290 unsigned long parent_rate;
291 const char *clk_name;
292
293 parent = __clk_get_parent(clk);
294 parent_rate = __clk_get_rate(parent);
295 clk_name = __clk_get_name(clk);
284 296
285 if (!clk->clksel || !clk->clksel_mask) 297 if (!clk->clksel || !clk->clksel_mask)
286 return ~0; 298 return ~0;
287 299
288 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 300 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
289 clk->name, target_rate); 301 clk_name, target_rate);
290 302
291 *new_div = 1; 303 *new_div = 1;
292 304
293 clks = _get_clksel_by_parent(clk, clk->parent); 305 clks = _get_clksel_by_parent(clk, parent);
294 if (!clks) 306 if (!clks)
295 return ~0; 307 return ~0;
296 308
@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
300 312
301 /* Sanity check */ 313 /* Sanity check */
302 if (clkr->div <= last_div) 314 if (clkr->div <= last_div)
303 pr_err("clock: clksel_rate table not sorted " 315 pr_err("clock: %s: clksel_rate table not sorted\n",
304 "for clock %s", clk->name); 316 clk_name);
305 317
306 last_div = clkr->div; 318 last_div = clkr->div;
307 319
308 test_rate = clk->parent->rate / clkr->div; 320 test_rate = parent_rate / clkr->div;
309 321
310 if (test_rate <= target_rate) 322 if (test_rate <= target_rate)
311 break; /* found it */ 323 break; /* found it */
312 } 324 }
313 325
314 if (!clkr->div) { 326 if (!clkr->div) {
315 pr_err("clock: Could not find divisor for target " 327 pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
316 "rate %ld for clock %s parent %s\n", target_rate, 328 clk_name, target_rate, __clk_get_name(parent));
317 clk->name, clk->parent->name);
318 return ~0; 329 return ~0;
319 } 330 }
320 331
321 *new_div = clkr->div; 332 *new_div = clkr->div;
322 333
323 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, 334 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
324 (clk->parent->rate / clkr->div)); 335 (parent_rate / clkr->div));
325 336
326 return clk->parent->rate / clkr->div; 337 return parent_rate / clkr->div;
327} 338}
328 339
329/* 340/*
@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
345 const struct clksel *clks; 356 const struct clksel *clks;
346 const struct clksel_rate *clkr; 357 const struct clksel_rate *clkr;
347 u32 r, found = 0; 358 u32 r, found = 0;
359 struct clk *parent;
360 const char *clk_name;
348 361
349 if (!clk->clksel || !clk->clksel_mask) 362 if (!clk->clksel || !clk->clksel_mask)
350 return; 363 return;
351 364
365 parent = __clk_get_parent(clk);
366 clk_name = __clk_get_name(clk);
367
352 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 368 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
353 r >>= __ffs(clk->clksel_mask); 369 r >>= __ffs(clk->clksel_mask);
354 370
@@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
358 continue; 374 continue;
359 375
360 if (clkr->val == r) { 376 if (clkr->val == r) {
361 if (clk->parent != clks->parent) { 377 if (parent != clks->parent) {
362 pr_debug("clock: inited %s parent " 378 pr_debug("clock: inited %s parent "
363 "to %s (was %s)\n", 379 "to %s (was %s)\n",
364 clk->name, clks->parent->name, 380 clk_name,
365 ((clk->parent) ? 381 __clk_get_name(clks->parent),
366 clk->parent->name : "NULL")); 382 ((parent) ?
383 __clk_get_name(parent) :
384 "NULL"));
367 clk_reparent(clk, clks->parent); 385 clk_reparent(clk, clks->parent);
368 }; 386 };
369 found = 1; 387 found = 1;
@@ -373,7 +391,7 @@ void omap2_init_clksel_parent(struct clk *clk)
373 391
374 /* This indicates a data error */ 392 /* This indicates a data error */
375 WARN(!found, "clock: %s: init parent: could not find regval %0x\n", 393 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
376 clk->name, r); 394 clk_name, r);
377 395
378 return; 396 return;
379} 397}
@@ -391,15 +409,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
391{ 409{
392 unsigned long rate; 410 unsigned long rate;
393 u32 div = 0; 411 u32 div = 0;
412 struct clk *parent;
394 413
395 div = _read_divisor(clk); 414 div = _read_divisor(clk);
396 if (div == 0) 415 if (div == 0)
397 return clk->rate; 416 return __clk_get_rate(clk);
398 417
399 rate = clk->parent->rate / div; 418 parent = __clk_get_parent(clk);
419 rate = __clk_get_rate(parent) / div;
400 420
401 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, 421 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
402 rate, div); 422 __clk_get_name(clk), rate, div);
403 423
404 return rate; 424 return rate;
405} 425}
@@ -454,9 +474,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
454 474
455 _write_clksel_reg(clk, field_val); 475 _write_clksel_reg(clk, field_val);
456 476
457 clk->rate = clk->parent->rate / new_div; 477 clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
458 478
459 pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); 479 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
480 __clk_get_rate(clk));
460 481
461 return 0; 482 return 0;
462} 483}
@@ -498,13 +519,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
498 clk_reparent(clk, new_parent); 519 clk_reparent(clk, new_parent);
499 520
500 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 521 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
501 clk->rate = new_parent->rate; 522 clk->rate = __clk_get_rate(new_parent);
502 523
503 if (parent_div > 0) 524 if (parent_div > 0)
504 clk->rate /= parent_div; 525 __clk_get_rate(clk) /= parent_div;
505 526
506 pr_debug("clock: %s: set parent to %s (new rate %ld)\n", 527 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
507 clk->name, clk->parent->name, clk->rate); 528 __clk_get_name(clk),
529 __clk_get_name(__clk_get_parent(clk)),
530 __clk_get_rate(clk));
508 531
509 return 0; 532 return 0;
510} 533}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 0bf0ec3e352c..470828e6f293 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
87 dd = clk->dpll_data; 87 dd = clk->dpll_data;
88 88
89 /* DPLL divider must result in a valid jitter correction val */ 89 /* DPLL divider must result in a valid jitter correction val */
90 fint = clk->parent->rate / n; 90 fint = __clk_get_rate(__clk_get_parent(clk)) / n;
91 91
92 if (cpu_is_omap24xx()) { 92 if (cpu_is_omap24xx()) {
93 /* Should not be called for OMAP2, so warn if it is called */ 93 /* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
252 if (cpu_is_omap24xx()) { 252 if (cpu_is_omap24xx()) {
253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
254 v == OMAP2XXX_EN_DPLL_FRBYPASS) 254 v == OMAP2XXX_EN_DPLL_FRBYPASS)
255 return dd->clk_bypass->rate; 255 return __clk_get_rate(dd->clk_bypass);
256 } else if (cpu_is_omap34xx()) { 256 } else if (cpu_is_omap34xx()) {
257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
258 v == OMAP3XXX_EN_DPLL_FRBYPASS) 258 v == OMAP3XXX_EN_DPLL_FRBYPASS)
259 return dd->clk_bypass->rate; 259 return __clk_get_rate(dd->clk_bypass);
260 } else if (soc_is_am33xx() || cpu_is_omap44xx()) { 260 } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
262 v == OMAP4XXX_EN_DPLL_FRBYPASS || 262 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
263 v == OMAP4XXX_EN_DPLL_MNBYPASS) 263 v == OMAP4XXX_EN_DPLL_MNBYPASS)
264 return dd->clk_bypass->rate; 264 return __clk_get_rate(dd->clk_bypass);
265 } 265 }
266 266
267 v = __raw_readl(dd->mult_div1_reg); 267 v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
270 dpll_div = v & dd->div1_mask; 270 dpll_div = v & dd->div1_mask;
271 dpll_div >>= __ffs(dd->div1_mask); 271 dpll_div >>= __ffs(dd->div1_mask);
272 272
273 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 273 dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
274 do_div(dpll_clk, dpll_div + 1); 274 do_div(dpll_clk, dpll_div + 1);
275 275
276 return dpll_clk; 276 return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
296 unsigned long scaled_rt_rp; 296 unsigned long scaled_rt_rp;
297 unsigned long new_rate = 0; 297 unsigned long new_rate = 0;
298 struct dpll_data *dd; 298 struct dpll_data *dd;
299 unsigned long ref_rate;
300 const char *clk_name;
299 301
300 if (!clk || !clk->dpll_data) 302 if (!clk || !clk->dpll_data)
301 return ~0; 303 return ~0;
302 304
303 dd = clk->dpll_data; 305 dd = clk->dpll_data;
304 306
307 ref_rate = __clk_get_rate(dd->clk_ref);
308 clk_name = __clk_get_name(clk);
305 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", 309 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
306 clk->name, target_rate); 310 clk_name, target_rate);
307 311
308 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 312 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
309 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 313 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
310 314
311 dd->last_rounded_rate = 0; 315 dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
332 break; 336 break;
333 337
334 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 338 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
335 dd->clk_ref->rate); 339 ref_rate);
336 340
337 /* m can't be set low enough for this n - try with a larger n */ 341 /* m can't be set low enough for this n - try with a larger n */
338 if (r == DPLL_MULT_UNDERFLOW) 342 if (r == DPLL_MULT_UNDERFLOW)
339 continue; 343 continue;
340 344
341 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", 345 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
342 clk->name, m, n, new_rate); 346 clk_name, m, n, new_rate);
343 347
344 if (target_rate == new_rate) { 348 if (target_rate == new_rate) {
345 dd->last_rounded_m = m; 349 dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
350 } 354 }
351 355
352 if (target_rate != new_rate) { 356 if (target_rate != new_rate) {
353 pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, 357 pr_debug("clock: %s: cannot round to rate %ld\n",
354 target_rate); 358 clk_name, target_rate);
355 return ~0; 359 return ~0;
356 } 360 }
357 361
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1a1f97f3ca69..fbcd82b8a7d0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
78 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 78 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
79 79
80 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, 80 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
81 clk->name); 81 __clk_get_name(clk));
82} 82}
83 83
84/* Public functions */ 84/* Public functions */
@@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
94void omap2_init_clk_clkdm(struct clk *clk) 94void omap2_init_clk_clkdm(struct clk *clk)
95{ 95{
96 struct clockdomain *clkdm; 96 struct clockdomain *clkdm;
97 const char *clk_name;
97 98
98 if (!clk->clkdm_name) 99 if (!clk->clkdm_name)
99 return; 100 return;
100 101
102 clk_name = __clk_get_name(clk);
103
101 clkdm = clkdm_lookup(clk->clkdm_name); 104 clkdm = clkdm_lookup(clk->clkdm_name);
102 if (clkdm) { 105 if (clkdm) {
103 pr_debug("clock: associated clk %s to clkdm %s\n", 106 pr_debug("clock: associated clk %s to clkdm %s\n",
104 clk->name, clk->clkdm_name); 107 clk_name, clk->clkdm_name);
105 clk->clkdm = clkdm; 108 clk->clkdm = clkdm;
106 } else { 109 } else {
107 pr_debug("clock: could not associate clk %s to " 110 pr_debug("clock: could not associate clk %s to clkdm %s\n",
108 "clkdm %s\n", clk->name, clk->clkdm_name); 111 clk_name, clk->clkdm_name);
109 } 112 }
110} 113}
111 114
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f48043dbac8a..02e74c1e62cf 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
63 const struct dpll_data *dd; 63 const struct dpll_data *dd;
64 int i = 0; 64 int i = 0;
65 int ret = -EINVAL; 65 int ret = -EINVAL;
66 const char *clk_name;
66 67
67 dd = clk->dpll_data; 68 dd = clk->dpll_data;
69 clk_name = __clk_get_name(clk);
68 70
69 state <<= __ffs(dd->idlest_mask); 71 state <<= __ffs(dd->idlest_mask);
70 72
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
76 78
77 if (i == MAX_DPLL_WAIT_TRIES) { 79 if (i == MAX_DPLL_WAIT_TRIES) {
78 printk(KERN_ERR "clock: %s failed transition to '%s'\n", 80 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
79 clk->name, (state) ? "locked" : "bypassed"); 81 clk_name, (state) ? "locked" : "bypassed");
80 } else { 82 } else {
81 pr_debug("clock: %s transition to '%s' in %d loops\n", 83 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk->name, (state) ? "locked" : "bypassed", i); 84 clk_name, (state) ? "locked" : "bypassed", i);
83 85
84 ret = 0; 86 ret = 0;
85 } 87 }
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
93 unsigned long fint; 95 unsigned long fint;
94 u16 f = 0; 96 u16 f = 0;
95 97
96 fint = clk->dpll_data->clk_ref->rate / n; 98 fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
97 99
98 pr_debug("clock: fint is %lu\n", fint); 100 pr_debug("clock: fint is %lu\n", fint);
99 101
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
140 u8 state = 1; 142 u8 state = 1;
141 int r = 0; 143 int r = 0;
142 144
143 pr_debug("clock: locking DPLL %s\n", clk->name); 145 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
144 146
145 dd = clk->dpll_data; 147 dd = clk->dpll_data;
146 state <<= __ffs(dd->idlest_mask); 148 state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
187 return -EINVAL; 189 return -EINVAL;
188 190
189 pr_debug("clock: configuring DPLL %s for low-power bypass\n", 191 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
190 clk->name); 192 __clk_get_name(clk));
191 193
192 ai = omap3_dpll_autoidle_read(clk); 194 ai = omap3_dpll_autoidle_read(clk);
193 195
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
217 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) 219 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
218 return -EINVAL; 220 return -EINVAL;
219 221
220 pr_debug("clock: stopping DPLL %s\n", clk->name); 222 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
221 223
222 ai = omap3_dpll_autoidle_read(clk); 224 ai = omap3_dpll_autoidle_read(clk);
223 225
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
245{ 247{
246 unsigned long fint, clkinp; /* watch out for overflow */ 248 unsigned long fint, clkinp; /* watch out for overflow */
247 249
248 clkinp = clk->parent->rate; 250 clkinp = __clk_get_rate(__clk_get_parent(clk));
249 fint = (clkinp / n) * m; 251 fint = (clkinp / n) * m;
250 252
251 if (fint < 1000000000) 253 if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
271 unsigned long clkinp, sd; /* watch out for overflow */ 273 unsigned long clkinp, sd; /* watch out for overflow */
272 int mod1, mod2; 274 int mod1, mod2;
273 275
274 clkinp = clk->parent->rate; 276 clkinp = __clk_get_rate(__clk_get_parent(clk));
275 277
276 /* 278 /*
277 * target sigma-delta to near 250MHz 279 * target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
380{ 382{
381 int r; 383 int r;
382 struct dpll_data *dd; 384 struct dpll_data *dd;
385 struct clk *parent;
383 386
384 dd = clk->dpll_data; 387 dd = clk->dpll_data;
385 if (!dd) 388 if (!dd)
386 return -EINVAL; 389 return -EINVAL;
387 390
388 if (clk->rate == dd->clk_bypass->rate) { 391 parent = __clk_get_parent(clk);
389 WARN_ON(clk->parent != dd->clk_bypass); 392
393 if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
394 WARN_ON(parent != dd->clk_bypass);
390 r = _omap3_noncore_dpll_bypass(clk); 395 r = _omap3_noncore_dpll_bypass(clk);
391 } else { 396 } else {
392 WARN_ON(clk->parent != dd->clk_ref); 397 WARN_ON(parent != dd->clk_ref);
393 r = _omap3_noncore_dpll_lock(clk); 398 r = _omap3_noncore_dpll_lock(clk);
394 } 399 }
395 /* 400 /*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
432int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) 437int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
433{ 438{
434 struct clk *new_parent = NULL; 439 struct clk *new_parent = NULL;
435 unsigned long hw_rate; 440 unsigned long hw_rate, bypass_rate;
436 u16 freqsel = 0; 441 u16 freqsel = 0;
437 struct dpll_data *dd; 442 struct dpll_data *dd;
438 int ret; 443 int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
456 omap2_clk_enable(dd->clk_bypass); 461 omap2_clk_enable(dd->clk_bypass);
457 omap2_clk_enable(dd->clk_ref); 462 omap2_clk_enable(dd->clk_ref);
458 463
459 if (dd->clk_bypass->rate == rate && 464 bypass_rate = __clk_get_rate(dd->clk_bypass);
465 if (bypass_rate == rate &&
460 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 466 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
461 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); 467 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
462 468
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
479 } 485 }
480 486
481 pr_debug("clock: %s: set rate: locking rate to %lu.\n", 487 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
482 clk->name, rate); 488 __clk_get_name(clk), rate);
483 489
484 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, 490 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
485 dd->last_rounded_n, freqsel); 491 dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
557 563
558 if (!dd->autoidle_reg) { 564 if (!dd->autoidle_reg) {
559 pr_debug("clock: DPLL %s: autoidle not supported\n", 565 pr_debug("clock: DPLL %s: autoidle not supported\n",
560 clk->name); 566 __clk_get_name(clk));
561 return; 567 return;
562 } 568 }
563 569
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
591 597
592 if (!dd->autoidle_reg) { 598 if (!dd->autoidle_reg) {
593 pr_debug("clock: DPLL %s: autoidle not supported\n", 599 pr_debug("clock: DPLL %s: autoidle not supported\n",
594 clk->name); 600 __clk_get_name(clk));
595 return; 601 return;
596 } 602 }
597 603
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
617 unsigned long rate; 623 unsigned long rate;
618 u32 v; 624 u32 v;
619 struct clk *pclk; 625 struct clk *pclk;
626 unsigned long parent_rate;
620 627
621 /* Walk up the parents of clk, looking for a DPLL */ 628 /* Walk up the parents of clk, looking for a DPLL */
622 pclk = clk->parent; 629 pclk = __clk_get_parent(clk);
623 while (pclk && !pclk->dpll_data) 630 while (pclk && !pclk->dpll_data)
624 pclk = pclk->parent; 631 pclk = __clk_get_parent(pclk);
625 632
626 /* clk does not have a DPLL as a parent? */ 633 /* clk does not have a DPLL as a parent? */
627 WARN_ON(!pclk); 634 WARN_ON(!pclk);
@@ -630,12 +637,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
630 637
631 WARN_ON(!dd->enable_mask); 638 WARN_ON(!dd->enable_mask);
632 639
640 parent_rate = __clk_get_rate(__clk_get_parent(clk));
633 v = __raw_readl(dd->control_reg) & dd->enable_mask; 641 v = __raw_readl(dd->control_reg) & dd->enable_mask;
634 v >>= __ffs(dd->enable_mask); 642 v >>= __ffs(dd->enable_mask);
635 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) 643 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
636 rate = clk->parent->rate; 644 rate = parent_rate;
637 else 645 else
638 rate = clk->parent->rate * 2; 646 rate = parent_rate * 2;
639 return rate; 647 return rate;
640} 648}
641 649
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 428dca631e12..acff6b7b79a2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -697,7 +697,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
697 697
698 if (!oh->_clk->clkdm) 698 if (!oh->_clk->clkdm)
699 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", 699 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
700 oh->main_clk, oh->_clk->name); 700 oh->name, oh->main_clk);
701 701
702 return ret; 702 return ret;
703} 703}
@@ -854,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
854 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 854 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
855 if (oc->_clk) { 855 if (oc->_clk) {
856 pr_debug("omap_hwmod: enable %s:%s\n", oc->role, 856 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
857 oc->_clk->name); 857 __clk_get_name(oc->_clk));
858 clk_enable(oc->_clk); 858 clk_enable(oc->_clk);
859 } 859 }
860} 860}
@@ -869,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
869 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 869 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
870 if (oc->_clk) { 870 if (oc->_clk) {
871 pr_debug("omap_hwmod: disable %s:%s\n", oc->role, 871 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
872 oc->_clk->name); 872 __clk_get_name(oc->_clk));
873 clk_disable(oc->_clk); 873 clk_disable(oc->_clk);
874 } 874 }
875} 875}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5cede0f50..40012e3e3b89 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
188 goto exit; 188 goto exit;
189 } 189 }
190 190
191 freq = clk->rate; 191 freq = clk_get_rate(clk);
192 clk_put(clk); 192 clk_put(clk);
193 193
194 rcu_read_lock(); 194 rcu_read_lock();
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b9862279e..e2e2d045e428 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
19struct clk; 19struct clk;
20struct clockdomain; 20struct clockdomain;
21 21
22/* Temporary, needed during the common clock framework conversion */
23#define __clk_get_name(clk) (clk->name)
24#define __clk_get_parent(clk) (clk->parent)
25#define __clk_get_rate(clk) (clk->rate)
26
22/** 27/**
23 * struct clkops - some clock function pointers 28 * struct clkops - some clock function pointers
24 * @enable: fn ptr that enables the current clock in hardware 29 * @enable: fn ptr that enables the current clock in hardware