115 files changed, 1725 insertions, 1013 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f1d9297b1050..9d2608363390 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -23,6 +23,7 @@ config ARM
        select PERF_USE_VMALLOC
        select HAVE_REGS_AND_STACK_ACCESS_API
        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
+        select HAVE_C_RECORDMCOUNT
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -1164,7 +1165,7 @@ config ISA_DMA_API
        bool
 config PCI
-        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
+        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX || SA1100_NANOENGINE
        help
          Find out whether you have a PCI motherboard. PCI is the name of a
          bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1175,6 +1176,12 @@ config PCI_DOMAINS
        bool
        depends on PCI
+config PCI_NANOENGINE
+        bool "BSE nanoEngine PCI support"
+        depends on SA1100_NANOENGINE
+        help
+          Enable PCI on the BSE nanoEngine board.
 config PCI_SYSCALL
        def_bool PCI
@@ -1311,7 +1318,7 @@ config HZ
 config THUMB2_KERNEL
        bool "Compile the kernel in Thumb-2 mode"
-        depends on CPU_V7 && EXPERIMENTAL
+        depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
        select AEABI
        select ARM_ASM_UNIFIED
        help
@@ -1650,6 +1657,19 @@ config ATAGS_PROC
          Should the atags used to boot the kernel be exported in an "atags"
          file in procfs. Useful with kexec.
+config CRASH_DUMP
+        bool "Build kdump crash kernel (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        help
+          Generate crash dump after being started by kexec. This should
+          be normally only set in special crash dump kernels which are
+          loaded in the main kernel with kexec-tools into a specially
+          reserved region and then later executed after a crash by
+          kdump/kexec. The crash dump kernel must be compiled to a
+          memory address not used by the main kernel
+          For more details see Documentation/kdump/kdump.txt
 config AUTO_ZRELADDR
        bool "Auto calculation of the decompressed kernel image address"
        depends on !ZBOOT_ROM && !ARCH_U300
@@ -1759,7 +1779,7 @@ comment "At least one emulation must be selected"
 config FPE_NWFPE
        bool "NWFPE math emulation"
-        depends on !AEABI || OABI_COMPAT
+        depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
        ---help---
          Say Y to include the NWFPE floating point emulator in the kernel.
          This is necessary to run most binaries. Linux does not currently
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 65a7c1c588a9..0a8f748e506a 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -45,6 +45,10 @@ else
 endif
 endif
+ifeq ($(CONFIG_ARCH_SHMOBILE),y)
+OBJS            += head-shmobile.o
+endif
 #
 # We now have a PIC decompressor implementation.  Decompressors running
 # from RAM should not define ZTEXTADDR.  Decompressors running directly
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
new file mode 100644
index 000000000000..30973b76e6ae
--- /dev/null
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -0,0 +1,53 @@
+/*
+ * The head-file for SH-Mobile ARM platforms
+ *
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#ifdef CONFIG_ZBOOT_ROM
+        .section        ".start", "ax"
+        /* load board-specific initialization code */
+#include <mach/zboot.h>
+        b       1f
+__atags:@ tag #1
+        .long   12                      @ tag->hdr.size = tag_size(tag_core);
+        .long   0x54410001              @ tag->hdr.tag = ATAG_CORE;
+        .long   0                       @ tag->u.core.flags = 0;
+        .long   0                       @ tag->u.core.pagesize = 0;
+        .long   0                       @ tag->u.core.rootdev = 0;
+        @ tag #2
+        .long   8                       @ tag->hdr.size = tag_size(tag_mem32);
+        .long   0x54410002              @ tag->hdr.tag = ATAG_MEM;
+        .long   CONFIG_MEMORY_SIZE      @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
+        .long   CONFIG_MEMORY_START     @ @ tag->u.mem.start = CONFIG_MEMORY_START;
+        @ tag #3
+        .long   0                       @ tag->hdr.size = 0
+        .long   0                       @ tag->hdr.tag = ATAG_NONE;
+1:
+        /* Set board ID necessary for boot */
+        ldr     r7, 1f                          @ Set machine type register
+        adr     r8, __atags                     @ Set atag register
+        b       2f
+1 :     .long MACH_TYPE
+2 :
+#endif /* CONFIG_ZBOOT_ROM */
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e6e8664a9413..e7521bca2c35 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_IXP2000)	+= uengine.o
 obj-$(CONFIG_ARCH_IXP23XX)      += uengine.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_COMMON_CLKDEV)     += clkdev.o
+obj-$(CONFIG_ARM_TIMER_SP804)   += timer-sp.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index e6388dcd8cfa..0b89ef001330 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -35,6 +35,9 @@
 static DEFINE_SPINLOCK(irq_controller_lock);
+/* Address of GIC 0 CPU interface */
+void __iomem *gic_cpu_base_addr __read_mostly;
 struct gic_chip_data {
        unsigned int irq_offset;
        void __iomem *dist_base;
@@ -45,7 +48,7 @@ struct gic_chip_data {
 #define MAX_GIC_NR      1
 #endif
-static struct gic_chip_data gic_data[MAX_GIC_NR];
+static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
 static inline void __iomem *gic_dist_base(unsigned int irq)
 {
@@ -213,21 +216,16 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        set_irq_chained_handler(irq, gic_handle_cascade_irq);
 }
-void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
+static void __init gic_dist_init(struct gic_chip_data *gic,
-                          unsigned int irq_start)
+        unsigned int irq_start)
 {
        unsigned int gic_irqs, irq_limit, i;
+        void __iomem *base = gic->dist_base;
        u32 cpumask = 1 << smp_processor_id();
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
        cpumask |= cpumask << 8;
        cpumask |= cpumask << 16;
-        gic_data[gic_nr].dist_base = base;
-        gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
        writel(0, base + GIC_DIST_CTRL);
        /*
@@ -267,7 +265,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
        /*
         * Limit number of interrupts registered to the platform maximum
         */
-        irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
+        irq_limit = gic->irq_offset + gic_irqs;
        if (WARN_ON(irq_limit > NR_IRQS))
                irq_limit = NR_IRQS;
@@ -276,7 +274,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
         */
        for (i = irq_start; i < irq_limit; i++) {
                set_irq_chip(i, &gic_chip);
-                set_irq_chip_data(i, &gic_data[gic_nr]);
+                set_irq_chip_data(i, gic);
                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
@@ -284,19 +282,12 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
        writel(1, base + GIC_DIST_CTRL);
 }
-void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
+static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
-        void __iomem *dist_base;
+        void __iomem *dist_base = gic->dist_base;
+        void __iomem *base = gic->cpu_base;
        int i;
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-        dist_base = gic_data[gic_nr].dist_base;
-        BUG_ON(!dist_base);
-        gic_data[gic_nr].cpu_base = base;
        /*
         * Deal with the banked PPI and SGI interrupts - disable all
         * PPI interrupts, ensure all SGI interrupts are enabled.
@@ -314,6 +305,42 @@ void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
        writel(1, base + GIC_CPU_CTRL);
 }
+void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
+        void __iomem *dist_base, void __iomem *cpu_base)
+{
+        struct gic_chip_data *gic;
+        BUG_ON(gic_nr >= MAX_GIC_NR);
+        gic = &gic_data[gic_nr];
+        gic->dist_base = dist_base;
+        gic->cpu_base = cpu_base;
+        gic->irq_offset = (irq_start - 1) & ~31;
+        if (gic_nr == 0)
+                gic_cpu_base_addr = cpu_base;
+        gic_dist_init(gic, irq_start);
+        gic_cpu_init(gic);
+}
+void __cpuinit gic_secondary_init(unsigned int gic_nr)
+{
+        BUG_ON(gic_nr >= MAX_GIC_NR);
+        gic_cpu_init(&gic_data[gic_nr]);
+}
+void __cpuinit gic_enable_ppi(unsigned int irq)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        irq_to_desc(irq)->status |= IRQ_NOPROBE;
+        gic_unmask_irq(irq);
+        local_irq_restore(flags);
+}
 #ifdef CONFIG_SMP
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 1bec96e85196..42ff90b46dfb 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -352,3 +352,4 @@ struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
        return pci_scan_bus(nr, &it8152_ops, sys);
 }
+EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/plat-versatile/timer-sp.c b/arch/arm/common/timer-sp.c
index fb0d1c299718..4740313daa5b 100644
--- a/arch/arm/plat-versatile/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-versatile/timer-sp.c
+ *  linux/arch/arm/common/timer-sp.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
@@ -26,8 +26,6 @@
 #include <asm/hardware/arm_timer.h>
-#include <plat/timer-sp.h>
 /*
 * These timers are currently always setup to be clocked at 1MHz.
 */
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 8bb66bca2e3e..c3cd8755e648 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -99,6 +99,8 @@ struct elf32_hdr;
 extern int elf_check_arch(const struct elf32_hdr *);
 #define elf_check_arch elf_check_arch
+#define vmcore_elf64_check_arch(x) (0)
 extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int);
 #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk)
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
new file mode 100644
index 000000000000..c115b82fe80a
--- /dev/null
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/include/asm/hardware/entry-macro-gic.S
+ *
+ * Low-level IRQ helper macros for GIC
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware/gic.h>
+#ifndef HAVE_GET_IRQNR_PREAMBLE
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =gic_cpu_base_addr
+        ldr     \base, [\base]
+        .endm
+#endif
+/*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec.  To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local.  We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an interrupt if it's
+ * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number of the highest
+ * priority enabled interrupt.  We then just need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+        /* bits 12-10 = src CPU, 9-0 = int # */
+        ldr     \tmp, =1021
+        bic     \irqnr, \irqstat, #0x1c00
+        cmp     \irqnr, #29
+        cmpcc   \irqnr, \irqnr
+        cmpne   \irqnr, \tmp
+        cmpcs   \irqnr, \irqnr
+        .endm
+/* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt on the
+ * controller, since this requires the original irqstat value which
+ * we won't easily be able to recreate later.
+ */
+        .macro test_for_ipi, irqnr, irqstat, base, tmp
+        bic     \irqnr, \irqstat, #0x1c00
+        cmp     \irqnr, #16
+        strcc   \irqstat, [\base, #GIC_CPU_EOI]
+        cmpcs   \irqnr, \irqnr
+        .endm
+/* As above, this assumes that irqstat and base are preserved.. */
+        .macro test_for_ltirq, irqnr, irqstat, base, tmp
+        bic     \irqnr, \irqstat, #0x1c00
+        mov     \tmp, #0
+        cmp     \irqnr, #29
+        moveq   \tmp, #1
+        streq   \irqstat, [\base, #GIC_CPU_EOI]
+        cmp     \tmp, #0
+        .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 7f34333bb545..84557d321001 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,10 +33,13 @@
 #define GIC_DIST_SOFTINT                0xf00
 #ifndef __ASSEMBLY__
-void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
+extern void __iomem *gic_cpu_base_addr;
-void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
+void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
+void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
+void gic_enable_ppi(unsigned int);
 #endif
 #endif
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 21fa272301f8..b2f95c72287c 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -76,6 +76,7 @@ extern unsigned long it8152_base_address;
  IT8152_PD_IRQ(0)  Audio controller (ACR)
 */
 #define IT8152_IRQ(x)   (IRQ_BOARD_START + (x))
+#define IT8152_LAST_IRQ (IRQ_BOARD_START + 40)
 /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
 #define IT8152_LD_IRQ_COUNT     9
diff --git a/arch/arm/plat-versatile/include/plat/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 21e75e30d497..21e75e30d497 100644
--- a/arch/arm/plat-versatile/include/plat/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 1fc684e70ab6..7080e2c8fa62 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -25,9 +25,6 @@ extern void *kmap_high(struct page *page);
 extern void *kmap_high_get(struct page *page);
 extern void kunmap_high(struct page *page);
-extern void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte);
-extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte);
 /*
 * The following functions are already defined by <linux/highmem.h>
 * when CONFIG_HIGHMEM is not set.
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index 8ec9ef5c3c7b..c0094d8edae4 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -33,10 +33,20 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
        if (oldregs) {
                memcpy(newregs, oldregs, sizeof(*newregs));
        } else {
-                __asm__ __volatile__ ("stmia %0, {r0 - r15}"
+                __asm__ __volatile__ (
-                                      : : "r" (&newregs->ARM_r0));
+                        "stmia  %[regs_base], {r0-r12}\n\t"
-                __asm__ __volatile__ ("mrs %0, cpsr"
+                        "mov    %[_ARM_sp], sp\n\t"
-                                      : "=r" (newregs->ARM_cpsr));
+                        "str    lr, %[_ARM_lr]\n\t"
+                        "adr    %[_ARM_pc], 1f\n\t"
+                        "mrs    %[_ARM_cpsr], cpsr\n\t"
+                "1:"
+                        : [_ARM_pc] "=r" (newregs->ARM_pc),
+                          [_ARM_cpsr] "=r" (newregs->ARM_cpsr),
+                          [_ARM_sp] "=r" (newregs->ARM_sp),
+                          [_ARM_lr] "=o" (newregs->ARM_lr)
+                        : [regs_base] "r" (&newregs->ARM_r0)
+                        : "memory"
+                );
        }
 }
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index cbb0bc295d2b..12c8e680cbff 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -8,11 +8,6 @@
 struct unwind_table;
 #ifdef CONFIG_ARM_UNWIND
-struct arm_unwind_mapping {
-        Elf_Shdr *unw_sec;
-        Elf_Shdr *sec_text;
-        struct unwind_table *unwind;
-};
 enum {
        ARM_SEC_INIT,
        ARM_SEC_DEVINIT,
@@ -21,13 +16,13 @@ enum {
        ARM_SEC_DEVEXIT,
        ARM_SEC_MAX,
 };
+#endif
 struct mod_arch_specific {
-        struct arm_unwind_mapping map[ARM_SEC_MAX];
+#ifdef CONFIG_ARM_UNWIND
-};
+        struct unwind_table *unwind[ARM_SEC_MAX];
-#else
-struct mod_arch_specific {
-};
 #endif
+};
 /*
 * Include the ARM architecture version.
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 4fc1565e4f93..316bb2b2be3d 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -13,9 +13,6 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/* DO NOT EDIT!! - this file automatically generated
- *                 from .s file by awk -f s2h.awk
- */
 /*  Size definitions
 *  Copyright (C) ARM Limited 1998. All rights reserved.
 */
@@ -25,6 +22,9 @@
 /* handy sizes */
 #define SZ_16                           0x00000010
+#define SZ_32                           0x00000020
+#define SZ_64                           0x00000040
+#define SZ_128                          0x00000080
 #define SZ_256                          0x00000100
 #define SZ_512                          0x00000200
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1120f18a6b17..80025948b8ad 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -150,6 +150,7 @@ extern unsigned int user_debug;
 #define rmb()           dmb()
 #define wmb()           mb()
 #else
+#include <asm/memory.h>
 #define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 8bfa98757cd2..80bf8cd88d7c 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -29,6 +29,9 @@ ret_fast_syscall:
        ldr     r1, [tsk, #TI_FLAGS]
        tst     r1, #_TIF_WORK_MASK
        bne     fast_work_pending
+#if defined(CONFIG_IRQSOFF_TRACER)
+        asm_trace_hardirqs_on
+#endif
        /* perform architecture specific actions before user return */
        arch_ret_to_user r1, lr
@@ -65,6 +68,9 @@ ret_slow_syscall:
        tst     r1, #_TIF_WORK_MASK
        bne     work_pending
 no_work_pending:
+#if defined(CONFIG_IRQSOFF_TRACER)
+        asm_trace_hardirqs_on
+#endif
        /* perform architecture specific actions before user return */
        arch_ret_to_user r1, lr
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 3a8fd5140d7a..30ead135ff5f 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -23,6 +23,8 @@ extern unsigned long kexec_indirection_page;
 extern unsigned long kexec_mach_type;
 extern unsigned long kexec_boot_atags;
+static atomic_t waiting_for_crash_ipi;
 /*
 * Provide a dummy crash_notes definition while crash dump arrives to arm.
 * This prevents breakage of crash_notes attribute in kernel/ksysfs.c.
@@ -37,9 +39,37 @@ void machine_kexec_cleanup(struct kimage *image)
 {
 }
+void machine_crash_nonpanic_core(void *unused)
+{
+        struct pt_regs regs;
+        crash_setup_regs(&regs, NULL);
+        printk(KERN_DEBUG "CPU %u will stop doing anything useful since another CPU has crashed\n",
+               smp_processor_id());
+        crash_save_cpu(&regs, smp_processor_id());
+        flush_cache_all();
+        atomic_dec(&waiting_for_crash_ipi);
+        while (1)
+                cpu_relax();
+}
 void machine_crash_shutdown(struct pt_regs *regs)
 {
+        unsigned long msecs;
        local_irq_disable();
+        atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
+        smp_call_function(machine_crash_nonpanic_core, NULL, false);
+        msecs = 1000; /* Wait at most a second for the other cpus to stop */
+        while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {
+                mdelay(1);
+                msecs--;
+        }
+        if (atomic_read(&waiting_for_crash_ipi) > 0)
+                printk(KERN_WARNING "Non-crashing CPUs did not react to IPI\n");
        crash_save_cpu(regs, smp_processor_id());
        printk(KERN_INFO "Loading crashdump kernel...\n");
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index d9bd786ce23d..0c1bb68ff4a8 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -67,35 +67,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
                              char *secstrings,
                              struct module *mod)
 {
-#ifdef CONFIG_ARM_UNWIND
-        Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
-        struct arm_unwind_mapping *maps = mod->arch.map;
-        for (s = sechdrs; s < sechdrs_end; s++) {
-                char const *secname = secstrings + s->sh_name;
-                if (strcmp(".ARM.exidx.init.text", secname) == 0)
-                        maps[ARM_SEC_INIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx", secname) == 0)
-                        maps[ARM_SEC_CORE].unw_sec = s;
-                else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
-                        maps[ARM_SEC_EXIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
-                else if (strcmp(".init.text", secname) == 0)
-                        maps[ARM_SEC_INIT].sec_text = s;
-                else if (strcmp(".devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].sec_text = s;
-                else if (strcmp(".text", secname) == 0)
-                        maps[ARM_SEC_CORE].sec_text = s;
-                else if (strcmp(".exit.text", secname) == 0)
-                        maps[ARM_SEC_EXIT].sec_text = s;
-                else if (strcmp(".devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].sec_text = s;
-        }
-#endif
        return 0;
 }
@@ -300,41 +271,69 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
        return -ENOEXEC;
 }
-#ifdef CONFIG_ARM_UNWIND
+struct mod_unwind_map {
-static void register_unwind_tables(struct module *mod)
+        const Elf_Shdr *unw_sec;
+        const Elf_Shdr *txt_sec;
+};
+int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
+                    struct module *mod)
 {
+#ifdef CONFIG_ARM_UNWIND
+        const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+        const Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
+        struct mod_unwind_map maps[ARM_SEC_MAX];
        int i;
-        for (i = 0; i < ARM_SEC_MAX; ++i) {
-                struct arm_unwind_mapping *map = &mod->arch.map[i];
+        memset(maps, 0, sizeof(maps));
-                if (map->unw_sec && map->sec_text)
-                        map->unwind = unwind_table_add(map->unw_sec->sh_addr,
+        for (s = sechdrs; s < sechdrs_end; s++) {
-                                                       map->unw_sec->sh_size,
+                const char *secname = secstrs + s->sh_name;
-                                                       map->sec_text->sh_addr,
-                                                       map->sec_text->sh_size);
+                if (!(s->sh_flags & SHF_ALLOC))
+                        continue;
+                if (strcmp(".ARM.exidx.init.text", secname) == 0)
+                        maps[ARM_SEC_INIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
+                        maps[ARM_SEC_DEVINIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx", secname) == 0)
+                        maps[ARM_SEC_CORE].unw_sec = s;
+                else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
+                        maps[ARM_SEC_EXIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
+                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
+                else if (strcmp(".init.text", secname) == 0)
+                        maps[ARM_SEC_INIT].txt_sec = s;
+                else if (strcmp(".devinit.text", secname) == 0)
+                        maps[ARM_SEC_DEVINIT].txt_sec = s;
+                else if (strcmp(".text", secname) == 0)
+                        maps[ARM_SEC_CORE].txt_sec = s;
+                else if (strcmp(".exit.text", secname) == 0)
+                        maps[ARM_SEC_EXIT].txt_sec = s;
+                else if (strcmp(".devexit.text", secname) == 0)
+                        maps[ARM_SEC_DEVEXIT].txt_sec = s;
        }
-}
-static void unregister_unwind_tables(struct module *mod)
+        for (i = 0; i < ARM_SEC_MAX; i++)
-{
+                if (maps[i].unw_sec && maps[i].txt_sec)
-        int i = ARM_SEC_MAX;
+                        mod->arch.unwind[i] =
-        while (--i >= 0)
+                                unwind_table_add(maps[i].unw_sec->sh_addr,
-                unwind_table_del(mod->arch.map[i].unwind);
+                                                 maps[i].unw_sec->sh_size,
-}
+                                                 maps[i].txt_sec->sh_addr,
-#else
+                                                 maps[i].txt_sec->sh_size);
-static inline void register_unwind_tables(struct module *mod) { }
-static inline void unregister_unwind_tables(struct module *mod) { }
 #endif
-int
-module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
-                struct module *module)
-{
-        register_unwind_tables(module);
        return 0;
 }
 void
 module_arch_cleanup(struct module *mod)
 {
-        unregister_unwind_tables(mod);
+#ifdef CONFIG_ARM_UNWIND
+        int i;
+        for (i = 0; i < ARM_SEC_MAX; i++)
+                if (mod->arch.unwind[i])
+                        unwind_table_del(mod->arch.unwind[i]);
+#endif
 }
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8c1959590252..9066473c0ebc 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -310,7 +310,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         * All kernel threads share the same mm context; grab a
         * reference and switch to it.
         */
-        atomic_inc(&mm->mm_users);
        atomic_inc(&mm->mm_count);
        current->active_mm = mm;
        cpumask_set_cpu(cpu, mm_cpumask(mm));
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 35882fbf37f9..67f933ec4177 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -127,8 +127,6 @@ static void __cpuinit twd_calibrate_rate(void)
 */
 void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
-        unsigned long flags;
        twd_calibrate_rate();
        clk->name = "local_timer";
@@ -143,10 +141,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
        clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
        /* Make sure our local interrupt controller has this enabled */
-        local_irq_save(flags);
+        gic_enable_ppi(clk->irq);
-        irq_to_desc(clk->irq)->status |= IRQ_NOPROBE;
-        get_irq_chip(clk->irq)->unmask(clk->irq);
-        local_irq_restore(flags);
        clockevents_register_device(clk);
 }
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 62d686f0b426..d13add71f72a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
-obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o
+obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index bba5a560e02b..feb65787c30b 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -31,6 +31,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/stamp9g20.h>
 #include "sam9_smc.h"
 #include "generic.h"
@@ -38,11 +39,7 @@
 static void __init pcontrol_g20_map_io(void)
 {
-        /* Initialize processor: 18.432 MHz crystal */
+        stamp9g20_map_io();
-        at91sam9260_initialize(18432000);
-        /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */
-        at91_register_uart(0, 0, 0);
        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@@ -54,9 +51,6 @@ static void __init pcontrol_g20_map_io(void)
        /* USART2 on ttyS3. (Rx, Tx)  9bit-Bus  Multidrop-mode  X4 */
        at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
@@ -66,38 +60,6 @@ static void __init init_irq(void)
 }
-/*
- * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB
- */
-static struct atmel_nand_data __initdata nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-};
-/*
- * Bus timings; unit = 7.57ns
- */
-static struct sam9_smc_config __initdata nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
 static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
        .ncs_read_setup         = 16,
        .nrd_setup              = 18,
@@ -138,14 +100,6 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
        .tdf_cycles             = 1,
 } };
-static void __init add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &nand_smc_config);
-        at91_add_device_nand(&nand_data);
-}
 static void __init add_device_pcontrol(void)
 {
        /* configure chip-select 4 (IO compatible to 8051  X4 ) */
@@ -156,23 +110,6 @@ static void __init add_device_pcontrol(void)
 /*
- * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static struct mci_platform_data __initdata mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-        },
-};
-#else
-static struct at91_mmc_data __initdata mmc_data = {
-        .wire4          = 1,
-};
-#endif
-/*
 * USB Host port
 */
 static struct at91_usbh_data __initdata usbh_data = {
@@ -265,42 +202,13 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
 };
-/*
- * Dallas 1-Wire  DS2431
- */
-static struct w1_gpio_platform_data w1_gpio_pdata = {
-        .pin            = AT91_PIN_PA29,
-        .is_open_drain  = 1,
-};
-static struct platform_device w1_device = {
-        .name                   = "w1-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &w1_gpio_pdata,
-};
-static void add_wire1(void)
-{
-        at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
-        at91_set_multi_drive(w1_gpio_pdata.pin, 1);
-        platform_device_register(&w1_device);
-}
 static void __init pcontrol_g20_board_init(void)
 {
-        at91_add_device_serial();
+        stamp9g20_board_init();
-        add_device_nand();
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-        at91_add_device_mci(0, &mmc_data);
-#else
-        at91_add_device_mmc(0, &mmc_data);
-#endif
        at91_add_device_usbh(&usbh_data);
        at91_add_device_eth(&macb_data);
        at91_add_device_i2c(pcontrol_g20_i2c_devices,
                ARRAY_SIZE(pcontrol_g20_i2c_devices));
-        add_wire1();
        add_device_pcontrol();
        at91_add_device_spi(pcontrol_g20_spi_devices,
                ARRAY_SIZE(pcontrol_g20_spi_devices));
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 5206eef4a67e..f8902b118960 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,7 +32,7 @@
 #include "generic.h"
-static void __init portuxg20_map_io(void)
+void __init stamp9g20_map_io(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91sam9260_initialize(18432000);
@@ -40,6 +40,24 @@ static void __init portuxg20_map_io(void)
        /* DGBU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init stamp9g20evb_map_io(void)
+{
+        stamp9g20_map_io();
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
+                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
+}
+static void __init portuxg20_map_io(void)
+{
+        stamp9g20_map_io();
        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
@@ -56,26 +74,6 @@ static void __init portuxg20_map_io(void)
        /* USART5 on ttyS6. (Rx, Tx only) */
        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-static void __init stamp9g20_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91sam9260_initialize(18432000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static void __init init_irq(void)
@@ -156,7 +154,7 @@ static struct at91_udc_data __initdata portuxg20_udc_data = {
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
-static struct at91_udc_data __initdata stamp9g20_udc_data = {
+static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
        .vbus_pin       = AT91_PIN_PA22,
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
@@ -190,7 +188,7 @@ static struct gpio_led portuxg20_leds[] = {
        }
 };
-static struct gpio_led stamp9g20_leds[] = {
+static struct gpio_led stamp9g20evb_leds[] = {
        {
                .name                   = "D8",
                .gpio                   = AT91_PIN_PB18,
@@ -250,7 +248,7 @@ void add_w1(void)
 }
-static void __init generic_board_init(void)
+void __init stamp9g20_board_init(void)
 {
        /* Serial */
        at91_add_device_serial();
@@ -262,34 +260,40 @@ static void __init generic_board_init(void)
 #else
        at91_add_device_mmc(0, &mmc_data);
 #endif
-        /* USB Host */
-        at91_add_device_usbh(&usbh_data);
-        /* Ethernet */
-        at91_add_device_eth(&macb_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
        /* W1 */
        add_w1();
 }
 static void __init portuxg20_board_init(void)
 {
-        generic_board_init();
+        stamp9g20_board_init();
-        /* SPI */
+        /* USB Host */
-        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
+        at91_add_device_usbh(&usbh_data);
        /* USB Device */
        at91_add_device_udc(&portuxg20_udc_data);
+        /* Ethernet */
+        at91_add_device_eth(&macb_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* SPI */
+        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
        /* LEDs */
        at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
 }
-static void __init stamp9g20_board_init(void)
+static void __init stamp9g20evb_board_init(void)
 {
-        generic_board_init();
+        stamp9g20_board_init();
+        /* USB Host */
+        at91_add_device_usbh(&usbh_data);
        /* USB Device */
-        at91_add_device_udc(&stamp9g20_udc_data);
+        at91_add_device_udc(&stamp9g20evb_udc_data);
+        /* Ethernet */
+        at91_add_device_eth(&macb_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
        /* LEDs */
-        at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds));
+        at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
 }
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
@@ -305,7 +309,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
        /* Maintainer: taskit GmbH */
        .boot_params    = AT91_SDRAM_BASE + 0x100,
        .timer          = &at91sam926x_timer,
-        .map_io         = stamp9g20_map_io,
+        .map_io         = stamp9g20evb_map_io,
        .init_irq       = init_irq,
-        .init_machine   = stamp9g20_board_init,
+        .init_machine   = stamp9g20evb_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7525cee3983f..9113da6845f1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -658,7 +658,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-        uhpck.rate_hz = utmi_clk.parent->rate_hz;
+        uhpck.rate_hz = utmi_clk.rate_hz;
        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h
index 57f8ee154943..27ac6f550fe3 100644
--- a/arch/arm/mach-at91/include/mach/at91_mci.h
+++ b/arch/arm/mach-at91/include/mach/at91_mci.h
@@ -74,6 +74,8 @@
 #define                 AT91_MCI_TRTYP_BLOCK    (0 << 19)
 #define                 AT91_MCI_TRTYP_MULTIPLE (1 << 19)
 #define                 AT91_MCI_TRTYP_STREAM   (2 << 19)
+#define                 AT91_MCI_TRTYP_SDIO_BYTE        (4 << 19)
+#define                 AT91_MCI_TRTYP_SDIO_BLOCK       (5 << 19)
 #define AT91_MCI_BLKR           0x18            /* Block Register */
 #define         AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 000000000000..6120f9c46d59
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_STAMP9G20_H
+#define __MACH_STAMP9G20_H
+void stamp9g20_map_io(void);
+void stamp9g20_board_init(void);
+#endif
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 9ca4d581016f..da30078a80c1 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -69,13 +69,10 @@ void __init cns3xxx_map_io(void)
 }
 /* used by entry-macro.S */
-void __iomem *gic_cpu_base_addr;
 void __init cns3xxx_init_irq(void)
 {
-        gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
+        gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
-        gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
+                 __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
-        gic_cpu_init(0, gic_cpu_base_addr);
 }
 void cns3xxx_power_off(void)
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index 6b33ec11346e..ef9e5116b1a9 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,7 +11,6 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
-extern void __iomem *gic_cpu_base_addr;
 extern struct sys_timer cns3xxx_timer;
 void __init cns3xxx_map_io(void);
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index 5e1c5545680f..6bd83ed90afe 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -9,74 +9,10 @@
 */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* As above, this assumes that irqstat and base are preserved.. */
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 6258c90d020c..1713ecf0c95f 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -41,7 +41,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 #include "common.h"
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 24498a932ba6..a54b3db80366 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -513,4 +513,4 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
 EXPORT_SYMBOL(ixp4xx_pci_read);
 EXPORT_SYMBOL(ixp4xx_pci_write);
+EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index daf3993349f8..2e3dd08ccc3f 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -126,7 +126,6 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
 static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
 static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
 static APMU_CLK(nand, NAND, 0xbf, 100000000);
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 7486a681cc71..9b5eb2b4ae1b 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -28,8 +28,6 @@
 #include <mach/board.h>
 #include <mach/msm_iomap.h>
-void __iomem *gic_cpu_base_addr;
 unsigned long clk_get_max_axi_khz(void)
 {
        return 0;
@@ -44,9 +42,8 @@ static void __init msm8x60_init_irq(void)
 {
        unsigned int i;
-        gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
+        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-        gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
+                 (void *)MSM_QGIC_CPU_BASE);
-        gic_cpu_init(0, MSM_QGIC_CPU_BASE);
        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 86c9b2102952..9db9203667df 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -216,7 +216,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
        {
                .name           = "wl1271",
                .mmc            = 3,
-                .caps           = MMC_CAP_4_BIT_DATA,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
                .gpio_wp        = -EINVAL,
                .gpio_cd        = -EINVAL,
                .nonremovable   = true,
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1fc28a..d54c4f89a8bd 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -105,6 +105,35 @@ omap_irq_base:	.word	0
 9999:
                .endm
+#ifdef CONFIG_SMP
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt
+                 * on the controller, since this requires the original irqstat
+                 * value which we won't easily be able to recreate later.
+                 */
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                it      cc
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                it      cs
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* As above, this assumes that irqstat and base are preserved */
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                itt     eq
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
+#endif  /* CONFIG_SMP */
 #else   /* MULTI_OMAP2 */
@@ -141,74 +170,16 @@ omap_irq_base:	.word	0
 #ifdef CONFIG_ARCH_OMAP4
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
                .macro  get_irqnr_preamble, base, tmp
                ldr     \base, =OMAP4_IRQ_BASE
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020.  The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt.
-                 * We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
 #endif
-#endif  /* MULTI_OMAP2 */
-#ifdef CONFIG_SMP
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
+#endif  /* MULTI_OMAP2 */
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* As above, this assumes that irqstat and base are preserved */
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
-#endif  /* CONFIG_SMP */
                .macro  irq_prio_table
                .endm
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 2744dfee1ff4..5b0270b28934 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -24,7 +24,6 @@
 extern void __iomem *l2cache_base;
 #endif
-extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *gic_dist_base_addr;
 extern void __init gic_init_irq(void);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 40562ddd3ee4..a1939b1e6f82 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -297,7 +297,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
                return 0;
        dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
-        if (!dpll3_m2_ck)
+        if (IS_ERR(dpll3_m2_ck))
                return -EINVAL;
        rate = clk_get_rate(dpll3_m2_ck);
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e18e3c..9fbac2c39104 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -50,7 +50,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
        /*
         * Synchronise with the boot thread.
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 2f895553e6a8..666e852988d5 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -26,21 +26,22 @@
 void __iomem *l2cache_base;
 #endif
-void __iomem *gic_cpu_base_addr;
 void __iomem *gic_dist_base_addr;
 void __init gic_init_irq(void)
 {
+        void __iomem *gic_cpu_base;
        /* Static mapping, never released */
        gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
        BUG_ON(!gic_dist_base_addr);
-        gic_dist_init(0, gic_dist_base_addr, 29);
        /* Static mapping, never released */
-        gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+        gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
-        BUG_ON(!gic_cpu_base_addr);
+        BUG_ON(!gic_cpu_base);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
 }
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 5e81517a7af2..a8afb610c7d8 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -161,6 +161,23 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
                printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 }
+void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+{
+        u32 tick_rate, cycles;
+        if (!seconds && !milliseconds)
+                return;
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+        omap_dm_timer_stop(gptimer_wakeup);
+        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+        pr_info("PM: Resume timer in %u.%03u secs"
+                " (%d ticks at %d ticks/sec.)\n",
+                seconds, milliseconds, cycles, tick_rate);
+}
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -354,23 +371,6 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
        pwrdm->timer = t;
 }
-void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-        if (!seconds && !milliseconds)
-                return;
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
 {
        struct seq_file *s = (struct seq_file *)user;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index c85923e56b85..aaeea49b9bdd 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,19 @@
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                  void __iomem *sdrc_power);
@@ -120,8 +133,9 @@ static void omap2_enter_full_retention(void)
                goto no_sleep;
        /* Block console output in case it is on one of the OMAP UARTs */
-        if (try_acquire_console_sem())
+        if (!is_suspending())
-                goto no_sleep;
+                if (try_acquire_console_sem())
+                        goto no_sleep;
        omap_uart_prepare_idle(0);
        omap_uart_prepare_idle(1);
@@ -136,7 +150,8 @@ static void omap2_enter_full_retention(void)
        omap_uart_resume_idle(1);
        omap_uart_resume_idle(0);
-        release_console_sem();
+        if (!is_suspending())
+                release_console_sem();
 no_sleep:
        if (omap2_pm_debug) {
@@ -284,6 +299,12 @@ out:
        local_irq_enable();
 }
+static int omap2_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        return 0;
+}
 static int omap2_pm_prepare(void)
 {
        /* We cannot sleep in idle until we have resumed */
@@ -333,10 +354,17 @@ static void omap2_pm_finish(void)
        enable_hlt();
 }
+static void omap2_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+}
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap2_pm_begin,
        .prepare        = omap2_pm_prepare,
        .enter          = omap2_pm_enter,
        .finish         = omap2_pm_finish,
+        .end            = omap2_pm_end,
        .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0ec8a04b7473..648b8c50d024 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -50,6 +50,19 @@
 #include "sdrc.h"
 #include "control.h"
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
 /* Scratchpad offsets */
 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
@@ -387,10 +400,11 @@ void omap_sram_idle(void)
        }
        /* Block console output in case it is on one of the OMAP UARTs */
-        if (per_next_state < PWRDM_POWER_ON ||
+        if (!is_suspending())
-            core_next_state < PWRDM_POWER_ON)
+                if (per_next_state < PWRDM_POWER_ON ||
-                if (try_acquire_console_sem())
+                    core_next_state < PWRDM_POWER_ON)
-                        goto console_still_active;
+                        if (try_acquire_console_sem())
+                                goto console_still_active;
        /* PER */
        if (per_next_state < PWRDM_POWER_ON) {
@@ -470,7 +484,8 @@ void omap_sram_idle(void)
                omap_uart_resume_idle(3);
        }
-        release_console_sem();
+        if (!is_suspending())
+                release_console_sem();
 console_still_active:
        /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -514,8 +529,6 @@ out:
 }
 #ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state;
 static int omap3_pm_prepare(void)
 {
        disable_hlt();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 298a22a754e2..f81acee4738d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -243,13 +243,14 @@
 #define OMAP24XX_EN_GPT1_MASK                           (1 << 0)
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT                         (1 << 2)
+#define OMAP24XX_ST_GPIOS_SHIFT                         2
-#define OMAP24XX_ST_GPIOS_MASK                          2
+#define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
-#define OMAP24XX_ST_GPT1_SHIFT                          (1 << 0)
+#define OMAP24XX_ST_GPT1_SHIFT                          0
-#define OMAP24XX_ST_GPT1_MASK                           0
+#define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT                           (1 << 0)
+#define OMAP2430_ST_MDM_SHIFT                           0
+#define OMAP2430_ST_MDM_MASK                            (1 << 0)
 /* 3430 register bits shared between CM & PRM registers */
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index dd235ecc9d6c..c93e73d54dd1 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -540,6 +540,7 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
        bool "PXA based Toshiba e-series PDAs"
        select PXA25x
+        select FB_W100
 config MACH_E330
        bool "Toshiba e330"
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index d2060a1d1d68..e5c9932b7588 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -241,7 +241,8 @@ static inline void palmtx_keys_init(void) {}
 /******************************************************************************
 * NAND Flash
 ******************************************************************************/
-#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
+#if defined(CONFIG_MTD_NAND_PLATFORM) || \
+        defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
                                 unsigned int ctrl)
 {
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 52c30b01a671..ae008110db4e 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -353,8 +353,8 @@ resume_turn_on_mmu:
        @ Let us ensure we jump to resume_after_mmu only when the mcr above
        @ actually took effect.  They call it the "cpwait" operation.
-        mrc     p15, 0, r1, c2, c0, 0           @ queue a dependency on CP15
+        mrc     p15, 0, r0, c2, c0, 0           @ queue a dependency on CP15
-        sub     pc, r2, r1, lsr #32             @ jump to virtual addr
+        sub     pc, r2, r0, lsr #32             @ jump to virtual addr
        nop
        nop
        nop
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 07c08151dfe6..14fbe50376b6 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -50,13 +50,10 @@
 #include <mach/clkdev.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 #include "core.h"
-/* used by entry-macro.S and platsmp.c */
-void __iomem *gic_cpu_base_addr;
 #ifdef CONFIG_ZONE_DMA
 /*
 * Adjust the zones if there are restrictions for DMA access.
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 781bca68a9fa..693239ddc39e 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -53,7 +53,6 @@ extern struct platform_device realview_i2c_device;
 extern struct mmci_platform_data realview_mmc0_plat_data;
 extern struct mmci_platform_data realview_mmc1_plat_data;
 extern struct clcd_board clcd_plat_data;
-extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *timer0_va_base;
 extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 340a5c276946..4071164aebaa 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -8,74 +8,11 @@
 * warranty of any kind, whether express or implied.
 */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* As above, this assumes that irqstat and base are preserved.. */
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 009265818d55..6da8a2e53c44 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -69,7 +69,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
        /*
         * let the primary processor know we're out of the
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index f2697106f809..6ef5c5e528b2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -364,21 +364,19 @@ static void __init gic_init_irq(void)
                writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
                /* core tile GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
+                gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
-                gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
+                         __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
-                gic_cpu_init(0, gic_cpu_base_addr);
 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
                /* board GIC, secondary */
-                gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
+                gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE),
-                gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
+                         __io_address(REALVIEW_EB_GIC_CPU_BASE));
                gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
 #endif
        } else {
                /* board GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
+                gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
-                gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
+                         __io_address(REALVIEW_EB_GIC_CPU_BASE));
-                gic_cpu_init(0, gic_cpu_base_addr);
        }
 }
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index a4125619d71b..cbdc97a5685f 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -304,13 +304,14 @@ static struct platform_device char_lcd_device = {
 static void __init gic_init_irq(void)
 {
        /* ARM1176 DevChip GIC, primary */
-        gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
+        gic_init(0, IRQ_DC1176_GIC_START,
-        gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
+                 __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
-        gic_cpu_init(0, gic_cpu_base_addr);
+                 __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
        /* board GIC, secondary */
-        gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
+        gic_init(1, IRQ_PB1176_GIC_START,
-        gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+                 __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
        gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
 }
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 117b95b2ca15..8e8ab7d29a6a 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -309,13 +309,13 @@ static void __init gic_init_irq(void)
        writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
        /* ARM11MPCore test chip GIC, primary */
-        gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
+        gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
-        gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
+                 __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
-        gic_cpu_init(0, gic_cpu_base_addr);
        /* board GIC, secondary */
-        gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
+        gic_init(1, IRQ_PB11MP_GIC_START,
-        gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+                 __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
        gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
 }
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 929b8dc12e81..841118e3e118 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -273,9 +273,9 @@ static struct platform_device pmu_device = {
 static void __init gic_init_irq(void)
 {
        /* ARM PB-A8 on-board GIC */
-        gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE);
+        gic_init(0, IRQ_PBA8_GIC_START,
-        gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START);
+                 __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
-        gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
+                 __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
 }
 static void __init realview_pba8_timer_init(void)
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index b9f9e20031a7..02b755b009db 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -313,15 +313,12 @@ static void __init gic_init_irq(void)
 {
        /* ARM PBX on-board GIC */
        if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
-                gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
+                gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
-                gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+                         __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
-                              29);
-                gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
        } else {
-                gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
+                gic_init(0, IRQ_PBX_GIC_START,
-                gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
+                         __io_address(REALVIEW_PBX_GIC_DIST_BASE),
-                              IRQ_PBX_GIC_START);
+                         __io_address(REALVIEW_PBX_GIC_CPU_BASE));
-                gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
        }
 }
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index cef6a65637bd..6983cb4d4cae 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -16,7 +16,7 @@ config CPU_S3C2412
 config CPU_S3C2412_ONLY
        bool
        depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
-                   !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
                   !CPU_S3C2443 && CPU_S3C2412
        default y if CPU_S3C2412
@@ -28,9 +28,16 @@ config S3C2412_DMA
 config S3C2412_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2412 power management
+config S3C2412_PM_SLEEP
+        bool
+        help
+          Internal config node to apply sleep for S3C2412 power management.
+          Can be selected by another SoCs with similar sleep procedure.
 # Note, the S3C2412 IOtiming support is in plat-s3c24xx
 config S3C2412_CPUFREQ
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 530ec46cbaea..6c48a91ea39e 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_CPU_S3C2412)	+= irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
 obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
-obj-$(CONFIG_S3C2412_PM)        += pm.o sleep.o
+obj-$(CONFIG_S3C2412_PM)        += pm.o
+obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
 # Machine support
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 87b9c9f003bd..df8d14974c90 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -27,6 +27,7 @@ config S3C2416_DMA
 config S3C2416_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2416 power management
@@ -35,9 +36,12 @@ menu "S3C2416 Machines"
 config MACH_SMDK2416
        bool "SMDK2416"
        select CPU_S3C2416
+        select MACH_SMDK
        select S3C_DEV_FB
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC1
+        select S3C_DEV_NAND
+        select S3C_DEV_USB_HOST
        select S3C2416_PM if PM
        help
          Say Y here if you are using an SMDK2416
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index ff024a6c0f85..a0cb2581894f 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -18,6 +18,7 @@ config CPU_S3C2440
 config CPU_S3C2442
        bool
        select CPU_ARM920T
+        select S3C_GPIO_PULL_DOWN
        select S3C2410_CLOCK
        select S3C2410_GPIO
        select S3C2410_PM if PM
@@ -178,6 +179,9 @@ config MACH_MINI2440
        bool "MINI2440 development board"
        select CPU_S3C2440
        select EEPROM_AT24
+        select NEW_LEDS
+        select LEDS_CLASS
+        select LEDS_TRIGGER
        select LEDS_TRIGGER_BACKLIGHT
        select S3C_DEV_NAND
        select S3C_DEV_USB_HOST
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index d50f3ae6173d..f7663f731ea0 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -46,9 +46,6 @@ int __init s3c2440_init(void)
 {
        printk("S3C2440: Initialising architecture\n");
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
        /* change irq for watchdog */
        s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
@@ -58,3 +55,11 @@ int __init s3c2440_init(void)
        return sysdev_register(&s3c2440_sysdev);
 }
+void __init s3c2440_map_io(void)
+{
+        s3c244x_map_io();
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+}
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 188ad1e57dc0..ecf813546554 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/mutex.h>
+#include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -43,6 +44,11 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/s3c244x.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
 /* S3C2442 extended clock support */
@@ -163,3 +169,11 @@ int __init s3c2442_init(void)
        return sysdev_register(&s3c2442_sysdev);
 }
+void __init s3c2442_map_io(void)
+{
+        s3c244x_map_io();
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
+}
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 4fef723126fa..31babec90cec 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -5,6 +5,7 @@
 config CPU_S3C2443
        bool
        depends on ARCH_S3C2410
+        select CPU_ARM920T
        select S3C2443_DMA if S3C2410_DMA
        select CPU_LLSERIAL_S3C2440
        select SAMSUNG_CLKSRC
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 28677caf3613..461aa035afc0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -378,6 +378,12 @@ static struct max8998_regulator_data aquila_regulators[] = {
 static struct max8998_platform_data aquila_max8998_pdata = {
        .num_regulators = ARRAY_SIZE(aquila_regulators),
        .regulators     = aquila_regulators,
+        .buck1_set1     = S5PV210_GPH0(3),
+        .buck1_set2     = S5PV210_GPH0(4),
+        .buck2_set3     = S5PV210_GPH0(5),
+        .buck1_max_voltage1 = 1200000,
+        .buck1_max_voltage2 = 1200000,
+        .buck2_max_voltage = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index b1dcf964a768..e22d5112fd44 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -518,6 +518,12 @@ static struct max8998_regulator_data goni_regulators[] = {
 static struct max8998_platform_data goni_max8998_pdata = {
        .num_regulators = ARRAY_SIZE(goni_regulators),
        .regulators     = goni_regulators,
+        .buck1_set1     = S5PV210_GPH0(3),
+        .buck1_set2     = S5PV210_GPH0(4),
+        .buck2_set3     = S5PV210_GPH0(5),
+        .buck1_max_voltage1 = 1200000,
+        .buck1_max_voltage2 = 1200000,
+        .buck2_max_voltage = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 82ce4aa6d61a..72ab289e7816 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -24,8 +24,6 @@
 #include <mach/regs-irq.h>
-void __iomem *gic_cpu_base_addr;
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                         unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -122,9 +120,7 @@ void __init s5pv310_init_irq(void)
 {
        int irq;
-        gic_cpu_base_addr = S5P_VA_GIC_CPU;
+        gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-        gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER);
-        gic_cpu_init(0, S5P_VA_GIC_CPU);
        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index b7ec252384f4..e1cc6a251c6a 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -9,8 +9,6 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_mpidr.h>
-extern void __iomem *gic_cpu_base_addr;
 /*
 * We use IRQ1 as the IPI
 */
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
index d357c198edee..15929c169f81 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-s5pv310/platsmp.c
@@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
        /*
         * let the primary processor know we're out of the
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 5da8c35aa0de..42625e4d949a 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -118,6 +118,16 @@ config SA1100_LART
          (also known as the LART).  See <http://www.lartmaker.nl/> for
          information on the LART.
+config SA1100_NANOENGINE
+        bool "nanoEngine"
+        select CPU_FREQ_SA1110
+        select PCI
+        select PCI_NANOENGINE
+        help
+          Say Y here if you are using the Bright Star Engineering nanoEngine.
+          See <http://www.brightstareng.com/arm/nanoeng.htm> for information
+          on the BSE nanoEngine.
 config SA1100_PLEB
        bool "PLEB"
        select CPU_FREQ_SA1100
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 89349c1dd7a6..e697691eed28 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_SA1100_JORNADA720_SSP)	+= jornada720_ssp.o
 obj-$(CONFIG_SA1100_LART)               += lart.o
 led-$(CONFIG_SA1100_LART)               += leds-lart.o
+obj-$(CONFIG_SA1100_NANOENGINE)         += nanoengine.o
+obj-$(CONFIG_PCI_NANOENGINE)            += pci-nanoengine.o
 obj-$(CONFIG_SA1100_PLEB)               += pleb.o
 obj-$(CONFIG_SA1100_SHANNON)            += shannon.o
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 96f7dc103b59..07d4e8ba3719 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -94,48 +94,47 @@
 #include "generic.h"
-typedef struct {
+struct sa1100_dram_regs {
        int speed;
        u32 mdcnfg;
        u32 mdcas0;
        u32 mdcas1;
        u32 mdcas2;
-} sa1100_dram_regs_t;
+};
 static struct cpufreq_driver sa1100_driver;
-static sa1100_dram_regs_t sa1100_dram_settings[] =
+static struct sa1100_dram_regs sa1100_dram_settings[] = {
-{
+        /*speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2,   clock freq */
-        /* speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2  clock frequency */
+        { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  59.0 MHz */
-        {  59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  59.0 MHz */
+        { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  73.7 MHz */
-        {  73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  73.7 MHz */
+        { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  88.5 MHz */
-        {  88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  88.5 MHz */
+        {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
-        { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */
+        {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
-        { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */
+        {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
-        { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */
+        {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
-        { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */
+        {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
-        { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */
+        {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
-        { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */
+        {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
-        { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */
+        {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
-        { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */
+        {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
-        { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */
+        {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
-        { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */
+        {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
-        { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */
+        {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
-        { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */
+        {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
-        { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */
        { 0, 0, 0, 0, 0 } /* last entry */
 };
 static void sa1100_update_dram_timings(int current_speed, int new_speed)
 {
-        sa1100_dram_regs_t *settings = sa1100_dram_settings;
+        struct sa1100_dram_regs *settings = sa1100_dram_settings;
        /* find speed */
        while (settings->speed != 0) {
-                if(new_speed == settings->speed)
+                if (new_speed == settings->speed)
                        break;
-                
                settings++;
        }
@@ -149,7 +148,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed)
                /* We're going FASTER, so first relax the memory
                 * timings before changing the core frequency
                 */
-                
                /* Half the memory access clock */
                MDCNFG |= MDCNFG_CDB2;
@@ -187,7 +186,7 @@ static int sa1100_target(struct cpufreq_policy *policy,
        struct cpufreq_freqs freqs;
        new_ppcr = sa11x0_freq_to_ppcr(target_freq);
-        switch(relation){
+        switch (relation) {
        case CPUFREQ_RELATION_L:
                if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
                        new_ppcr--;
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 7252874d328b..675bf8ef97e8 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -16,28 +16,24 @@
 *
 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
 */
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
-#include <mach/hardware.h>
 #include <asm/cputype.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
+#include <mach/hardware.h>
 #include "generic.h"
 #undef DEBUG
-static struct cpufreq_driver sa1110_driver;
 struct sdram_params {
-        const char name[16];
+        const char name[20];
        u_char  rows;           /* bits                          */
        u_char  cas_latency;    /* cycles                        */
        u_char  tck;            /* clock cycle time (ns)         */
@@ -107,6 +103,15 @@ static struct sdram_params sdram_tbl[] __initdata = {
                .twr            = 8,
                .refresh        = 64000,
                .cas_latency    = 3,
+        }, {    /* Micron MT48LC8M16A2TG-75 */
+                .name           = "MT48LC8M16A2TG-75",
+                .rows           = 12,
+                .tck            = 8,
+                .trcd           = 20,
+                .trp            = 20,
+                .twr            = 8,
+                .refresh        = 64000,
+                .cas_latency    = 3,
        },
 };
@@ -180,11 +185,13 @@ sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
                sd->mdrefr |= MDREFR_K1DB2;
        /* initial number of '1's in MDCAS + 1 */
-        set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
+        set_mdcas(sd->mdcas, sd_khz >= 62000,
+                ns_to_cycles(sdram->trcd, mem_khz));
 #ifdef DEBUG
-        printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
+        printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
-                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
+                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
+                sd->mdcas[2]);
 #endif
 }
@@ -213,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
 #ifdef DEBUG
        mdelay(250);
-        printk("new dri value = %d\n", dri);
+        printk(KERN_DEBUG "new dri value = %d\n", dri);
 #endif
        sdram_set_refresh(dri);
@@ -232,7 +239,7 @@ static int sa1110_target(struct cpufreq_policy *policy,
        unsigned long flags;
        unsigned int ppcr, unused;
-        switch(relation){
+        switch (relation) {
        case CPUFREQ_RELATION_L:
                ppcr = sa11x0_freq_to_ppcr(target_freq);
                if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
@@ -280,11 +287,10 @@ static int sa1110_target(struct cpufreq_policy *policy,
         * We wait 20ms to be safe.
         */
        sdram_set_refresh(2);
-        if (!irqs_disabled()) {
+        if (!irqs_disabled())
                msleep(20);
-        } else {
+        else
                mdelay(20);
-        }
        /*
         * Reprogram the DRAM timings with interrupts disabled, and
@@ -295,7 +301,7 @@ static int sa1110_target(struct cpufreq_policy *policy,
        local_irq_save(flags);
        asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
        udelay(10);
-        __asm__ __volatile__("                                  \n\
+        __asm__ __volatile__("\n\
                b       2f                                      \n\
                .align  5                                       \n\
 1:              str     %3, [%1, #0]            @ MDCNFG        \n\
@@ -336,7 +342,9 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
        return 0;
 }
-static struct cpufreq_driver sa1110_driver = {
+/* sa1110_driver needs __refdata because it must remain after init registers
+ * it with cpufreq_register_driver() */
+static struct cpufreq_driver sa1110_driver __refdata = {
        .flags          = CPUFREQ_STICKY,
        .verify         = sa11x0_verify_speed,
        .target         = sa1110_target,
@@ -349,7 +357,8 @@ static struct sdram_params *sa1110_find_sdram(const char *name)
 {
        struct sdram_params *sdram;
-        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
+        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
+             sdram++)
                if (strcmp(name, sdram->name) == 0)
                        return sdram;
@@ -369,14 +378,14 @@ static int __init sa1110_clk_init(void)
        if (!name[0]) {
                if (machine_is_assabet())
                        name = "TC59SM716-CL3";
                if (machine_is_pt_system3())
                        name = "K4S641632D";
                if (machine_is_h3100())
                        name = "KM416S4030CT";
                if (machine_is_jornada720())
-                        name = "K4S281632B-1H";
+                        name = "K4S281632B-1H";
+                if (machine_is_nanoengine())
+                        name = "MT48LC8M16A2TG-75";
        }
        sdram = sa1110_find_sdram(name);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 3c1fcd696714..3555d616774c 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -163,10 +163,15 @@ static void sa11x0_register_device(struct platform_device *dev, void *data)
 static struct resource sa11x0udc_resources[] = {
        [0] = {
-                .start  = 0x80000000,
+                .start  = __PREG(Ser0UDCCR),
-                .end    = 0x8000ffff,
+                .end    = __PREG(Ser0UDCCR) + 0xffff,
                .flags  = IORESOURCE_MEM,
        },
+        [1] = {
+                .start  = IRQ_Ser0UDC,
+                .end    = IRQ_Ser0UDC,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
@@ -184,10 +189,15 @@ static struct platform_device sa11x0udc_device = {
 static struct resource sa11x0uart1_resources[] = {
        [0] = {
-                .start  = 0x80010000,
+                .start  = __PREG(Ser1UTCR0),
-                .end    = 0x8001ffff,
+                .end    = __PREG(Ser1UTCR0) + 0xffff,
                .flags  = IORESOURCE_MEM,
        },
+        [1] = {
+                .start  = IRQ_Ser1UART,
+                .end    = IRQ_Ser1UART,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static struct platform_device sa11x0uart1_device = {
@@ -199,10 +209,15 @@ static struct platform_device sa11x0uart1_device = {
 static struct resource sa11x0uart3_resources[] = {
        [0] = {
-                .start  = 0x80050000,
+                .start  = __PREG(Ser3UTCR0),
-                .end    = 0x8005ffff,
+                .end    = __PREG(Ser3UTCR0) + 0xffff,
                .flags  = IORESOURCE_MEM,
        },
+        [1] = {
+                .start  = IRQ_Ser3UART,
+                .end    = IRQ_Ser3UART,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static struct platform_device sa11x0uart3_device = {
@@ -214,10 +229,15 @@ static struct platform_device sa11x0uart3_device = {
 static struct resource sa11x0mcp_resources[] = {
        [0] = {
-                .start  = 0x80060000,
+                .start  = __PREG(Ser4MCCR0),
-                .end    = 0x8006ffff,
+                .end    = __PREG(Ser4MCCR0) + 0xffff,
                .flags  = IORESOURCE_MEM,
        },
+        [1] = {
+                .start  = IRQ_Ser4MCP,
+                .end    = IRQ_Ser4MCP,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
@@ -244,6 +264,11 @@ static struct resource sa11x0ssp_resources[] = {
                .end    = 0x8007ffff,
                .flags  = IORESOURCE_MEM,
        },
+        [1] = {
+                .start  = IRQ_Ser4SSP,
+                .end    = IRQ_Ser4SSP,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de4..967ae7684390 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void)
 #include "SA-1101.h"
 #endif
+#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO          0
+#define PCIBIOS_MIN_MEM         0
+#define pcibios_assign_all_busses()     1
+#define HAVE_ARCH_PCI_SET_DMA_MASK      1
+#endif
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
new file mode 100644
index 000000000000..14f8382d0665
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/nanoengine.h
+ *
+ * This file contains the hardware specific definitions for nanoEngine.
+ * Only include this file from SA1100-specific files.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_ARCH_NANOENGINE_H
+#define __ASM_ARCH_NANOENGINE_H
+#include <mach/irqs.h>
+#define GPIO_PC_READY0  GPIO_GPIO(11) /* ready for socket 0 (active high)*/
+#define GPIO_PC_READY1  GPIO_GPIO(12) /* ready for socket 1 (active high) */
+#define GPIO_PC_CD0     GPIO_GPIO(13) /* detect for socket 0 (active low) */
+#define GPIO_PC_CD1     GPIO_GPIO(14) /* detect for socket 1 (active low) */
+#define GPIO_PC_RESET0  GPIO_GPIO(15) /* reset socket 0 */
+#define GPIO_PC_RESET1  GPIO_GPIO(16) /* reset socket 1 */
+#define NANOENGINE_IRQ_GPIO_PCI         IRQ_GPIO0
+#define NANOENGINE_IRQ_GPIO_PC_READY0   IRQ_GPIO11
+#define NANOENGINE_IRQ_GPIO_PC_READY1   IRQ_GPIO12
+#define NANOENGINE_IRQ_GPIO_PC_CD0      IRQ_GPIO13
+#define NANOENGINE_IRQ_GPIO_PC_CD1      IRQ_GPIO14
+/*
+ * nanoEngine Memory Map:
+ *
+ * 0000.0000 - 003F.0000 -   4 MB Flash
+ * C000.0000 - C1FF.FFFF -  32 MB SDRAM
+ * 1860.0000 - 186F.FFFF -   1 MB Internal PCI Memory Read/Write
+ * 18A1.0000 - 18A1.FFFF -  64 KB Internal PCI Config Space
+ * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
+ * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
+ *
+ */
+#define NANO_PCI_MEM_RW_PHYS            0x18600000
+#define NANO_PCI_MEM_RW_VIRT            0xf1000000
+#define NANO_PCI_MEM_RW_SIZE            SZ_1M
+#define NANO_PCI_CONFIG_SPACE_PHYS      0x18A10000
+#define NANO_PCI_CONFIG_SPACE_VIRT      0xf2000000
+#define NANO_PCI_CONFIG_SPACE_SIZE      SZ_64K
+#endif
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
new file mode 100644
index 000000000000..72087f0658b7
--- /dev/null
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -0,0 +1,119 @@
+/*
+ * linux/arch/arm/mach-sa1100/nanoengine.c
+ *
+ * Bright Star Engineering's nanoEngine board init code.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/root_dev.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/serial_sa1100.h>
+#include <mach/hardware.h>
+#include <mach/nanoengine.h>
+#include "generic.h"
+/* Flash bank 0 */
+static struct mtd_partition nanoengine_partitions[] = {
+        {
+                .name   = "nanoEngine boot firmware and parameter table",
+                .size           = 0x00010000,  /* 32K */
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel/initrd reserved",
+                .size           = 0x002f0000,
+                .offset         = 0x00010000,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "experimental filesystem allocation",
+                .size           = 0x00100000,
+                .offset         = 0x00300000,
+                .mask_flags     = MTD_WRITEABLE,
+        }
+};
+static struct flash_platform_data nanoengine_flash_data = {
+        .map_name       = "jedec_probe",
+        .parts          = nanoengine_partitions,
+        .nr_parts       = ARRAY_SIZE(nanoengine_partitions),
+};
+static struct resource nanoengine_flash_resources[] = {
+        {
+                .start  = SA1100_CS0_PHYS,
+                .end    = SA1100_CS0_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = SA1100_CS1_PHYS,
+                .end    = SA1100_CS1_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct map_desc nanoengine_io_desc[] __initdata = {
+        {
+                /* System Registers */
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0x10000000),
+                .length         = 0x00100000,
+                .type           = MT_DEVICE
+        }, {
+                /* Internal PCI Memory Read/Write */
+                .virtual        = NANO_PCI_MEM_RW_VIRT,
+                .pfn            = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
+                .length         = NANO_PCI_MEM_RW_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                /* Internal PCI Config Space */
+                .virtual        = NANO_PCI_CONFIG_SPACE_VIRT,
+                .pfn            = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
+                .length         = NANO_PCI_CONFIG_SPACE_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+static void __init nanoengine_map_io(void)
+{
+        sa1100_map_io();
+        iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
+        sa1100_register_uart(0, 1);
+        sa1100_register_uart(1, 2);
+        sa1100_register_uart(2, 3);
+        Ser1SDCR0 |= SDCR0_UART;
+        /* disable IRDA -- UART2 is used as a normal serial port */
+        Ser2UTCR4 = 0;
+        Ser2HSCR0 = 0;
+}
+static void __init nanoengine_init(void)
+{
+        sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
+                ARRAY_SIZE(nanoengine_flash_resources));
+}
+MACHINE_START(NANOENGINE, "BSE nanoEngine")
+        .boot_params    = 0xc0000000,
+        .map_io         = nanoengine_map_io,
+        .init_irq       = sa1100_init_irq,
+        .timer          = &sa1100_timer,
+        .init_machine   = nanoengine_init,
+MACHINE_END
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
new file mode 100644
index 000000000000..fba7a913f12b
--- /dev/null
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -0,0 +1,284 @@
+/*
+ * linux/arch/arm/mach-sa1100/pci-nanoengine.c
+ *
+ * PCI functions for BSE nanoEngine PCI
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <mach/nanoengine.h>
+static DEFINE_SPINLOCK(nano_lock);
+static int nanoengine_get_pci_address(struct pci_bus *bus,
+        unsigned int devfn, int where, unsigned long *address)
+{
+        int ret = PCIBIOS_DEVICE_NOT_FOUND;
+        unsigned int busnr = bus->number;
+        *address = NANO_PCI_CONFIG_SPACE_VIRT +
+                ((bus->number << 16) | (devfn << 8) | (where & ~3));
+        ret = (busnr > 255 || devfn > 255 || where > 255) ?
+                PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+        return ret;
+}
+static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+        int size, u32 *val)
+{
+        int ret;
+        unsigned long address;
+        unsigned long flags;
+        u32 v;
+        /* nanoEngine PCI bridge does not return -1 for a non-existing
+         * device. We must fake the answer. We know that the only valid
+         * device is device zero at bus 0, which is the network chip. */
+        if (bus->number != 0 || (devfn >> 3) != 0) {
+                v = -1;
+                nanoengine_get_pci_address(bus, devfn, where, &address);
+                goto exit_function;
+        }
+        spin_lock_irqsave(&nano_lock, flags);
+        ret = nanoengine_get_pci_address(bus, devfn, where, &address);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        v = __raw_readl(address);
+        spin_unlock_irqrestore(&nano_lock, flags);
+        v >>= ((where & 3) * 8);
+        v &= (unsigned long)(-1) >> ((4 - size) * 8);
+exit_function:
+        *val = v;
+        return PCIBIOS_SUCCESSFUL;
+}
+static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+        int size, u32 val)
+{
+        int ret;
+        unsigned long address;
+        unsigned long flags;
+        unsigned shift;
+        u32 v;
+        shift = (where & 3) * 8;
+        spin_lock_irqsave(&nano_lock, flags);
+        ret = nanoengine_get_pci_address(bus, devfn, where, &address);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        v = __raw_readl(address);
+        switch (size) {
+        case 1:
+                v &= ~(0xFF << shift);
+                v |= val << shift;
+                break;
+        case 2:
+                v &= ~(0xFFFF << shift);
+                v |= val << shift;
+                break;
+        case 4:
+                v = val;
+                break;
+        }
+        __raw_writel(v, address);
+        spin_unlock_irqrestore(&nano_lock, flags);
+        return PCIBIOS_SUCCESSFUL;
+}
+static struct pci_ops pci_nano_ops = {
+        .read   = nanoengine_read_config,
+        .write  = nanoengine_write_config,
+};
+static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return NANOENGINE_IRQ_GPIO_PCI;
+}
+struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
+}
+static struct resource pci_io_ports = {
+        .name   = "PCI IO",
+        .start  = 0x400,
+        .end    = 0x7FF,
+        .flags  = IORESOURCE_IO,
+};
+static struct resource pci_non_prefetchable_memory = {
+        .name   = "PCI non-prefetchable",
+        .start  = NANO_PCI_MEM_RW_PHYS,
+        /* nanoEngine documentation says there is a 1 Megabyte window here,
+         * but PCI reports just 128 + 8 kbytes. */
+        .end    = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
+/*      .end    = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
+        .flags  = IORESOURCE_MEM,
+};
+/*
+ * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
+ * overlaps with previously defined memory.
+ *
+ * Here is what happens:
+ *
+# dmesg
+...
+pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
+pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
+pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
+pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
+pci 0000:00:00.0: supports D1 D2
+pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
+pci 0000:00:00.0: PME# disabled
+PCI: bus0: Fast back to back transfers enabled
+pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
+pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
+pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
+pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
+pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
+pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
+pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
+ *
+ * On the other hand, if we do not request the prefetchable memory resource,
+ * linux will alloc it first and the two non-prefetchable memory areas that
+ * are our real interest will not be mapped. So we choose to map it to an
+ * unused area. It gets recognized as expansion ROM, but becomes disabled.
+ *
+ * Here is what happens then:
+ *
+# dmesg
+...
+pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
+pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
+pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
+pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
+pci 0000:00:00.0: supports D1 D2
+pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
+pci 0000:00:00.0: PME# disabled
+PCI: bus0: Fast back to back transfers enabled
+pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
+pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
+pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
+pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
+pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
+pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
+pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
+# lspci -vv -s 0000:00:00.0
+00:00.0 Class 0200: Device 8086:1209 (rev 09)
+        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
+        Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
+        Interrupt: pin A routed to IRQ 0
+        Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
+        Region 1: I/O ports at 0400 [size=64]
+        Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
+        [virtual] Expansion ROM at 78000000 [disabled] [size=1M]
+        Capabilities: [dc] Power Management version 2
+                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
+                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
+        Kernel driver in use: e100
+        Kernel modules: e100
+ *
+ */
+static struct resource pci_prefetchable_memory = {
+        .name   = "PCI prefetchable",
+        .start  = 0x78000000,
+        .end    = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
+        .flags  = IORESOURCE_MEM  | IORESOURCE_PREFETCH,
+};
+static int __init pci_nanoengine_setup_resources(struct resource **resource)
+{
+        if (request_resource(&ioport_resource, &pci_io_ports)) {
+                printk(KERN_ERR "PCI: unable to allocate io port region\n");
+                return -EBUSY;
+        }
+        if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
+                release_resource(&pci_io_ports);
+                printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
+                return -EBUSY;
+        }
+        if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
+                release_resource(&pci_io_ports);
+                release_resource(&pci_non_prefetchable_memory);
+                printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
+                return -EBUSY;
+        }
+        resource[0] = &pci_io_ports;
+        resource[1] = &pci_non_prefetchable_memory;
+        resource[2] = &pci_prefetchable_memory;
+        return 1;
+}
+int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
+{
+        int ret = 0;
+        if (nr == 0) {
+                sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
+                sys->io_offset = 0x400;
+                ret = pci_nanoengine_setup_resources(sys->resource);
+                /* Enable alternate memory bus master mode, see
+                 * "Intel StrongARM SA1110 Developer's Manual",
+                 * section 10.8, "Alternate Memory Bus Master Mode". */
+                GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
+                GAFR |= GPIO_MBGNT | GPIO_MBREQ;
+                TUCR |= TUCR_MBGPIO;
+        }
+        return ret;
+}
+static struct hw_pci nanoengine_pci __initdata = {
+        .map_irq                = pci_nanoengine_map_irq,
+        .nr_controllers         = 1,
+        .scan                   = pci_nanoengine_scan_bus,
+        .setup                  = pci_nanoengine_setup,
+};
+static int __init nanoengine_pci_init(void)
+{
+        if (machine_is_nanoengine())
+                pci_common_init(&nanoengine_pci);
+        return 0;
+}
+subsys_initcall(nanoengine_pci_init);
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 27692d0ffbe8..cfb76077bd25 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -166,9 +166,6 @@ static void __init simpad_map_io(void)
        PCFR = 0;
        PSDR = 0;
-        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
-                              ARRAY_SIZE(simpad_flash_resources));
-        sa11x0_register_mcp(&simpad_mcp_data);
 }
 static void simpad_power_off(void)
@@ -216,6 +213,10 @@ static int __init simpad_init(void)
        pm_power_off = simpad_power_off;
+        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
+                              ARRAY_SIZE(simpad_flash_resources));
+        sa11x0_register_mcp(&simpad_mcp_data);
        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
        if(ret)
                printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device");
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index d440e5f456ad..ac429ff2c20d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,6 +61,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/setup.h>
 /*
 * Address      Interface               BusWidth        note
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index a285d13c7416..f428c4db2b60 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2010 Magnus Damm
 * Copyright (C) 2008 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
@@ -14,24 +15,45 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <mach/hardware.h>
 #include <mach/irqs.h>
+#define INTCA_BASE      0xe6980000
+#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
+#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
+#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
+#define INTLVLB_OFFS    0x00000034 /* previous priority level */
        .macro  disable_fiq
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =INTFLGA
+        ldr     \base, =INTCA_BASE
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base]
+        /* The single INTFLGA read access below results in the following:
+         *
+         * 1. INTLVLB is updated with old priority value from INTLVLA
+         * 2. Highest priority interrupt is accepted
+         * 3. INTLVLA is updated to contain priority of accepted interrupt
+         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
+         */
+        ldr     \irqnr, [\base, #INTFLGA_OFFS]
+        /* Restore INTLVLA with the value saved in INTLVLB.
+         * This is required to support interrupt priorities properly.
+         */
+        ldrb    \tmp, [\base, #INTLVLB_OFFS]
+        strb    \tmp, [\base, #INTLVLA_OFFS]
+        /* Handle invalid vector number case */
        cmp     \irqnr, #0
        beq     1000f
-        /* intevt to irq number */
+        /* Convert vector to irq number, same as the evt2irq() macro */
        lsr     \irqnr, \irqnr, #0x5
        subs    \irqnr, \irqnr, #16
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
new file mode 100644
index 000000000000..e3ebfa73956e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -0,0 +1,87 @@
+LIST "partner-jet-setup.txt"
+LIST "(C) Copyright 2010 Renesas Solutions Corp"
+LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
+LIST "RWT Setting"
+EW 0xE6020004, 0xA500
+EW 0xE6030004, 0xA500
+DD 0x01001000, 0x01001000
+LIST "GPIO Setting"
+EB 0xE6051013, 0xA2
+LIST "CPG"
+ED 0xE6150080, 0x00000180
+ED 0xE61500C0, 0x00000002
+WAIT 1, 0xFE40009C
+LIST "FRQCR"
+ED 0xE6150000, 0x2D1305C3
+ED 0xE61500E0, 0x9E40358E
+ED 0xE6150004, 0x80331050
+WAIT 1, 0xFE40009C
+ED 0xE61500E4, 0x00002000
+WAIT 1, 0xFE40009C
+LIST "PLL"
+ED 0xE6150028, 0x00004000
+WAIT 1, 0xFE40009C
+ED 0xE615002C, 0x93000040
+WAIT 1, 0xFE40009C
+LIST "BSC"
+ED 0xFEC10000, 0x00E0001B
+LIST "SBSC1"
+ED 0xFE400354, 0x01AD8000
+ED 0xFE400354, 0x01AD8001
+WAIT 5, 0xFE40009C
+ED 0xFE400008, 0xBCC90151
+ED 0xFE400040, 0x41774113
+ED 0xFE400044, 0x2712E229
+ED 0xFE400048, 0x20C18505
+ED 0xFE40004C, 0x00110209
+ED 0xFE400010, 0x00000087
+WAIT 10, 0xFE40009C
+ED 0xFE400084, 0x0000003F
+EB 0xFE500000, 0x00
+WAIT 5, 0xFE40009C
+ED 0xFE400084, 0x0000FF0A
+EB 0xFE500000, 0x00
+WAIT 1, 0xFE40009C
+ED 0xFE400084, 0x00002201
+EB 0xFE500000, 0x00
+ED 0xFE400084, 0x00000302
+EB 0xFE500000, 0x00
+EB 0xFE5C0000, 0x00
+ED 0xFE400008, 0xBCC90159
+ED 0xFE40008C, 0x88800004
+ED 0xFE400094, 0x00000004
+ED 0xFE400028, 0xA55A0032
+ED 0xFE40002C, 0xA55A000C
+ED 0xFE400020, 0xA55A2048
+ED 0xFE400008, 0xBCC90959
+LIST "Change CPGA setting"
+ED 0xE61500E0, 0x9E40352E
+ED 0xE6150004, 0x80331050
+WAIT 1, 0xFE40009C
+ED 0xE6150354, 0x00000002
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
index 4aecf6e3a859..2b8fd8b942fe 100644
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -2,6 +2,6 @@
 #define __ASM_MACH_VMALLOC_H
 /* Vmalloc at ... - 0xe5ffffff */
-#define VMALLOC_END 0xe6000000
+#define VMALLOC_END 0xe6000000UL
 #endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
new file mode 100644
index 000000000000..3ad86b7708e9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -0,0 +1,20 @@
+#ifndef ZBOOT_H
+#define ZBOOT_H
+#include <asm/mach-types.h>
+#include <mach/zboot_macros.h>
+/**************************************************
+ *
+ *              board specific settings
+ *
+ **************************************************/
+#ifdef CONFIG_MACH_AP4EVB
+#define MACH_TYPE       MACH_TYPE_AP4EVB
+#include "mach/head-ap4evb.txt"
+#else
+#error "unsupported board."
+#endif
+#endif /* ZBOOT_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
new file mode 100644
index 000000000000..aa6111fbc989
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
@@ -0,0 +1,65 @@
+#ifndef __ZBOOT_MACRO_H
+#define __ZBOOT_MACRO_H
+/* The LIST command is used to include comments in the script */
+.macro  LIST comment
+.endm
+/* The ED command is used to write a 32-bit word */
+.macro ED, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STR     r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+/* The EW command is used to write a 16-bit word */
+.macro EW, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STRH    r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+/* The EB command is used to write an 8-bit word */
+.macro EB, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STRB    r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+/* The WAIT command is used to delay the execution */
+.macro  WAIT, time, reg
+        LDR     r1, 1f
+        LDR     r0, 2f
+        STR     r0, [r1]
+10 :
+        LDR     r0, [r1]
+        CMP     r0, #0x00000000
+        BNE     10b
+        NOP
+        B       3f
+1 :     .long   \reg
+2 :     .long   \time * 100
+3 :
+.endm
+/* The DD command is used to read a 32-bit word */
+.macro  DD, start, end
+        LDR     r1, 1f
+        B       2f
+1 :     .long   \start
+2 :
+.endm
+#endif /* __ZBOOT_MACRO_H */
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index 2ba9e5c9d2f6..dd165c53889d 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -16,8 +16,8 @@
 #include <mach/io.h>
 #if defined(CONFIG_ARM_GIC)
+#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
        /* Uses the GIC interrupt controller built into the cpu */
 #define ICTRL_BASE (IO_CPU_VIRT + 0x100)
@@ -32,68 +32,6 @@
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        /*
-         * The interrupt numbering scheme is defined in the
-         * interrupt controller spec.  To wit:
-         *
-         * Interrupts 0-15 are IPI
-         * 16-28 are reserved
-         * 29-31 are local.  We allow 30 to be used for the watchdog.
-         * 32-1020 are global
-         * 1021-1022 are reserved
-         * 1023 is "spurious" (no interrupt)
-         *
-         * For now, we ignore all local interrupts so only return an interrupt
-         * if it's between 30 and 1020.  The test_for_ipi routine below will
-         * pick up on IPIs.
-         *
-         * A simple read from the controller will tell us the number of the
-         * highest priority enabled interrupt.  We then just need to check
-         * whether it is in the valid range for an IRQ (30-1020 inclusive).
-         */
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        /* bits 12-10 = src CPU, 9-0 = int # */
-        ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-        ldr             \tmp, =1021
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #29
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-        .endm
-        /* We assume that irqstat (the raw value of the IRQ acknowledge
-         * register) is preserved from the macro above.
-         * If there is an IPI, we immediately signal end of interrupt on the
-         * controller, since this requires the original irqstat value which
-         * we won't easily be able to recreate later.
-         */
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #16
-        strcc   \irqstat, [\base, #GIC_CPU_EOI]
-        cmpcs   \irqnr, \irqnr
-        .endm
-        /* As above, this assumes that irqstat and base are preserved.. */
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        mov     \tmp, #0
-        cmp     \irqnr, #29
-        moveq   \tmp, #1
-        streq   \irqstat, [\base, #GIC_CPU_EOI]
-        cmp     \tmp, #0
-        .endm
 #else
        /* legacy interrupt controller for AP16 */
        .macro  disable_fiq
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 50a8dfb9a0cf..5407de01abf0 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -94,8 +94,8 @@ void __init tegra_init_irq(void)
                writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS);
        }
-        gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
+        gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
-        gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+                 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
        gic = get_irq_chip(29);
        gic_unmask_irq = gic->unmask;
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1c0fd92cab39..3b7376c4f356 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -48,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
+        gic_secondary_init(0);
        /*
         * Synchronise with the boot thread.
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 608a1372b172..7328c0179769 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -61,8 +61,8 @@ void __init ux500_init_devices(void)
 void __init ux500_init_irq(void)
 {
-        gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
+        gic_init(0, 29, __io_address(UX500_GIC_DIST_BASE),
-        gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
+                 __io_address(UX500_GIC_CPU_BASE));
        /*
         * Init clocks here so that they are available for system timer
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index 60ea88db8283..a37f585a3ecb 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -11,7 +11,8 @@
 * warranty of any kind, whether express or implied.
 */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
@@ -22,68 +23,3 @@
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020. The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt. We then just
-                 * need to check whether it is in the valid range for an
-                 * IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ
-                 * acknowledge register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of
-                 * interrupt on the controller, since this requires the
-                 * original irqstat value which we won't easily be able
-                 * to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* As above, this assumes that irqstat and base
-                 * are preserved..
-                 */
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 9e4c678de785..b5077b4c419f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
+        gic_secondary_init(0);
        /*
         * let the primary processor know we're out of the
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e38acb0f89c8..6b93bd600271 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -49,7 +49,7 @@
 #include <mach/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 #include "core.h"
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 57dd95ce41f9..362780d868de 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -22,5 +22,3 @@ struct map_desc;
 void v2m_map_io(struct map_desc *tile, size_t num);
 extern struct sys_timer v2m_timer;
-extern void __iomem *gic_cpu_base_addr;
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index fd25ccd7272f..cb5793ef3ee0 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -21,7 +21,7 @@
 #include <mach/clkdev.h>
 #include <mach/ct-ca9x4.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -60,13 +60,10 @@ static void __init ct_ca9x4_map_io(void)
        v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
-void __iomem *gic_cpu_base_addr;
 static void __init ct_ca9x4_init_irq(void)
 {
-        gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
+        gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-        gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
+                 MMIO_P2V(A9_MPCORE_GIC_CPU));
-        gic_cpu_init(0, gic_cpu_base_addr);
 }
 #if 0
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
index 20e9fb514f0a..73c11297509e 100644
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
@@ -1,67 +1,7 @@
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =gic_cpu_base_addr
-        ldr     \base, [\base]
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        /*
-         * The interrupt numbering scheme is defined in the
-         * interrupt controller spec.  To wit:
-         *
-         * Interrupts 0-15 are IPI
-         * 16-28 are reserved
-         * 29-31 are local.  We allow 30 to be used for the watchdog.
-         * 32-1020 are global
-         * 1021-1022 are reserved
-         * 1023 is "spurious" (no interrupt)
-         *
-         * For now, we ignore all local interrupts so only return an interrupt if it's
-         * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-         *
-         * A simple read from the controller will tell us the number of the highest
-         * priority enabled interrupt.  We then just need to check whether it is in the
-         * valid range for an IRQ (30-1020 inclusive).
-         */
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-        ldr     \tmp, =1021
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #29
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-        .endm
-        /* We assume that irqstat (the raw value of the IRQ acknowledge
-         * register) is preserved from the macro above.
-         * If there is an IPI, we immediately signal end of interrupt on the
-         * controller, since this requires the original irqstat value which
-         * we won't easily be able to recreate later.
-         */
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #16
-        strcc   \irqstat, [\base, #GIC_CPU_EOI]
-        cmpcs   \irqnr, \irqnr
-        .endm
-        /* As above, this assumes that irqstat and base are preserved.. */
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        mov     \tmp, #0
-        cmp     \irqnr, #29
-        moveq   \tmp, #1
-        streq   \irqstat, [\base, #GIC_CPU_EOI]
-        cmp     \tmp, #0
-        .endm
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 670970699ba9..dfb591031d17 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -51,7 +51,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
        /*
         * let the primary processor know we're out of the
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 7eaa232180a5..91ff2e0df856 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -22,7 +22,7 @@
 #include <mach/clkdev.h>
 #include <mach/motherboard.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 #include "core.h"
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 6e77c042d8e9..e0b0e7a4ec68 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -13,13 +13,9 @@
 */
 #include <linux/init.h>
+#include <linux/highmem.h>
 #include <asm/cacheflush.h>
-#include <asm/kmap_types.h>
-#include <asm/fixmap.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
 #include <plat/cache-feroceon-l2.h>
-#include "mm.h"
 /*
 * Low-level cache maintenance operations.
@@ -39,27 +35,30 @@
 * between which we don't want to be preempted.
 */
-static inline unsigned long l2_start_va(unsigned long paddr)
+static inline unsigned long l2_get_va(unsigned long paddr)
 {
 #ifdef CONFIG_HIGHMEM
        /*
-         * Let's do our own fixmap stuff in a minimal way here.
         * Because range ops can't be done on physical addresses,
         * we simply install a virtual mapping for it only for the
         * TLB lookup to occur, hence no need to flush the untouched
-         * memory mapping.  This is protected with the disabling of
+         * memory mapping afterwards (note: a cache flush may happen
-         * interrupts by the caller.
+         * in some circumstances depending on the path taken in kunmap_atomic).
         */
-        unsigned long idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
+        void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);
-        unsigned long vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        return (unsigned long)vaddr + (paddr & ~PAGE_MASK);
-        set_pte_ext(TOP_PTE(vaddr), pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL), 0);
-        local_flush_tlb_kernel_page(vaddr);
-        return vaddr + (paddr & ~PAGE_MASK);
 #else
        return __phys_to_virt(paddr);
 #endif
 }
+static inline void l2_put_va(unsigned long vaddr)
+{
+#ifdef CONFIG_HIGHMEM
+        kunmap_atomic((void *)vaddr);
+#endif
+}
 static inline void l2_clean_pa(unsigned long addr)
 {
        __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
@@ -76,13 +75,14 @@ static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
         */
        BUG_ON((start ^ end) >> PAGE_SHIFT);
-        raw_local_irq_save(flags);
+        va_start = l2_get_va(start);
-        va_start = l2_start_va(start);
        va_end = va_start + (end - start);
+        raw_local_irq_save(flags);
        __asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
                "mcr p15, 1, %1, c15, c9, 5"
                : : "r" (va_start), "r" (va_end));
        raw_local_irq_restore(flags);
+        l2_put_va(va_start);
 }
 static inline void l2_clean_inv_pa(unsigned long addr)
@@ -106,13 +106,14 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
         */
        BUG_ON((start ^ end) >> PAGE_SHIFT);
-        raw_local_irq_save(flags);
+        va_start = l2_get_va(start);
-        va_start = l2_start_va(start);
        va_end = va_start + (end - start);
+        raw_local_irq_save(flags);
        __asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
                "mcr p15, 1, %1, c15, c11, 5"
                : : "r" (va_start), "r" (va_end));
        raw_local_irq_restore(flags);
+        l2_put_va(va_start);
 }
 static inline void l2_inv_all(void)
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 99fa688dfadd..c96fa1b3f49f 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -203,6 +203,10 @@ ENTRY(v6_flush_kern_dcache_area)
 *      - end     - virtual end address of region
 */
 v6_dma_inv_range:
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrb    r2, [r0]                        @ read for ownership
+        strb    r2, [r0]                        @ write for ownership
+#endif
        tst     r0, #D_CACHE_LINE_SIZE - 1
        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -211,6 +215,10 @@ v6_dma_inv_range:
        mcrne   p15, 0, r0, c7, c11, 1          @ clean unified line
 #endif
        tst     r1, #D_CACHE_LINE_SIZE - 1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrneb  r2, [r1, #-1]                   @ read for ownership
+        strneb  r2, [r1, #-1]                   @ write for ownership
+#endif
        bic     r1, r1, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
        mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D line
@@ -218,10 +226,6 @@ v6_dma_inv_range:
        mcrne   p15, 0, r1, c7, c15, 1          @ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_DMA_CACHE_RWFO
-        ldr     r2, [r0]                        @ read for ownership
-        str     r2, [r0]                        @ write for ownership
-#endif
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D line
 #else
@@ -229,6 +233,10 @@ v6_dma_inv_range:
 #endif
        add     r0, r0, #D_CACHE_LINE_SIZE
        cmp     r0, r1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrlo   r2, [r0]                        @ read for ownership
+        strlo   r2, [r0]                        @ write for ownership
+#endif
        blo     1b
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
@@ -263,12 +271,12 @@ v6_dma_clean_range:
 *      - end     - virtual end address of region
 */
 ENTRY(v6_dma_flush_range)
-        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
-1:
 #ifdef CONFIG_DMA_CACHE_RWFO
-        ldr     r2, [r0]                        @ read for ownership
+        ldrb    r2, [r0]                @ read for ownership
-        str     r2, [r0]                        @ write for ownership
+        strb    r2, [r0]                @ write for ownership
 #endif
+        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
+1:
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 #else
@@ -276,6 +284,10 @@ ENTRY(v6_dma_flush_range)
 #endif
        add     r0, r0, #D_CACHE_LINE_SIZE
        cmp     r0, r1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrlob  r2, [r0]                        @ read for ownership
+        strlob  r2, [r0]                        @ write for ownership
+#endif
        blo     1b
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a3ebf7a4f49b..6136e68ce953 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -173,15 +173,22 @@ ENTRY(v7_coherent_user_range)
 UNWIND(.fnstart                )
        dcache_line_size r2, r3
        sub     r3, r2, #1
-        bic     r0, r0, r3
+        bic     r12, r0, r3
 1:
- USER(  mcr     p15, 0, r0, c7, c11, 1  )       @ clean D line to the point of unification
+ USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
+        add     r12, r12, r2
+        cmp     r12, r1
+        blo     1b
        dsb
- USER(  mcr     p15, 0, r0, c7, c5, 1   )       @ invalidate I line
+        icache_line_size r2, r3
-        add     r0, r0, r2
+        sub     r3, r2, #1
+        bic     r12, r0, r3
 2:
-        cmp     r0, r1
+ USER(  mcr     p15, 0, r12, c7, c5, 1  )       @ invalidate I line
-        blo     1b
+        add     r12, r12, r2
+        cmp     r12, r1
+        blo     2b
+3:
        mov     r0, #0
        ALT_SMP(mcr     p15, 0, r0, c7, c1, 6)  @ invalidate BTB Inner Shareable
        ALT_UP(mcr      p15, 0, r0, c7, c5, 6)  @ invalidate BTB
@@ -194,10 +201,10 @@ ENTRY(v7_coherent_user_range)
 * isn't mapped, just try the next page.
 */
 9001:
-        mov     r0, r0, lsr #12
+        mov     r12, r12, lsr #12
-        mov     r0, r0, lsl #12
+        mov     r12, r12, lsl #12
-        add     r0, r0, #4096
+        add     r12, r12, #4096
-        b       2b
+        b       3b
 UNWIND(.fnend          )
 ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index c3154928bccd..5a32020471e3 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -17,14 +17,10 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
 #include <linux/init.h>
+#include <linux/highmem.h>
 #include <asm/system.h>
 #include <asm/cputype.h>
 #include <asm/cacheflush.h>
-#include <asm/kmap_types.h>
-#include <asm/fixmap.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
-#include "mm.h"
 #define CR_L2   (1 << 26)
@@ -71,16 +67,15 @@ static inline void xsc3_l2_inv_all(void)
        dsb();
 }
+static inline void l2_unmap_va(unsigned long va)
+{
 #ifdef CONFIG_HIGHMEM
-#define l2_map_save_flags(x)            raw_local_save_flags(x)
+        if (va != -1)
-#define l2_map_restore_flags(x)         raw_local_irq_restore(x)
+                kunmap_atomic((void *)va);
-#else
-#define l2_map_save_flags(x)            ((x) = 0)
-#define l2_map_restore_flags(x)         ((void)(x))
 #endif
+}
-static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
+static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va)
-                                      unsigned long flags)
 {
 #ifdef CONFIG_HIGHMEM
        unsigned long va = prev_va & PAGE_MASK;
@@ -89,17 +84,10 @@ static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
                /*
                 * Switching to a new page.  Because cache ops are
                 * using virtual addresses only, we must put a mapping
-                 * in place for it.  We also enable interrupts for a
+                 * in place for it.
-                 * short while and disable them again to protect this
-                 * mapping.
                 */
-                unsigned long idx;
+                l2_unmap_va(prev_va);
-                raw_local_irq_restore(flags);
+                va = (unsigned long)kmap_atomic_pfn(pa >> PAGE_SHIFT);
-                idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
-                va = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-                raw_local_irq_restore(flags | PSR_I_BIT);
-                set_pte_ext(TOP_PTE(va), pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL), 0);
-                local_flush_tlb_kernel_page(va);
        }
        return va + (pa_offset >> (32 - PAGE_SHIFT));
 #else
@@ -109,7 +97,7 @@ static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
 static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
 {
-        unsigned long vaddr, flags;
+        unsigned long vaddr;
        if (start == 0 && end == -1ul) {
                xsc3_l2_inv_all();
@@ -117,13 +105,12 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
        }
        vaddr = -1;  /* to force the first mapping */
-        l2_map_save_flags(flags);
        /*
         * Clean and invalidate partial first cache line.
         */
        if (start & (CACHE_LINE_SIZE - 1)) {
-                vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr, flags);
+                vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);
                xsc3_l2_clean_mva(vaddr);
                xsc3_l2_inv_mva(vaddr);
                start = (start | (CACHE_LINE_SIZE - 1)) + 1;
@@ -133,7 +120,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
         * Invalidate all full cache lines between 'start' and 'end'.
         */
        while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_inv_mva(vaddr);
                start += CACHE_LINE_SIZE;
        }
@@ -142,31 +129,30 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
         * Clean and invalidate partial last cache line.
         */
        if (start < end) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_clean_mva(vaddr);
                xsc3_l2_inv_mva(vaddr);
        }
-        l2_map_restore_flags(flags);
+        l2_unmap_va(vaddr);
        dsb();
 }
 static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
 {
-        unsigned long vaddr, flags;
+        unsigned long vaddr;
        vaddr = -1;  /* to force the first mapping */
-        l2_map_save_flags(flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_clean_mva(vaddr);
                start += CACHE_LINE_SIZE;
        }
-        l2_map_restore_flags(flags);
+        l2_unmap_va(vaddr);
        dsb();
 }
@@ -193,7 +179,7 @@ static inline void xsc3_l2_flush_all(void)
 static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
 {
-        unsigned long vaddr, flags;
+        unsigned long vaddr;
        if (start == 0 && end == -1ul) {
                xsc3_l2_flush_all();
@@ -201,17 +187,16 @@ static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
        }
        vaddr = -1;  /* to force the first mapping */
-        l2_map_save_flags(flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_clean_mva(vaddr);
                xsc3_l2_inv_mva(vaddr);
                start += CACHE_LINE_SIZE;
        }
-        l2_map_restore_flags(flags);
+        l2_unmap_va(vaddr);
        dsb();
 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ac6a36142fcd..809f1bf9fa29 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/highmem.h>
 #include <asm/memory.h>
 #include <asm/highmem.h>
@@ -480,10 +481,10 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
                                op(vaddr, len, dir);
                                kunmap_high(page);
                        } else if (cache_is_vipt()) {
-                                pte_t saved_pte;
+                                /* unmapped pages might still be cached */
-                                vaddr = kmap_high_l1_vipt(page, &saved_pte);
+                                vaddr = kmap_atomic(page);
                                op(vaddr + offset, len, dir);
-                                kunmap_high_l1_vipt(page, saved_pte);
+                                kunmap_atomic(vaddr);
                        }
                } else {
                        vaddr = page_address(page) + offset;
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 391ffae75098..c29f2839f1d2 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/pagemap.h>
+#include <linux/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -180,10 +181,10 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
                        kunmap_high(page);
                } else if (cache_is_vipt()) {
-                        pte_t saved_pte;
+                        /* unmapped pages might still be cached */
-                        addr = kmap_high_l1_vipt(page, &saved_pte);
+                        addr = kmap_atomic(page);
                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                        kunmap_high_l1_vipt(page, saved_pte);
+                        kunmap_atomic(addr);
                }
        }
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index c435fd9e1da9..807c0573abbe 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -140,90 +140,3 @@ struct page *kmap_atomic_to_page(const void *ptr)
        pte = TOP_PTE(vaddr);
        return pte_page(*pte);
 }
-#ifdef CONFIG_CPU_CACHE_VIPT
-#include <linux/percpu.h>
-/*
- * The VIVT cache of a highmem page is always flushed before the page
- * is unmapped. Hence unmapped highmem pages need no cache maintenance
- * in that case.
- *
- * However unmapped pages may still be cached with a VIPT cache, and
- * it is not possible to perform cache maintenance on them using physical
- * addresses unfortunately.  So we have no choice but to set up a temporary
- * virtual mapping for that purpose.
- *
- * Yet this VIPT cache maintenance may be triggered from DMA support
- * functions which are possibly called from interrupt context. As we don't
- * want to keep interrupt disabled all the time when such maintenance is
- * taking place, we therefore allow for some reentrancy by preserving and
- * restoring the previous fixmap entry before the interrupted context is
- * resumed.  If the reentrancy depth is 0 then there is no need to restore
- * the previous fixmap, and leaving the current one in place allow it to
- * be reused the next time without a TLB flush (common with DMA).
- */
-static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth);
-void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte)
-{
-        unsigned int idx, cpu;
-        int *depth;
-        unsigned long vaddr, flags;
-        pte_t pte, *ptep;
-        if (!in_interrupt())
-                preempt_disable();
-        cpu = smp_processor_id();
-        depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
-        idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
-        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-        ptep = TOP_PTE(vaddr);
-        pte = mk_pte(page, kmap_prot);
-        raw_local_irq_save(flags);
-        (*depth)++;
-        if (pte_val(*ptep) == pte_val(pte)) {
-                *saved_pte = pte;
-        } else {
-                *saved_pte = *ptep;
-                set_pte_ext(ptep, pte, 0);
-                local_flush_tlb_kernel_page(vaddr);
-        }
-        raw_local_irq_restore(flags);
-        return (void *)vaddr;
-}
-void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte)
-{
-        unsigned int idx, cpu = smp_processor_id();
-        int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
-        unsigned long vaddr, flags;
-        pte_t pte, *ptep;
-        idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
-        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-        ptep = TOP_PTE(vaddr);
-        pte = mk_pte(page, kmap_prot);
-        BUG_ON(pte_val(*ptep) != pte_val(pte));
-        BUG_ON(*depth <= 0);
-        raw_local_irq_save(flags);
-        (*depth)--;
-        if (*depth != 0 && pte_val(pte) != pte_val(saved_pte)) {
-                set_pte_ext(ptep, saved_pte, 0);
-                local_flush_tlb_kernel_page(vaddr);
-        }
-        raw_local_irq_restore(flags);
-        if (!in_interrupt())
-                preempt_enable();
-}
-#endif  /* CONFIG_CPU_CACHE_VIPT */
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63beaf9745..b795afd0a2c6 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -61,17 +61,27 @@
        .endm
 /*
- * cache_line_size - get the cache line size from the CSIDR register
+ * dcache_line_size - get the minimum D-cache line size from the CTR register
- * (available on ARMv7+). It assumes that the CSSR register was configured
+ * on ARMv7.
- * to access the L1 data cache CSIDR.
 */
        .macro  dcache_line_size, reg, tmp
-        mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
+        mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
-        and     \tmp, \tmp, #7                  @ cache line size encoding
+        lsr     \tmp, \tmp, #16
-        mov     \reg, #16                       @ size offset
+        and     \tmp, \tmp, #0xf                @ cache line size encoding
+        mov     \reg, #4                        @ bytes per word
        mov     \reg, \reg, lsl \tmp            @ actual cache line size
        .endm
+/*
+ * icache_line_size - get the minimum I-cache line size from the CTR register
+ * on ARMv7.
+ */
+        .macro  icache_line_size, reg, tmp
+        mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
+        and     \tmp, \tmp, #0xf                @ cache line size encoding
+        mov     \reg, #4                        @ bytes per word
+        mov     \reg, \reg, lsl \tmp            @ actual cache line size
+        .endm
 /*
 * Sanity check the PTE configuration for the code below - which makes
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 155fe43a672b..8722a136f3a5 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/err.h>
 #include <plat/common.h>
 #include <plat/board.h>
@@ -164,7 +165,7 @@ static int __init omap_init_clocksource_32k(void)
                        return -ENODEV;
                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-                if (sync_32k_ick)
+                if (!IS_ERR(sync_32k_ick))
                        clk_enable(sync_32k_ick);
                clocksource_32k.mult = clocksource_hz2mult(32768,
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e2c8eebe6b3a..74dac419d328 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -166,7 +166,7 @@ static void __init omap_detect_sram(void)
                     cpu_is_omap1710())
                        omap_sram_size = 0x4000;        /* 16K */
                else if (cpu_is_omap1611())
-                        omap_sram_size = 0x3e800;       /* 250K */
+                        omap_sram_size = SZ_256K;
                else {
                        printk(KERN_ERR "Could not detect SRAM size\n");
                        omap_sram_size = 0x4000;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5a27b1b538f2..eb105e61c746 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C24XX
        default y
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
-        select S3C_DEVICE_NAND
+        select S3C_DEV_NAND
        select S3C_GPIO_CFG_S3C24XX
        help
          Base platform code for any Samsung S3C24XX device
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 76d0858c3cbb..4a10c0f684b2 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -88,7 +88,7 @@ static struct cpu_table cpu_ids[] __initdata = {
        {
                .idcode         = 0x32440000,
                .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2440_map_io,
                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2440_init,
@@ -97,7 +97,7 @@ static struct cpu_table cpu_ids[] __initdata = {
        {
                .idcode         = 0x32440001,
                .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2440_map_io,
                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2440_init,
@@ -106,7 +106,7 @@ static struct cpu_table cpu_ids[] __initdata = {
        {
                .idcode         = 0x32440aaa,
                .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2442_map_io,
                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2442_init,
@@ -115,7 +115,7 @@ static struct cpu_table cpu_ids[] __initdata = {
        {
                .idcode         = 0x32440aab,
                .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2442_map_io,
                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2442_init,
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 24c6f5a30596..243b6411050d 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -82,8 +82,6 @@ static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
 struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
        .set_config     = s3c_gpio_setcfg_s3c24xx,
        .get_config     = s3c_gpio_getcfg_s3c24xx,
-        .set_pull       = s3c_gpio_setpull_1up,
-        .get_pull       = s3c_gpio_getpull_1up,
 };
 struct s3c_gpio_chip s3c24xx_gpios[] = {
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
index 307248d1ccbb..89e8d0a25f87 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
@@ -21,17 +21,22 @@ extern void s3c244x_init_clocks(int xtal);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
-#define s3c244x_map_io NULL
 #endif
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
+extern void s3c2440_map_io(void);
 #else
 #define s3c2440_init NULL
+#define s3c2440_map_io NULL
 #endif
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
+extern void s3c2442_map_io(void);
 #else
 #define s3c2442_init NULL
+#define s3c2442_map_io NULL
 #endif
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index b732b773b9af..0aa32f242ee4 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -280,18 +280,17 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
 }
 #endif
-#ifdef CONFIG_S3C_GPIO_PULL_UP
+#if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN)
-int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip,
-                         unsigned int off, s3c_gpio_pull_t pull)
+                         unsigned int off, s3c_gpio_pull_t pull,
+                         s3c_gpio_pull_t updown)
 {
        void __iomem *reg = chip->base + 0x08;
        u32 pup = __raw_readl(reg);
-        pup = __raw_readl(reg);
+        if (pull == updown)
-        if (pup == S3C_GPIO_PULL_UP)
                pup &= ~(1 << off);
-        else if (pup == S3C_GPIO_PULL_NONE)
+        else if (pull == S3C_GPIO_PULL_NONE)
                pup |= (1 << off);
        else
                return -EINVAL;
@@ -300,17 +299,45 @@ int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
        return 0;
 }
-s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip,
-                                     unsigned int off)
+                                     unsigned int off, s3c_gpio_pull_t updown)
 {
        void __iomem *reg = chip->base + 0x08;
        u32 pup = __raw_readl(reg);
        pup &= (1 << off);
-        return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
+        return pup ? S3C_GPIO_PULL_NONE : updown;
+}
+#endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */
+#ifdef CONFIG_S3C_GPIO_PULL_UP
+s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
+}
+int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull)
+{
+        return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
 }
 #endif /* CONFIG_S3C_GPIO_PULL_UP */
+#ifdef CONFIG_S3C_GPIO_PULL_DOWN
+s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
+}
+int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull)
+{
+        return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
+}
+#endif /* CONFIG_S3C_GPIO_PULL_DOWN */
 #ifdef CONFIG_S5P_GPIO_DRVSTR
 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
 {
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 8fd65d8b5863..0d2c5703f1ee 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -210,6 +210,17 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
                                            unsigned int off);
 /**
+ * s3c_gpio_getpull_1down() - Get configuration for choice of down or none
+ * @chip: The gpio chip that the GPIO pin belongs to
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-down resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_1down.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
+                                            unsigned int off);
+/**
 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
 * @chip: The gpio chip that is being configured.
 * @off: The offset for the GPIO being configured.
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 5cf88e8427b1..aaa571d17924 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,5 +1,4 @@
 obj-y   := clock.o
-obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
 obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
 obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
 ifeq ($(CONFIG_LEDS_CLASS),y)
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 55590a4d87c9..2fea897ebeb1 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Thu Sep 9 22:43:01 2010
+# Last update: Sun Dec 12 23:24:27 2010
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2321,7 +2321,7 @@ mx31txtr		MACH_MX31TXTR		MX31TXTR		2332
 u380                    MACH_U380               U380                    2333
 oamp3_hualu             MACH_HUALU_BOARD        HUALU_BOARD             2334
 npcmx50                 MACH_NPCMX50            NPCMX50                 2335
-mx51_lange51            MACH_MX51_LANGE51       MX51_LANGE51            2336
+mx51_efikamx            MACH_MX51_EFIKAMX       MX51_EFIKAMX            2336
 mx51_lange52            MACH_MX51_LANGE52       MX51_LANGE52            2337
 riom                    MACH_RIOM               RIOM                    2338
 comcas                  MACH_COMCAS             COMCAS                  2339
@@ -2355,7 +2355,7 @@ at91sam9263cs		MACH_AT91SAM9263CS	AT91SAM9263CS		2366
 csb732                  MACH_CSB732             CSB732                  2367
 u8500                   MACH_U8500              U8500                   2368
 huqiu                   MACH_HUQIU              HUQIU                   2369
-mx51_kunlun             MACH_MX51_KUNLUN        MX51_KUNLUN             2370
+mx51_efikasb            MACH_MX51_EFIKASB       MX51_EFIKASB            2370
 pmt1g                   MACH_PMT1G              PMT1G                   2371
 htcelf                  MACH_HTCELF             HTCELF                  2372
 armadillo420            MACH_ARMADILLO420       ARMADILLO420            2373
@@ -2971,7 +2971,7 @@ premierwave_en		MACH_PREMIERWAVE_EN	PREMIERWAVE_EN		2985
 wasabi                  MACH_WASABI             WASABI                  2986
 vivow                   MACH_VIVOW              VIVOW                   2987
 mx50_rdp                MACH_MX50_RDP           MX50_RDP                2988
-universal               MACH_UNIVERSAL          UNIVERSAL               2989
+universal_c210          MACH_UNIVERSAL_C210     UNIVERSAL_C210          2989
 real6410                MACH_REAL6410           REAL6410                2990
 spx_sakura              MACH_SPX_SAKURA         SPX_SAKURA              2991
 ij3k_2440               MACH_IJ3K_2440          IJ3K_2440               2992
@@ -3044,3 +3044,178 @@ harvest_desoto		MACH_HARVEST_DESOTO	HARVEST_DESOTO		3059
 msm8x60_qrdc            MACH_MSM8X60_QRDC       MSM8X60_QRDC            3060
 spear900                MACH_SPEAR900           SPEAR900                3061
 pcontrol_g20            MACH_PCONTROL_G20       PCONTROL_G20            3062
+rdstor                  MACH_RDSTOR             RDSTOR                  3063
+usdloader               MACH_USDLOADER          USDLOADER               3064
+tsoploader              MACH_TSOPLOADER         TSOPLOADER              3065
+kronos                  MACH_KRONOS             KRONOS                  3066
+ffcore                  MACH_FFCORE             FFCORE                  3067
+mone                    MACH_MONE               MONE                    3068
+unit2s                  MACH_UNIT2S             UNIT2S                  3069
+acer_a5                 MACH_ACER_A5            ACER_A5                 3070
+etherpro_isp            MACH_ETHERPRO_ISP       ETHERPRO_ISP            3071
+stretchs7000            MACH_STRETCHS7000       STRETCHS7000            3072
+p87_smartsim            MACH_P87_SMARTSIM       P87_SMARTSIM            3073
+tulip                   MACH_TULIP              TULIP                   3074
+sunflower               MACH_SUNFLOWER          SUNFLOWER               3075
+rib                     MACH_RIB                RIB                     3076
+clod                    MACH_CLOD               CLOD                    3077
+rump                    MACH_RUMP               RUMP                    3078
+tenderloin              MACH_TENDERLOIN         TENDERLOIN              3079
+shortloin               MACH_SHORTLOIN          SHORTLOIN               3080
+crespo                  MACH_CRESPO             CRESPO                  3081
+antares                 MACH_ANTARES            ANTARES                 3082
+wb40n                   MACH_WB40N              WB40N                   3083
+herring                 MACH_HERRING            HERRING                 3084
+naxy400                 MACH_NAXY400            NAXY400                 3085
+naxy1200                MACH_NAXY1200           NAXY1200                3086
+vpr200                  MACH_VPR200             VPR200                  3087
+bug20                   MACH_BUG20              BUG20                   3088
+goflexnet               MACH_GOFLEXNET          GOFLEXNET               3089
+torbreck                MACH_TORBRECK           TORBRECK                3090
+saarb_mg1               MACH_SAARB_MG1          SAARB_MG1               3091
+callisto                MACH_CALLISTO           CALLISTO                3092
+multhsu                 MACH_MULTHSU            MULTHSU                 3093
+saluda                  MACH_SALUDA             SALUDA                  3094
+pemp_omap3_apollo       MACH_PEMP_OMAP3_APOLLO  PEMP_OMAP3_APOLLO       3095
+vc0718                  MACH_VC0718             VC0718                  3096
+mvblx                   MACH_MVBLX              MVBLX                   3097
+inhand_apeiron          MACH_INHAND_APEIRON     INHAND_APEIRON          3098
+inhand_fury             MACH_INHAND_FURY        INHAND_FURY             3099
+inhand_siren            MACH_INHAND_SIREN       INHAND_SIREN            3100
+hdnvp                   MACH_HDNVP              HDNVP                   3101
+softwinner              MACH_SOFTWINNER         SOFTWINNER              3102
+prima2_evb              MACH_PRIMA2_EVB         PRIMA2_EVB              3103
+nas6210                 MACH_NAS6210            NAS6210                 3104
+unisdev                 MACH_UNISDEV            UNISDEV                 3105
+sbca11                  MACH_SBCA11             SBCA11                  3106
+saga                    MACH_SAGA               SAGA                    3107
+ns_k330                 MACH_NS_K330            NS_K330                 3108
+tanna                   MACH_TANNA              TANNA                   3109
+imate8502               MACH_IMATE8502          IMATE8502               3110
+aspen                   MACH_ASPEN              ASPEN                   3111
+daintree_cwac           MACH_DAINTREE_CWAC      DAINTREE_CWAC           3112
+zmx25                   MACH_ZMX25              ZMX25                   3113
+maple1                  MACH_MAPLE1             MAPLE1                  3114
+qsd8x72_surf            MACH_QSD8X72_SURF       QSD8X72_SURF            3115
+qsd8x72_ffa             MACH_QSD8X72_FFA        QSD8X72_FFA             3116
+abilene                 MACH_ABILENE            ABILENE                 3117
+eigen_ttr               MACH_EIGEN_TTR          EIGEN_TTR               3118
+iomega_ix2_200          MACH_IOMEGA_IX2_200     IOMEGA_IX2_200          3119
+coretec_vcx7400         MACH_CORETEC_VCX7400    CORETEC_VCX7400         3120
+santiago                MACH_SANTIAGO           SANTIAGO                3121
+mx257sol                MACH_MX257SOL           MX257SOL                3122
+strasbourg              MACH_STRASBOURG         STRASBOURG              3123
+msm8x60_fluid           MACH_MSM8X60_FLUID      MSM8X60_FLUID           3124
+smartqv5                MACH_SMARTQV5           SMARTQV5                3125
+smartqv3                MACH_SMARTQV3           SMARTQV3                3126
+smartqv7                MACH_SMARTQV7           SMARTQV7                3127
+paz00                   MACH_PAZ00              PAZ00                   3128
+acmenetusfoxg20         MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
+htcwillow               MACH_HTCWILLOW          HTCWILLOW               3130
+fwbd_0404               MACH_FWBD_0404          FWBD_0404               3131
+hdgu                    MACH_HDGU               HDGU                    3132
+pyramid                 MACH_PYRAMID            PYRAMID                 3133
+epiphan                 MACH_EPIPHAN            EPIPHAN                 3134
+omap_bender             MACH_OMAP_BENDER        OMAP_BENDER             3135
+gurnard                 MACH_GURNARD            GURNARD                 3136
+gtl_it5100              MACH_GTL_IT5100         GTL_IT5100              3137
+bcm2708                 MACH_BCM2708            BCM2708                 3138
+mx51_ggc                MACH_MX51_GGC           MX51_GGC                3139
+sharespace              MACH_SHARESPACE         SHARESPACE              3140
+haba_knx_explorer       MACH_HABA_KNX_EXPLORER  HABA_KNX_EXPLORER       3141
+simtec_kirkmod          MACH_SIMTEC_KIRKMOD     SIMTEC_KIRKMOD          3142
+crux                    MACH_CRUX               CRUX                    3143
+mx51_bravo              MACH_MX51_BRAVO         MX51_BRAVO              3144
+charon                  MACH_CHARON             CHARON                  3145
+picocom3                MACH_PICOCOM3           PICOCOM3                3146
+picocom4                MACH_PICOCOM4           PICOCOM4                3147
+serrano                 MACH_SERRANO            SERRANO                 3148
+doubleshot              MACH_DOUBLESHOT         DOUBLESHOT              3149
+evsy                    MACH_EVSY               EVSY                    3150
+huashan                 MACH_HUASHAN            HUASHAN                 3151
+lausanne                MACH_LAUSANNE           LAUSANNE                3152
+emerald                 MACH_EMERALD            EMERALD                 3153
+tqma35                  MACH_TQMA35             TQMA35                  3154
+marvel                  MACH_MARVEL             MARVEL                  3155
+manuae                  MACH_MANUAE             MANUAE                  3156
+chacha                  MACH_CHACHA             CHACHA                  3157
+lemon                   MACH_LEMON              LEMON                   3158
+csc                     MACH_CSC                CSC                     3159
+gira_knxip_router       MACH_GIRA_KNXIP_ROUTER  GIRA_KNXIP_ROUTER       3160
+t20                     MACH_T20                T20                     3161
+hdmini                  MACH_HDMINI             HDMINI                  3162
+sciphone_g2             MACH_SCIPHONE_G2        SCIPHONE_G2             3163
+express                 MACH_EXPRESS            EXPRESS                 3164
+express_kt              MACH_EXPRESS_KT         EXPRESS_KT              3165
+maximasp                MACH_MAXIMASP           MAXIMASP                3166
+nitrogen_imx51          MACH_NITROGEN_IMX51     NITROGEN_IMX51          3167
+nitrogen_imx53          MACH_NITROGEN_IMX53     NITROGEN_IMX53          3168
+sunfire                 MACH_SUNFIRE            SUNFIRE                 3169
+arowana                 MACH_AROWANA            AROWANA                 3170
+tegra_daytona           MACH_TEGRA_DAYTONA      TEGRA_DAYTONA           3171
+tegra_swordfish         MACH_TEGRA_SWORDFISH    TEGRA_SWORDFISH         3172
+edison                  MACH_EDISON             EDISON                  3173
+svp8500v1               MACH_SVP8500V1          SVP8500V1               3174
+svp8500v2               MACH_SVP8500V2          SVP8500V2               3175
+svp5500                 MACH_SVP5500            SVP5500                 3176
+b5500                   MACH_B5500              B5500                   3177
+s5500                   MACH_S5500              S5500                   3178
+icon                    MACH_ICON               ICON                    3179
+elephant                MACH_ELEPHANT           ELEPHANT                3180
+msm8x60_fusion          MACH_MSM8X60_FUSION     MSM8X60_FUSION          3181
+shooter                 MACH_SHOOTER            SHOOTER                 3182
+spade_lte               MACH_SPADE_LTE          SPADE_LTE               3183
+philhwani               MACH_PHILHWANI          PHILHWANI               3184
+gsncomm                 MACH_GSNCOMM            GSNCOMM                 3185
+strasbourg_a2           MACH_STRASBOURG_A2      STRASBOURG_A2           3186
+mmm                     MACH_MMM                MMM                     3187
+davinci_dm365_bv        MACH_DAVINCI_DM365_BV   DAVINCI_DM365_BV        3188
+ag5evm                  MACH_AG5EVM             AG5EVM                  3189
+sc575plc                MACH_SC575PLC           SC575PLC                3190
+sc575hmi                MACH_SC575IPC           SC575IPC                3191
+omap3_tdm3730           MACH_OMAP3_TDM3730      OMAP3_TDM3730           3192
+g7                      MACH_G7                 G7                      3193
+top9000_eval            MACH_TOP9000_EVAL       TOP9000_EVAL            3194
+top9000_su              MACH_TOP9000_SU         TOP9000_SU              3195
+utm300                  MACH_UTM300             UTM300                  3196
+tsunagi                 MACH_TSUNAGI            TSUNAGI                 3197
+ts75xx                  MACH_TS75XX             TS75XX                  3198
+msm8x60_fusn_ffa        MACH_MSM8X60_FUSN_FFA   MSM8X60_FUSN_FFA        3199
+ts47xx                  MACH_TS47XX             TS47XX                  3200
+da850_k5                MACH_DA850_K5           DA850_K5                3201
+ax502                   MACH_AX502              AX502                   3202
+igep0032                MACH_IGEP0032           IGEP0032                3203
+antero                  MACH_ANTERO             ANTERO                  3204
+synergy                 MACH_SYNERGY            SYNERGY                 3205
+ics_if_voip             MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
+wlf_cragg_6410          MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207
+punica                  MACH_PUNICA             PUNICA                  3208
+sbc_nt250               MACH_SBC_NT250          SBC_NT250               3209
+mx27_wmultra            MACH_MX27_WMULTRA       MX27_WMULTRA            3210
+mackerel                MACH_MACKEREL           MACKEREL                3211
+fa9x27                  MACH_FA9X27             FA9X27                  3213
+ns2816tb                MACH_NS2816TB           NS2816TB                3214
+ns2816_ntpad            MACH_NS2816_NTPAD       NS2816_NTPAD            3215
+ns2816_ntnb             MACH_NS2816_NTNB        NS2816_NTNB             3216
+kaen                    MACH_KAEN               KAEN                    3217
+nv1000                  MACH_NV1000             NV1000                  3218
+nuc950ts                MACH_NUC950TS           NUC950TS                3219
+nokia_rm680             MACH_NOKIA_RM680        NOKIA_RM680             3220
+ast2200                 MACH_AST2200            AST2200                 3221
+lead                    MACH_LEAD               LEAD                    3222
+unino1                  MACH_UNINO1             UNINO1                  3223
+greeco                  MACH_GREECO             GREECO                  3224
+verdi                   MACH_VERDI              VERDI                   3225
+dm6446_adbox            MACH_DM6446_ADBOX       DM6446_ADBOX            3226
+quad_salsa              MACH_QUAD_SALSA         QUAD_SALSA              3227
+abb_gma_1_1             MACH_ABB_GMA_1_1        ABB_GMA_1_1             3228
+svcid                   MACH_SVCID              SVCID                   3229
+msm8960_sim             MACH_MSM8960_SIM        MSM8960_SIM             3230
+msm8960_rumi3           MACH_MSM8960_RUMI3      MSM8960_RUMI3           3231
+icon_g                  MACH_ICON_G             ICON_G                  3232
+mb3                     MACH_MB3                MB3                     3233
+gsia18s                 MACH_GSIA18S            GSIA18S                 3234
+pivicc                  MACH_PIVICC             PIVICC                  3235
+pcm048                  MACH_PCM048             PCM048                  3236
+dds                     MACH_DDS                DDS                     3237
+chalten_xa1             MACH_CHALTEN_XA1        CHALTEN_XA1             3238