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-rw-r--r--arch/arm/plat-omap/Kconfig4
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/common.c42
-rw-r--r--arch/arm/plat-omap/counter_32k.c3
-rw-r--r--arch/arm/plat-omap/debug-devices.c3
-rw-r--r--arch/arm/plat-omap/debug-leds.c294
-rw-r--r--arch/arm/plat-omap/devices.c92
-rw-r--r--arch/arm/plat-omap/dma.c54
-rw-r--r--arch/arm/plat-omap/dmtimer.c6
-rw-r--r--arch/arm/plat-omap/fb.c2
-rw-r--r--arch/arm/plat-omap/i2c.c4
-rw-r--r--arch/arm/plat-omap/include/plat/am33xx.h25
-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h71
-rw-r--r--arch/arm/plat-omap/include/plat/board-sx1.h52
-rw-r--r--arch/arm/plat-omap/include/plat/board-voiceblue.h19
-rw-r--r--arch/arm/plat-omap/include/plat/board.h138
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h6
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h2
-rw-r--r--arch/arm/plat-omap/include/plat/dsp.h34
-rw-r--r--arch/arm/plat-omap/include/plat/flash.h17
-rw-r--r--arch/arm/plat-omap/include/plat/gpio-switch.h54
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h228
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smc91x.h42
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smsc911x.h35
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h19
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h293
-rw-r--r--arch/arm/plat-omap/include/plat/hdq1w.h36
-rw-r--r--arch/arm/plat-omap/include/plat/irda.h33
-rw-r--r--arch/arm/plat-omap/include/plat/irqs-44xx.h144
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h453
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h52
-rw-r--r--arch/arm/plat-omap/include/plat/l3_2xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l3_3xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l4_2xxx.h24
-rw-r--r--arch/arm/plat-omap/include/plat/l4_3xxx.h34
-rw-r--r--arch/arm/plat-omap/include/plat/lcd_mipid.h29
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h62
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h23
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h1
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h9
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h454
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h44
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h54
-rw-r--r--arch/arm/plat-omap/include/plat/omap1510.h50
-rw-r--r--arch/arm/plat-omap/include/plat/omap16xx.h202
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h89
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h101
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h6
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h62
-rw-r--r--arch/arm/plat-omap/include/plat/omap54xx.h32
-rw-r--r--arch/arm/plat-omap/include/plat/omap7xx.h107
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h2
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h53
-rw-r--r--arch/arm/plat-omap/include/plat/param.h8
-rw-r--r--arch/arm/plat-omap/include/plat/remoteproc.h57
-rw-r--r--arch/arm/plat-omap/include/plat/ti81xx.h27
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h4
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h1
-rw-r--r--arch/arm/plat-omap/include/plat/voltage.h39
-rw-r--r--arch/arm/plat-omap/mailbox.c2
-rw-r--r--arch/arm/plat-omap/mux.c90
-rw-r--r--arch/arm/plat-omap/omap-pm-noop.c39
-rw-r--r--arch/arm/plat-omap/omap_device.c160
-rw-r--r--arch/arm/plat-omap/sram.c12
65 files changed, 306 insertions, 3873 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba9506c..ca83a7659aef 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
25 bool "TI OMAP2/3/4" 25 bool "TI OMAP2/3/4"
26 select CLKDEV_LOOKUP 26 select CLKDEV_LOOKUP
27 select GENERIC_IRQ_CHIP 27 select GENERIC_IRQ_CHIP
28 select SPARSE_IRQ
28 select OMAP_DM_TIMER 29 select OMAP_DM_TIMER
29 select USE_OF 30 select USE_OF
30 select PROC_DEVICETREE if PROC_FS 31 select PROC_DEVICETREE if PROC_FS
@@ -41,9 +42,8 @@ config OMAP_DEBUG_DEVICES
41 For debug cards on TI reference boards. 42 For debug cards on TI reference boards.
42 43
43config OMAP_DEBUG_LEDS 44config OMAP_DEBUG_LEDS
44 bool 45 def_bool y if NEW_LEDS
45 depends on OMAP_DEBUG_DEVICES 46 depends on OMAP_DEBUG_DEVICES
46 default y if LEDS_CLASS
47 47
48config POWER_AVS_OMAP 48config POWER_AVS_OMAP
49 bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2" 49 bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 961bf859bc0c..dacaee009a4e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ 6obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
7 fb.o counter_32k.o
8obj-m := 7obj-m :=
9obj-n := 8obj-n :=
10obj- := 9obj- :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 89a3723b3538..111315a69354 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -17,52 +17,12 @@
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18 18
19#include <plat/common.h> 19#include <plat/common.h>
20#include <plat/board.h>
21#include <plat/vram.h> 20#include <plat/vram.h>
22#include <plat/dsp.h> 21#include <linux/platform_data/dsp-omap.h>
23#include <plat/dma.h> 22#include <plat/dma.h>
24 23
25#include <plat/omap-secure.h> 24#include <plat/omap-secure.h>
26 25
27
28#define NO_LENGTH_CHECK 0xffffffff
29
30struct omap_board_config_kernel *omap_board_config __initdata;
31int omap_board_config_size;
32
33static const void *__init get_config(u16 tag, size_t len,
34 int skip, size_t *len_out)
35{
36 struct omap_board_config_kernel *kinfo = NULL;
37 int i;
38
39 /* Try to find the config from the board-specific structures
40 * in the kernel. */
41 for (i = 0; i < omap_board_config_size; i++) {
42 if (omap_board_config[i].tag == tag) {
43 if (skip == 0) {
44 kinfo = &omap_board_config[i];
45 break;
46 } else {
47 skip--;
48 }
49 }
50 }
51 if (kinfo == NULL)
52 return NULL;
53 return kinfo->data;
54}
55
56const void *__init __omap_get_config(u16 tag, size_t len, int nr)
57{
58 return get_config(tag, len, nr, NULL);
59}
60
61const void *__init omap_get_var_config(u16 tag, size_t *len)
62{
63 return get_config(tag, NO_LENGTH_CHECK, 0, len);
64}
65
66void __init omap_reserve(void) 26void __init omap_reserve(void)
67{ 27{
68 omap_vram_reserve_sdram_memblock(); 28 omap_vram_reserve_sdram_memblock();
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index dbf1e03029a5..2e826f1faf7b 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,10 +22,7 @@
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23#include <asm/sched_clock.h> 23#include <asm/sched_clock.h>
24 24
25#include <plat/hardware.h>
26#include <plat/common.h> 25#include <plat/common.h>
27#include <plat/board.h>
28
29#include <plat/clock.h> 26#include <plat/clock.h>
30 27
31/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ 28/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index caa1f7b6cc21..c7a4c0902b38 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -17,9 +17,6 @@
17 17
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19 19
20#include <plat/board.h>
21
22
23/* Many OMAP development platforms reuse the same "debug board"; these 20/* Many OMAP development platforms reuse the same "debug board"; these
24 * platforms include H2, H3, H4, and Perseus2. 21 * platforms include H2, H3, H4, and Perseus2.
25 */ 22 */
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cbe34c6..ea29bbe8e5cf 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -1,279 +1,119 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/debug-leds.c 2 * linux/arch/arm/plat-omap/debug-leds.c
3 * 3 *
4 * Copyright 2011 by Bryan Wu <bryan.wu@canonical.com>
4 * Copyright 2003 by Texas Instruments Incorporated 5 * Copyright 2003 by Texas Instruments Incorporated
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
9 */ 10 */
10#include <linux/gpio.h> 11
12#include <linux/kernel.h>
11#include <linux/init.h> 13#include <linux/init.h>
12#include <linux/platform_device.h> 14#include <linux/platform_device.h>
13#include <linux/leds.h> 15#include <linux/leds.h>
14#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/slab.h>
15 19
16#include <mach/hardware.h> 20#include <mach/hardware.h>
17#include <asm/leds.h>
18#include <asm/mach-types.h> 21#include <asm/mach-types.h>
19 22
20#include <plat/fpga.h> 23#include <plat/fpga.h>
21 24
22
23/* Many OMAP development platforms reuse the same "debug board"; these 25/* Many OMAP development platforms reuse the same "debug board"; these
24 * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the 26 * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the
25 * debug board (all green), accessed through FPGA registers. 27 * debug board (all green), accessed through FPGA registers.
26 *
27 * The "surfer" expansion board and H2 sample board also have two-color
28 * green+red LEDs (in parallel), used here for timer and idle indicators
29 * in preference to the ones on the debug board, for a "Disco LED" effect.
30 *
31 * This driver exports either the original ARM LED API, the new generic
32 * one, or both.
33 */
34
35static spinlock_t lock;
36static struct h2p2_dbg_fpga __iomem *fpga;
37static u16 led_state, hw_led_state;
38
39
40#ifdef CONFIG_OMAP_DEBUG_LEDS
41#define new_led_api() 1
42#else
43#define new_led_api() 0
44#endif
45
46
47/*-------------------------------------------------------------------------*/
48
49/* original ARM debug LED API:
50 * - timer and idle leds (some boards use non-FPGA leds here);
51 * - up to 4 generic leds, easily accessed in-kernel (any context)
52 */ 28 */
53 29
54#define GPIO_LED_RED 3 30static struct h2p2_dbg_fpga __iomem *fpga;
55#define GPIO_LED_GREEN OMAP_MPUIO(4)
56
57#define LED_STATE_ENABLED 0x01
58#define LED_STATE_CLAIMED 0x02
59#define LED_TIMER_ON 0x04
60
61#define GPIO_IDLE GPIO_LED_GREEN
62#define GPIO_TIMER GPIO_LED_RED
63
64static void h2p2_dbg_leds_event(led_event_t evt)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&lock, flags);
69
70 if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
71 goto done;
72
73 switch (evt) {
74 case led_start:
75 if (fpga)
76 led_state |= LED_STATE_ENABLED;
77 break;
78
79 case led_stop:
80 case led_halted:
81 /* all leds off during suspend or shutdown */
82
83 if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
84 gpio_set_value(GPIO_TIMER, 0);
85 gpio_set_value(GPIO_IDLE, 0);
86 }
87
88 __raw_writew(~0, &fpga->leds);
89 led_state &= ~LED_STATE_ENABLED;
90 goto done;
91
92 case led_claim:
93 led_state |= LED_STATE_CLAIMED;
94 hw_led_state = 0;
95 break;
96
97 case led_release:
98 led_state &= ~LED_STATE_CLAIMED;
99 break;
100
101#ifdef CONFIG_LEDS_TIMER
102 case led_timer:
103 led_state ^= LED_TIMER_ON;
104
105 if (machine_is_omap_perseus2() || machine_is_omap_h4())
106 hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
107 else {
108 gpio_set_value(GPIO_TIMER,
109 led_state & LED_TIMER_ON);
110 goto done;
111 }
112
113 break;
114#endif
115
116#ifdef CONFIG_LEDS_CPU
117 /* LED lit iff busy */
118 case led_idle_start:
119 if (machine_is_omap_perseus2() || machine_is_omap_h4())
120 hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
121 else {
122 gpio_set_value(GPIO_IDLE, 1);
123 goto done;
124 }
125
126 break;
127 31
128 case led_idle_end: 32static u16 fpga_led_state;
129 if (machine_is_omap_perseus2() || machine_is_omap_h4())
130 hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
131 else {
132 gpio_set_value(GPIO_IDLE, 0);
133 goto done;
134 }
135
136 break;
137#endif
138
139 case led_green_on:
140 hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
141 break;
142 case led_green_off:
143 hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
144 break;
145
146 case led_amber_on:
147 hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
148 break;
149 case led_amber_off:
150 hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
151 break;
152
153 case led_red_on:
154 hw_led_state |= H2P2_DBG_FPGA_LED_RED;
155 break;
156 case led_red_off:
157 hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
158 break;
159
160 case led_blue_on:
161 hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
162 break;
163 case led_blue_off:
164 hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
165 break;
166
167 default:
168 break;
169 }
170
171
172 /*
173 * Actually burn the LEDs
174 */
175 if (led_state & LED_STATE_ENABLED)
176 __raw_writew(~hw_led_state, &fpga->leds);
177
178done:
179 spin_unlock_irqrestore(&lock, flags);
180}
181
182/*-------------------------------------------------------------------------*/
183
184/* "new" LED API
185 * - with syfs access and generic triggering
186 * - not readily accessible to in-kernel drivers
187 */
188 33
189struct dbg_led { 34struct dbg_led {
190 struct led_classdev cdev; 35 struct led_classdev cdev;
191 u16 mask; 36 u16 mask;
192}; 37};
193 38
194static struct dbg_led dbg_leds[] = { 39static const struct {
195 /* REVISIT at least H2 uses different timer & cpu leds... */ 40 const char *name;
196#ifndef CONFIG_LEDS_TIMER 41 const char *trigger;
197 { .mask = 1 << 0, .cdev.name = "d4:green", 42} dbg_leds[] = {
198 .cdev.default_trigger = "heartbeat", }, 43 { "dbg:d4", "heartbeat", },
199#endif 44 { "dbg:d5", "cpu0", },
200#ifndef CONFIG_LEDS_CPU 45 { "dbg:d6", "default-on", },
201 { .mask = 1 << 1, .cdev.name = "d5:green", }, /* !idle */ 46 { "dbg:d7", },
202#endif 47 { "dbg:d8", },
203 { .mask = 1 << 2, .cdev.name = "d6:green", }, 48 { "dbg:d9", },
204 { .mask = 1 << 3, .cdev.name = "d7:green", }, 49 { "dbg:d10", },
205 50 { "dbg:d11", },
206 { .mask = 1 << 4, .cdev.name = "d8:green", }, 51 { "dbg:d12", },
207 { .mask = 1 << 5, .cdev.name = "d9:green", }, 52 { "dbg:d13", },
208 { .mask = 1 << 6, .cdev.name = "d10:green", }, 53 { "dbg:d14", },
209 { .mask = 1 << 7, .cdev.name = "d11:green", }, 54 { "dbg:d15", },
210 55 { "dbg:d16", },
211 { .mask = 1 << 8, .cdev.name = "d12:green", }, 56 { "dbg:d17", },
212 { .mask = 1 << 9, .cdev.name = "d13:green", }, 57 { "dbg:d18", },
213 { .mask = 1 << 10, .cdev.name = "d14:green", }, 58 { "dbg:d19", },
214 { .mask = 1 << 11, .cdev.name = "d15:green", },
215
216#ifndef CONFIG_LEDS
217 { .mask = 1 << 12, .cdev.name = "d16:green", },
218 { .mask = 1 << 13, .cdev.name = "d17:green", },
219 { .mask = 1 << 14, .cdev.name = "d18:green", },
220 { .mask = 1 << 15, .cdev.name = "d19:green", },
221#endif
222}; 59};
223 60
224static void 61/*
225fpga_led_set(struct led_classdev *cdev, enum led_brightness value) 62 * The triggers lines up below will only be used if the
63 * LED triggers are compiled in.
64 */
65static void dbg_led_set(struct led_classdev *cdev,
66 enum led_brightness b)
226{ 67{
227 struct dbg_led *led = container_of(cdev, struct dbg_led, cdev); 68 struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
228 unsigned long flags; 69 u16 reg;
229 70
230 spin_lock_irqsave(&lock, flags); 71 reg = __raw_readw(&fpga->leds);
231 if (value == LED_OFF) 72 if (b != LED_OFF)
232 hw_led_state &= ~led->mask; 73 reg |= led->mask;
233 else 74 else
234 hw_led_state |= led->mask; 75 reg &= ~led->mask;
235 __raw_writew(~hw_led_state, &fpga->leds); 76 __raw_writew(reg, &fpga->leds);
236 spin_unlock_irqrestore(&lock, flags);
237} 77}
238 78
239static void __init newled_init(struct device *dev) 79static enum led_brightness dbg_led_get(struct led_classdev *cdev)
240{ 80{
241 unsigned i; 81 struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
242 struct dbg_led *led; 82 u16 reg;
243 int status;
244 83
245 for (i = 0, led = dbg_leds; i < ARRAY_SIZE(dbg_leds); i++, led++) { 84 reg = __raw_readw(&fpga->leds);
246 led->cdev.brightness_set = fpga_led_set; 85 return (reg & led->mask) ? LED_FULL : LED_OFF;
247 status = led_classdev_register(dev, &led->cdev);
248 if (status < 0)
249 break;
250 }
251 return;
252} 86}
253 87
254 88static int fpga_probe(struct platform_device *pdev)
255/*-------------------------------------------------------------------------*/
256
257static int /* __init */ fpga_probe(struct platform_device *pdev)
258{ 89{
259 struct resource *iomem; 90 struct resource *iomem;
260 91 int i;
261 spin_lock_init(&lock);
262 92
263 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 93 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
264 if (!iomem) 94 if (!iomem)
265 return -ENODEV; 95 return -ENODEV;
266 96
267 fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE); 97 fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
268 __raw_writew(~0, &fpga->leds); 98 __raw_writew(0xff, &fpga->leds);
99
100 for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
101 struct dbg_led *led;
102
103 led = kzalloc(sizeof(*led), GFP_KERNEL);
104 if (!led)
105 break;
269 106
270#ifdef CONFIG_LEDS 107 led->cdev.name = dbg_leds[i].name;
271 leds_event = h2p2_dbg_leds_event; 108 led->cdev.brightness_set = dbg_led_set;
272 leds_event(led_start); 109 led->cdev.brightness_get = dbg_led_get;
273#endif 110 led->cdev.default_trigger = dbg_leds[i].trigger;
111 led->mask = BIT(i);
274 112
275 if (new_led_api()) { 113 if (led_classdev_register(NULL, &led->cdev) < 0) {
276 newled_init(&pdev->dev); 114 kfree(led);
115 break;
116 }
277 } 117 }
278 118
279 return 0; 119 return 0;
@@ -281,13 +121,15 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
281 121
282static int fpga_suspend_noirq(struct device *dev) 122static int fpga_suspend_noirq(struct device *dev)
283{ 123{
284 __raw_writew(~0, &fpga->leds); 124 fpga_led_state = __raw_readw(&fpga->leds);
125 __raw_writew(0xff, &fpga->leds);
126
285 return 0; 127 return 0;
286} 128}
287 129
288static int fpga_resume_noirq(struct device *dev) 130static int fpga_resume_noirq(struct device *dev)
289{ 131{
290 __raw_writew(~hw_led_state, &fpga->leds); 132 __raw_writew(~fpga_led_state, &fpga->leds);
291 return 0; 133 return 0;
292} 134}
293 135
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644
index 1cba9273d2cb..000000000000
--- a/arch/arm/plat-omap/devices.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/devices.c
3 *
4 * Common platform device setup/initialization for OMAP1 and OMAP2
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/gpio.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/memblock.h>
19
20#include <mach/hardware.h>
21#include <asm/mach-types.h>
22#include <asm/mach/map.h>
23#include <asm/memblock.h>
24
25#include <plat/tc.h>
26#include <plat/board.h>
27#include <plat/mmc.h>
28#include <plat/menelaus.h>
29#include <plat/omap44xx.h>
30
31/*-------------------------------------------------------------------------*/
32
33#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
34
35#ifdef CONFIG_ARCH_OMAP2
36#define OMAP_RNG_BASE 0x480A0000
37#else
38#define OMAP_RNG_BASE 0xfffe5000
39#endif
40
41static struct resource rng_resources[] = {
42 {
43 .start = OMAP_RNG_BASE,
44 .end = OMAP_RNG_BASE + 0x4f,
45 .flags = IORESOURCE_MEM,
46 },
47};
48
49static struct platform_device omap_rng_device = {
50 .name = "omap_rng",
51 .id = -1,
52 .num_resources = ARRAY_SIZE(rng_resources),
53 .resource = rng_resources,
54};
55
56static void omap_init_rng(void)
57{
58 (void) platform_device_register(&omap_rng_device);
59}
60#else
61static inline void omap_init_rng(void) {}
62#endif
63
64/*
65 * This gets called after board-specific INIT_MACHINE, and initializes most
66 * on-chip peripherals accessible on this board (except for few like USB):
67 *
68 * (a) Does any "standard config" pin muxing needed. Board-specific
69 * code will have muxed GPIO pins and done "nonstandard" setup;
70 * that code could live in the boot loader.
71 * (b) Populating board-specific platform_data with the data drivers
72 * rely on to handle wiring variations.
73 * (c) Creating platform devices as meaningful on this board and
74 * with this kernel configuration.
75 *
76 * Claiming GPIOs, and setting their direction and initial values, is the
77 * responsibility of the device drivers. So is responding to probe().
78 *
79 * Board-specific knowledge like creating devices or pin setup is to be
80 * kept out of drivers as much as possible. In particular, pin setup
81 * may be handled by the boot loader, and drivers should expect it will
82 * normally have been done by the time they're probed.
83 */
84static int __init omap_init_devices(void)
85{
86 /* please keep these calls, and their implementations above,
87 * in alphabetical order so they're easier to sort through.
88 */
89 omap_init_rng();
90 return 0;
91}
92arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fe626761e53..c76ed8bff838 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,8 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/delay.h> 37#include <linux/delay.h>
38 38
39#include <mach/hardware.h> 39#include <plat/cpu.h>
40#include <plat/dma.h> 40#include <plat/dma.h>
41
42#include <plat/tc.h> 41#include <plat/tc.h>
43 42
44/* 43/*
@@ -969,8 +968,7 @@ void omap_stop_dma(int lch)
969 l = p->dma_read(CCR, lch); 968 l = p->dma_read(CCR, lch);
970 } 969 }
971 if (i >= 100) 970 if (i >= 100)
972 printk(KERN_ERR "DMA drain did not complete on " 971 pr_err("DMA drain did not complete on lch %d\n", lch);
973 "lch %d\n", lch);
974 /* Restore OCP_SYSCONFIG */ 972 /* Restore OCP_SYSCONFIG */
975 p->dma_write(sys_cf, OCP_SYSCONFIG, lch); 973 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
976 } else { 974 } else {
@@ -1154,8 +1152,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
1154 1152
1155 if ((dma_chan[lch_head].dev_id == -1) || 1153 if ((dma_chan[lch_head].dev_id == -1) ||
1156 (dma_chan[lch_queue].dev_id == -1)) { 1154 (dma_chan[lch_queue].dev_id == -1)) {
1157 printk(KERN_ERR "omap_dma: trying to link " 1155 pr_err("omap_dma: trying to link non requested channels\n");
1158 "non requested channels\n");
1159 dump_stack(); 1156 dump_stack();
1160 } 1157 }
1161 1158
@@ -1181,15 +1178,13 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
1181 1178
1182 if (dma_chan[lch_head].next_lch != lch_queue || 1179 if (dma_chan[lch_head].next_lch != lch_queue ||
1183 dma_chan[lch_head].next_lch == -1) { 1180 dma_chan[lch_head].next_lch == -1) {
1184 printk(KERN_ERR "omap_dma: trying to unlink " 1181 pr_err("omap_dma: trying to unlink non linked channels\n");
1185 "non linked channels\n");
1186 dump_stack(); 1182 dump_stack();
1187 } 1183 }
1188 1184
1189 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1190 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { 1186 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1191 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1187 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1192 "before unlinking\n");
1193 dump_stack(); 1188 dump_stack();
1194 } 1189 }
1195 1190
@@ -1831,16 +1826,15 @@ static int omap1_dma_handle_ch(int ch)
1831 if ((csr & 0x3f) == 0) 1826 if ((csr & 0x3f) == 0)
1832 return 0; 1827 return 0;
1833 if (unlikely(dma_chan[ch].dev_id == -1)) { 1828 if (unlikely(dma_chan[ch].dev_id == -1)) {
1834 printk(KERN_WARNING "Spurious interrupt from DMA channel " 1829 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1835 "%d (CSR %04x)\n", ch, csr); 1830 ch, csr);
1836 return 0; 1831 return 0;
1837 } 1832 }
1838 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) 1833 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1839 printk(KERN_WARNING "DMA timeout with device %d\n", 1834 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1840 dma_chan[ch].dev_id);
1841 if (unlikely(csr & OMAP_DMA_DROP_IRQ)) 1835 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1842 printk(KERN_WARNING "DMA synchronization event drop occurred " 1836 pr_warn("DMA synchronization event drop occurred with device %d\n",
1843 "with device %d\n", dma_chan[ch].dev_id); 1837 dma_chan[ch].dev_id);
1844 if (likely(csr & OMAP_DMA_BLOCK_IRQ)) 1838 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1845 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; 1839 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1846 if (likely(dma_chan[ch].callback != NULL)) 1840 if (likely(dma_chan[ch].callback != NULL))
@@ -1880,21 +1874,19 @@ static int omap2_dma_handle_ch(int ch)
1880 1874
1881 if (!status) { 1875 if (!status) {
1882 if (printk_ratelimit()) 1876 if (printk_ratelimit())
1883 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", 1877 pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1884 ch);
1885 p->dma_write(1 << ch, IRQSTATUS_L0, ch); 1878 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1886 return 0; 1879 return 0;
1887 } 1880 }
1888 if (unlikely(dma_chan[ch].dev_id == -1)) { 1881 if (unlikely(dma_chan[ch].dev_id == -1)) {
1889 if (printk_ratelimit()) 1882 if (printk_ratelimit())
1890 printk(KERN_WARNING "IRQ %04x for non-allocated DMA" 1883 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1891 "channel %d\n", status, ch); 1884 status, ch);
1892 return 0; 1885 return 0;
1893 } 1886 }
1894 if (unlikely(status & OMAP_DMA_DROP_IRQ)) 1887 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1895 printk(KERN_INFO 1888 pr_info("DMA synchronization event drop occurred with device %d\n",
1896 "DMA synchronization event drop occurred with device " 1889 dma_chan[ch].dev_id);
1897 "%d\n", dma_chan[ch].dev_id);
1898 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { 1890 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1899 printk(KERN_INFO "DMA transaction error with device %d\n", 1891 printk(KERN_INFO "DMA transaction error with device %d\n",
1900 dma_chan[ch].dev_id); 1892 dma_chan[ch].dev_id);
@@ -2014,8 +2006,9 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2014 2006
2015 p = pdev->dev.platform_data; 2007 p = pdev->dev.platform_data;
2016 if (!p) { 2008 if (!p) {
2017 dev_err(&pdev->dev, "%s: System DMA initialized without" 2009 dev_err(&pdev->dev,
2018 "platform data\n", __func__); 2010 "%s: System DMA initialized without platform data\n",
2011 __func__);
2019 return -EINVAL; 2012 return -EINVAL;
2020 } 2013 }
2021 2014
@@ -2090,8 +2083,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2090 } 2083 }
2091 ret = setup_irq(dma_irq, &omap24xx_dma_irq); 2084 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2092 if (ret) { 2085 if (ret) {
2093 dev_err(&pdev->dev, "set_up failed for IRQ %d" 2086 dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
2094 "for DMA (error %d)\n", dma_irq, ret); 2087 dma_irq, ret);
2095 goto exit_dma_lch_fail; 2088 goto exit_dma_lch_fail;
2096 } 2089 }
2097 } 2090 }
@@ -2099,8 +2092,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2099 /* reserve dma channels 0 and 1 in high security devices */ 2092 /* reserve dma channels 0 and 1 in high security devices */
2100 if (cpu_is_omap34xx() && 2093 if (cpu_is_omap34xx() &&
2101 (omap_type() != OMAP2_DEVICE_TYPE_GP)) { 2094 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2102 printk(KERN_INFO "Reserving DMA channels 0 and 1 for " 2095 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2103 "HS ROM code\n");
2104 dma_chan[0].dev_id = 0; 2096 dma_chan[0].dev_id = 0;
2105 dma_chan[1].dev_id = 1; 2097 dma_chan[1].dev_id = 1;
2106 } 2098 }
@@ -2108,8 +2100,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2108 return 0; 2100 return 0;
2109 2101
2110exit_dma_irq_fail: 2102exit_dma_irq_fail:
2111 dev_err(&pdev->dev, "unable to request IRQ %d" 2103 dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
2112 "for DMA (error %d)\n", dma_irq, ret); 2104 dma_irq, ret);
2113 for (irq_rel = 0; irq_rel < ch; irq_rel++) { 2105 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2114 dma_irq = platform_get_irq(pdev, irq_rel); 2106 dma_irq = platform_get_irq(pdev, irq_rel);
2115 free_irq(dma_irq, (void *)(irq_rel + 1)); 2107 free_irq(dma_irq, (void *)(irq_rel + 1));
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 626ad8cad7a9..938b50a33439 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -189,6 +189,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
189 timer->reserved = 1; 189 timer->reserved = 1;
190 break; 190 break;
191 } 191 }
192 spin_unlock_irqrestore(&dm_timer_lock, flags);
192 193
193 if (timer) { 194 if (timer) {
194 ret = omap_dm_timer_prepare(timer); 195 ret = omap_dm_timer_prepare(timer);
@@ -197,7 +198,6 @@ struct omap_dm_timer *omap_dm_timer_request(void)
197 timer = NULL; 198 timer = NULL;
198 } 199 }
199 } 200 }
200 spin_unlock_irqrestore(&dm_timer_lock, flags);
201 201
202 if (!timer) 202 if (!timer)
203 pr_debug("%s: timer request failed!\n", __func__); 203 pr_debug("%s: timer request failed!\n", __func__);
@@ -220,6 +220,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
220 break; 220 break;
221 } 221 }
222 } 222 }
223 spin_unlock_irqrestore(&dm_timer_lock, flags);
223 224
224 if (timer) { 225 if (timer) {
225 ret = omap_dm_timer_prepare(timer); 226 ret = omap_dm_timer_prepare(timer);
@@ -228,7 +229,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
228 timer = NULL; 229 timer = NULL;
229 } 230 }
230 } 231 }
231 spin_unlock_irqrestore(&dm_timer_lock, flags);
232 232
233 if (!timer) 233 if (!timer)
234 pr_debug("%s: timer%d request failed!\n", __func__, id); 234 pr_debug("%s: timer%d request failed!\n", __func__, id);
@@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
258 258
259void omap_dm_timer_disable(struct omap_dm_timer *timer) 259void omap_dm_timer_disable(struct omap_dm_timer *timer)
260{ 260{
261 pm_runtime_put(&timer->pdev->dev); 261 pm_runtime_put_sync(&timer->pdev->dev);
262} 262}
263EXPORT_SYMBOL_GPL(omap_dm_timer_disable); 263EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
264 264
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index dd6f92c99e56..bcbb9d5dc293 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -33,8 +33,6 @@
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include <plat/board.h>
37
38#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 36#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
39 37
40static bool omapfb_lcd_configured; 38static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc71c4d..6013831a043e 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -32,13 +32,13 @@
32#include <linux/clk.h> 32#include <linux/clk.h>
33 33
34#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <plat/mux.h>
36#include <plat/i2c.h> 35#include <plat/i2c.h>
37#include <plat/omap-pm.h> 36#include <plat/omap-pm.h>
38#include <plat/omap_device.h> 37#include <plat/omap_device.h>
39 38
40#define OMAP_I2C_SIZE 0x3f 39#define OMAP_I2C_SIZE 0x3f
41#define OMAP1_I2C_BASE 0xfffb3800 40#define OMAP1_I2C_BASE 0xfffb3800
41#define OMAP1_INT_I2C (32 + 4)
42 42
43static const char name[] = "omap_i2c"; 43static const char name[] = "omap_i2c";
44 44
@@ -105,7 +105,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
105 res = pdev->resource; 105 res = pdev->resource;
106 res[0].start = OMAP1_I2C_BASE; 106 res[0].start = OMAP1_I2C_BASE;
107 res[0].end = res[0].start + OMAP_I2C_SIZE; 107 res[0].end = res[0].start + OMAP_I2C_SIZE;
108 res[1].start = INT_I2C; 108 res[1].start = OMAP1_INT_I2C;
109 pdata = &i2c_pdata[bus_id - 1]; 109 pdata = &i2c_pdata[bus_id - 1];
110 110
111 /* all OMAP1 have IP version 1 register set */ 111 /* all OMAP1 have IP version 1 register set */
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
deleted file mode 100644
index 06c19bb7bca6..000000000000
--- a/arch/arm/plat-omap/include/plat/am33xx.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file contains the address info for various AM33XX modules.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_AM33XX_H
17#define __ASM_ARCH_AM33XX_H
18
19#define L4_SLOW_AM33XX_BASE 0x48000000
20
21#define AM33XX_SCM_BASE 0x44E10000
22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
23#define AM33XX_PRCM_BASE 0x44E00000
24
25#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
deleted file mode 100644
index ad6f865d1f16..000000000000
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-ams-delta.h
3 *
4 * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
27#define __ASM_ARCH_OMAP_AMS_DELTA_H
28
29#if defined (CONFIG_MACH_AMS_DELTA)
30
31#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
32#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
33#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
34
35#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
36#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
37#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
38#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
39#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
40#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
41#define AMS_DELTA_GPIO_PIN_CONFIG 11
42#define AMS_DELTA_GPIO_PIN_NAND_RB 12
43
44#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
45#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
46#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
47#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
48#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
49#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
50#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
51#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
52#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
53#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
54#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
55#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
56#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
57#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
58
59#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
60#define AMS_DELTA_LATCH2_NGPIO 16
61
62#ifndef __ASSEMBLY__
63void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
64#define ams_delta_latch2_write(mask, value) \
65 ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
66 AMS_DELTA_LATCH2_NGPIO, (mask), (value))
67#endif
68
69#endif /* CONFIG_MACH_AMS_DELTA */
70
71#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
diff --git a/arch/arm/plat-omap/include/plat/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
deleted file mode 100644
index 355adbdaae33..000000000000
--- a/arch/arm/plat-omap/include/plat/board-sx1.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Siemens SX1 board definitions
3 *
4 * Copyright: Vovan888 at gmail com
5 *
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 */
14
15#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
16#define __ASM_ARCH_SX1_I2C_CHIPS_H
17
18#define SOFIA_MAX_LIGHT_VAL 0x2B
19
20#define SOFIA_I2C_ADDR 0x32
21/* Sofia reg 3 bits masks */
22#define SOFIA_POWER1_REG 0x03
23
24#define SOFIA_USB_POWER 0x01
25#define SOFIA_MMC_POWER 0x04
26#define SOFIA_BLUETOOTH_POWER 0x08
27#define SOFIA_MMILIGHT_POWER 0x20
28
29#define SOFIA_POWER2_REG 0x04
30#define SOFIA_BACKLIGHT_REG 0x06
31#define SOFIA_KEYLIGHT_REG 0x07
32#define SOFIA_DIMMING_REG 0x09
33
34
35/* Function Prototypes for SX1 devices control on I2C bus */
36
37int sx1_setbacklight(u8 backlight);
38int sx1_getbacklight(u8 *backlight);
39int sx1_setkeylight(u8 keylight);
40int sx1_getkeylight(u8 *keylight);
41
42int sx1_setmmipower(u8 onoff);
43int sx1_setusbpower(u8 onoff);
44int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
45int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
46
47/* MMC prototypes */
48
49extern void sx1_mmc_init(void);
50extern void sx1_mmc_slot_cover_handler(void *arg, int state);
51
52#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/arch/arm/plat-omap/include/plat/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
deleted file mode 100644
index 27916b210f57..000000000000
--- a/arch/arm/plat-omap/include/plat/board-voiceblue.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
3 *
4 * Hardware definitions for OMAP5910 based VoiceBlue board.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_VOICEBLUE_H
12#define __ASM_ARCH_VOICEBLUE_H
13
14extern void voiceblue_wdt_enable(void);
15extern void voiceblue_wdt_disable(void);
16extern void voiceblue_wdt_ping(void);
17
18#endif /* __ASM_ARCH_VOICEBLUE_H */
19
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
deleted file mode 100644
index e62f20a5c0af..000000000000
--- a/arch/arm/plat-omap/include/plat/board.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/board.h
3 *
4 * Information structures for board-specific data
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 */
9
10#ifndef _OMAP_BOARD_H
11#define _OMAP_BOARD_H
12
13#include <linux/types.h>
14
15#include <plat/gpio-switch.h>
16
17/*
18 * OMAP35x EVM revision
19 * Run time detection of EVM revision is done by reading Ethernet
20 * PHY ID -
21 * GEN_1 = 0x01150000
22 * GEN_2 = 0x92200000
23 */
24enum {
25 OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
26 OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
27};
28
29/* Different peripheral ids */
30#define OMAP_TAG_CLOCK 0x4f01
31#define OMAP_TAG_GPIO_SWITCH 0x4f06
32#define OMAP_TAG_STI_CONSOLE 0x4f09
33#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
34
35#define OMAP_TAG_BOOT_REASON 0x4f80
36#define OMAP_TAG_FLASH_PART 0x4f81
37#define OMAP_TAG_VERSION_STR 0x4f82
38
39struct omap_clock_config {
40 /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
41 u8 system_clock_type;
42};
43
44struct omap_serial_console_config {
45 u8 console_uart;
46 u32 console_speed;
47};
48
49struct omap_sti_console_config {
50 unsigned enable:1;
51 u8 channel;
52};
53
54struct omap_camera_sensor_config {
55 u16 reset_gpio;
56 int (*power_on)(void * data);
57 int (*power_off)(void * data);
58};
59
60struct omap_lcd_config {
61 char panel_name[16];
62 char ctrl_name[16];
63 s16 nreset_gpio;
64 u8 data_lines;
65};
66
67struct device;
68struct fb_info;
69struct omap_backlight_config {
70 int default_intensity;
71 int (*set_power)(struct device *dev, int state);
72};
73
74struct omap_fbmem_config {
75 u32 start;
76 u32 size;
77};
78
79struct omap_pwm_led_platform_data {
80 const char *name;
81 int intensity_timer;
82 int blink_timer;
83 void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
84};
85
86struct omap_uart_config {
87 /* Bit field of UARTs present; bit 0 --> UART1 */
88 unsigned int enabled_uarts;
89};
90
91
92struct omap_flash_part_config {
93 char part_table[0];
94};
95
96struct omap_boot_reason_config {
97 char reason_str[12];
98};
99
100struct omap_version_config {
101 char component[12];
102 char version[12];
103};
104
105struct omap_board_config_entry {
106 u16 tag;
107 u16 len;
108 u8 data[0];
109};
110
111struct omap_board_config_kernel {
112 u16 tag;
113 const void *data;
114};
115
116extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
117
118#define omap_get_config(tag, type) \
119 ((const type *) __omap_get_config((tag), sizeof(type), 0))
120#define omap_get_nr_config(tag, type, nr) \
121 ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
122
123extern const void *__init omap_get_var_config(u16 tag, size_t *len);
124
125extern struct omap_board_config_kernel *omap_board_config;
126extern int omap_board_config_size;
127
128
129/* for TI reference platforms sharing the same debug card */
130extern int debug_card_init(u32 addr, unsigned gpio);
131
132/* OMAP3EVM revision */
133#if defined(CONFIG_MACH_OMAP3EVM)
134u8 get_omap3_evm_rev(void);
135#else
136#define get_omap3_evm_rev() (-EINVAL)
137#endif
138#endif
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 68b180edcfff..67da857783ce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
30#ifndef __ASM_ARCH_OMAP_CPU_H 30#ifndef __ASM_ARCH_OMAP_CPU_H
31#define __ASM_ARCH_OMAP_CPU_H 31#define __ASM_ARCH_OMAP_CPU_H
32 32
33#ifndef __ASSEMBLY__
34
33#include <linux/bitops.h> 35#include <linux/bitops.h>
34#include <plat/multi.h> 36#include <plat/multi.h>
35 37
@@ -372,7 +374,8 @@ IS_OMAP_TYPE(3430, 0x3430)
372#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ 374#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
373 cpu_is_omap16xx()) 375 cpu_is_omap16xx())
374#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ 376#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
375 cpu_is_omap44xx() || soc_is_omap54xx()) 377 cpu_is_omap44xx() || soc_is_omap54xx() || \
378 soc_is_am33xx())
376 379
377/* Various silicon revisions for omap2 */ 380/* Various silicon revisions for omap2 */
378#define OMAP242X_CLASS 0x24200024 381#define OMAP242X_CLASS 0x24200024
@@ -492,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
492OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) 495OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
493OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) 496OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
494 497
498#endif /* __ASSEMBLY__ */
495#endif 499#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index c5811d4409b0..0a87b052f8f7 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -31,6 +31,8 @@
31/* Move omap4 specific defines to dma-44xx.h */ 31/* Move omap4 specific defines to dma-44xx.h */
32#include "dma-44xx.h" 32#include "dma-44xx.h"
33 33
34#define INT_DMA_LCD 25
35
34/* DMA channels for omap1 */ 36/* DMA channels for omap1 */
35#define OMAP_DMA_NO_DEVICE 0 37#define OMAP_DMA_NO_DEVICE 0
36#define OMAP_DMA_MCSI1_TX 1 38#define OMAP_DMA_MCSI1_TX 1
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
deleted file mode 100644
index 5927709b1908..000000000000
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef __OMAP_DSP_H__
2#define __OMAP_DSP_H__
3
4#include <linux/types.h>
5
6struct omap_dsp_platform_data {
7 void (*dsp_set_min_opp) (u8 opp_id);
8 u8 (*dsp_get_opp) (void);
9 void (*cpu_set_freq) (unsigned long f);
10 unsigned long (*cpu_get_freq) (void);
11 unsigned long mpu_speed[6];
12
13 /* functions to write and read PRCM registers */
14 void (*dsp_prm_write)(u32, s16 , u16);
15 u32 (*dsp_prm_read)(s16 , u16);
16 u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
17 void (*dsp_cm_write)(u32, s16 , u16);
18 u32 (*dsp_cm_read)(s16 , u16);
19 u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
20
21 void (*set_bootaddr)(u32);
22 void (*set_bootmode)(u8);
23
24 phys_addr_t phys_mempool_base;
25 phys_addr_t phys_mempool_size;
26};
27
28#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
29extern void omap_dsp_reserve_sdram_memblock(void);
30#else
31static inline void omap_dsp_reserve_sdram_memblock(void) { }
32#endif
33
34#endif
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
deleted file mode 100644
index 0d88499b79e9..000000000000
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Flash support for OMAP1
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __OMAP_FLASH_H
10#define __OMAP_FLASH_H
11
12#include <linux/mtd/map.h>
13
14struct platform_device;
15extern void omap1_set_vpp(struct platform_device *pdev, int enable);
16
17#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
deleted file mode 100644
index 10da0e07c0cf..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio-switch.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * GPIO switch definitions
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
12#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
13
14#include <linux/types.h>
15
16/* Cover:
17 * high -> closed
18 * low -> open
19 * Connection:
20 * high -> connected
21 * low -> disconnected
22 * Activity:
23 * high -> active
24 * low -> inactive
25 *
26 */
27#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
28#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
29#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
30#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
31#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
32
33struct omap_gpio_switch {
34 const char *name;
35 s16 gpio;
36 unsigned flags:4;
37 unsigned type:4;
38
39 /* Time in ms to debounce when transitioning from
40 * inactive state to active state. */
41 u16 debounce_rising;
42 /* Same for transition from active to inactive state. */
43 u16 debounce_falling;
44
45 /* notify board-specific code about state changes */
46 void (* notify)(void *data, int state);
47 void *notify_data;
48};
49
50/* Call at init time only */
51extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
52 int count);
53
54#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
deleted file mode 100644
index 50fb7cc000ea..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ /dev/null
@@ -1,228 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpio.h
3 *
4 * OMAP GPIO handling defines and functions
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 *
8 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_GPIO_H
27#define __ASM_ARCH_OMAP_GPIO_H
28
29#include <linux/io.h>
30#include <linux/platform_device.h>
31#include <mach/irqs.h>
32
33#define OMAP1_MPUIO_BASE 0xfffb5000
34
35/*
36 * These are the omap15xx/16xx offsets. The omap7xx offset are
37 * OMAP_MPUIO_ / 2 offsets below.
38 */
39#define OMAP_MPUIO_INPUT_LATCH 0x00
40#define OMAP_MPUIO_OUTPUT 0x04
41#define OMAP_MPUIO_IO_CNTL 0x08
42#define OMAP_MPUIO_KBR_LATCH 0x10
43#define OMAP_MPUIO_KBC 0x14
44#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
45#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
46#define OMAP_MPUIO_KBD_INT 0x20
47#define OMAP_MPUIO_GPIO_INT 0x24
48#define OMAP_MPUIO_KBD_MASKIT 0x28
49#define OMAP_MPUIO_GPIO_MASKIT 0x2c
50#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
51#define OMAP_MPUIO_LATCH 0x34
52
53#define OMAP34XX_NR_GPIOS 6
54
55/*
56 * OMAP1510 GPIO registers
57 */
58#define OMAP1510_GPIO_DATA_INPUT 0x00
59#define OMAP1510_GPIO_DATA_OUTPUT 0x04
60#define OMAP1510_GPIO_DIR_CONTROL 0x08
61#define OMAP1510_GPIO_INT_CONTROL 0x0c
62#define OMAP1510_GPIO_INT_MASK 0x10
63#define OMAP1510_GPIO_INT_STATUS 0x14
64#define OMAP1510_GPIO_PIN_CONTROL 0x18
65
66#define OMAP1510_IH_GPIO_BASE 64
67
68/*
69 * OMAP1610 specific GPIO registers
70 */
71#define OMAP1610_GPIO_REVISION 0x0000
72#define OMAP1610_GPIO_SYSCONFIG 0x0010
73#define OMAP1610_GPIO_SYSSTATUS 0x0014
74#define OMAP1610_GPIO_IRQSTATUS1 0x0018
75#define OMAP1610_GPIO_IRQENABLE1 0x001c
76#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
77#define OMAP1610_GPIO_DATAIN 0x002c
78#define OMAP1610_GPIO_DATAOUT 0x0030
79#define OMAP1610_GPIO_DIRECTION 0x0034
80#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
81#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
82#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
83#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
84#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
85#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
86#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
87#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
88
89/*
90 * OMAP7XX specific GPIO registers
91 */
92#define OMAP7XX_GPIO_DATA_INPUT 0x00
93#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
94#define OMAP7XX_GPIO_DIR_CONTROL 0x08
95#define OMAP7XX_GPIO_INT_CONTROL 0x0c
96#define OMAP7XX_GPIO_INT_MASK 0x10
97#define OMAP7XX_GPIO_INT_STATUS 0x14
98
99/*
100 * omap2+ specific GPIO registers
101 */
102#define OMAP24XX_GPIO_REVISION 0x0000
103#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
104#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
105#define OMAP24XX_GPIO_IRQENABLE2 0x002c
106#define OMAP24XX_GPIO_IRQENABLE1 0x001c
107#define OMAP24XX_GPIO_WAKE_EN 0x0020
108#define OMAP24XX_GPIO_CTRL 0x0030
109#define OMAP24XX_GPIO_OE 0x0034
110#define OMAP24XX_GPIO_DATAIN 0x0038
111#define OMAP24XX_GPIO_DATAOUT 0x003c
112#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
113#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
114#define OMAP24XX_GPIO_RISINGDETECT 0x0048
115#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
116#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
117#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
118#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
119#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
120#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
121#define OMAP24XX_GPIO_SETWKUENA 0x0084
122#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
123#define OMAP24XX_GPIO_SETDATAOUT 0x0094
124
125#define OMAP4_GPIO_REVISION 0x0000
126#define OMAP4_GPIO_EOI 0x0020
127#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
128#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
129#define OMAP4_GPIO_IRQSTATUS0 0x002c
130#define OMAP4_GPIO_IRQSTATUS1 0x0030
131#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
132#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
133#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
134#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
135#define OMAP4_GPIO_IRQWAKEN0 0x0044
136#define OMAP4_GPIO_IRQWAKEN1 0x0048
137#define OMAP4_GPIO_IRQENABLE1 0x011c
138#define OMAP4_GPIO_WAKE_EN 0x0120
139#define OMAP4_GPIO_IRQSTATUS2 0x0128
140#define OMAP4_GPIO_IRQENABLE2 0x012c
141#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138
144#define OMAP4_GPIO_DATAOUT 0x013c
145#define OMAP4_GPIO_LEVELDETECT0 0x0140
146#define OMAP4_GPIO_LEVELDETECT1 0x0144
147#define OMAP4_GPIO_RISINGDETECT 0x0148
148#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
152#define OMAP4_GPIO_SETIRQENABLE1 0x0164
153#define OMAP4_GPIO_CLEARWKUENA 0x0180
154#define OMAP4_GPIO_SETWKUENA 0x0184
155#define OMAP4_GPIO_CLEARDATAOUT 0x0190
156#define OMAP4_GPIO_SETDATAOUT 0x0194
157
158#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
159#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
160
161struct omap_gpio_dev_attr {
162 int bank_width; /* GPIO bank width */
163 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
164};
165
166struct omap_gpio_reg_offs {
167 u16 revision;
168 u16 direction;
169 u16 datain;
170 u16 dataout;
171 u16 set_dataout;
172 u16 clr_dataout;
173 u16 irqstatus;
174 u16 irqstatus2;
175 u16 irqstatus_raw0;
176 u16 irqstatus_raw1;
177 u16 irqenable;
178 u16 irqenable2;
179 u16 set_irqenable;
180 u16 clr_irqenable;
181 u16 debounce;
182 u16 debounce_en;
183 u16 ctrl;
184 u16 wkup_en;
185 u16 leveldetect0;
186 u16 leveldetect1;
187 u16 risingdetect;
188 u16 fallingdetect;
189 u16 irqctrl;
190 u16 edgectrl1;
191 u16 edgectrl2;
192 u16 pinctrl;
193
194 bool irqenable_inv;
195};
196
197struct omap_gpio_platform_data {
198 int bank_type;
199 int bank_width; /* GPIO bank width */
200 int bank_stride; /* Only needed for omap1 MPUIO */
201 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
202 bool loses_context; /* whether the bank would ever lose context */
203 bool is_mpuio; /* whether the bank is of type MPUIO */
204 u32 non_wakeup_gpios;
205
206 struct omap_gpio_reg_offs *regs;
207
208 /* Return context loss count due to PM states changing */
209 int (*get_context_loss_count)(struct device *dev);
210};
211
212extern void omap2_gpio_prepare_for_idle(int off_mode);
213extern void omap2_gpio_resume_after_idle(void);
214extern void omap_set_gpio_debounce(int gpio, int enable);
215extern void omap_set_gpio_debounce_time(int gpio, int enable);
216/*-------------------------------------------------------------------------*/
217
218/*
219 * Wrappers for "new style" GPIO calls, using the new infrastructure
220 * which lets us plug in FPGA, I2C, and other implementations.
221 *
222 * The original OMAP-specific calls should eventually be removed.
223 */
224
225#include <linux/errno.h>
226#include <asm-generic/gpio.h>
227
228#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
deleted file mode 100644
index b64fbee4d567..000000000000
--- a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
12
13#define GPMC_TIMINGS_SMC91C96 (1 << 4)
14#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
15#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
16#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
17
18struct omap_smc91x_platform_data {
19 int cs;
20 int gpio_irq;
21 int gpio_pwrdwn;
22 int gpio_reset;
23 int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
24 u32 flags;
25 int (*retime)(void);
26};
27
28#if defined(CONFIG_SMC91X) || \
29 defined(CONFIG_SMC91X_MODULE)
30
31extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
32
33#else
34
35#define board_smc91x_data NULL
36
37static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
38{
39}
40
41#endif
42#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
deleted file mode 100644
index ea6c9c88c725..000000000000
--- a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
15
16struct omap_smsc911x_platform_data {
17 int id;
18 int cs;
19 int gpio_irq;
20 int gpio_reset;
21 u32 flags;
22};
23
24#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
25
26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
27
28#else
29
30static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
31{
32}
33
34#endif
35#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index f37764a36072..2e6e2597178c 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -133,6 +133,25 @@ struct gpmc_timings {
133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
134}; 134};
135 135
136struct gpmc_nand_regs {
137 void __iomem *gpmc_status;
138 void __iomem *gpmc_nand_command;
139 void __iomem *gpmc_nand_address;
140 void __iomem *gpmc_nand_data;
141 void __iomem *gpmc_prefetch_config1;
142 void __iomem *gpmc_prefetch_config2;
143 void __iomem *gpmc_prefetch_control;
144 void __iomem *gpmc_prefetch_status;
145 void __iomem *gpmc_ecc_config;
146 void __iomem *gpmc_ecc_control;
147 void __iomem *gpmc_ecc_size_config;
148 void __iomem *gpmc_ecc1_result;
149 void __iomem *gpmc_bch_result0;
150};
151
152extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
153extern int gpmc_get_client_irq(unsigned irq_config);
154
136extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 155extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
137extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); 156extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
138extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 157extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
deleted file mode 100644
index ddbde38e1e33..000000000000
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ /dev/null
@@ -1,293 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__
41#include <asm/types.h>
42#include <plat/cpu.h>
43#endif
44#include <plat/serial.h>
45
46/*
47 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors
49 * NOTE: Put all processor or board specific parts to the special header
50 * files.
51 * ---------------------------------------------------------------------------
52 */
53
54/*
55 * ----------------------------------------------------------------------------
56 * Timers
57 * ----------------------------------------------------------------------------
58 */
59#define OMAP_MPU_TIMER1_BASE (0xfffec500)
60#define OMAP_MPU_TIMER2_BASE (0xfffec600)
61#define OMAP_MPU_TIMER3_BASE (0xfffec700)
62#define MPU_TIMER_FREE (1 << 6)
63#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
64#define MPU_TIMER_AR (1 << 1)
65#define MPU_TIMER_ST (1 << 0)
66
67/*
68 * ----------------------------------------------------------------------------
69 * Clocks
70 * ----------------------------------------------------------------------------
71 */
72#define CLKGEN_REG_BASE (0xfffece00)
73#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
74#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
75#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
76#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
77#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
78#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
79#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
80#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
81
82#define CK_RATEF 1
83#define CK_IDLEF 2
84#define CK_ENABLEF 4
85#define CK_SELECTF 8
86#define SETARM_IDLE_SHIFT
87
88/* DPLL control registers */
89#define DPLL_CTL (0xfffecf00)
90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
96#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
97
98/*
99 * ---------------------------------------------------------------------------
100 * UPLD
101 * ---------------------------------------------------------------------------
102 */
103#define ULPD_REG_BASE (0xfffe0800)
104#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
105#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
106#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
107# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
108# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
109#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
110# define SOFT_UDC_REQ (1 << 4)
111# define SOFT_USB_CLK_REQ (1 << 3)
112# define SOFT_DPLL_REQ (1 << 0)
113#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
114#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
115#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
116#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
117#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
118# define DIS_MMC2_DPLL_REQ (1 << 11)
119# define DIS_MMC1_DPLL_REQ (1 << 10)
120# define DIS_UART3_DPLL_REQ (1 << 9)
121# define DIS_UART2_DPLL_REQ (1 << 8)
122# define DIS_UART1_DPLL_REQ (1 << 7)
123# define DIS_USB_HOST_DPLL_REQ (1 << 6)
124#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
125#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
126
127/*
128 * ---------------------------------------------------------------------------
129 * Watchdog timer
130 * ---------------------------------------------------------------------------
131 */
132
133/* Watchdog timer within the OMAP3.2 gigacell */
134#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
135#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
136#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
137#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
138#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
139
140/*
141 * ---------------------------------------------------------------------------
142 * Interrupts
143 * ---------------------------------------------------------------------------
144 */
145#ifdef CONFIG_ARCH_OMAP1
146
147/*
148 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
149 * or something similar.. -- PFM.
150 */
151
152#define OMAP_IH1_BASE 0xfffecb00
153#define OMAP_IH2_BASE 0xfffe0000
154
155#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
156#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
157#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
158#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
159#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
160#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
161#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
162
163#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
164#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
165#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
166#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
167#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
168#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
169#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
170
171#define IRQ_ITR_REG_OFFSET 0x00
172#define IRQ_MIR_REG_OFFSET 0x04
173#define IRQ_SIR_IRQ_REG_OFFSET 0x10
174#define IRQ_SIR_FIQ_REG_OFFSET 0x14
175#define IRQ_CONTROL_REG_OFFSET 0x18
176#define IRQ_ISR_REG_OFFSET 0x9c
177#define IRQ_ILR0_REG_OFFSET 0x1c
178#define IRQ_GMR_REG_OFFSET 0xa0
179
180#endif
181
182/*
183 * ----------------------------------------------------------------------------
184 * System control registers
185 * ----------------------------------------------------------------------------
186 */
187#define MOD_CONF_CTRL_0 0xfffe1080
188#define MOD_CONF_CTRL_1 0xfffe1110
189
190/*
191 * ----------------------------------------------------------------------------
192 * Pin multiplexing registers
193 * ----------------------------------------------------------------------------
194 */
195#define FUNC_MUX_CTRL_0 0xfffe1000
196#define FUNC_MUX_CTRL_1 0xfffe1004
197#define FUNC_MUX_CTRL_2 0xfffe1008
198#define COMP_MODE_CTRL_0 0xfffe100c
199#define FUNC_MUX_CTRL_3 0xfffe1010
200#define FUNC_MUX_CTRL_4 0xfffe1014
201#define FUNC_MUX_CTRL_5 0xfffe1018
202#define FUNC_MUX_CTRL_6 0xfffe101C
203#define FUNC_MUX_CTRL_7 0xfffe1020
204#define FUNC_MUX_CTRL_8 0xfffe1024
205#define FUNC_MUX_CTRL_9 0xfffe1028
206#define FUNC_MUX_CTRL_A 0xfffe102C
207#define FUNC_MUX_CTRL_B 0xfffe1030
208#define FUNC_MUX_CTRL_C 0xfffe1034
209#define FUNC_MUX_CTRL_D 0xfffe1038
210#define PULL_DWN_CTRL_0 0xfffe1040
211#define PULL_DWN_CTRL_1 0xfffe1044
212#define PULL_DWN_CTRL_2 0xfffe1048
213#define PULL_DWN_CTRL_3 0xfffe104c
214#define PULL_DWN_CTRL_4 0xfffe10ac
215
216/* OMAP-1610 specific multiplexing registers */
217#define FUNC_MUX_CTRL_E 0xfffe1090
218#define FUNC_MUX_CTRL_F 0xfffe1094
219#define FUNC_MUX_CTRL_10 0xfffe1098
220#define FUNC_MUX_CTRL_11 0xfffe109c
221#define FUNC_MUX_CTRL_12 0xfffe10a0
222#define PU_PD_SEL_0 0xfffe10b4
223#define PU_PD_SEL_1 0xfffe10b8
224#define PU_PD_SEL_2 0xfffe10bc
225#define PU_PD_SEL_3 0xfffe10c0
226#define PU_PD_SEL_4 0xfffe10c4
227
228/* Timer32K for 1610 and 1710*/
229#define OMAP_TIMER32K_BASE 0xFFFBC400
230
231/*
232 * ---------------------------------------------------------------------------
233 * TIPB bus interface
234 * ---------------------------------------------------------------------------
235 */
236#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
237#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
238#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
239#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
240
241/*
242 * ----------------------------------------------------------------------------
243 * MPUI interface
244 * ----------------------------------------------------------------------------
245 */
246#define MPUI_BASE (0xfffec900)
247#define MPUI_CTRL (MPUI_BASE + 0x0)
248#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
249#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
250#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
251#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
252#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
253#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
254#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
255
256/*
257 * ----------------------------------------------------------------------------
258 * LED Pulse Generator
259 * ----------------------------------------------------------------------------
260 */
261#define OMAP_LPG1_BASE 0xfffbd000
262#define OMAP_LPG2_BASE 0xfffbd800
263#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
264#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
265#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
266#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
267
268/*
269 * ----------------------------------------------------------------------------
270 * Pulse-Width Light
271 * ----------------------------------------------------------------------------
272 */
273#define OMAP_PWL_BASE 0xfffb5800
274#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
275#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
276
277/*
278 * ---------------------------------------------------------------------------
279 * Processor specific defines
280 * ---------------------------------------------------------------------------
281 */
282
283#include <plat/omap7xx.h>
284#include <plat/omap1510.h>
285#include <plat/omap16xx.h>
286#include <plat/omap24xx.h>
287#include <plat/omap34xx.h>
288#include <plat/omap44xx.h>
289#include <plat/ti81xx.h>
290#include <plat/am33xx.h>
291#include <plat/omap54xx.h>
292
293#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/plat-omap/include/plat/hdq1w.h
deleted file mode 100644
index 0c1efc846d8d..000000000000
--- a/arch/arm/plat-omap/include/plat/hdq1w.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Shared macros and function prototypes for the HDQ1W/1-wire IP block
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 */
21#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
22#define ARCH_ARM_MACH_OMAP2_HDQ1W_H
23
24#include <plat/omap_hwmod.h>
25
26/*
27 * XXX A future cleanup patch should modify
28 * drivers/w1/masters/omap_hdq.c to use these macros
29 */
30#define HDQ_CTRL_STATUS_OFFSET 0x0c
31#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT 5
32
33
34extern int omap_hdq1w_reset(struct omap_hwmod *oh);
35
36#endif
diff --git a/arch/arm/plat-omap/include/plat/irda.h b/arch/arm/plat-omap/include/plat/irda.h
deleted file mode 100644
index 40f60339d1c6..000000000000
--- a/arch/arm/plat-omap/include/plat/irda.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/irda.h
3 *
4 * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_ARCH_IRDA_H
11#define ASMARM_ARCH_IRDA_H
12
13/* board specific transceiver capabilities */
14
15#define IR_SEL 1 /* Selects IrDA */
16#define IR_SIRMODE 2
17#define IR_FIRMODE 4
18#define IR_MIRMODE 8
19
20struct omap_irda_config {
21 int transceiver_cap;
22 int (*transceiver_mode)(struct device *dev, int mode);
23 int (*select_irda)(struct device *dev, int state);
24 int rx_channel;
25 int tx_channel;
26 unsigned long dest_start;
27 unsigned long src_start;
28 int tx_trigger;
29 int rx_trigger;
30 int mode;
31};
32
33#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644
index 518322c80116..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * OMAP4 Interrupt lines definitions
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Santosh Shilimkar (santosh.shilimkar@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
21#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
22
23/* OMAP44XX IRQs numbers definitions */
24#define OMAP44XX_IRQ_LOCALTIMER 29
25#define OMAP44XX_IRQ_LOCALWDT 30
26
27#define OMAP44XX_IRQ_GIC_START 32
28
29#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START)
30#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START)
31#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START)
32#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START)
33#define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START)
34#define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START)
35#define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START)
36#define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START)
37#define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START)
38#define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START)
39#define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START)
40#define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START)
41#define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START)
42#define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START)
43#define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START)
44#define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START)
45#define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START)
46#define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START)
47#define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START)
48#define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START)
49#define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START)
50#define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START)
51#define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START)
52#define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START)
53#define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START)
54#define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START)
55#define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START)
56#define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START)
57#define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START)
58#define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START)
59#define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START)
60#define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START)
61#define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START)
62#define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START)
63#define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START)
64#define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START)
65#define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START)
66#define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START)
67#define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START)
68#define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START)
69#define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START)
70#define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START)
71#define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START)
72#define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START)
73#define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START)
74#define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START)
75#define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START)
76#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START)
77#define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START)
78#define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START)
79#define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START)
80#define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START)
81#define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START)
82#define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START)
83#define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START)
84#define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START)
85#define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START)
86#define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START)
87#define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START)
88#define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START)
89#define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START)
90#define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START)
91#define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START)
92#define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START)
93#define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START)
94#define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START)
95#define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START)
96#define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START)
97#define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START)
98#define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START)
99#define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START)
100#define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START)
101#define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START)
102#define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START)
103#define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START)
104#define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START)
105#define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START)
106#define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START)
107#define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START)
108#define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START)
109#define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START)
110#define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START)
111#define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START)
112#define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START)
113#define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START)
114#define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START)
115#define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START)
116#define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START)
117#define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START)
118#define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START)
119#define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START)
120#define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START)
121#define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START)
122#define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START)
123#define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START)
124#define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START)
125#define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START)
126#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START)
127#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START)
128#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START)
129#define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START)
130#define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START)
131#define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START)
132#define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START)
133#define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START)
134#define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START)
135#define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START)
136#define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START)
137#define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START)
138#define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START)
139#define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START)
140#define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START)
141#define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START)
142#define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START)
143
144#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
deleted file mode 100644
index 37bbbbb981b2..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ /dev/null
@@ -1,453 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
25 * are different.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H
30
31/* All OMAP4 specific defines are moved to irqs-44xx.h */
32#include "irqs-44xx.h"
33
34/*
35 * IRQ numbers for interrupt handler 1
36 *
37 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
38 *
39 */
40#define INT_CAMERA 1
41#define INT_FIQ 3
42#define INT_RTDX 6
43#define INT_DSP_MMU_ABORT 7
44#define INT_HOST 8
45#define INT_ABORT 9
46#define INT_BRIDGE_PRIV 13
47#define INT_GPIO_BANK1 14
48#define INT_UART3 15
49#define INT_TIMER3 16
50#define INT_DMA_CH0_6 19
51#define INT_DMA_CH1_7 20
52#define INT_DMA_CH2_8 21
53#define INT_DMA_CH3 22
54#define INT_DMA_CH4 23
55#define INT_DMA_CH5 24
56#define INT_DMA_LCD 25
57#define INT_TIMER1 26
58#define INT_WD_TIMER 27
59#define INT_BRIDGE_PUB 28
60#define INT_TIMER2 30
61#define INT_LCD_CTRL 31
62
63/*
64 * OMAP-1510 specific IRQ numbers for interrupt handler 1
65 */
66#define INT_1510_IH2_IRQ 0
67#define INT_1510_RES2 2
68#define INT_1510_SPI_TX 4
69#define INT_1510_SPI_RX 5
70#define INT_1510_DSP_MAILBOX1 10
71#define INT_1510_DSP_MAILBOX2 11
72#define INT_1510_RES12 12
73#define INT_1510_LB_MMU 17
74#define INT_1510_RES18 18
75#define INT_1510_LOCAL_BUS 29
76
77/*
78 * OMAP-1610 specific IRQ numbers for interrupt handler 1
79 */
80#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
81#define INT_1610_IH2_FIQ 2
82#define INT_1610_McBSP2_TX 4
83#define INT_1610_McBSP2_RX 5
84#define INT_1610_DSP_MAILBOX1 10
85#define INT_1610_DSP_MAILBOX2 11
86#define INT_1610_LCD_LINE 12
87#define INT_1610_GPTIMER1 17
88#define INT_1610_GPTIMER2 18
89#define INT_1610_SSR_FIFO_0 29
90
91/*
92 * OMAP-7xx specific IRQ numbers for interrupt handler 1
93 */
94#define INT_7XX_IH2_FIQ 0
95#define INT_7XX_IH2_IRQ 1
96#define INT_7XX_USB_NON_ISO 2
97#define INT_7XX_USB_ISO 3
98#define INT_7XX_ICR 4
99#define INT_7XX_EAC 5
100#define INT_7XX_GPIO_BANK1 6
101#define INT_7XX_GPIO_BANK2 7
102#define INT_7XX_GPIO_BANK3 8
103#define INT_7XX_McBSP2TX 10
104#define INT_7XX_McBSP2RX 11
105#define INT_7XX_McBSP2RX_OVF 12
106#define INT_7XX_LCD_LINE 14
107#define INT_7XX_GSM_PROTECT 15
108#define INT_7XX_TIMER3 16
109#define INT_7XX_GPIO_BANK5 17
110#define INT_7XX_GPIO_BANK6 18
111#define INT_7XX_SPGIO_WR 29
112
113/*
114 * IRQ numbers for interrupt handler 2
115 *
116 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
117 */
118#define IH2_BASE 32
119
120#define INT_KEYBOARD (1 + IH2_BASE)
121#define INT_uWireTX (2 + IH2_BASE)
122#define INT_uWireRX (3 + IH2_BASE)
123#define INT_I2C (4 + IH2_BASE)
124#define INT_MPUIO (5 + IH2_BASE)
125#define INT_USB_HHC_1 (6 + IH2_BASE)
126#define INT_McBSP3TX (10 + IH2_BASE)
127#define INT_McBSP3RX (11 + IH2_BASE)
128#define INT_McBSP1TX (12 + IH2_BASE)
129#define INT_McBSP1RX (13 + IH2_BASE)
130#define INT_UART1 (14 + IH2_BASE)
131#define INT_UART2 (15 + IH2_BASE)
132#define INT_BT_MCSI1TX (16 + IH2_BASE)
133#define INT_BT_MCSI1RX (17 + IH2_BASE)
134#define INT_SOSSI_MATCH (19 + IH2_BASE)
135#define INT_USB_W2FC (20 + IH2_BASE)
136#define INT_1WIRE (21 + IH2_BASE)
137#define INT_OS_TIMER (22 + IH2_BASE)
138#define INT_MMC (23 + IH2_BASE)
139#define INT_GAUGE_32K (24 + IH2_BASE)
140#define INT_RTC_TIMER (25 + IH2_BASE)
141#define INT_RTC_ALARM (26 + IH2_BASE)
142#define INT_MEM_STICK (27 + IH2_BASE)
143
144/*
145 * OMAP-1510 specific IRQ numbers for interrupt handler 2
146 */
147#define INT_1510_DSP_MMU (28 + IH2_BASE)
148#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
149
150/*
151 * OMAP-1610 specific IRQ numbers for interrupt handler 2
152 */
153#define INT_1610_FAC (0 + IH2_BASE)
154#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
155#define INT_1610_USB_OTG (8 + IH2_BASE)
156#define INT_1610_SoSSI (9 + IH2_BASE)
157#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
158#define INT_1610_DSP_MMU (28 + IH2_BASE)
159#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
160#define INT_1610_STI (32 + IH2_BASE)
161#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
162#define INT_1610_GPTIMER3 (34 + IH2_BASE)
163#define INT_1610_GPTIMER4 (35 + IH2_BASE)
164#define INT_1610_GPTIMER5 (36 + IH2_BASE)
165#define INT_1610_GPTIMER6 (37 + IH2_BASE)
166#define INT_1610_GPTIMER7 (38 + IH2_BASE)
167#define INT_1610_GPTIMER8 (39 + IH2_BASE)
168#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
169#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
170#define INT_1610_MMC2 (42 + IH2_BASE)
171#define INT_1610_CF (43 + IH2_BASE)
172#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
173#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
174#define INT_1610_SPI (49 + IH2_BASE)
175#define INT_1610_DMA_CH6 (53 + IH2_BASE)
176#define INT_1610_DMA_CH7 (54 + IH2_BASE)
177#define INT_1610_DMA_CH8 (55 + IH2_BASE)
178#define INT_1610_DMA_CH9 (56 + IH2_BASE)
179#define INT_1610_DMA_CH10 (57 + IH2_BASE)
180#define INT_1610_DMA_CH11 (58 + IH2_BASE)
181#define INT_1610_DMA_CH12 (59 + IH2_BASE)
182#define INT_1610_DMA_CH13 (60 + IH2_BASE)
183#define INT_1610_DMA_CH14 (61 + IH2_BASE)
184#define INT_1610_DMA_CH15 (62 + IH2_BASE)
185#define INT_1610_NAND (63 + IH2_BASE)
186#define INT_1610_SHA1MD5 (91 + IH2_BASE)
187
188/*
189 * OMAP-7xx specific IRQ numbers for interrupt handler 2
190 */
191#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
192#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
193#define INT_7XX_CFCD (2 + IH2_BASE)
194#define INT_7XX_CFIREQ (3 + IH2_BASE)
195#define INT_7XX_I2C (4 + IH2_BASE)
196#define INT_7XX_PCC (5 + IH2_BASE)
197#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
198#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
199#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
200#define INT_7XX_VLYNQ (9 + IH2_BASE)
201#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
202#define INT_7XX_McBSP1TX (11 + IH2_BASE)
203#define INT_7XX_McBSP1RX (12 + IH2_BASE)
204#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
205#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
206#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
207#define INT_7XX_MCSI (16 + IH2_BASE)
208#define INT_7XX_uWireTX (17 + IH2_BASE)
209#define INT_7XX_uWireRX (18 + IH2_BASE)
210#define INT_7XX_SMC_CD (19 + IH2_BASE)
211#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
212#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
213#define INT_7XX_TIMER32K (22 + IH2_BASE)
214#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
215#define INT_7XX_UPLD (24 + IH2_BASE)
216#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
217#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
218#define INT_7XX_USB_GENI (29 + IH2_BASE)
219#define INT_7XX_USB_OTG (30 + IH2_BASE)
220#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
221#define INT_7XX_RNG (32 + IH2_BASE)
222#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
223#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
224#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
225#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
226#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
227#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
228#define INT_7XX_MPUIO (39 + IH2_BASE)
229#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
230#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
231#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
232#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
233#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
234#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
235#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
236#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
237#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
238#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
239#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
240#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
241#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
242#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
243#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
244#define INT_7XX_NAND (63 + IH2_BASE)
245
246#define INT_24XX_SYS_NIRQ 7
247#define INT_24XX_SDMA_IRQ0 12
248#define INT_24XX_SDMA_IRQ1 13
249#define INT_24XX_SDMA_IRQ2 14
250#define INT_24XX_SDMA_IRQ3 15
251#define INT_24XX_CAM_IRQ 24
252#define INT_24XX_DSS_IRQ 25
253#define INT_24XX_MAIL_U0_MPU 26
254#define INT_24XX_DSP_UMA 27
255#define INT_24XX_DSP_MMU 28
256#define INT_24XX_GPIO_BANK1 29
257#define INT_24XX_GPIO_BANK2 30
258#define INT_24XX_GPIO_BANK3 31
259#define INT_24XX_GPIO_BANK4 32
260#define INT_24XX_GPIO_BANK5 33
261#define INT_24XX_MAIL_U3_MPU 34
262#define INT_24XX_GPTIMER1 37
263#define INT_24XX_GPTIMER2 38
264#define INT_24XX_GPTIMER3 39
265#define INT_24XX_GPTIMER4 40
266#define INT_24XX_GPTIMER5 41
267#define INT_24XX_GPTIMER6 42
268#define INT_24XX_GPTIMER7 43
269#define INT_24XX_GPTIMER8 44
270#define INT_24XX_GPTIMER9 45
271#define INT_24XX_GPTIMER10 46
272#define INT_24XX_GPTIMER11 47
273#define INT_24XX_GPTIMER12 48
274#define INT_24XX_SHA1MD5 51
275#define INT_24XX_MCBSP4_IRQ_TX 54
276#define INT_24XX_MCBSP4_IRQ_RX 55
277#define INT_24XX_I2C1_IRQ 56
278#define INT_24XX_I2C2_IRQ 57
279#define INT_24XX_HDQ_IRQ 58
280#define INT_24XX_MCBSP1_IRQ_TX 59
281#define INT_24XX_MCBSP1_IRQ_RX 60
282#define INT_24XX_MCBSP2_IRQ_TX 62
283#define INT_24XX_MCBSP2_IRQ_RX 63
284#define INT_24XX_SPI1_IRQ 65
285#define INT_24XX_SPI2_IRQ 66
286#define INT_24XX_UART1_IRQ 72
287#define INT_24XX_UART2_IRQ 73
288#define INT_24XX_UART3_IRQ 74
289#define INT_24XX_USB_IRQ_GEN 75
290#define INT_24XX_USB_IRQ_NISO 76
291#define INT_24XX_USB_IRQ_ISO 77
292#define INT_24XX_USB_IRQ_HGEN 78
293#define INT_24XX_USB_IRQ_HSOF 79
294#define INT_24XX_USB_IRQ_OTG 80
295#define INT_24XX_MCBSP5_IRQ_TX 81
296#define INT_24XX_MCBSP5_IRQ_RX 82
297#define INT_24XX_MMC_IRQ 83
298#define INT_24XX_MMC2_IRQ 86
299#define INT_24XX_MCBSP3_IRQ_TX 89
300#define INT_24XX_MCBSP3_IRQ_RX 90
301#define INT_24XX_SPI3_IRQ 91
302
303#define INT_243X_MCBSP2_IRQ 16
304#define INT_243X_MCBSP3_IRQ 17
305#define INT_243X_MCBSP4_IRQ 18
306#define INT_243X_MCBSP5_IRQ 19
307#define INT_243X_MCBSP1_IRQ 64
308#define INT_243X_HS_USB_MC 92
309#define INT_243X_HS_USB_DMA 93
310#define INT_243X_CARKIT_IRQ 94
311
312#define INT_34XX_BENCH_MPU_EMUL 3
313#define INT_34XX_ST_MCBSP2_IRQ 4
314#define INT_34XX_ST_MCBSP3_IRQ 5
315#define INT_34XX_SSM_ABORT_IRQ 6
316#define INT_34XX_SYS_NIRQ 7
317#define INT_34XX_D2D_FW_IRQ 8
318#define INT_34XX_L3_DBG_IRQ 9
319#define INT_34XX_L3_APP_IRQ 10
320#define INT_34XX_PRCM_MPU_IRQ 11
321#define INT_34XX_MCBSP1_IRQ 16
322#define INT_34XX_MCBSP2_IRQ 17
323#define INT_34XX_GPMC_IRQ 20
324#define INT_34XX_MCBSP3_IRQ 22
325#define INT_34XX_MCBSP4_IRQ 23
326#define INT_34XX_CAM_IRQ 24
327#define INT_34XX_MCBSP5_IRQ 27
328#define INT_34XX_GPIO_BANK1 29
329#define INT_34XX_GPIO_BANK2 30
330#define INT_34XX_GPIO_BANK3 31
331#define INT_34XX_GPIO_BANK4 32
332#define INT_34XX_GPIO_BANK5 33
333#define INT_34XX_GPIO_BANK6 34
334#define INT_34XX_USIM_IRQ 35
335#define INT_34XX_WDT3_IRQ 36
336#define INT_34XX_SPI4_IRQ 48
337#define INT_34XX_SHA1MD52_IRQ 49
338#define INT_34XX_FPKA_READY_IRQ 50
339#define INT_34XX_SHA1MD51_IRQ 51
340#define INT_34XX_RNG_IRQ 52
341#define INT_34XX_I2C3_IRQ 61
342#define INT_34XX_FPKA_ERROR_IRQ 64
343#define INT_34XX_PBIAS_IRQ 75
344#define INT_34XX_OHCI_IRQ 76
345#define INT_34XX_EHCI_IRQ 77
346#define INT_34XX_TLL_IRQ 78
347#define INT_34XX_PARTHASH_IRQ 79
348#define INT_34XX_MMC3_IRQ 94
349#define INT_34XX_GPT12_IRQ 95
350
351#define INT_36XX_UART4_IRQ 80
352
353#define INT_35XX_HECC0_IRQ 24
354#define INT_35XX_HECC1_IRQ 28
355#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
356#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68
357#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
358#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
359#define INT_35XX_USBOTG_IRQ 71
360#define INT_35XX_UART4_IRQ 84
361#define INT_35XX_CCDC_VD0_IRQ 88
362#define INT_35XX_CCDC_VD1_IRQ 92
363#define INT_35XX_CCDC_VD2_IRQ 93
364
365/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
366 * 16 MPUIO lines */
367#define OMAP_MAX_GPIO_LINES 192
368#define IH_GPIO_BASE (128 + IH2_BASE)
369#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
370#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
371
372/* External FPGA handles interrupts on Innovator boards */
373#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
374#ifdef CONFIG_MACH_OMAP_INNOVATOR
375#define OMAP_FPGA_NR_IRQS 24
376#else
377#define OMAP_FPGA_NR_IRQS 0
378#endif
379#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
380
381/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
382#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
383#ifdef CONFIG_TWL4030_CORE
384#define TWL4030_BASE_NR_IRQS 8
385#define TWL4030_PWR_NR_IRQS 8
386#else
387#define TWL4030_BASE_NR_IRQS 0
388#define TWL4030_PWR_NR_IRQS 0
389#endif
390#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
391#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
392#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
393
394/* External TWL4030 gpio interrupts are optional */
395#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
396#ifdef CONFIG_GPIO_TWL4030
397#define TWL4030_GPIO_NR_IRQS 18
398#else
399#define TWL4030_GPIO_NR_IRQS 0
400#endif
401#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
402
403#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
404#ifdef CONFIG_TWL4030_CORE
405#define TWL6030_BASE_NR_IRQS 20
406#else
407#define TWL6030_BASE_NR_IRQS 0
408#endif
409#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
410
411#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
412#ifdef CONFIG_TWL6040_CODEC
413#define TWL6040_CODEC_NR_IRQS 6
414#else
415#define TWL6040_CODEC_NR_IRQS 0
416#endif
417#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
418
419/* Total number of interrupts depends on the enabled blocks above */
420#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
421#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
422#else
423#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
424#endif
425
426/* GPMC related */
427#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
428#define OMAP_GPMC_NR_IRQS 8
429#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
430
431/* PRCM IRQ handler */
432#ifdef CONFIG_ARCH_OMAP2PLUS
433#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
434#define OMAP_PRCM_NR_IRQS 64
435#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
436#else
437#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
438#endif
439
440#define NR_IRQS OMAP_PRCM_IRQ_END
441
442#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
443
444#define INTCPS_NR_MIR_REGS 3
445#define INTCPS_NR_IRQS 96
446
447#include <mach/hardware.h>
448
449#ifdef CONFIG_FIQ
450#define FIQ_START 1024
451#endif
452
453#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
deleted file mode 100644
index a6b21eddb212..000000000000
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/keypad.h
3 *
4 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_ARCH_KEYPAD_H
11#define ASMARM_ARCH_KEYPAD_H
12
13#ifndef CONFIG_ARCH_OMAP1
14#warning Please update the board to use matrix-keypad driver
15#define omap_readw(reg) 0
16#define omap_writew(val, reg) do {} while (0)
17#endif
18#include <linux/input/matrix_keypad.h>
19
20struct omap_kp_platform_data {
21 int rows;
22 int cols;
23 const struct matrix_keymap_data *keymap_data;
24 bool rep;
25 unsigned long delay;
26 bool dbounce;
27 /* specific to OMAP242x*/
28 unsigned int *row_gpios;
29 unsigned int *col_gpios;
30};
31
32/* Group (0..3) -- when multiple keys are pressed, only the
33 * keys pressed in the same group are considered as pressed. This is
34 * in order to workaround certain crappy HW designs that produce ghost
35 * keypresses. Two free bits, not used by neither row/col nor keynum,
36 * must be available for use as group bits. The below GROUP_SHIFT
37 * macro definition is based on some prior knowledge of the
38 * matrix_keypad defined KEY() macro internals.
39 */
40#define GROUP_SHIFT 14
41#define GROUP_0 (0 << GROUP_SHIFT)
42#define GROUP_1 (1 << GROUP_SHIFT)
43#define GROUP_2 (2 << GROUP_SHIFT)
44#define GROUP_3 (3 << GROUP_SHIFT)
45#define GROUP_MASK GROUP_3
46#if KEY_MAX & GROUP_MASK
47#error Group bits in conflict with keynum bits
48#endif
49
50
51#endif
52
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
deleted file mode 100644
index b8b5641379b0..000000000000
--- a/arch/arm/plat-omap/include/plat/l3_2xxx.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
15
16/* L3 CONNIDs */
17/* Display Sub system (DSS) */
18#define OMAP2_L3_CORE_FW_CONNID_DSS 8
19
20#endif
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
deleted file mode 100644
index cde1938c5f82..000000000000
--- a/arch/arm/plat-omap/include/plat/l3_3xxx.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
15
16/* L3 Initiator IDs */
17/* Display Sub system (DSS) */
18#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29
19
20#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
deleted file mode 100644
index 3f39cf8a35c6..000000000000
--- a/arch/arm/plat-omap/include/plat/l4_2xxx.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
15
16/* L4 CORE */
17/* Display Sub system (DSS) */
18#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
19#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
20#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
21#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
22#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
23
24#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
deleted file mode 100644
index 881a858b1ffc..000000000000
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
15
16/* L4 CORE */
17#define OMAP3_L4_CORE_FW_I2C1_REGION 21
18#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22
19#define OMAP3_L4_CORE_FW_I2C2_REGION 23
20#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24
21#define OMAP3_L4_CORE_FW_I2C3_REGION 73
22#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
23
24/* Display Sub system (DSS) */
25#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2
26
27#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104
28#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3
29#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4
30#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4
31#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5
32#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6
33#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7
34#endif
diff --git a/arch/arm/plat-omap/include/plat/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
deleted file mode 100644
index 8e52c6572281..000000000000
--- a/arch/arm/plat-omap/include/plat/lcd_mipid.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef __LCD_MIPID_H
2#define __LCD_MIPID_H
3
4enum mipid_test_num {
5 MIPID_TEST_RGB_LINES,
6};
7
8enum mipid_test_result {
9 MIPID_TEST_SUCCESS,
10 MIPID_TEST_INVALID,
11 MIPID_TEST_FAILED,
12};
13
14#ifdef __KERNEL__
15
16struct mipid_platform_data {
17 int nreset_gpio;
18 int data_lines;
19
20 void (*shutdown)(struct mipid_platform_data *pdata);
21 void (*set_bklight_level)(struct mipid_platform_data *pdata,
22 int level);
23 int (*get_bklight_level)(struct mipid_platform_data *pdata);
24 int (*get_bklight_max)(struct mipid_platform_data *pdata);
25};
26
27#endif
28
29#endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
deleted file mode 100644
index 18814127809a..000000000000
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/mcbsp.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H
26
27#include <linux/spinlock.h>
28#include <linux/clk.h>
29
30#define MCBSP_CONFIG_TYPE2 0x2
31#define MCBSP_CONFIG_TYPE3 0x3
32#define MCBSP_CONFIG_TYPE4 0x4
33
34/* Platform specific configuration */
35struct omap_mcbsp_ops {
36 void (*request)(unsigned int);
37 void (*free)(unsigned int);
38};
39
40struct omap_mcbsp_platform_data {
41 struct omap_mcbsp_ops *ops;
42 u16 buffer_size;
43 u8 reg_size;
44 u8 reg_step;
45
46 /* McBSP platform and instance specific features */
47 bool has_wakeup; /* Wakeup capability */
48 bool has_ccr; /* Transceiver has configuration control registers */
49 int (*enable_st_clock)(unsigned int, bool);
50 int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
51 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
52};
53
54/**
55 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
56 * @sidetone: name of the sidetone device
57 */
58struct omap_mcbsp_dev_attr {
59 const char *sidetone;
60};
61
62#endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
deleted file mode 100644
index a357eb26bd25..000000000000
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifndef _OMAP2_MCSPI_H
2#define _OMAP2_MCSPI_H
3
4#define OMAP2_MCSPI_REV 0
5#define OMAP3_MCSPI_REV 1
6#define OMAP4_MCSPI_REV 2
7
8#define OMAP4_MCSPI_REG_OFFSET 0x100
9
10struct omap2_mcspi_platform_config {
11 unsigned short num_cs;
12 unsigned int regs_offset;
13};
14
15struct omap2_mcspi_dev_attr {
16 unsigned short num_chipselect;
17};
18
19struct omap2_mcspi_device_config {
20 unsigned turbo_mode:1;
21};
22
23#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index eb3e4d555343..8b4e4f2da2f5 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,6 @@
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/mmc/host.h> 16#include <linux/mmc/host.h>
17 17
18#include <plat/board.h>
19#include <plat/omap_hwmod.h> 18#include <plat/omap_hwmod.h>
20 19
21#define OMAP15XX_NR_MMC 1 20#define OMAP15XX_NR_MMC 1
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 045e320f1067..324d31b14852 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -108,4 +108,13 @@
108# endif 108# endif
109#endif 109#endif
110 110
111#ifdef CONFIG_SOC_AM33XX
112# ifdef OMAP_NAME
113# undef MULTI_OMAP2
114# define MULTI_OMAP2
115# else
116# define OMAP_NAME am33xx
117# endif
118#endif
119
111#endif /* __PLAT_OMAP_MULTI_H */ 120#endif /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
deleted file mode 100644
index 323948959200..000000000000
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ /dev/null
@@ -1,454 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
9 *
10 * Written by Tony Lindgren
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * NOTE: Please use the following naming style for new pin entries.
27 * For example, W8_1610_MMC2_DAT0, where:
28 * - W8 = ball
29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
30 * - MMC2_DAT0 = function
31 */
32
33#ifndef __ASM_ARCH_MUX_H
34#define __ASM_ARCH_MUX_H
35
36#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
37#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
38
39#ifdef CONFIG_OMAP_MUX_DEBUG
40#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mask_offset = mode_offset, \
43 .mask = mode,
44
45#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
46 .pull_reg = PULL_DWN_CTRL_##reg, \
47 .pull_bit = bit, \
48 .pull_val = status,
49
50#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status,
53
54#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \
57 .mask = mode,
58
59#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60 .pull_reg = OMAP7XX_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64#else
65
66#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
67 .mask_offset = mode_offset, \
68 .mask = mode,
69
70#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
71 .pull_bit = bit, \
72 .pull_val = status,
73
74#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
75 .pu_pd_val = status,
76
77#define MUX_REG_7XX(reg, mode_offset, mode) \
78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
79 .mask_offset = mode_offset, \
80 .mask = mode,
81
82#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
83 .pull_bit = bit, \
84 .pull_val = status,
85
86#endif /* CONFIG_OMAP_MUX_DEBUG */
87
88#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
89 pull_reg, pull_bit, pull_status, \
90 pu_pd_reg, pu_pd_status, debug_status) \
91{ \
92 .name = desc, \
93 .debug = debug_status, \
94 MUX_REG(mux_reg, mode_offset, mode) \
95 PULL_REG(pull_reg, pull_bit, pull_status) \
96 PU_PD_REG(pu_pd_reg, pu_pd_status) \
97},
98
99
100/*
101 * OMAP730/850 has a slightly different config for the pin mux.
102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
103 * not the FUNC_MUX_CTRL_x regs from hardware.h
104 * - for pull-up/down, only has one enable bit which is is in the same register
105 * as mux config
106 */
107#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
108 pull_bit, pull_status, debug_status)\
109{ \
110 .name = desc, \
111 .debug = debug_status, \
112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
114 PU_PD_REG(NA, 0) \
115},
116
117struct pin_config {
118 char *name;
119 const unsigned int mux_reg;
120 unsigned char debug;
121
122 const unsigned char mask_offset;
123 const unsigned char mask;
124
125 const char *pull_name;
126 const unsigned int pull_reg;
127 const unsigned char pull_val;
128 const unsigned char pull_bit;
129
130 const char *pu_pd_name;
131 const unsigned int pu_pd_reg;
132 const unsigned char pu_pd_val;
133
134#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
135 const char *mux_reg_name;
136#endif
137
138};
139
140enum omap7xx_index {
141 /* OMAP 730 keyboard */
142 E2_7XX_KBR0,
143 J7_7XX_KBR1,
144 E1_7XX_KBR2,
145 F3_7XX_KBR3,
146 D2_7XX_KBR4,
147 C2_7XX_KBC0,
148 D3_7XX_KBC1,
149 E4_7XX_KBC2,
150 F4_7XX_KBC3,
151 E3_7XX_KBC4,
152
153 /* USB */
154 AA17_7XX_USB_DM,
155 W16_7XX_USB_PU_EN,
156 W17_7XX_USB_VBUSI,
157 W18_7XX_USB_DMCK_OUT,
158 W19_7XX_USB_DCRST,
159
160 /* MMC */
161 MMC_7XX_CMD,
162 MMC_7XX_CLK,
163 MMC_7XX_DAT0,
164
165 /* I2C */
166 I2C_7XX_SCL,
167 I2C_7XX_SDA,
168
169 /* SPI */
170 SPI_7XX_1,
171 SPI_7XX_2,
172 SPI_7XX_3,
173 SPI_7XX_4,
174 SPI_7XX_5,
175 SPI_7XX_6,
176
177 /* UART */
178 UART_7XX_1,
179 UART_7XX_2,
180};
181
182enum omap1xxx_index {
183 /* UART1 (BT_UART_GATING)*/
184 UART1_TX = 0,
185 UART1_RTS,
186
187 /* UART2 (COM_UART_GATING)*/
188 UART2_TX,
189 UART2_RX,
190 UART2_CTS,
191 UART2_RTS,
192
193 /* UART3 (GIGA_UART_GATING) */
194 UART3_TX,
195 UART3_RX,
196 UART3_CTS,
197 UART3_RTS,
198 UART3_CLKREQ,
199 UART3_BCLK, /* 12MHz clock out */
200 Y15_1610_UART3_RTS,
201
202 /* PWT & PWL */
203 PWT,
204 PWL,
205
206 /* USB master generic */
207 R18_USB_VBUS,
208 R18_1510_USB_GPIO0,
209 W4_USB_PUEN,
210 W4_USB_CLKO,
211 W4_USB_HIGHZ,
212 W4_GPIO58,
213
214 /* USB1 master */
215 USB1_SUSP,
216 USB1_SEO,
217 W13_1610_USB1_SE0,
218 USB1_TXEN,
219 USB1_TXD,
220 USB1_VP,
221 USB1_VM,
222 USB1_RCV,
223 USB1_SPEED,
224 R13_1610_USB1_SPEED,
225 R13_1710_USB1_SE0,
226
227 /* USB2 master */
228 USB2_SUSP,
229 USB2_VP,
230 USB2_TXEN,
231 USB2_VM,
232 USB2_RCV,
233 USB2_SEO,
234 USB2_TXD,
235
236 /* OMAP-1510 GPIO */
237 R18_1510_GPIO0,
238 R19_1510_GPIO1,
239 M14_1510_GPIO2,
240
241 /* OMAP1610 GPIO */
242 P18_1610_GPIO3,
243 Y15_1610_GPIO17,
244
245 /* OMAP-1710 GPIO */
246 R18_1710_GPIO0,
247 V2_1710_GPIO10,
248 N21_1710_GPIO14,
249 W15_1710_GPIO40,
250
251 /* MPUIO */
252 MPUIO2,
253 N15_1610_MPUIO2,
254 MPUIO4,
255 MPUIO5,
256 T20_1610_MPUIO5,
257 W11_1610_MPUIO6,
258 V10_1610_MPUIO7,
259 W11_1610_MPUIO9,
260 V10_1610_MPUIO10,
261 W10_1610_MPUIO11,
262 E20_1610_MPUIO13,
263 U20_1610_MPUIO14,
264 E19_1610_MPUIO15,
265
266 /* MCBSP2 */
267 MCBSP2_CLKR,
268 MCBSP2_CLKX,
269 MCBSP2_DR,
270 MCBSP2_DX,
271 MCBSP2_FSR,
272 MCBSP2_FSX,
273
274 /* MCBSP3 */
275 MCBSP3_CLKX,
276
277 /* Misc ballouts */
278 BALLOUT_V8_ARMIO3,
279 N20_HDQ,
280
281 /* OMAP-1610 MMC2 */
282 W8_1610_MMC2_DAT0,
283 V8_1610_MMC2_DAT1,
284 W15_1610_MMC2_DAT2,
285 R10_1610_MMC2_DAT3,
286 Y10_1610_MMC2_CLK,
287 Y8_1610_MMC2_CMD,
288 V9_1610_MMC2_CMDDIR,
289 V5_1610_MMC2_DATDIR0,
290 W19_1610_MMC2_DATDIR1,
291 R18_1610_MMC2_CLKIN,
292
293 /* OMAP-1610 External Trace Interface */
294 M19_1610_ETM_PSTAT0,
295 L15_1610_ETM_PSTAT1,
296 L18_1610_ETM_PSTAT2,
297 L19_1610_ETM_D0,
298 J19_1610_ETM_D6,
299 J18_1610_ETM_D7,
300
301 /* OMAP16XX GPIO */
302 P20_1610_GPIO4,
303 V9_1610_GPIO7,
304 W8_1610_GPIO9,
305 N20_1610_GPIO11,
306 N19_1610_GPIO13,
307 P10_1610_GPIO22,
308 V5_1610_GPIO24,
309 AA20_1610_GPIO_41,
310 W19_1610_GPIO48,
311 M7_1610_GPIO62,
312 V14_16XX_GPIO37,
313 R9_16XX_GPIO18,
314 L14_16XX_GPIO49,
315
316 /* OMAP-1610 uWire */
317 V19_1610_UWIRE_SCLK,
318 U18_1610_UWIRE_SDI,
319 W21_1610_UWIRE_SDO,
320 N14_1610_UWIRE_CS0,
321 P15_1610_UWIRE_CS3,
322 N15_1610_UWIRE_CS1,
323
324 /* OMAP-1610 SPI */
325 U19_1610_SPIF_SCK,
326 U18_1610_SPIF_DIN,
327 P20_1610_SPIF_DIN,
328 W21_1610_SPIF_DOUT,
329 R18_1610_SPIF_DOUT,
330 N14_1610_SPIF_CS0,
331 N15_1610_SPIF_CS1,
332 T19_1610_SPIF_CS2,
333 P15_1610_SPIF_CS3,
334
335 /* OMAP-1610 Flash */
336 L3_1610_FLASH_CS2B_OE,
337 M8_1610_FLASH_CS2B_WE,
338
339 /* First MMC */
340 MMC_CMD,
341 MMC_DAT1,
342 MMC_DAT2,
343 MMC_DAT0,
344 MMC_CLK,
345 MMC_DAT3,
346
347 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
348 M15_1710_MMC_CLKI,
349 P19_1710_MMC_CMDDIR,
350 P20_1710_MMC_DATDIR0,
351
352 /* OMAP-1610 USB0 alternate pin configuration */
353 W9_USB0_TXEN,
354 AA9_USB0_VP,
355 Y5_USB0_RCV,
356 R9_USB0_VM,
357 V6_USB0_TXD,
358 W5_USB0_SE0,
359 V9_USB0_SPEED,
360 V9_USB0_SUSP,
361
362 /* USB2 */
363 W9_USB2_TXEN,
364 AA9_USB2_VP,
365 Y5_USB2_RCV,
366 R9_USB2_VM,
367 V6_USB2_TXD,
368 W5_USB2_SE0,
369
370 /* 16XX UART */
371 R13_1610_UART1_TX,
372 V14_16XX_UART1_RX,
373 R14_1610_UART1_CTS,
374 AA15_1610_UART1_RTS,
375 R9_16XX_UART2_RX,
376 L14_16XX_UART3_RX,
377
378 /* I2C OMAP-1610 */
379 I2C_SCL,
380 I2C_SDA,
381
382 /* Keypad */
383 F18_1610_KBC0,
384 D20_1610_KBC1,
385 D19_1610_KBC2,
386 E18_1610_KBC3,
387 C21_1610_KBC4,
388 G18_1610_KBR0,
389 F19_1610_KBR1,
390 H14_1610_KBR2,
391 E20_1610_KBR3,
392 E19_1610_KBR4,
393 N19_1610_KBR5,
394
395 /* Power management */
396 T20_1610_LOW_PWR,
397
398 /* MCLK Settings */
399 V5_1710_MCLK_ON,
400 V5_1710_MCLK_OFF,
401 R10_1610_MCLK_ON,
402 R10_1610_MCLK_OFF,
403
404 /* CompactFlash controller */
405 P11_1610_CF_CD2,
406 R11_1610_CF_IOIS16,
407 V10_1610_CF_IREQ,
408 W10_1610_CF_RESET,
409 W11_1610_CF_CD1,
410
411 /* parallel camera */
412 J15_1610_CAM_LCLK,
413 J18_1610_CAM_D7,
414 J19_1610_CAM_D6,
415 J14_1610_CAM_D5,
416 K18_1610_CAM_D4,
417 K19_1610_CAM_D3,
418 K15_1610_CAM_D2,
419 K14_1610_CAM_D1,
420 L19_1610_CAM_D0,
421 L18_1610_CAM_VS,
422 L15_1610_CAM_HS,
423 M19_1610_CAM_RSTZ,
424 Y15_1610_CAM_OUTCLK,
425
426 /* serial camera */
427 H19_1610_CAM_EXCLK,
428 Y12_1610_CCP_CLKP,
429 W13_1610_CCP_CLKM,
430 W14_1610_CCP_DATAP,
431 Y14_1610_CCP_DATAM,
432
433};
434
435struct omap_mux_cfg {
436 struct pin_config *pins;
437 unsigned long size;
438 int (*cfg_reg)(const struct pin_config *cfg);
439};
440
441#ifdef CONFIG_OMAP_MUX
442/* setup pin muxing in Linux */
443extern int omap1_mux_init(void);
444extern int omap_mux_register(struct omap_mux_cfg *);
445extern int omap_cfg_reg(unsigned long reg_cfg);
446#else
447/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
448static inline int omap1_mux_init(void) { return 0; }
449static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
450#endif
451
452extern int omap2_mux_init(void);
453
454#endif
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
deleted file mode 100644
index 67fc5060183e..000000000000
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/nand.h
3 *
4 * Copyright (C) 2006 Micron Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <plat/gpmc.h>
12#include <linux/mtd/partitions.h>
13
14enum nand_io {
15 NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
16 NAND_OMAP_POLLED, /* polled mode, without prefetch */
17 NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
18 NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
19};
20
21struct omap_nand_platform_data {
22 int cs;
23 struct mtd_partition *parts;
24 struct gpmc_timings *gpmc_t;
25 int nr_parts;
26 bool dev_ready;
27 int gpmc_irq;
28 enum nand_io xfer_type;
29 unsigned long phys_base;
30 int devsize;
31 enum omap_ecc ecc_opt;
32};
33
34/* minimum size for IO mapping */
35#define NAND_IO_SIZE 4
36
37#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
38extern int gpmc_nand_init(struct omap_nand_platform_data *d);
39#else
40static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
41{
42 return 0;
43}
44#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725ffcf2..f4a4cd014795 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -18,11 +18,9 @@
18#define __OMAP_SERIAL_H__ 18#define __OMAP_SERIAL_H__
19 19
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/device.h>
22#include <linux/pm_qos.h> 22#include <linux/pm_qos.h>
23 23
24#include <plat/mux.h>
25
26#define DRIVER_NAME "omap_uart" 24#define DRIVER_NAME "omap_uart"
27 25
28/* 26/*
@@ -42,10 +40,10 @@
42#define OMAP_UART_WER_MOD_WKUP 0X7F 40#define OMAP_UART_WER_MOD_WKUP 0X7F
43 41
44/* Enable XON/XOFF flow control on output */ 42/* Enable XON/XOFF flow control on output */
45#define OMAP_UART_SW_TX 0x04 43#define OMAP_UART_SW_TX 0x8
46 44
47/* Enable XON/XOFF flow control on input */ 45/* Enable XON/XOFF flow control on input */
48#define OMAP_UART_SW_RX 0x04 46#define OMAP_UART_SW_RX 0x2
49 47
50#define OMAP_UART_SYSC_RESET 0X07 48#define OMAP_UART_SYSC_RESET 0X07
51#define OMAP_UART_TCR_TRIG 0X0F 49#define OMAP_UART_TCR_TRIG 0X0F
@@ -54,7 +52,7 @@
54 52
55#define OMAP_UART_DMA_CH_FREE -1 53#define OMAP_UART_DMA_CH_FREE -1
56 54
57#define OMAP_MAX_HSUART_PORTS 4 55#define OMAP_MAX_HSUART_PORTS 6
58 56
59#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 57#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
60 58
@@ -69,11 +67,14 @@ struct omap_uart_port_info {
69 unsigned int dma_rx_timeout; 67 unsigned int dma_rx_timeout;
70 unsigned int autosuspend_timeout; 68 unsigned int autosuspend_timeout;
71 unsigned int dma_rx_poll_rate; 69 unsigned int dma_rx_poll_rate;
70 int DTR_gpio;
71 int DTR_inverted;
72 int DTR_present;
72 73
73 int (*get_context_loss_count)(struct device *); 74 int (*get_context_loss_count)(struct device *);
74 void (*set_forceidle)(struct platform_device *); 75 void (*set_forceidle)(struct device *);
75 void (*set_noidle)(struct platform_device *); 76 void (*set_noidle)(struct device *);
76 void (*enable_wakeup)(struct platform_device *, bool); 77 void (*enable_wakeup)(struct device *, bool);
77}; 78};
78 79
79struct uart_omap_dma { 80struct uart_omap_dma {
@@ -102,39 +103,4 @@ struct uart_omap_dma {
102 unsigned int rx_timeout; 103 unsigned int rx_timeout;
103}; 104};
104 105
105struct uart_omap_port {
106 struct uart_port port;
107 struct uart_omap_dma uart_dma;
108 struct platform_device *pdev;
109
110 unsigned char ier;
111 unsigned char lcr;
112 unsigned char mcr;
113 unsigned char fcr;
114 unsigned char efr;
115 unsigned char dll;
116 unsigned char dlh;
117 unsigned char mdr1;
118 unsigned char scr;
119
120 int use_dma;
121 /*
122 * Some bits in registers are cleared on a read, so they must
123 * be saved whenever the register is read but the bits will not
124 * be immediately processed.
125 */
126 unsigned int lsr_break_flag;
127 unsigned char msr_saved_flags;
128 char name[20];
129 unsigned long port_activity;
130 u32 context_loss_cnt;
131 u32 errata;
132 u8 wakeups_enabled;
133
134 struct pm_qos_request pm_qos_request;
135 u32 latency;
136 u32 calc_latency;
137 struct work_struct qos_work;
138};
139
140#endif /* __OMAP_SERIAL_H__ */ 106#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
deleted file mode 100644
index d24004668138..000000000000
--- a/arch/arm/plat-omap/include/plat/omap1510.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap1510.h
2 *
3 * Hardware definitions for TI OMAP1510 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_H
29#define __ASM_ARCH_OMAP15XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP1510_DSP_BASE 0xE0000000
40#define OMAP1510_DSP_SIZE 0x28000
41#define OMAP1510_DSP_START 0xE0000000
42
43#define OMAP1510_DSPREG_BASE 0xE1000000
44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000
46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
49#endif /* __ASM_ARCH_OMAP15XX_H */
50
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
deleted file mode 100644
index e69e1d857b45..000000000000
--- a/arch/arm/plat-omap/include/plat/omap16xx.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap16xx.h
2 *
3 * Hardware definitions for TI OMAP1610/5912/1710 processors.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP16XX_H
29#define __ASM_ARCH_OMAP16XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP16XX_DSP_BASE 0xE0000000
40#define OMAP16XX_DSP_SIZE 0x28000
41#define OMAP16XX_DSP_START 0xE0000000
42
43#define OMAP16XX_DSPREG_BASE 0xE1000000
44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000
46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
52/*
53 * ---------------------------------------------------------------------------
54 * Interrupts
55 * ---------------------------------------------------------------------------
56 */
57#define OMAP_IH2_0_BASE (0xfffe0000)
58#define OMAP_IH2_1_BASE (0xfffe0100)
59#define OMAP_IH2_2_BASE (0xfffe0200)
60#define OMAP_IH2_3_BASE (0xfffe0300)
61
62#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
63#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
64#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
65#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
66#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
67#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
68#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
69
70#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
71#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
72#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
73#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
74#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
75#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
76#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
77
78#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
79#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
80#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
81#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
82#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
83#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
84#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
85
86#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
87#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
88#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
89#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
90#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
91#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
92#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
93
94/*
95 * ----------------------------------------------------------------------------
96 * Clocks
97 * ----------------------------------------------------------------------------
98 */
99#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
100
101/*
102 * ----------------------------------------------------------------------------
103 * Pin configuration registers
104 * ----------------------------------------------------------------------------
105 */
106#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
107#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
108#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
109#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
110#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
111
112/*
113 * ----------------------------------------------------------------------------
114 * System control registers
115 * ----------------------------------------------------------------------------
116 */
117#define OMAP1610_RESET_CONTROL 0xfffe1140
118
119/*
120 * ---------------------------------------------------------------------------
121 * TIPB bus interface
122 * ---------------------------------------------------------------------------
123 */
124#define TIPB_SWITCH_BASE (0xfffbc800)
125#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
126
127/* UART3 Registers Mapping through MPU bus */
128#define UART3_RHR (OMAP1_UART3_BASE + 0)
129#define UART3_THR (OMAP1_UART3_BASE + 0)
130#define UART3_DLL (OMAP1_UART3_BASE + 0)
131#define UART3_IER (OMAP1_UART3_BASE + 4)
132#define UART3_DLH (OMAP1_UART3_BASE + 4)
133#define UART3_IIR (OMAP1_UART3_BASE + 8)
134#define UART3_FCR (OMAP1_UART3_BASE + 8)
135#define UART3_EFR (OMAP1_UART3_BASE + 8)
136#define UART3_LCR (OMAP1_UART3_BASE + 0x0C)
137#define UART3_MCR (OMAP1_UART3_BASE + 0x10)
138#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10)
139#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14)
140#define UART3_LSR (OMAP1_UART3_BASE + 0x14)
141#define UART3_TCR (OMAP1_UART3_BASE + 0x18)
142#define UART3_MSR (OMAP1_UART3_BASE + 0x18)
143#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18)
144#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C)
145#define UART3_SPR (OMAP1_UART3_BASE + 0x1C)
146#define UART3_TLR (OMAP1_UART3_BASE + 0x1C)
147#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20)
148#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24)
149#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28)
150#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28)
151#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C)
152#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C)
153#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30)
154#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30)
155#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34)
156#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34)
157#define UART3_BLR (OMAP1_UART3_BASE + 0x38)
158#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C)
159#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C)
160#define UART3_SCR (OMAP1_UART3_BASE + 0x40)
161#define UART3_SSR (OMAP1_UART3_BASE + 0x44)
162#define UART3_EBLR (OMAP1_UART3_BASE + 0x48)
163#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C)
164#define UART3_MVR (OMAP1_UART3_BASE + 0x50)
165
166/*
167 * ---------------------------------------------------------------------------
168 * Watchdog timer
169 * ---------------------------------------------------------------------------
170 */
171
172/* 32-bit Watchdog timer in OMAP 16XX */
173#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
174#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
175#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
176#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
177#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
178#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
179#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
180#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
181#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
182#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
183
184#define WCLR_PRE_SHIFT 5
185#define WCLR_PTV_SHIFT 2
186
187#define WWPS_W_PEND_WSPR (1 << 4)
188#define WWPS_W_PEND_WTGR (1 << 3)
189#define WWPS_W_PEND_WLDR (1 << 2)
190#define WWPS_W_PEND_WCRR (1 << 1)
191#define WWPS_W_PEND_WCLR (1 << 0)
192
193#define WSPR_ENABLE_0 (0x0000bbbb)
194#define WSPR_ENABLE_1 (0x00004444)
195#define WSPR_DISABLE_0 (0x0000aaaa)
196#define WSPR_DISABLE_1 (0x00005555)
197
198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
200
201#endif /* __ASM_ARCH_OMAP16XX_H */
202
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
deleted file mode 100644
index 92df9e27cc5c..000000000000
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap24xx.h
3 *
4 * This file contains the processor specific definitions
5 * of the TI OMAP24XX.
6 *
7 * Copyright (C) 2007 Texas Instruments.
8 * Copyright (C) 2007 Nokia Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP2_H
27#define __ASM_ARCH_OMAP2_H
28
29/*
30 * Please place only base defines here and put the rest in device
31 * specific headers. Note also that some of these defines are needed
32 * for omap1 to compile without adding ifdefs.
33 */
34
35#define L4_24XX_BASE 0x48000000
36#define L4_WK_243X_BASE 0x49000000
37#define L3_24XX_BASE 0x68000000
38
39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42
43#define OMAP242X_CTRL_BASE L4_24XX_BASE
44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
47#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
48#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
49#define OMAP2420_SMS_BASE 0x68008000
50#define OMAP2420_GPMC_BASE 0x6800a000
51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
54#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
55#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
56
57#define OMAP243X_SMS_BASE 0x6C000000
58#define OMAP243X_SDRC_BASE 0x6D000000
59#define OMAP243X_GPMC_BASE 0x6E000000
60#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
61#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
62#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
63
64/* DSP SS */
65#define OMAP2420_DSP_BASE 0x58000000
66#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
67#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
68#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
69
70#define OMAP243X_DSP_BASE 0x5C000000
71#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
72#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
73
74/* Mailbox */
75#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
76
77/* Camera */
78#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
79
80/* Security */
81#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
82#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
83#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
84#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87
88#endif /* __ASM_ARCH_OMAP2_H */
89
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
deleted file mode 100644
index 0d818acf3917..000000000000
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP3_H
25#define __ASM_ARCH_OMAP3_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_PER_34XX_BASE 0x49000000
35#define L4_EMU_34XX_BASE 0x54000000
36#define L3_34XX_BASE 0x68000000
37
38#define L4_WK_AM33XX_BASE 0x44C00000
39
40#define OMAP3430_32KSYNCT_BASE 0x48320000
41#define OMAP3430_CM_BASE 0x48004800
42#define OMAP3430_PRM_BASE 0x48306800
43#define OMAP343X_SMS_BASE 0x6C000000
44#define OMAP343X_SDRC_BASE 0x6D000000
45#define OMAP34XX_GPMC_BASE 0x6E000000
46#define OMAP343X_SCM_BASE 0x48002000
47#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
48
49#define OMAP34XX_IC_BASE 0x48200000
50
51#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
52#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
53#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
54#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
55#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
56#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
57#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
58#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
59#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
60#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
61#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800)
62#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970)
63#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0)
64#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00)
65#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70)
66#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0)
67
68#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
69#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
70#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
71#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
72#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
73#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
74#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
75#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
76#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
77#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
78#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
79#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
80#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
81#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
82#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
83#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
84
85#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
86#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
87#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
88#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
89#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
90#define OMAP34XX_SR1_BASE 0x480C9000
91#define OMAP34XX_SR2_BASE 0x480CB000
92
93#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
94
95/* Security */
96#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000)
97#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000)
98#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000)
99
100#endif /* __ASM_ARCH_OMAP3_H */
101
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
deleted file mode 100644
index 8ad0a377a54b..000000000000
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
3
4extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
5 struct omap_board_data *);
6#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
deleted file mode 100644
index c0d478e55c84..000000000000
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*:
2 * Address mappings and base address for OMAP4 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_ARCH_OMAP44XX_H
14#define __ASM_ARCH_OMAP44XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_44XX_BASE 0x4a000000
21#define L4_WK_44XX_BASE 0x4a300000
22#define L4_PER_44XX_BASE 0x48000000
23#define L4_EMU_44XX_BASE 0x54000000
24#define L3_44XX_BASE 0x44000000
25#define OMAP44XX_EMIF1_BASE 0x4c000000
26#define OMAP44XX_EMIF2_BASE 0x4d000000
27#define OMAP44XX_DMM_BASE 0x4e000000
28#define OMAP4430_32KSYNCT_BASE 0x4a304000
29#define OMAP4430_CM1_BASE 0x4a004000
30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
31#define OMAP4430_CM2_BASE 0x4a008000
32#define OMAP4430_PRM_BASE 0x4a306000
33#define OMAP4430_PRCM_MPU_BASE 0x48243000
34#define OMAP44XX_GPMC_BASE 0x50000000
35#define OMAP443X_SCM_BASE 0x4a002000
36#define OMAP443X_CTRL_BASE 0x4a100000
37#define OMAP44XX_IC_BASE 0x48200000
38#define OMAP44XX_IVA_INTC_BASE 0x40000000
39#define IRQ_SIR_IRQ 0x0040
40#define OMAP44XX_GIC_DIST_BASE 0x48241000
41#define OMAP44XX_GIC_CPU_BASE 0x48240100
42#define OMAP44XX_SCU_BASE 0x48240000
43#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
44#define OMAP44XX_L2CACHE_BASE 0x48242000
45#define OMAP44XX_WKUPGEN_BASE 0x48281000
46#define OMAP44XX_MCPDM_BASE 0x40132000
47#define OMAP44XX_MCPDM_L3_BASE 0x49032000
48#define OMAP44XX_SAR_RAM_BASE 0x4a326000
49
50#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
51#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
52
53#define OMAP4_MMU1_BASE 0x55082000
54#define OMAP4_MMU2_BASE 0x4A066000
55
56#define OMAP44XX_USBTLL_BASE (L4_44XX_BASE + 0x62000)
57#define OMAP44XX_UHH_CONFIG_BASE (L4_44XX_BASE + 0x64000)
58#define OMAP44XX_HSUSB_OHCI_BASE (L4_44XX_BASE + 0x64800)
59#define OMAP44XX_HSUSB_EHCI_BASE (L4_44XX_BASE + 0x64C00)
60
61#endif /* __ASM_ARCH_OMAP44XX_H */
62
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
deleted file mode 100644
index a2582bb3cab3..000000000000
--- a/arch/arm/plat-omap/include/plat/omap54xx.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*:
2 * Address mappings and base address for OMAP5 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2012 Texas Instruments
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_SOC_OMAP54XX_H
14#define __ASM_SOC_OMAP54XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_54XX_BASE 0x4a000000
21#define L4_WK_54XX_BASE 0x4ae00000
22#define L4_PER_54XX_BASE 0x48000000
23#define L3_54XX_BASE 0x44000000
24#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
25#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
26#define OMAP54XX_CM_CORE_BASE 0x4a008000
27#define OMAP54XX_PRM_BASE 0x4ae06000
28#define OMAP54XX_PRCM_MPU_BASE 0x48243000
29#define OMAP54XX_SCM_BASE 0x4a002000
30#define OMAP54XX_CTRL_BASE 0x4a002800
31
32#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
deleted file mode 100644
index 48e4757e1e30..000000000000
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap7xx.h
2 *
3 * Hardware definitions for TI OMAP7XX processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_OMAP7XX_H
31#define __ASM_ARCH_OMAP7XX_H
32
33/*
34 * ----------------------------------------------------------------------------
35 * Base addresses
36 * ----------------------------------------------------------------------------
37 */
38
39/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
40
41#define OMAP7XX_DSP_BASE 0xE0000000
42#define OMAP7XX_DSP_SIZE 0x50000
43#define OMAP7XX_DSP_START 0xE0000000
44
45#define OMAP7XX_DSPREG_BASE 0xE1000000
46#define OMAP7XX_DSPREG_SIZE SZ_128K
47#define OMAP7XX_DSPREG_START 0xE1000000
48
49#define OMAP7XX_SPI1_BASE 0xfffc0800
50#define OMAP7XX_SPI2_BASE 0xfffc1000
51
52/*
53 * ----------------------------------------------------------------------------
54 * OMAP7XX specific configuration registers
55 * ----------------------------------------------------------------------------
56 */
57#define OMAP7XX_CONFIG_BASE 0xfffe1000
58#define OMAP7XX_IO_CONF_0 0xfffe1070
59#define OMAP7XX_IO_CONF_1 0xfffe1074
60#define OMAP7XX_IO_CONF_2 0xfffe1078
61#define OMAP7XX_IO_CONF_3 0xfffe107c
62#define OMAP7XX_IO_CONF_4 0xfffe1080
63#define OMAP7XX_IO_CONF_5 0xfffe1084
64#define OMAP7XX_IO_CONF_6 0xfffe1088
65#define OMAP7XX_IO_CONF_7 0xfffe108c
66#define OMAP7XX_IO_CONF_8 0xfffe1090
67#define OMAP7XX_IO_CONF_9 0xfffe1094
68#define OMAP7XX_IO_CONF_10 0xfffe1098
69#define OMAP7XX_IO_CONF_11 0xfffe109c
70#define OMAP7XX_IO_CONF_12 0xfffe10a0
71#define OMAP7XX_IO_CONF_13 0xfffe10a4
72
73#define OMAP7XX_MODE_1 0xfffe1010
74#define OMAP7XX_MODE_2 0xfffe1014
75
76/* CSMI specials: in terms of base + offset */
77#define OMAP7XX_MODE2_OFFSET 0x14
78
79/*
80 * ----------------------------------------------------------------------------
81 * OMAP7XX traffic controller configuration registers
82 * ----------------------------------------------------------------------------
83 */
84#define OMAP7XX_FLASH_CFG_0 0xfffecc10
85#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
86#define OMAP7XX_FLASH_CFG_1 0xfffecc14
87#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
88
89/*
90 * ----------------------------------------------------------------------------
91 * OMAP7XX DSP control registers
92 * ----------------------------------------------------------------------------
93 */
94#define OMAP7XX_ICR_BASE 0xfffbb800
95#define OMAP7XX_DSP_M_CTL 0xfffbb804
96#define OMAP7XX_DSP_MMU_BASE 0xfffed200
97
98/*
99 * ----------------------------------------------------------------------------
100 * OMAP7XX PCC_UPLD configuration registers
101 * ----------------------------------------------------------------------------
102 */
103#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
104#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
105
106#endif /* __ASM_ARCH_OMAP7XX_H */
107
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 4327b2c90c3d..e7259c0d33ec 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
60 * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM 60 * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
61 * @_state: one of OMAP_DEVICE_STATE_* (see above) 61 * @_state: one of OMAP_DEVICE_STATE_* (see above)
62 * @flags: device flags 62 * @flags: device flags
63 * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
63 * 64 *
64 * Integrates omap_hwmod data into Linux platform_device. 65 * Integrates omap_hwmod data into Linux platform_device.
65 * 66 *
@@ -73,6 +74,7 @@ struct omap_device {
73 struct omap_device_pm_latency *pm_lats; 74 struct omap_device_pm_latency *pm_lats;
74 u32 dev_wakeup_lat; 75 u32 dev_wakeup_lat;
75 u32 _dev_wakeup_lat_limit; 76 u32 _dev_wakeup_lat_limit;
77 unsigned long _driver_status;
76 u8 pm_lats_cnt; 78 u8 pm_lats_cnt;
77 s8 pm_lat_level; 79 s8 pm_lat_level;
78 u8 hwmods_cnt; 80 u8 hwmods_cnt;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972aff37..05330735f23f 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
615 615
616int omap_hwmod_count_resources(struct omap_hwmod *oh); 616int omap_hwmod_count_resources(struct omap_hwmod *oh);
617int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); 617int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
618int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
618int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, 619int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
619 const char *name, struct resource *res); 620 const char *name, struct resource *res);
620 621
@@ -658,6 +659,7 @@ extern int omap2420_hwmod_init(void);
658extern int omap2430_hwmod_init(void); 659extern int omap2430_hwmod_init(void);
659extern int omap3xxx_hwmod_init(void); 660extern int omap3xxx_hwmod_init(void);
660extern int omap44xx_hwmod_init(void); 661extern int omap44xx_hwmod_init(void);
662extern int am33xx_hwmod_init(void);
661 663
662extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 664extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
663 665
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
deleted file mode 100644
index 2858667d2e4f..000000000000
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/onenand.h
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Author: Juha Yrjola
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14
15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1)
17
18struct onenand_freq_info {
19 u16 maf_id;
20 u16 dev_id;
21 u16 ver_id;
22};
23
24struct omap_onenand_platform_data {
25 int cs;
26 int gpio_irq;
27 struct mtd_partition *parts;
28 int nr_parts;
29 int (*onenand_setup)(void __iomem *, int *freq_ptr);
30 int (*get_freq)(const struct onenand_freq_info *freq_info,
31 bool *clk_dep);
32 int dma_channel;
33 u8 flags;
34 u8 regulator_can_sleep;
35 u8 skip_initial_unlocking;
36};
37
38#define ONENAND_MAX_PARTITIONS 8
39
40#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
41 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
42
43extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
44
45#else
46
47#define board_onenand_data NULL
48
49static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
50{
51}
52
53#endif
diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h
deleted file mode 100644
index 1eb4dc326979..000000000000
--- a/arch/arm/plat-omap/include/plat/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/param.h
3 *
4 */
5
6#ifdef CONFIG_OMAP_32K_TIMER_HZ
7#define HZ CONFIG_OMAP_32K_TIMER_HZ
8#endif
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
deleted file mode 100644
index b10eac89e2e9..000000000000
--- a/arch/arm/plat-omap/include/plat/remoteproc.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Remote Processor - omap-specific bits
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Copyright (C) 2011 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _PLAT_REMOTEPROC_H
18#define _PLAT_REMOTEPROC_H
19
20struct rproc_ops;
21struct platform_device;
22
23/*
24 * struct omap_rproc_pdata - omap remoteproc's platform data
25 * @name: the remoteproc's name
26 * @oh_name: omap hwmod device
27 * @oh_name_opt: optional, secondary omap hwmod device
28 * @firmware: name of firmware file to load
29 * @mbox_name: name of omap mailbox device to use with this rproc
30 * @ops: start/stop rproc handlers
31 * @device_enable: omap-specific handler for enabling a device
32 * @device_shutdown: omap-specific handler for shutting down a device
33 */
34struct omap_rproc_pdata {
35 const char *name;
36 const char *oh_name;
37 const char *oh_name_opt;
38 const char *firmware;
39 const char *mbox_name;
40 const struct rproc_ops *ops;
41 int (*device_enable) (struct platform_device *pdev);
42 int (*device_shutdown) (struct platform_device *pdev);
43};
44
45#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
46
47void __init omap_rproc_reserve_cma(void);
48
49#else
50
51void __init omap_rproc_reserve_cma(void)
52{
53}
54
55#endif
56
57#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/plat-omap/include/plat/ti81xx.h
deleted file mode 100644
index 8f9843f78422..000000000000
--- a/arch/arm/plat-omap/include/plat/ti81xx.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This file contains the address data for various TI81XX modules.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_TI81XX_H
17#define __ASM_ARCH_TI81XX_H
18
19#define L4_SLOW_TI81XX_BASE 0x48000000
20
21#define TI81XX_SCM_BASE 0x48140000
22#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
23#define TI81XX_PRCM_BASE 0x48180000
24
25#define TI81XX_ARM_INTC_BASE 0x48200000
26
27#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index b8d19a136781..7f7b112acccb 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -110,7 +110,7 @@ static inline void flush(void)
110 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ 110 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
111 AM33XXUART##p) 111 AM33XXUART##p)
112 112
113static inline void __arch_decomp_setup(unsigned long arch_id) 113static inline void arch_decomp_setup(void)
114{ 114{
115 int port = 0; 115 int port = 0;
116 116
@@ -198,8 +198,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
198 } while (0); 198 } while (0);
199} 199}
200 200
201#define arch_decomp_setup() __arch_decomp_setup(arch_id)
202
203/* 201/*
204 * nothing to do 202 * nothing to do
205 */ 203 */
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index e68d0998d55f..87ee140fefaa 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -6,7 +6,6 @@
6#include <linux/io.h> 6#include <linux/io.h>
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/usb/musb.h> 8#include <linux/usb/musb.h>
9#include <plat/board.h>
10 9
11#define OMAP3_HS_USB_PORTS 3 10#define OMAP3_HS_USB_PORTS 3
12 11
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
deleted file mode 100644
index 5be4d5def427..000000000000
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * OMAP Voltage Management Routines
3 *
4 * Copyright (C) 2011, Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
12#define __ARCH_ARM_OMAP_VOLTAGE_H
13
14/**
15 * struct omap_volt_data - Omap voltage specific data.
16 * @voltage_nominal: The possible voltage value in uV
17 * @sr_efuse_offs: The offset of the efuse register(from system
18 * control module base address) from where to read
19 * the n-target value for the smartreflex module.
20 * @sr_errminlimit: Error min limit value for smartreflex. This value
21 * differs at differnet opp and thus is linked
22 * with voltage.
23 * @vp_errorgain: Error gain value for the voltage processor. This
24 * field also differs according to the voltage/opp.
25 */
26struct omap_volt_data {
27 u32 volt_nominal;
28 u32 sr_efuse_offs;
29 u8 sr_errminlimit;
30 u8 vp_errgain;
31};
32struct voltagedomain;
33
34struct voltagedomain *voltdm_lookup(const char *name);
35int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
36unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
37struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
38 unsigned long volt);
39#endif
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 5e13c3884aa4..42377ef9ea3d 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -310,7 +310,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
310 omap_mbox_disable_irq(mbox, IRQ_RX); 310 omap_mbox_disable_irq(mbox, IRQ_RX);
311 free_irq(mbox->irq, mbox); 311 free_irq(mbox->irq, mbox);
312 tasklet_kill(&mbox->txq->tasklet); 312 tasklet_kill(&mbox->txq->tasklet);
313 flush_work_sync(&mbox->rxq->work); 313 flush_work(&mbox->rxq->work);
314 mbox_queue_free(mbox->txq); 314 mbox_queue_free(mbox->txq);
315 mbox_queue_free(mbox->rxq); 315 mbox_queue_free(mbox->rxq);
316 } 316 }
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
deleted file mode 100644
index cff8712122bb..000000000000
--- a/arch/arm/plat-omap/mux.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/mux.c
3 *
4 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
5 *
6 * Copyright (C) 2003 - 2008 Nokia Corporation
7 *
8 * Written by Tony Lindgren
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/io.h>
29#include <linux/spinlock.h>
30
31#include <asm/system.h>
32
33#include <plat/cpu.h>
34#include <plat/mux.h>
35
36#ifdef CONFIG_OMAP_MUX
37
38static struct omap_mux_cfg *mux_cfg;
39
40int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
41{
42 if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
43 || !arch_mux_cfg->cfg_reg) {
44 printk(KERN_ERR "Invalid pin table\n");
45 return -EINVAL;
46 }
47
48 mux_cfg = arch_mux_cfg;
49
50 return 0;
51}
52
53/*
54 * Sets the Omap MUX and PULL_DWN registers based on the table
55 */
56int __init_or_module omap_cfg_reg(const unsigned long index)
57{
58 struct pin_config *reg;
59
60 if (!cpu_class_is_omap1()) {
61 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
62 index);
63 WARN_ON(1);
64 return -EINVAL;
65 }
66
67 if (mux_cfg == NULL) {
68 printk(KERN_ERR "Pin mux table not initialized\n");
69 return -ENODEV;
70 }
71
72 if (index >= mux_cfg->size) {
73 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
74 index, mux_cfg->size);
75 dump_stack();
76 return -ENODEV;
77 }
78
79 reg = (struct pin_config *)&mux_cfg->pins[index];
80
81 if (!mux_cfg->cfg_reg)
82 return -ENODEV;
83
84 return mux_cfg->cfg_reg(reg);
85}
86EXPORT_SYMBOL(omap_cfg_reg);
87#else
88#define omap_mux_init() do {} while(0)
89#define omap_cfg_reg(x) do {} while(0)
90#endif /* CONFIG_OMAP_MUX */
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 5a97b4d98d41..9f6413324df9 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -41,11 +41,11 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
41 }; 41 };
42 42
43 if (t == -1) 43 if (t == -1)
44 pr_debug("OMAP PM: remove max MPU wakeup latency constraint: " 44 pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
45 "dev %s\n", dev_name(dev)); 45 dev_name(dev));
46 else 46 else
47 pr_debug("OMAP PM: add max MPU wakeup latency constraint: " 47 pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
48 "dev %s, t = %ld usec\n", dev_name(dev), t); 48 dev_name(dev), t);
49 49
50 /* 50 /*
51 * For current Linux, this needs to map the MPU to a 51 * For current Linux, this needs to map the MPU to a
@@ -70,11 +70,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
70 }; 70 };
71 71
72 if (r == 0) 72 if (r == 0)
73 pr_debug("OMAP PM: remove min bus tput constraint: " 73 pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
74 "dev %s for agent_id %d\n", dev_name(dev), agent_id); 74 dev_name(dev), agent_id);
75 else 75 else
76 pr_debug("OMAP PM: add min bus tput constraint: " 76 pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
77 "dev %s for agent_id %d: rate %ld KiB\n",
78 dev_name(dev), agent_id, r); 77 dev_name(dev), agent_id, r);
79 78
80 /* 79 /*
@@ -97,11 +96,11 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
97 }; 96 };
98 97
99 if (t == -1) 98 if (t == -1)
100 pr_debug("OMAP PM: remove max device latency constraint: " 99 pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
101 "dev %s\n", dev_name(dev)); 100 dev_name(dev));
102 else 101 else
103 pr_debug("OMAP PM: add max device latency constraint: " 102 pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
104 "dev %s, t = %ld usec\n", dev_name(dev), t); 103 dev_name(dev), t);
105 104
106 /* 105 /*
107 * For current Linux, this needs to map the device to a 106 * For current Linux, this needs to map the device to a
@@ -127,11 +126,11 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t)
127 }; 126 };
128 127
129 if (t == -1) 128 if (t == -1)
130 pr_debug("OMAP PM: remove max DMA latency constraint: " 129 pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
131 "dev %s\n", dev_name(dev)); 130 dev_name(dev));
132 else 131 else
133 pr_debug("OMAP PM: add max DMA latency constraint: " 132 pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
134 "dev %s, t = %ld usec\n", dev_name(dev), t); 133 dev_name(dev), t);
135 134
136 /* 135 /*
137 * For current Linux PM QOS params, this code should scan the 136 * For current Linux PM QOS params, this code should scan the
@@ -156,11 +155,11 @@ int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
156 } 155 }
157 156
158 if (r == 0) 157 if (r == 0)
159 pr_debug("OMAP PM: remove min clk rate constraint: " 158 pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
160 "dev %s\n", dev_name(dev)); 159 dev_name(dev));
161 else 160 else
162 pr_debug("OMAP PM: add min clk rate constraint: " 161 pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
163 "dev %s, rate = %ld Hz\n", dev_name(dev), r); 162 dev_name(dev), r);
164 163
165 /* 164 /*
166 * Code in a real implementation should keep track of these 165 * Code in a real implementation should keep track of these
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240bb82c..d5f617c542d3 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,4 +1,3 @@
1
2/* 1/*
3 * omap_device implementation 2 * omap_device implementation
4 * 3 *
@@ -153,21 +152,19 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
153 act_lat = timespec_to_ns(&c); 152 act_lat = timespec_to_ns(&c);
154 153
155 dev_dbg(&od->pdev->dev, 154 dev_dbg(&od->pdev->dev,
156 "omap_device: pm_lat %d: activate: elapsed time " 155 "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
157 "%llu nsec\n", od->pm_lat_level, act_lat); 156 od->pm_lat_level, act_lat);
158 157
159 if (act_lat > odpl->activate_lat) { 158 if (act_lat > odpl->activate_lat) {
160 odpl->activate_lat_worst = act_lat; 159 odpl->activate_lat_worst = act_lat;
161 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { 160 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
162 odpl->activate_lat = act_lat; 161 odpl->activate_lat = act_lat;
163 dev_dbg(&od->pdev->dev, 162 dev_dbg(&od->pdev->dev,
164 "new worst case activate latency " 163 "new worst case activate latency %d: %llu\n",
165 "%d: %llu\n",
166 od->pm_lat_level, act_lat); 164 od->pm_lat_level, act_lat);
167 } else 165 } else
168 dev_warn(&od->pdev->dev, 166 dev_warn(&od->pdev->dev,
169 "activate latency %d " 167 "activate latency %d higher than expected. (%llu > %d)\n",
170 "higher than exptected. (%llu > %d)\n",
171 od->pm_lat_level, act_lat, 168 od->pm_lat_level, act_lat,
172 odpl->activate_lat); 169 odpl->activate_lat);
173 } 170 }
@@ -220,21 +217,19 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
220 deact_lat = timespec_to_ns(&c); 217 deact_lat = timespec_to_ns(&c);
221 218
222 dev_dbg(&od->pdev->dev, 219 dev_dbg(&od->pdev->dev,
223 "omap_device: pm_lat %d: deactivate: elapsed time " 220 "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
224 "%llu nsec\n", od->pm_lat_level, deact_lat); 221 od->pm_lat_level, deact_lat);
225 222
226 if (deact_lat > odpl->deactivate_lat) { 223 if (deact_lat > odpl->deactivate_lat) {
227 odpl->deactivate_lat_worst = deact_lat; 224 odpl->deactivate_lat_worst = deact_lat;
228 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { 225 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
229 odpl->deactivate_lat = deact_lat; 226 odpl->deactivate_lat = deact_lat;
230 dev_dbg(&od->pdev->dev, 227 dev_dbg(&od->pdev->dev,
231 "new worst case deactivate latency " 228 "new worst case deactivate latency %d: %llu\n",
232 "%d: %llu\n",
233 od->pm_lat_level, deact_lat); 229 od->pm_lat_level, deact_lat);
234 } else 230 } else
235 dev_warn(&od->pdev->dev, 231 dev_warn(&od->pdev->dev,
236 "deactivate latency %d " 232 "deactivate latency %d higher than expected. (%llu > %d)\n",
237 "higher than exptected. (%llu > %d)\n",
238 od->pm_lat_level, deact_lat, 233 od->pm_lat_level, deact_lat,
239 odpl->deactivate_lat); 234 odpl->deactivate_lat);
240 } 235 }
@@ -370,6 +365,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
370 goto odbfd_exit1; 365 goto odbfd_exit1;
371 } 366 }
372 367
368 /* Fix up missing resource names */
369 for (i = 0; i < pdev->num_resources; i++) {
370 struct resource *r = &pdev->resource[i];
371
372 if (r->name == NULL)
373 r->name = dev_name(&pdev->dev);
374 }
375
373 if (of_get_property(node, "ti,no_idle_on_suspend", NULL)) 376 if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
374 omap_device_disable_idle_on_suspend(pdev); 377 omap_device_disable_idle_on_suspend(pdev);
375 378
@@ -385,17 +388,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
385 unsigned long event, void *dev) 388 unsigned long event, void *dev)
386{ 389{
387 struct platform_device *pdev = to_platform_device(dev); 390 struct platform_device *pdev = to_platform_device(dev);
391 struct omap_device *od;
388 392
389 switch (event) { 393 switch (event) {
390 case BUS_NOTIFY_ADD_DEVICE:
391 if (pdev->dev.of_node)
392 omap_device_build_from_dt(pdev);
393 break;
394
395 case BUS_NOTIFY_DEL_DEVICE: 394 case BUS_NOTIFY_DEL_DEVICE:
396 if (pdev->archdata.od) 395 if (pdev->archdata.od)
397 omap_device_delete(pdev->archdata.od); 396 omap_device_delete(pdev->archdata.od);
398 break; 397 break;
398 case BUS_NOTIFY_ADD_DEVICE:
399 if (pdev->dev.of_node)
400 omap_device_build_from_dt(pdev);
401 /* fall through */
402 default:
403 od = to_omap_device(pdev);
404 if (od)
405 od->_driver_status = event;
399 } 406 }
400 407
401 return NOTIFY_DONE; 408 return NOTIFY_DONE;
@@ -449,8 +456,8 @@ static int omap_device_count_resources(struct omap_device *od)
449 for (i = 0; i < od->hwmods_cnt; i++) 456 for (i = 0; i < od->hwmods_cnt; i++)
450 c += omap_hwmod_count_resources(od->hwmods[i]); 457 c += omap_hwmod_count_resources(od->hwmods[i]);
451 458
452 pr_debug("omap_device: %s: counted %d total resources across %d " 459 pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
453 "hwmods\n", od->pdev->name, c, od->hwmods_cnt); 460 od->pdev->name, c, od->hwmods_cnt);
454 461
455 return c; 462 return c;
456} 463}
@@ -486,6 +493,33 @@ static int omap_device_fill_resources(struct omap_device *od,
486} 493}
487 494
488/** 495/**
496 * _od_fill_dma_resources - fill in array of struct resource with dma resources
497 * @od: struct omap_device *
498 * @res: pointer to an array of struct resource to be filled in
499 *
500 * Populate one or more empty struct resource pointed to by @res with
501 * the dma resource data for this omap_device @od. Used by
502 * omap_device_alloc() after calling omap_device_count_resources().
503 *
504 * Ideally this function would not be needed at all. If we have
505 * mechanism to get dma resources from DT.
506 *
507 * Returns 0.
508 */
509static int _od_fill_dma_resources(struct omap_device *od,
510 struct resource *res)
511{
512 int i, r;
513
514 for (i = 0; i < od->hwmods_cnt; i++) {
515 r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
516 res += r;
517 }
518
519 return 0;
520}
521
522/**
489 * omap_device_alloc - allocate an omap_device 523 * omap_device_alloc - allocate an omap_device
490 * @pdev: platform_device that will be included in this omap_device 524 * @pdev: platform_device that will be included in this omap_device
491 * @oh: ptr to the single omap_hwmod that backs this omap_device 525 * @oh: ptr to the single omap_hwmod that backs this omap_device
@@ -524,24 +558,44 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
524 od->hwmods = hwmods; 558 od->hwmods = hwmods;
525 od->pdev = pdev; 559 od->pdev = pdev;
526 560
561 res_count = omap_device_count_resources(od);
527 /* 562 /*
528 * HACK: Ideally the resources from DT should match, and hwmod 563 * DT Boot:
529 * should just add the missing ones. Since the name is not 564 * OF framework will construct the resource structure (currently
530 * properly populated by DT, stick to hwmod resources only. 565 * does for MEM & IRQ resource) and we should respect/use these
566 * resources, killing hwmod dependency.
567 * If pdev->num_resources > 0, we assume that MEM & IRQ resources
568 * have been allocated by OF layer already (through DTB).
569 *
570 * Non-DT Boot:
571 * Here, pdev->num_resources = 0, and we should get all the
572 * resources from hwmod.
573 *
574 * TODO: Once DMA resource is available from OF layer, we should
575 * kill filling any resources from hwmod.
531 */ 576 */
532 if (pdev->num_resources && pdev->resource) 577 if (res_count > pdev->num_resources) {
533 dev_warn(&pdev->dev, "%s(): resources already allocated %d\n", 578 /* Allocate resources memory to account for new resources */
534 __func__, pdev->num_resources);
535
536 res_count = omap_device_count_resources(od);
537 if (res_count > 0) {
538 dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
539 __func__, res_count);
540 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); 579 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
541 if (!res) 580 if (!res)
542 goto oda_exit3; 581 goto oda_exit3;
543 582
544 omap_device_fill_resources(od, res); 583 /*
584 * If pdev->num_resources > 0, then assume that,
585 * MEM and IRQ resources will only come from DT and only
586 * fill DMA resource from hwmod layer.
587 */
588 if (pdev->num_resources && pdev->resource) {
589 dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
590 __func__, res_count);
591 memcpy(res, pdev->resource,
592 sizeof(struct resource) * pdev->num_resources);
593 _od_fill_dma_resources(od, &res[pdev->num_resources]);
594 } else {
595 dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
596 __func__, res_count);
597 omap_device_fill_resources(od, res);
598 }
545 599
546 ret = platform_device_add_resources(pdev, res, res_count); 600 ret = platform_device_add_resources(pdev, res, res_count);
547 kfree(res); 601 kfree(res);
@@ -752,6 +806,10 @@ static int _od_suspend_noirq(struct device *dev)
752 struct omap_device *od = to_omap_device(pdev); 806 struct omap_device *od = to_omap_device(pdev);
753 int ret; 807 int ret;
754 808
809 /* Don't attempt late suspend on a driver that is not bound */
810 if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
811 return 0;
812
755 ret = pm_generic_suspend_noirq(dev); 813 ret = pm_generic_suspend_noirq(dev);
756 814
757 if (!ret && !pm_runtime_status_suspended(dev)) { 815 if (!ret && !pm_runtime_status_suspended(dev)) {
@@ -1125,3 +1183,41 @@ static int __init omap_device_init(void)
1125 return 0; 1183 return 0;
1126} 1184}
1127core_initcall(omap_device_init); 1185core_initcall(omap_device_init);
1186
1187/**
1188 * omap_device_late_idle - idle devices without drivers
1189 * @dev: struct device * associated with omap_device
1190 * @data: unused
1191 *
1192 * Check the driver bound status of this device, and idle it
1193 * if there is no driver attached.
1194 */
1195static int __init omap_device_late_idle(struct device *dev, void *data)
1196{
1197 struct platform_device *pdev = to_platform_device(dev);
1198 struct omap_device *od = to_omap_device(pdev);
1199
1200 if (!od)
1201 return 0;
1202
1203 /*
1204 * If omap_device state is enabled, but has no driver bound,
1205 * idle it.
1206 */
1207 if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
1208 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
1209 dev_warn(dev, "%s: enabled but no driver. Idling\n",
1210 __func__);
1211 omap_device_idle(pdev);
1212 }
1213 }
1214
1215 return 0;
1216}
1217
1218static int __init omap_device_late_init(void)
1219{
1220 bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
1221 return 0;
1222}
1223late_initcall(omap_device_late_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 766181cb5c95..28acb383e7df 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -26,7 +26,6 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28#include <plat/sram.h> 28#include <plat/sram.h>
29#include <plat/board.h>
30#include <plat/cpu.h> 29#include <plat/cpu.h>
31 30
32#include "sram.h" 31#include "sram.h"
@@ -68,6 +67,7 @@
68 67
69static unsigned long omap_sram_start; 68static unsigned long omap_sram_start;
70static void __iomem *omap_sram_base; 69static void __iomem *omap_sram_base;
70static unsigned long omap_sram_skip;
71static unsigned long omap_sram_size; 71static unsigned long omap_sram_size;
72static void __iomem *omap_sram_ceil; 72static void __iomem *omap_sram_ceil;
73 73
@@ -106,6 +106,7 @@ static int is_sram_locked(void)
106 */ 106 */
107static void __init omap_detect_sram(void) 107static void __init omap_detect_sram(void)
108{ 108{
109 omap_sram_skip = SRAM_BOOTLOADER_SZ;
109 if (cpu_class_is_omap2()) { 110 if (cpu_class_is_omap2()) {
110 if (is_sram_locked()) { 111 if (is_sram_locked()) {
111 if (cpu_is_omap34xx()) { 112 if (cpu_is_omap34xx()) {
@@ -113,6 +114,7 @@ static void __init omap_detect_sram(void)
113 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || 114 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
114 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { 115 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
115 omap_sram_size = 0x7000; /* 28K */ 116 omap_sram_size = 0x7000; /* 28K */
117 omap_sram_skip += SZ_16K;
116 } else { 118 } else {
117 omap_sram_size = 0x8000; /* 32K */ 119 omap_sram_size = 0x8000; /* 32K */
118 } 120 }
@@ -175,8 +177,10 @@ static void __init omap_map_sram(void)
175 return; 177 return;
176 178
177#ifdef CONFIG_OMAP4_ERRATA_I688 179#ifdef CONFIG_OMAP4_ERRATA_I688
180 if (cpu_is_omap44xx()) {
178 omap_sram_start += PAGE_SIZE; 181 omap_sram_start += PAGE_SIZE;
179 omap_sram_size -= SZ_16K; 182 omap_sram_size -= SZ_16K;
183 }
180#endif 184#endif
181 if (cpu_is_omap34xx()) { 185 if (cpu_is_omap34xx()) {
182 /* 186 /*
@@ -203,8 +207,8 @@ static void __init omap_map_sram(void)
203 * Looks like we need to preserve some bootloader code at the 207 * Looks like we need to preserve some bootloader code at the
204 * beginning of SRAM for jumping to flash for reboot to work... 208 * beginning of SRAM for jumping to flash for reboot to work...
205 */ 209 */
206 memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0, 210 memset_io(omap_sram_base + omap_sram_skip, 0,
207 omap_sram_size - SRAM_BOOTLOADER_SZ); 211 omap_sram_size - omap_sram_skip);
208} 212}
209 213
210/* 214/*
@@ -218,7 +222,7 @@ void *omap_sram_push_address(unsigned long size)
218{ 222{
219 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil; 223 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
220 224
221 available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ); 225 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
222 226
223 if (size > available) { 227 if (size > available) {
224 pr_err("Not enough space in SRAM\n"); 228 pr_err("Not enough space in SRAM\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 00:41:01 -0500