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-rw-r--r--arch/arm/plat-mxc/epit.c11
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h4
-rw-r--r--arch/arm/plat-mxc/time.c24
3 files changed, 24 insertions, 15 deletions
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index 9129c9e7d532..88726f4dbbfa 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -50,6 +50,7 @@
50#include <linux/irq.h> 50#include <linux/irq.h>
51#include <linux/clockchips.h> 51#include <linux/clockchips.h>
52#include <linux/clk.h> 52#include <linux/clk.h>
53#include <linux/err.h>
53 54
54#include <mach/hardware.h> 55#include <mach/hardware.h>
55#include <asm/mach/time.h> 56#include <asm/mach/time.h>
@@ -201,8 +202,16 @@ static int __init epit_clockevent_init(struct clk *timer_clk)
201 return 0; 202 return 0;
202} 203}
203 204
204void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) 205void __init epit_timer_init(void __iomem *base, int irq)
205{ 206{
207 struct clk *timer_clk;
208
209 timer_clk = clk_get_sys("imx-epit.0", NULL);
210 if (IS_ERR(timer_clk)) {
211 pr_err("i.MX epit: unable to get clk\n");
212 return;
213 }
214
206 clk_prepare_enable(timer_clk); 215 clk_prepare_enable(timer_clk);
207 216
208 timer_base = base; 217 timer_base = base;
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index cf663d84e7c1..e429ca1b814a 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -54,8 +54,8 @@ extern void imx50_soc_init(void);
54extern void imx51_soc_init(void); 54extern void imx51_soc_init(void);
55extern void imx53_soc_init(void); 55extern void imx53_soc_init(void);
56extern void imx51_init_late(void); 56extern void imx51_init_late(void);
57extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 57extern void epit_timer_init(void __iomem *base, int irq);
58extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 58extern void mxc_timer_init(void __iomem *, int);
59extern int mx1_clocks_init(unsigned long fref); 59extern int mx1_clocks_init(unsigned long fref);
60extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 60extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
61extern int mx25_clocks_init(void); 61extern int mx25_clocks_init(void);
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 99f958ca6cb8..00e8e659e667 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -58,6 +58,7 @@
58/* MX31, MX35, MX25, MX5 */ 58/* MX31, MX35, MX25, MX5 */
59#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 59#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
60#define V2_TCTL_CLK_IPG (1 << 6) 60#define V2_TCTL_CLK_IPG (1 << 6)
61#define V2_TCTL_CLK_PER (2 << 6)
61#define V2_TCTL_FRR (1 << 9) 62#define V2_TCTL_FRR (1 << 9)
62#define V2_IR 0x0c 63#define V2_IR 0x0c
63#define V2_TSTAT 0x08 64#define V2_TSTAT 0x08
@@ -280,23 +281,22 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
280 return 0; 281 return 0;
281} 282}
282 283
283void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) 284void __init mxc_timer_init(void __iomem *base, int irq)
284{ 285{
285 uint32_t tctl_val; 286 uint32_t tctl_val;
287 struct clk *timer_clk;
286 struct clk *timer_ipg_clk; 288 struct clk *timer_ipg_clk;
287 289
288 if (!timer_clk) { 290 timer_clk = clk_get_sys("imx-gpt.0", "per");
289 timer_clk = clk_get_sys("imx-gpt.0", "per"); 291 if (IS_ERR(timer_clk)) {
290 if (IS_ERR(timer_clk)) { 292 pr_err("i.MX timer: unable to get clk\n");
291 pr_err("i.MX timer: unable to get clk\n"); 293 return;
292 return;
293 }
294
295 timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
296 if (!IS_ERR(timer_ipg_clk))
297 clk_prepare_enable(timer_ipg_clk);
298 } 294 }
299 295
296 timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
297 if (!IS_ERR(timer_ipg_clk))
298 clk_prepare_enable(timer_ipg_clk);
299
300 clk_prepare_enable(timer_clk); 300 clk_prepare_enable(timer_clk);
301 301
302 timer_base = base; 302 timer_base = base;
@@ -309,7 +309,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
309 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 309 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
310 310
311 if (timer_is_v2()) 311 if (timer_is_v2())
312 tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 312 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
313 else 313 else
314 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 314 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
315 315