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-rw-r--r--arch/arm/plat-mxc/Kconfig39
-rw-r--r--arch/arm/plat-mxc/avic.c91
-rw-r--r--arch/arm/plat-mxc/cpu.c9
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig3
-rw-r--r--arch/arm/plat-mxc/devices/Makefile1
-rw-r--r--arch/arm/plat-mxc/devices/platform-pata_imx.c59
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S58
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h16
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h18
-rw-r--r--arch/arm/plat-mxc/irq-common.c21
-rw-r--r--arch/arm/plat-mxc/irq-common.h3
-rw-r--r--arch/arm/plat-mxc/pwm.c2
-rw-r--r--arch/arm/plat-mxc/tzic.c32
18 files changed, 227 insertions, 156 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index a5353fc0793f..502e45f03178 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,50 +4,31 @@ source "arch/arm/plat-mxc/devices/Kconfig"
4 4
5menu "Freescale MXC Implementations" 5menu "Freescale MXC Implementations"
6 6
7config ARCH_MX50_SUPPORTED
8 bool
9
10config ARCH_MX53_SUPPORTED
11 bool
12
13choice 7choice
14 prompt "Freescale CPU family:" 8 prompt "Freescale CPU family:"
15 default ARCH_MX3 9 default ARCH_MX3
16 10
17config ARCH_MX1 11config ARCH_IMX_V4_V5
18 bool "MX1-based" 12 bool "i.MX1, i.MX21, i.MX25, i.MX27"
19 help 13 select AUTO_ZRELADDR
20 This enables support for systems based on the Freescale i.MX1 family 14 select ARM_PATCH_PHYS_VIRT
21
22config ARCH_MX2
23 bool "MX2-based"
24 help
25 This enables support for systems based on the Freescale i.MX2 family
26
27config ARCH_MX25
28 bool "MX25-based"
29 help 15 help
30 This enables support for systems based on the Freescale i.MX25 family 16 This enables support for systems based on the Freescale i.MX ARMv4
17 and ARMv5 SoCs
31 18
32config ARCH_MX3 19config ARCH_MX3
33 bool "MX3-based" 20 bool "MX3-based"
34 help 21 help
35 This enables support for systems based on the Freescale i.MX3 family 22 This enables support for systems based on the Freescale i.MX3 family
36 23
37config ARCH_MX503 24config ARCH_MX5
38 bool "i.MX50 + i.MX53" 25 bool "i.MX50, i.MX51, i.MX53"
39 select ARCH_MX50_SUPPORTED 26 select AUTO_ZRELADDR
40 select ARCH_MX53_SUPPORTED 27 select ARM_PATCH_PHYS_VIRT
41 help 28 help
42 This enables support for machines using Freescale's i.MX50 and i.MX51 29 This enables support for machines using Freescale's i.MX50 and i.MX51
43 processors. 30 processors.
44 31
45config ARCH_MX51
46 bool "i.MX51"
47 select ARCH_MX51_SUPPORTED
48 help
49 This enables support for systems based on the Freescale i.MX51 family
50
51endchoice 32endchoice
52 33
53source "arch/arm/mach-imx/Kconfig" 34source "arch/arm/mach-imx/Kconfig"
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55d2534ec727..8875fb415f68 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -50,6 +50,8 @@
50 50
51void __iomem *avic_base; 51void __iomem *avic_base;
52 52
53static u32 avic_saved_mask_reg[2];
54
53#ifdef CONFIG_MXC_IRQ_PRIOR 55#ifdef CONFIG_MXC_IRQ_PRIOR
54static int avic_irq_set_priority(unsigned char irq, unsigned char prio) 56static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
55{ 57{
@@ -90,24 +92,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
90} 92}
91#endif /* CONFIG_FIQ */ 93#endif /* CONFIG_FIQ */
92 94
93/* Disable interrupt number "irq" in the AVIC */
94static void mxc_mask_irq(struct irq_data *d)
95{
96 __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
97}
98 95
99/* Enable interrupt number "irq" in the AVIC */ 96static struct mxc_extra_irq avic_extra_irq = {
100static void mxc_unmask_irq(struct irq_data *d)
101{
102 __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
103}
104
105static struct mxc_irq_chip mxc_avic_chip = {
106 .base = {
107 .irq_ack = mxc_mask_irq,
108 .irq_mask = mxc_mask_irq,
109 .irq_unmask = mxc_unmask_irq,
110 },
111#ifdef CONFIG_MXC_IRQ_PRIOR 97#ifdef CONFIG_MXC_IRQ_PRIOR
112 .set_priority = avic_irq_set_priority, 98 .set_priority = avic_irq_set_priority,
113#endif 99#endif
@@ -116,6 +102,68 @@ static struct mxc_irq_chip mxc_avic_chip = {
116#endif 102#endif
117}; 103};
118 104
105#ifdef CONFIG_PM
106static void avic_irq_suspend(struct irq_data *d)
107{
108 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
109 struct irq_chip_type *ct = gc->chip_types;
110 int idx = gc->irq_base >> 5;
111
112 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
113 __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
114}
115
116static void avic_irq_resume(struct irq_data *d)
117{
118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
119 struct irq_chip_type *ct = gc->chip_types;
120 int idx = gc->irq_base >> 5;
121
122 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
123}
124
125#else
126#define avic_irq_suspend NULL
127#define avic_irq_resume NULL
128#endif
129
130static __init void avic_init_gc(unsigned int irq_start)
131{
132 struct irq_chip_generic *gc;
133 struct irq_chip_type *ct;
134 int idx = irq_start >> 5;
135
136 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
137 handle_level_irq);
138 gc->private = &avic_extra_irq;
139 gc->wake_enabled = IRQ_MSK(32);
140
141 ct = gc->chip_types;
142 ct->chip.irq_mask = irq_gc_mask_clr_bit;
143 ct->chip.irq_unmask = irq_gc_mask_set_bit;
144 ct->chip.irq_ack = irq_gc_mask_clr_bit;
145 ct->chip.irq_set_wake = irq_gc_set_wake;
146 ct->chip.irq_suspend = avic_irq_suspend;
147 ct->chip.irq_resume = avic_irq_resume;
148 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
149 ct->regs.ack = ct->regs.mask;
150
151 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
152}
153
154asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
155{
156 u32 nivector;
157
158 do {
159 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
160 if (nivector == 0xffff)
161 break;
162
163 handle_IRQ(nivector, regs);
164 } while (1);
165}
166
119/* 167/*
120 * This function initializes the AVIC hardware and disables all the 168 * This function initializes the AVIC hardware and disables all the
121 * interrupts. It registers the interrupt enable and disable functions 169 * interrupts. It registers the interrupt enable and disable functions
@@ -140,11 +188,9 @@ void __init mxc_init_irq(void __iomem *irqbase)
140 /* all IRQ no FIQ */ 188 /* all IRQ no FIQ */
141 __raw_writel(0, avic_base + AVIC_INTTYPEH); 189 __raw_writel(0, avic_base + AVIC_INTTYPEH);
142 __raw_writel(0, avic_base + AVIC_INTTYPEL); 190 __raw_writel(0, avic_base + AVIC_INTTYPEL);
143 for (i = 0; i < AVIC_NUM_IRQS; i++) { 191
144 irq_set_chip_and_handler(i, &mxc_avic_chip.base, 192 for (i = 0; i < AVIC_NUM_IRQS; i += 32)
145 handle_level_irq); 193 avic_init_gc(i);
146 set_irq_flags(i, IRQF_VALID);
147 }
148 194
149 /* Set default priority value (0) for all IRQ's */ 195 /* Set default priority value (0) for all IRQ's */
150 for (i = 0; i < 8; i++) 196 for (i = 0; i < 8; i++)
@@ -157,4 +203,3 @@ void __init mxc_init_irq(void __iomem *irqbase)
157 203
158 printk(KERN_INFO "MXC IRQ initialized\n"); 204 printk(KERN_INFO "MXC IRQ initialized\n");
159} 205}
160
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index 386e0d52cf58..f5b7e0fa237f 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -1,5 +1,6 @@
1 1
2#include <linux/module.h> 2#include <linux/module.h>
3#include <mach/hardware.h>
3 4
4unsigned int __mxc_cpu_type; 5unsigned int __mxc_cpu_type;
5EXPORT_SYMBOL(__mxc_cpu_type); 6EXPORT_SYMBOL(__mxc_cpu_type);
@@ -9,3 +10,11 @@ void mxc_set_cpu_type(unsigned int type)
9 __mxc_cpu_type = type; 10 __mxc_cpu_type = type;
10} 11}
11 12
13void imx_print_silicon_rev(const char *cpu, int srev)
14{
15 if (srev == IMX_CHIP_REVISION_UNKNOWN)
16 pr_info("CPU identified as %s, unknown revision\n", cpu);
17 else
18 pr_info("CPU identified as %s, silicon rev %d.%d\n",
19 cpu, (srev >> 4) & 0xf, srev & 0xf);
20}
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 39b08957e8ad..b0f74f70b25c 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -31,6 +31,9 @@ config IMX_HAVE_PLATFORM_IMX_I2C
31config IMX_HAVE_PLATFORM_IMX_KEYPAD 31config IMX_HAVE_PLATFORM_IMX_KEYPAD
32 bool 32 bool
33 33
34config IMX_HAVE_PLATFORM_PATA_IMX
35 bool
36
34config IMX_HAVE_PLATFORM_IMX_SSI 37config IMX_HAVE_PLATFORM_IMX_SSI
35 bool 38 bool
36 39
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index b41bf972b54b..a093b454541d 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -10,6 +10,7 @@ obj-y += platform-imx-dma.o
10obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o 10obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
11obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o 11obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o 12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
13obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o 14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o 15obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
15obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o 16obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
diff --git a/arch/arm/plat-mxc/devices/platform-pata_imx.c b/arch/arm/plat-mxc/devices/platform-pata_imx.c
new file mode 100644
index 000000000000..70e2f2a44714
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-pata_imx.c
@@ -0,0 +1,59 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it under
3 * the terms of the GNU General Public License version 2 as published by the
4 * Free Software Foundation.
5 */
6#include <mach/hardware.h>
7#include <mach/devices-common.h>
8
9#define imx_pata_imx_data_entry_single(soc, _size) \
10 { \
11 .iobase = soc ## _ATA_BASE_ADDR, \
12 .iosize = _size, \
13 .irq = soc ## _INT_ATA, \
14 }
15
16#ifdef CONFIG_SOC_IMX27
17const struct imx_pata_imx_data imx27_pata_imx_data __initconst =
18 imx_pata_imx_data_entry_single(MX27, SZ_4K);
19#endif /* ifdef CONFIG_SOC_IMX27 */
20
21#ifdef CONFIG_SOC_IMX31
22const struct imx_pata_imx_data imx31_pata_imx_data __initconst =
23 imx_pata_imx_data_entry_single(MX31, SZ_16K);
24#endif /* ifdef CONFIG_SOC_IMX31 */
25
26#ifdef CONFIG_SOC_IMX35
27const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
28 imx_pata_imx_data_entry_single(MX35, SZ_16K);
29#endif /* ifdef CONFIG_SOC_IMX35 */
30
31#ifdef CONFIG_SOC_IMX51
32const struct imx_pata_imx_data imx51_pata_imx_data __initconst =
33 imx_pata_imx_data_entry_single(MX51, SZ_16K);
34#endif /* ifdef CONFIG_SOC_IMX51 */
35
36#ifdef CONFIG_SOC_IMX53
37const struct imx_pata_imx_data imx53_pata_imx_data __initconst =
38 imx_pata_imx_data_entry_single(MX53, SZ_16K);
39#endif /* ifdef CONFIG_SOC_IMX53 */
40
41struct platform_device *__init imx_add_pata_imx(
42 const struct imx_pata_imx_data *data)
43{
44 struct resource res[] = {
45 {
46 .start = data->iobase,
47 .end = data->iobase + data->iosize - 1,
48 .flags = IORESOURCE_MEM,
49 },
50 {
51 .start = data->irq,
52 .end = data->irq,
53 .flags = IORESOURCE_IRQ,
54 },
55 };
56 return imx_add_platform_device("pata_imx", -1,
57 res, ARRAY_SIZE(res), NULL, 0);
58}
59
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index d7149d1bd32c..ace4bb550edc 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -82,4 +82,19 @@ enum mxc_cpu_pwr_mode {
82 82
83extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); 83extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
84extern void (*imx_idle)(void); 84extern void (*imx_idle)(void);
85extern void imx_print_silicon_rev(const char *cpu, int srev);
86
87void avic_handle_irq(struct pt_regs *);
88void tzic_handle_irq(struct pt_regs *);
89
90#define imx1_handle_irq avic_handle_irq
91#define imx21_handle_irq avic_handle_irq
92#define imx25_handle_irq avic_handle_irq
93#define imx27_handle_irq avic_handle_irq
94#define imx31_handle_irq avic_handle_irq
95#define imx35_handle_irq avic_handle_irq
96#define imx50_handle_irq tzic_handle_irq
97#define imx51_handle_irq tzic_handle_irq
98#define imx53_handle_irq tzic_handle_irq
99
85#endif 100#endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 524538aabc4b..4cbad45edc15 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -251,6 +251,14 @@ struct platform_device *__init imx_add_mxc_nand(
251 const struct imx_mxc_nand_data *data, 251 const struct imx_mxc_nand_data *data,
252 const struct mxc_nand_platform_data *pdata); 252 const struct mxc_nand_platform_data *pdata);
253 253
254struct imx_pata_imx_data {
255 resource_size_t iobase;
256 resource_size_t iosize;
257 resource_size_t irq;
258};
259struct platform_device *__init imx_add_pata_imx(
260 const struct imx_pata_imx_data *data);
261
254struct imx_mxc_pwm_data { 262struct imx_mxc_pwm_data {
255 int id; 263 int id;
256 resource_size_t iobase; 264 resource_size_t iobase;
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 066d464d322d..842fbcb0d6cc 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,72 +9,16 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <mach/hardware.h> 12/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
13 13
14#define AVIC_NIMASK 0x04
15
16 @ this macro disables fast irq (not implemented)
17 .macro disable_fiq 14 .macro disable_fiq
18 .endm 15 .endm
19 16
20 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
21#ifndef CONFIG_MXC_TZIC
22 ldr \base, =avic_base
23 ldr \base, [\base]
24#ifdef CONFIG_MXC_IRQ_PRIOR
25 ldr r4, [\base, #AVIC_NIMASK]
26#endif
27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
31 .endm 18 .endm
32 19
33 .macro arch_ret_to_user, tmp1, tmp2 20 .macro arch_ret_to_user, tmp1, tmp2
34 .endm 21 .endm
35 22
36 @ this macro checks which interrupt occurred
37 @ and returns its number in irqnr
38 @ and returns if an interrupt occurred in irqstat
39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40#ifndef CONFIG_MXC_TZIC
41 @ Load offset & priority of the highest priority
42 @ interrupt pending from AVIC_NIVECSR
43 ldr \irqstat, [\base, #0x40]
44 @ Shift to get the decoded IRQ number, using ASR so
45 @ 'no interrupt pending' becomes 0xffffffff
46 mov \irqnr, \irqstat, asr #16
47 @ set zero flag if IRQ + 1 == 0
48 adds \tmp, \irqnr, #1
49#ifdef CONFIG_MXC_IRQ_PRIOR
50 bicne \tmp, \irqstat, #0xFFFFFFE0
51 strne \tmp, [\base, #AVIC_NIMASK]
52 streq r4, [\base, #AVIC_NIMASK]
53#endif
54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
57 @ 0x080 is INTSEC0 register
58 @ 0xD80 is HIPND0 register
59 mov \irqnr, #0
601000: add \irqstat, \base, \irqnr, lsr #3
61 ldr \tmp, [\irqstat, #0xd80]
62 ldr \irqstat, [\irqstat, #0x080]
63 ands \tmp, \tmp, \irqstat
64 bne 1001f
65 add \irqnr, \irqnr, #32
66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
80 .endm 24 .endm
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c92f0b1f216f..63f22a009a65 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -735,6 +735,7 @@ enum iomux_pins {
735#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) 735#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
736#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) 736#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
737#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) 737#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
738#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
738 739
739 740
740/* 741/*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 11be5cdbdd1a..35e6c7f4ffd1 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -21,22 +21,8 @@
21#define MX53_PHYS_OFFSET UL(0x70000000) 21#define MX53_PHYS_OFFSET UL(0x70000000)
22 22
23#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 23#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
24# if defined CONFIG_ARCH_MX1 24# if defined CONFIG_ARCH_MX3
25# define PLAT_PHYS_OFFSET MX1_PHYS_OFFSET
26# elif defined CONFIG_MACH_MX21
27# define PLAT_PHYS_OFFSET MX21_PHYS_OFFSET
28# elif defined CONFIG_ARCH_MX25
29# define PLAT_PHYS_OFFSET MX25_PHYS_OFFSET
30# elif defined CONFIG_MACH_MX27
31# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET
32# elif defined CONFIG_ARCH_MX3
33# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET 25# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET
34# elif defined CONFIG_ARCH_MX50
35# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET
36# elif defined CONFIG_ARCH_MX51
37# define PLAT_PHYS_OFFSET MX51_PHYS_OFFSET
38# elif defined CONFIG_ARCH_MX53
39# define PLAT_PHYS_OFFSET MX53_PHYS_OFFSET
40# endif 26# endif
41#endif 27#endif
42 28
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 087cd7ac8d52..ccebf5ba12f0 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -41,6 +41,7 @@
41#define MX25_SSI2_BASE_ADDR 0x50014000 41#define MX25_SSI2_BASE_ADDR 0x50014000
42#define MX25_SSI1_BASE_ADDR 0x50034000 42#define MX25_SSI1_BASE_ADDR 0x50034000
43#define MX25_NFC_BASE_ADDR 0xbb000000 43#define MX25_NFC_BASE_ADDR 0xbb000000
44#define MX25_IIM_BASE_ADDR 0x53ff0000
44#define MX25_DRYICE_BASE_ADDR 0x53ffc000 45#define MX25_DRYICE_BASE_ADDR 0x53ffc000
45#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 46#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
46#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 47#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
@@ -104,4 +105,8 @@
104#define MX25_DMA_REQ_SSI1_RX0 28 105#define MX25_DMA_REQ_SSI1_RX0 28
105#define MX25_DMA_REQ_SSI1_TX0 29 106#define MX25_DMA_REQ_SSI1_TX0 29
106 107
108#ifndef __ASSEMBLY__
109extern int mx25_revision(void);
110#endif
111
107#endif /* ifndef __MACH_MX25_H__ */ 112#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index d13dbfeef08a..80965a99aa55 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -36,7 +36,7 @@
36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) 36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) 37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
38#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) 38#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
39#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) 39#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
40#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) 40#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
41#define MX35_FEC_BASE_ADDR 0x50038000 41#define MX35_FEC_BASE_ADDR 0x50038000
42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) 42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 388a407d72d6..30dbf424583e 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -187,22 +187,8 @@
187/* Mandatory defines used globally */ 187/* Mandatory defines used globally */
188 188
189#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 189#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
190 190extern int mx35_revision(void);
191extern unsigned int mx31_cpu_rev; 191extern int mx31_revision(void);
192extern void mx31_read_cpu_rev(void);
193
194static inline int mx31_revision(void)
195{
196 return mx31_cpu_rev;
197}
198
199extern unsigned int mx35_cpu_rev;
200extern void mx35_read_cpu_rev(void);
201
202static inline int mx35_revision(void)
203{
204 return mx35_cpu_rev;
205}
206#endif 192#endif
207 193
208#endif /* ifndef __MACH_MX3x_H__ */ 194#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index 96953e2e4f11..b6e11458e5ae 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -23,17 +23,17 @@
23 23
24int imx_irq_set_priority(unsigned char irq, unsigned char prio) 24int imx_irq_set_priority(unsigned char irq, unsigned char prio)
25{ 25{
26 struct mxc_irq_chip *chip; 26 struct irq_chip_generic *gc;
27 struct irq_chip *base; 27 struct mxc_extra_irq *exirq;
28 int ret; 28 int ret;
29 29
30 ret = -ENOSYS; 30 ret = -ENOSYS;
31 31
32 base = irq_get_chip(irq); 32 gc = irq_get_chip_data(irq);
33 if (base) { 33 if (gc && gc->private) {
34 chip = container_of(base, struct mxc_irq_chip, base); 34 exirq = gc->private;
35 if (chip->set_priority) 35 if (exirq->set_priority)
36 ret = chip->set_priority(irq, prio); 36 ret = exirq->set_priority(irq, prio);
37 } 37 }
38 38
39 return ret; 39 return ret;
@@ -43,15 +43,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
43int mxc_set_irq_fiq(unsigned int irq, unsigned int type) 43int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
44{ 44{
45 struct irq_chip_generic *gc; 45 struct irq_chip_generic *gc;
46 int (*set_irq_fiq)(unsigned int, unsigned int); 46 struct mxc_extra_irq *exirq;
47 int ret; 47 int ret;
48 48
49 ret = -ENOSYS; 49 ret = -ENOSYS;
50 50
51 gc = irq_get_chip_data(irq); 51 gc = irq_get_chip_data(irq);
52 if (gc && gc->private) { 52 if (gc && gc->private) {
53 set_irq_fiq = gc->private; 53 exirq = gc->private;
54 ret = set_irq_fiq(irq, type); 54 if (exirq->set_irq_fiq)
55 ret = exirq->set_irq_fiq(irq, type);
55 } 56 }
56 57
57 return ret; 58 return ret;
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
index 7203543fb1b3..6ccb3a14c693 100644
--- a/arch/arm/plat-mxc/irq-common.h
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -19,9 +19,8 @@
19#ifndef __PLAT_MXC_IRQ_COMMON_H__ 19#ifndef __PLAT_MXC_IRQ_COMMON_H__
20#define __PLAT_MXC_IRQ_COMMON_H__ 20#define __PLAT_MXC_IRQ_COMMON_H__
21 21
22struct mxc_irq_chip 22struct mxc_extra_irq
23{ 23{
24 struct irq_chip base;
25 int (*set_priority)(unsigned char irq, unsigned char prio); 24 int (*set_priority)(unsigned char irq, unsigned char prio);
26 int (*set_irq_fiq)(unsigned int irq, unsigned int type); 25 int (*set_irq_fiq)(unsigned int irq, unsigned int type);
27}; 26};
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 761c3c940a68..42d74ea59084 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -57,7 +57,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
57 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) 57 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
58 return -EINVAL; 58 return -EINVAL;
59 59
60 if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { 60 if (!(cpu_is_mx1() || cpu_is_mx21())) {
61 unsigned long long c; 61 unsigned long long c;
62 unsigned long period_cycles, duty_cycles, prescale; 62 unsigned long period_cycles, duty_cycles, prescale;
63 u32 cr; 63 u32 cr;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index f257fccdc394..e993a184189a 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -42,7 +42,7 @@
42#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ 42#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
43#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ 43#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
44#define TZIC_PND0 0x0D00 /* Pending Register 0 */ 44#define TZIC_PND0 0x0D00 /* Pending Register 0 */
45#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ 45#define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
46#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ 46#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
47#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ 47#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
48#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ 48#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
@@ -74,6 +74,12 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
74 74
75static unsigned int *wakeup_intr[4]; 75static unsigned int *wakeup_intr[4];
76 76
77static struct mxc_extra_irq tzic_extra_irq = {
78#ifdef CONFIG_FIQ
79 .set_irq_fiq = tzic_set_irq_fiq,
80#endif
81};
82
77static __init void tzic_init_gc(unsigned int irq_start) 83static __init void tzic_init_gc(unsigned int irq_start)
78{ 84{
79 struct irq_chip_generic *gc; 85 struct irq_chip_generic *gc;
@@ -82,7 +88,7 @@ static __init void tzic_init_gc(unsigned int irq_start)
82 88
83 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, 89 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
84 handle_level_irq); 90 handle_level_irq);
85 gc->private = tzic_set_irq_fiq; 91 gc->private = &tzic_extra_irq;
86 gc->wake_enabled = IRQ_MSK(32); 92 gc->wake_enabled = IRQ_MSK(32);
87 wakeup_intr[idx] = &gc->wake_active; 93 wakeup_intr[idx] = &gc->wake_active;
88 94
@@ -96,6 +102,28 @@ static __init void tzic_init_gc(unsigned int irq_start)
96 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 102 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
97} 103}
98 104
105asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
106{
107 u32 stat;
108 int i, irqofs, handled;
109
110 do {
111 handled = 0;
112
113 for (i = 0; i < 4; i++) {
114 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
115 __raw_readl(tzic_base + TZIC_INTSEC0(i));
116
117 while (stat) {
118 handled = 1;
119 irqofs = fls(stat) - 1;
120 handle_IRQ(irqofs + i * 32, regs);
121 stat &= ~(1 << irqofs);
122 }
123 }
124 } while (handled);
125}
126
99/* 127/*
100 * This function initializes the TZIC hardware and disables all the 128 * This function initializes the TZIC hardware and disables all the
101 * interrupts. It registers the interrupt enable and disable functions 129 * interrupts. It registers the interrupt enable and disable functions
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 03:08:46 -0500