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Diffstat (limited to 'arch/arm/mach-ux500/clock.c')
-rw-r--r--arch/arm/mach-ux500/clock.c38
1 files changed, 16 insertions, 22 deletions
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index ec35f0aa5665..1762c4728f1e 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -149,9 +149,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
149 unsigned long mturate; 149 unsigned long mturate;
150 unsigned long retclk; 150 unsigned long retclk;
151 151
152 if (cpu_is_u5500()) 152 if (cpu_is_u8500_family())
153 addr = __io_address(U5500_PRCMU_BASE);
154 else if (cpu_is_u8500())
155 addr = __io_address(U8500_PRCMU_BASE); 153 addr = __io_address(U8500_PRCMU_BASE);
156 else 154 else
157 ux500_unknown_soc(); 155 ux500_unknown_soc();
@@ -336,6 +334,7 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
336 */ 334 */
337 335
338/* Peripheral Cluster #1 */ 336/* Peripheral Cluster #1 */
337static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
339static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); 338static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
340static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); 339static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
341static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); 340static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
@@ -382,14 +381,15 @@ static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
382/* Peripheral Cluster #6 */ 381/* Peripheral Cluster #6 */
383 382
384/* MTU ID in data */ 383/* MTU ID in data */
385static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); 384static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
386static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); 385static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
387static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); 386static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
388static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); 387static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
389static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); 388static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
390static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); 389static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
391static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); 390static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
392static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); 391static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
392static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
393static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); 393static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
394 394
395static struct clk clk_dummy_apb_pclk = { 395static struct clk clk_dummy_apb_pclk = {
@@ -405,7 +405,7 @@ static struct clk_lookup u8500_clks[] = {
405 CLK(slimbus0, "slimbus0", NULL), 405 CLK(slimbus0, "slimbus0", NULL),
406 CLK(i2c2, "nmk-i2c.2", NULL), 406 CLK(i2c2, "nmk-i2c.2", NULL),
407 CLK(sdi0, "sdi0", NULL), 407 CLK(sdi0, "sdi0", NULL),
408 CLK(msp0, "msp0", NULL), 408 CLK(msp0, "ux500-msp-i2s.0", NULL),
409 CLK(i2c1, "nmk-i2c.1", NULL), 409 CLK(i2c1, "nmk-i2c.1", NULL),
410 CLK(uart1, "uart1", NULL), 410 CLK(uart1, "uart1", NULL),
411 CLK(uart0, "uart0", NULL), 411 CLK(uart0, "uart0", NULL),
@@ -431,6 +431,7 @@ static struct clk_lookup u8500_clks[] = {
431 CLK(pka, "pka", NULL), 431 CLK(pka, "pka", NULL),
432 CLK(hash0, "hash0", NULL), 432 CLK(hash0, "hash0", NULL),
433 CLK(cryp0, "cryp0", NULL), 433 CLK(cryp0, "cryp0", NULL),
434 CLK(cryp1, "cryp1", NULL),
434 435
435 /* PRCMU level clock gating */ 436 /* PRCMU level clock gating */
436 437
@@ -455,7 +456,8 @@ static struct clk_lookup u8500_clks[] = {
455 /* Peripheral Cluster #1 */ 456 /* Peripheral Cluster #1 */
456 CLK(i2c4, "nmk-i2c.4", NULL), 457 CLK(i2c4, "nmk-i2c.4", NULL),
457 CLK(spi3, "spi3", NULL), 458 CLK(spi3, "spi3", NULL),
458 CLK(msp1, "msp1", NULL), 459 CLK(msp1, "ux500-msp-i2s.1", NULL),
460 CLK(msp3, "ux500-msp-i2s.3", NULL),
459 461
460 /* Peripheral Cluster #2 */ 462 /* Peripheral Cluster #2 */
461 CLK(gpio1, "gpio.6", NULL), 463 CLK(gpio1, "gpio.6", NULL),
@@ -465,7 +467,7 @@ static struct clk_lookup u8500_clks[] = {
465 CLK(spi0, "spi0", NULL), 467 CLK(spi0, "spi0", NULL),
466 CLK(sdi3, "sdi3", NULL), 468 CLK(sdi3, "sdi3", NULL),
467 CLK(sdi1, "sdi1", NULL), 469 CLK(sdi1, "sdi1", NULL),
468 CLK(msp2, "msp2", NULL), 470 CLK(msp2, "ux500-msp-i2s.2", NULL),
469 CLK(sdi4, "sdi4", NULL), 471 CLK(sdi4, "sdi4", NULL),
470 CLK(pwl, "pwl", NULL), 472 CLK(pwl, "pwl", NULL),
471 CLK(spi1, "spi1", NULL), 473 CLK(spi1, "spi1", NULL),
@@ -705,14 +707,6 @@ late_initcall(clk_init_smp_twd_cpufreq);
705 707
706int __init clk_init(void) 708int __init clk_init(void)
707{ 709{
708 if (cpu_is_u5500()) {
709 /* Clock tree for U5500 not implemented yet */
710 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
711 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
712 clk_uartclk.rate = 36360000;
713 clk_sdmmcclk.rate = 99900000;
714 }
715
716 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); 710 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
717 clkdev_add(&clk_smp_twd_lookup); 711 clkdev_add(&clk_smp_twd_lookup);
718 712