1 files changed, 15 insertions, 7 deletions

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index af8b63435727..54a816ff3847 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -408,7 +408,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[0].flags = IORESOURCE_IO;
         if (request_resource(&ioport_resource, &pp->res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[0]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -427,7 +427,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[1].flags = IORESOURCE_MEM;
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         /*
          * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -446,7 +446,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
         if (request_resource(&iomem_resource, &pp->res[2]))
                 panic("Request PCIe Prefetch Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[2]);
+        pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
 
         return 1;
 }
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
         afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
         u32 val, reg;
-        int i;
+        int i, timeout;
 
         /* Enable slot clock and pulse the reset signals */
         for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
         pads_writel(0xfa5cfa5c, 0xc8);
 
         /* Wait for the PLL to lock */
+        timeout = 300;
         do {
                 val = pads_readl(PADS_PLL_CTL);
+                usleep_range(1000, 1000);
+                if (--timeout == 0) {
+                        pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+                        return -EBUSY;
+                }
         } while (!(val & PADS_PLL_CTL_LOCKDET));
 
         /* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
         /* Disable all execptions */
         afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-        return;
+        return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
         if (err)
                 return err;
 
-        tegra_pcie_enable_controller();
+        err = tegra_pcie_enable_controller();
+        if (err)
+                return err;
 
         /* setup the AFI address translations */
         tegra_pcie_setup_translations();