diff options
Diffstat (limited to 'arch/arm/mach-shmobile/clock-sh7372.c')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 5a2894b1c965..430a90ffa120 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c | |||
| @@ -24,36 +24,36 @@ | |||
| 24 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 25 | 25 | ||
| 26 | /* SH7372 registers */ | 26 | /* SH7372 registers */ |
| 27 | #define FRQCRA 0xe6150000 | 27 | #define FRQCRA IOMEM(0xe6150000) |
| 28 | #define FRQCRB 0xe6150004 | 28 | #define FRQCRB IOMEM(0xe6150004) |
| 29 | #define FRQCRC 0xe61500e0 | 29 | #define FRQCRC IOMEM(0xe61500e0) |
| 30 | #define FRQCRD 0xe61500e4 | 30 | #define FRQCRD IOMEM(0xe61500e4) |
| 31 | #define VCLKCR1 0xe6150008 | 31 | #define VCLKCR1 IOMEM(0xe6150008) |
| 32 | #define VCLKCR2 0xe615000c | 32 | #define VCLKCR2 IOMEM(0xe615000c) |
| 33 | #define VCLKCR3 0xe615001c | 33 | #define VCLKCR3 IOMEM(0xe615001c) |
| 34 | #define FMSICKCR 0xe6150010 | 34 | #define FMSICKCR IOMEM(0xe6150010) |
| 35 | #define FMSOCKCR 0xe6150014 | 35 | #define FMSOCKCR IOMEM(0xe6150014) |
| 36 | #define FSIACKCR 0xe6150018 | 36 | #define FSIACKCR IOMEM(0xe6150018) |
| 37 | #define FSIBCKCR 0xe6150090 | 37 | #define FSIBCKCR IOMEM(0xe6150090) |
| 38 | #define SUBCKCR 0xe6150080 | 38 | #define SUBCKCR IOMEM(0xe6150080) |
| 39 | #define SPUCKCR 0xe6150084 | 39 | #define SPUCKCR IOMEM(0xe6150084) |
| 40 | #define VOUCKCR 0xe6150088 | 40 | #define VOUCKCR IOMEM(0xe6150088) |
| 41 | #define HDMICKCR 0xe6150094 | 41 | #define HDMICKCR IOMEM(0xe6150094) |
| 42 | #define DSITCKCR 0xe6150060 | 42 | #define DSITCKCR IOMEM(0xe6150060) |
| 43 | #define DSI0PCKCR 0xe6150064 | 43 | #define DSI0PCKCR IOMEM(0xe6150064) |
| 44 | #define DSI1PCKCR 0xe6150098 | 44 | #define DSI1PCKCR IOMEM(0xe6150098) |
| 45 | #define PLLC01CR 0xe6150028 | 45 | #define PLLC01CR IOMEM(0xe6150028) |
| 46 | #define PLLC2CR 0xe615002c | 46 | #define PLLC2CR IOMEM(0xe615002c) |
| 47 | #define RMSTPCR0 0xe6150110 | 47 | #define RMSTPCR0 IOMEM(0xe6150110) |
| 48 | #define RMSTPCR1 0xe6150114 | 48 | #define RMSTPCR1 IOMEM(0xe6150114) |
| 49 | #define RMSTPCR2 0xe6150118 | 49 | #define RMSTPCR2 IOMEM(0xe6150118) |
| 50 | #define RMSTPCR3 0xe615011c | 50 | #define RMSTPCR3 IOMEM(0xe615011c) |
| 51 | #define RMSTPCR4 0xe6150120 | 51 | #define RMSTPCR4 IOMEM(0xe6150120) |
| 52 | #define SMSTPCR0 0xe6150130 | 52 | #define SMSTPCR0 IOMEM(0xe6150130) |
| 53 | #define SMSTPCR1 0xe6150134 | 53 | #define SMSTPCR1 IOMEM(0xe6150134) |
| 54 | #define SMSTPCR2 0xe6150138 | 54 | #define SMSTPCR2 IOMEM(0xe6150138) |
| 55 | #define SMSTPCR3 0xe615013c | 55 | #define SMSTPCR3 IOMEM(0xe615013c) |
| 56 | #define SMSTPCR4 0xe6150140 | 56 | #define SMSTPCR4 IOMEM(0xe6150140) |
| 57 | 57 | ||
| 58 | #define FSIDIVA 0xFE1F8000 | 58 | #define FSIDIVA 0xFE1F8000 |
| 59 | #define FSIDIVB 0xFE1F8008 | 59 | #define FSIDIVB 0xFE1F8008 |