180 files changed, 7388 insertions, 2669 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fcd4e85c4ddc..a6219eaf1f68 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,12 +18,16 @@ config ARCH_OMAP2PLUS_TYPICAL
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
         select HIGHMEM
+        select PINCTRL
         help
           Compile a kernel suitable for booting most boards
 
 config SOC_HAS_OMAP2_SDRC
         bool "OMAP2 SDRAM Controller support"
 
+config SOC_HAS_REALTIME_COUNTER
+        bool "Real time free running counter"
+
 config ARCH_OMAP2
         bool "TI OMAP2"
         depends on ARCH_OMAP2PLUS
@@ -44,6 +48,7 @@ config ARCH_OMAP3
         select ARM_CPU_SUSPEND if PM
         select MULTI_IRQ_HANDLER
         select SOC_HAS_OMAP2_SDRC
+        select OMAP_INTERCONNECT
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -63,6 +68,7 @@ config ARCH_OMAP4
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
         select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+        select OMAP_INTERCONNECT
 
 config SOC_OMAP5
         bool "TI OMAP5"
@@ -70,6 +76,8 @@ config SOC_OMAP5
         select ARM_GIC
         select HAVE_SMP
         select ARM_CPU_SUSPEND if PM
+        select SOC_HAS_REALTIME_COUNTER
+        select ARM_ARCH_TIMER
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
@@ -232,10 +240,11 @@ config MACH_OMAP3_PANDORA
         select OMAP_PACKAGE_CBB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
-config MACH_OMAP3_TOUCHBOOK
+config MACH_TOUCHBOOK
         bool "OMAP3 Touch Book"
         depends on ARCH_OMAP3
         default y
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_3430SDP
         bool "OMAP 3430 SDP board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3f9c4f..fe40d9e488c9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,36 +4,30 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
 
-omap-2-3-common                         = irq.o
-hwmod-common                            = omap_hwmod.o \
-                                          omap_hwmod_common_data.o
-clock-common                            = clock.o clock_common_data.o \
-                                          clkt_dpll.o clkt_clksel.o
-secure-common                           = omap-smc.o omap-secure.o
+# INTCPS IP block support - XXX should be moved to drivers/
+obj-$(CONFIG_ARCH_OMAP2)                += irq.o
+obj-$(CONFIG_ARCH_OMAP3)                += irq.o
+obj-$(CONFIG_SOC_AM33XX)                += irq.o
 
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
-obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
+# Secure monitor API support
+obj-$(CONFIG_ARCH_OMAP3)                += omap-smc.o omap-secure.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap-smc.o omap-secure.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-smc.o omap-secure.o
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
 
-obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
+obj-$(CONFIG_TWL4030_CORE)              += omap_twl.o
 
 # SMP support ONLY available for OMAP4
 
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
-                                           sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
-obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap4-common.o omap-wakeupgen.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 
 # OPP table initialization
 ifeq ($(CONFIG_PM_OPP),y)
@@ -68,15 +63,15 @@ endif
 
 # Power Management
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o sleep44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)     += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
@@ -88,92 +83,76 @@ endif
 endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 endif
 
 # PRCM
-omap-prcm-4-5-common                    =  prcm.o cminst44xx.o cm44xx.o \
-                                           prcm_mpu44xx.o prminst44xx.o \
-                                           vc44xx_data.o vp44xx_data.o
-obj-y                                   += prm_common.o
-obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-y                                   += prcm.o prm_common.o
+obj-$(CONFIG_ARCH_OMAP2)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += prcm.o prm33xx.o cm33xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
+omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
+                                           prcm_mpu44xx.o prminst44xx.o \
+                                           vc44xx_data.o vp44xx_data.o \
+                                           prm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
-voltagedomain-common                    := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
+obj-y                                   += voltage.o vc.o vp.o
 obj-$(CONFIG_ARCH_OMAP2)                += voltagedomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
 
 # OMAP powerdomain framework
-powerdomain-common                      += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common)
+obj-y                                   += powerdomain.o powerdomain-common.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
 
 # PRCM clockdomain control
-clockdomain-common                      += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
+obj-y                                   += clockdomain.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
 
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_sys.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o
+obj-y                                   += clock.o clock_common_data.o \
+                                           clkt_dpll.o clkt_clksel.o
+obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o clkt2xxx_sys.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_virt_prcm_set.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_apll.o clkt2xxx_osc.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o clock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)                += clock33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
+obj-$(CONFIG_SOC_AM33XX)                += dpll3xxx.o clock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
@@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
+obj-y                                   += omap_hwmod_common_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
@@ -194,15 +174,12 @@ obj-$(CONFIG_SOC_OMAP2430)		+= omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
-
-# L3 interconnect
-obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap_l3_noc.o
+obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
 
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
@@ -229,10 +206,10 @@ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
 obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
@@ -255,7 +232,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP)		+= board-zoom-display.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
-obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o
+obj-$(CONFIG_MACH_TOUCHBOOK)            += board-omap3touchbook.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
new file mode 100644
index 000000000000..06c19bb7bca6
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE     0x48000000
+
+#define AM33XX_SCM_BASE         0x44E10000
+#define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE        0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 2c90ac686686..d0c54c573d34 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -19,7 +19,7 @@
 #include <linux/davinci_emac.h>
 #include <asm/system.h>
 #include <plat/omap_device.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include "control.h"
 #include "am35xx-emac.h"
 
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/am35xx.h
index 95594495fcf6..95594495fcf6 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/am35xx.h
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9511584fdc4f..95b384d54f8a 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,11 +33,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -212,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = {
 };
 
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
@@ -235,7 +231,7 @@ static int __init omap2430_i2c_init(void)
         sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
         omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
                         ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-        omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
+        omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
                         &sdp2430_twldata);
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index a98c688058a9..96cd3693e1ae 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,14 +24,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include <plat/usb.h>
 #include "common.h"
 #include <plat/dma.h>
@@ -39,7 +37,7 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include "board-flash.h"
 #include "mux.h"
@@ -191,9 +189,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
         .default_device = &sdp3430_lcd_device,
 };
 
-static struct omap_board_config_kernel sdp3430_config[] __initdata = {
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -233,9 +228,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .pulldowns      = BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                 | BIT(16) | BIT(17),
         .setup          = sdp3430_twl_gpio_setup,
@@ -576,8 +568,6 @@ static void __init omap_3430sdp_init(void)
         int gpio_pendown;
 
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap_board_config = sdp3430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
         omap_hsmmc_init(mmc);
         omap3430_i2c_init();
         omap_display_init(&sdp3430_dss_data);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 2dc9ba523c7a..fc224ad86747 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -17,8 +17,7 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/board.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
@@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
-static struct omap_board_config_kernel sdp_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        omap_board_config = sdp_config;
-        omap_board_config_size = ARRAY_SIZE(sdp_config);
         zoom_peripherals_init();
         omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
                                   h8mbx00u0mer0em_sdrc_params);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c165e20506c9..3669c120c7e8 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,23 +28,22 @@
 #include <linux/leds_pwm.h>
 #include <linux/platform_data/omap4-keypad.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-nokia-dsi.h>
 #include <video/omap-panel-picodlp.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
+#include "soc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
@@ -544,7 +543,14 @@ static struct twl6040_platform_data twl6040_data = {
         .codec          = &twl6040_codec,
         .vibra          = &twl6040_vibra,
         .audpwron_gpio  = 127,
-        .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+
+static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+                .irq = 119 + OMAP44XX_IRQ_GIC_START,
+                .platform_data = &twl6040_data,
+        },
 };
 
 static struct twl4030_platform_data sdp4430_twldata = {
@@ -580,8 +586,8 @@ static int __init omap4_i2c_init(void)
                         TWL_COMMON_REGULATOR_CLK32KG |
                         TWL_COMMON_REGULATOR_V1V8 |
                         TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &sdp4430_twldata,
-                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
+        omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
+                        ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
@@ -755,6 +761,32 @@ static struct omap_board_mux board_mux[] __initdata = {
         /* NIRQ2 for twl6040 */
         OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
                   OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
+        /* GPIO_127 for twl6040 */
+        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* McPDM */
+        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        /* DMIC */
+        OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        /* McBSP1 */
+        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
+                  OMAP_PULL_ENA),
+        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        /* McBSP2 */
+        OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
+                  OMAP_PULL_ENA),
+        OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
@@ -840,6 +872,7 @@ static void __init omap_4430sdp_init(void)
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(omap4_smp_ops),
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 92432c28673d..318feadb1d6e 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -21,12 +21,10 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 
@@ -37,11 +35,6 @@
 #define GPIO_USB_POWER          35
 #define GPIO_USB_NRESET         38
 
-
-/* Board initialization */
-static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -67,9 +60,6 @@ static void __init am3517_crane_init(void)
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
 
-        omap_board_config = am3517_crane_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
-
         /* Configure GPIO for EHCI port */
         if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
                 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 18f601096ce1..e16289755f2e 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -25,14 +25,13 @@
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <video/omapdss.h>
@@ -264,6 +263,16 @@ static __init void am3517_evm_musb_init(void)
         usb_musb_init(&musb_board_data);
 }
 
+static __init void am3517_evm_mcbsp1_init(void)
+{
+        u32 devconf0;
+
+        /* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
+        devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
+        omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
+}
+
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -296,8 +305,7 @@ static struct resource am3517_hecc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = INT_35XX_HECC0_IRQ,
-                .end    = INT_35XX_HECC0_IRQ,
+                .start  = 24 + OMAP_INTC_START,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -324,9 +332,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
         platform_device_register(&am3517_hecc_device);
 }
 
-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -346,8 +351,6 @@ static struct omap2_hsmmc_info mmc[] = {
 
 static void __init am3517_evm_init(void)
 {
-        omap_board_config = am3517_evm_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         am3517_evm_i2c_init();
@@ -373,6 +376,9 @@ static void __init am3517_evm_init(void)
         /* MUSB */
         am3517_evm_musb_init();
 
+        /* McBSP1 */
+        am3517_evm_mcbsp1_init();
+
         /* MMC init function */
         omap_hsmmc_init(mmc);
 }
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index e5fa46bfde2f..cea3abace815 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -29,13 +29,11 @@
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
 #include <plat/led.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 
@@ -204,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
                 return;
         }
 
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
         rate = clk_get_rate(gpmc_fck);
 
         eth_cs = APOLLON_ETH_CS;
@@ -248,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
                 gpmc_cs_free(APOLLON_ETH_CS);
         }
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 97d719047af3..376d26eb601c 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -23,6 +23,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
@@ -37,15 +38,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <mach/hardware.h>
 
@@ -64,7 +64,7 @@
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
         .id             = 0,
@@ -470,9 +470,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 }
 
 static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .setup          = cm_t35_twl_gpio_setup,
 };
 
@@ -714,13 +711,8 @@ static inline void cm_t35_init_mux(void) {}
 static inline void cm_t3730_init_mux(void) {}
 #endif
 
-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
-};
-
 static void __init cm_t3x_common_init(void)
 {
-        omap_board_config = cm_t35_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
         omap_sdrc_init(mt46h32m32lf6_sdrc_params,
@@ -731,6 +723,7 @@ static void __init cm_t3x_common_init(void)
         cm_t35_init_ethernet();
         cm_t35_init_led();
         cm_t35_init_display();
+        omap_twl4030_audio_init("cm-t3x");
 
         usb_musb_init(NULL);
         cm_t35_init_usbh();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a33ad4641d9a..59c0a45f75b0 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -38,13 +38,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 
-#include <mach/am35xx.h>
+#include "am35xx.h"
 
 #include "mux.h"
 #include "control.h"
@@ -90,8 +89,7 @@ static struct resource cm_t3517_hecc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = INT_35XX_HECC0_IRQ,
-                .end    = INT_35XX_HECC0_IRQ,
+                .start  = 24 + OMAP_INTC_START,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -249,9 +247,6 @@ static void __init cm_t3517_init_nand(void)
 static inline void cm_t3517_init_nand(void) {}
 #endif
 
-static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* GPIO186 - Green LED */
@@ -285,8 +280,6 @@ static void __init cm_t3517_init(void)
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
-        omap_board_config = cm_t3517_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
         cm_t3517_init_leds();
         cm_t3517_init_nand();
         cm_t3517_init_rtc();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 6567c1cd5572..1fd161e934c7 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -32,31 +32,27 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-
-#include <mach/hardware.h>
-#include <mach/id.h>
+#include "id.h"
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/dm9000.h>
 #include <linux/interrupt.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
-
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -236,9 +232,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .pulldowns      = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                 | BIT(15) | BIT(16) | BIT(17),
@@ -630,6 +623,7 @@ static void __init devkit8000_init(void)
         usbhs_init(&usbhs_bdata);
         omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
                              ARRAY_SIZE(devkit8000_nand_partitions));
+        omap_twl4030_audio_init("omap3beagle");
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 53c39d239d6e..e642acf9cad0 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -16,13 +16,14 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
-#include <plat/irqs.h>
 
+#include <plat/cpu.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/tc.h>
 
+#include "common.h"
 #include "board-flash.h"
 
 #define REG_FPGA_REV                    0x10
@@ -140,7 +141,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
         board_nand_data.devsize         = nand_type;
 
         board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-        board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
         gpmc_nand_init(&board_nand_data);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -218,7 +218,7 @@ void __init board_flash_init(struct flash_partitions partition_info[],
                         if (onenandcs > GPMC_CS_NUM)
                                 onenandcs = cs;
                         break;
-                };
+                }
                 cs++;
         }
 
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6f93a20536ea..601ecdfb1cf9 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -16,11 +16,9 @@
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include "common-board-devices.h"
 
@@ -127,6 +125,7 @@ static const char *omap4_boards_compat[] __initdata = {
 
 DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
         .init_irq       = omap_gic_of_init,
@@ -147,6 +146,7 @@ static const char *omap5_boards_compat[] __initdata = {
 
 DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
         .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
         .map_io         = omap5_map_io,
         .init_early     = omap5_init_early,
         .init_irq       = omap_gic_of_init,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index ace20482e3e1..8d04bf851af4 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -27,20 +27,19 @@
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
-#include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include "debug-devices.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 
@@ -266,9 +265,9 @@ static inline void __init h4_init_debug(void)
                 return;
         }
 
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
         rate = clk_get_rate(gpmc_fck);
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 
         if (is_gpmc_muxed())
@@ -312,7 +311,7 @@ static inline void __init h4_init_debug(void)
                 gpmc_cs_free(eth_cs);
 
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 28214483aaba..48d5e41dfbfa 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -29,13 +29,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -192,7 +192,7 @@ static void __init igep_flash_init(void) {}
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .cs             = IGEP2_SMSC911X_CS,
@@ -425,9 +425,6 @@ static int igep_twl_gpio_setup(struct device *dev,
 };
 
 static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .setup          = igep_twl_gpio_setup,
 };
@@ -628,6 +625,7 @@ static void __init igep_init(void)
 
         igep_flash_init();
         igep_leds_init();
+        omap_twl4030_audio_init("igep2");
 
         /*
          * WLAN-BT combo module from MuRata which has a Marvell WLAN
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ef9e82977499..ee8c3cfb95b3 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -28,21 +28,17 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
-
-#include <asm/delay.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -275,9 +271,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
 }
 
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .setup          = ldp_twl_gpio_setup,
 };
 
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 677357ff61ac..d95f727ca39a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,19 +20,16 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
-#include <mach/irqs.h>
-#include <plat/mcspi.h>
-#include <plat/onenand.h>
 #include <plat/mmc.h>
-#include <plat/serial.h>
 
 #include "mux.h"
 
@@ -553,8 +550,8 @@ static int n8x0_auto_sleep_regulators(void)
 
         ret = menelaus_set_regulator_sleep(1, val);
         if (ret < 0) {
-                printk(KERN_ERR "Could not set regulators to sleep on "
-                        "menelaus: %u\n", ret);
+                pr_err("Could not set regulators to sleep on menelaus: %u\n",
+                       ret);
                 return ret;
         }
         return 0;
@@ -566,8 +563,7 @@ static int n8x0_auto_voltage_scale(void)
 
         ret = menelaus_set_vcore_hw(1400, 1050);
         if (ret < 0) {
-                printk(KERN_ERR "Could not set VCORE voltage on "
-                        "menelaus: %u\n", ret);
+                pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
                 return ret;
         }
         return 0;
@@ -600,7 +596,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
 static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
         {
                 I2C_BOARD_INFO("menelaus", 0x72),
-                .irq = INT_24XX_SYS_NIRQ,
+                .irq = 7 + OMAP_INTC_START,
                 .platform_data = &n8x0_menelaus_platform_data,
         },
 };
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6202fc76e490..388c431c745a 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,18 +33,16 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
@@ -297,9 +295,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data beagle_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .pullups        = BIT(1),
         .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
@@ -466,7 +461,7 @@ static void __init beagle_opp_init(void)
                 mpu_dev = omap_device_get_by_hwmod_name("mpu");
                 iva_dev = omap_device_get_by_hwmod_name("iva");
 
-                if (!mpu_dev || !iva_dev) {
+                if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) {
                         pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
                                 __func__, mpu_dev, iva_dev);
                         return;
@@ -519,6 +514,7 @@ static void __init omap3_beagle_init(void)
         usbhs_init(&usbhs_bdata);
         omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
                              ARRAY_SIZE(omap3beagle_nand_partitions));
+        omap_twl4030_audio_init("omap3beagle");
 
         /* Ensure msecure is mux'd to be able to set the RTC. */
         omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 0d362e9f9cb9..b9b776b6c954 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -32,6 +32,7 @@
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/smsc911x.h>
 
 #include <linux/wl12xx.h>
@@ -40,16 +41,14 @@
 #include <linux/mmc/host.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
@@ -75,13 +74,24 @@
 #define OMAP3EVM_GEN1_ETHR_GPIO_RST     64
 #define OMAP3EVM_GEN2_ETHR_GPIO_RST     7
 
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+        OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
+        OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
+};
+
 static u8 omap3_evm_version;
 
-u8 get_omap3_evm_rev(void)
+static u8 get_omap3_evm_rev(void)
 {
         return omap3_evm_version;
 }
-EXPORT_SYMBOL(get_omap3_evm_rev);
 
 static void __init omap3_evm_get_revision(void)
 {
@@ -108,7 +118,7 @@ static void __init omap3_evm_get_revision(void)
 }
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .cs             = OMAP3EVM_SMSC911X_CS,
@@ -377,9 +387,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .setup          = omap3evm_twl_gpio_setup,
 };
@@ -526,9 +533,6 @@ static int __init omap3_evm_i2c_init(void)
         return 0;
 }
 
-static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
-};
-
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -688,9 +692,6 @@ static void __init omap3_evm_init(void)
         obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
         omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
-        omap_board_config = omap3_evm_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
-
         omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         omap_hsmmc_init(mmc);
 
@@ -737,6 +738,7 @@ static void __init omap3_evm_init(void)
         omap3evm_init_smsc911x();
         omap3_evm_display_init();
         omap3_evm_wl12xx_init();
+        omap_twl4030_audio_init("omap3evm");
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index fca93d1afd43..7bd8253b5d1d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -30,24 +30,21 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include "gpmc-smsc911x.h"
+#include <plat/gpmc.h>
+#include <plat/sdrc.h>
+#include <plat/usb.h>
+
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
 
-#include <plat/mux.h>
-#include <plat/board.h>
-#include "common.h"
-#include <plat/gpmc-smsc911x.h>
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/usb.h>
-
 #define OMAP3LOGIC_SMSC911X_CS                  1
 
 #define OMAP3530_LV_SOM_MMC_GPIO_CD             110
@@ -78,9 +75,6 @@ static struct regulator_init_data omap3logic_vmmc1 = {
 };
 
 static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .pullups        = BIT(1),
         .pulldowns      = BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 57aebee44fd0..00a1f4ae6e44 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -35,18 +35,16 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
-#include <mach/hardware.h>
-#include <plat/mcspi.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -321,9 +319,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .setup          = omap3pandora_twl_gpio_setup,
 };
 
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index b318f5602e36..731235eb319e 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -28,28 +28,26 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/interrupt.h>
+#include <linux/smsc911x.h>
+#include <linux/i2c/at24.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/mcspi.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/interrupt.h>
-#include <linux/smsc911x.h>
-#include <linux/i2c/at24.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
@@ -57,7 +55,7 @@
 #include "common-board-devices.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #define OMAP3STALKER_ETHR_START 0x2c000000
 #define OMAP3STALKER_ETHR_SIZE  1024
@@ -279,9 +277,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .setup          = omap3stalker_twl_gpio_setup,
 };
@@ -362,9 +357,6 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO   175
 
-static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
-};
-
 static struct platform_device *omap3_stalker_devices[] __initdata = {
         &keys_gpio,
 };
@@ -399,8 +391,6 @@ static void __init omap3_stalker_init(void)
 {
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
-        omap_board_config = omap3_stalker_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
         omap_mux_init_gpio(23, OMAP_PIN_INPUT);
         omap_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 485d14d6a8cd..944ffc436577 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -29,7 +29,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/spi/spi.h>
 
 #include <linux/spi/ads7846.h>
@@ -37,17 +37,15 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/system_info.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 
 #include "mux.h"
@@ -139,9 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data touchbook_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .pullups        = BIT(1),
         .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index cd4852e5ca57..bfcd397e233c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -32,19 +32,18 @@
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "soc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
@@ -172,7 +171,7 @@ static void __init omap4_ehci_init(void)
                 return;
         }
         clk_set_rate(phy_ref_clk, 19200000);
-        clk_enable(phy_ref_clk);
+        clk_prepare_enable(phy_ref_clk);
 
         /* disable the power to the usb hub prior to init and reset phy+hub */
         ret = gpio_request_array(panda_ehci_gpios,
@@ -248,8 +247,7 @@ static struct platform_device omap_vwlan_device = {
 };
 
 static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-        /* PANDA ref clock is 38.4 MHz */
-        .board_ref_clock = 2,
+        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
 };
 
 static struct twl6040_codec_data twl6040_codec = {
@@ -263,7 +261,14 @@ static struct twl6040_codec_data twl6040_codec = {
 static struct twl6040_platform_data twl6040_data = {
         .codec          = &twl6040_codec,
         .audpwron_gpio  = 127,
-        .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+
+static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+                .irq = 119 + OMAP44XX_IRQ_GIC_START,
+                .platform_data = &twl6040_data,
+        },
 };
 
 /* Panda board uses the common PMIC configuration */
@@ -293,8 +298,8 @@ static int __init omap4_panda_i2c_init(void)
                         TWL_COMMON_REGULATOR_CLK32KG |
                         TWL_COMMON_REGULATOR_V1V8 |
                         TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &omap4_panda_twldata,
-                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
+        omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
+                        ARRAY_SIZE(panda_i2c_1_boardinfo));
         omap_register_i2c_bus(2, 400, NULL, 0);
         /*
          * Bus 3 is attached to the DVI port where devices like the pico DLP
@@ -382,6 +387,21 @@ static struct omap_board_mux board_mux[] __initdata = {
         /* NIRQ2 for twl6040 */
         OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
                   OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
+        /* GPIO_127 for twl6040 */
+        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* McPDM */
+        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        /* McBSP1 */
+        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
+                  OMAP_PULL_ENA),
+        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
@@ -495,6 +515,7 @@ static void __init omap4_panda_init(void)
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         /* Maintainer: David Anders - Texas Instruments Inc */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(omap4_smp_ops),
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d8ba37..b700685762b5 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -37,21 +37,19 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
 
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <mach/hardware.h>
-#include <plat/nand.h>
-#include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
 #include "mux.h"
@@ -116,7 +114,7 @@ static inline void __init overo_ads7846_init(void) { return; }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .id             = 0,
@@ -399,9 +397,6 @@ static int overo_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data overo_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
         .setup          = overo_twl_gpio_setup,
 };
@@ -509,6 +504,7 @@ static void __init overo_init(void)
         overo_display_init();
         overo_init_led();
         overo_init_keys();
+        omap_twl4030_audio_init("overo");
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -522,8 +518,7 @@ static void __init overo_init(void)
                 udelay(10);
                 gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
         } else {
-                printk(KERN_ERR "could not obtain gpio for "
-                                        "OVERO_GPIO_W2W_NRESET\n");
+                pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
         }
 
         ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
@@ -542,8 +537,7 @@ static void __init overo_init(void)
         if (ret == 0)
                 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
         else
-                printk(KERN_ERR "could not obtain gpio for "
-                                        "OVERO_GPIO_USBH_CPEN\n");
+                pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
 }
 
 MACHINE_START(OVERO, "Gumstix Overo")
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 0ad1bb3bdb98..45997bfbcbd2 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -17,6 +17,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -26,7 +27,7 @@
 #include <plat/usb.h>
 #include <plat/gpmc.h>
 #include "common.h"
-#include <plat/onenand.h>
+#include <plat/serial.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -72,9 +73,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = {
 
 /* TWL */
 static struct twl4030_gpio_platform_data rm680_gpio_data = {
-        .gpio_base              = OMAP_MAX_GPIO_LINES,
-        .irq_base               = TWL4030_GPIO_IRQ_BASE,
-        .irq_end                = TWL4030_GPIO_IRQ_END,
         .pullups                = BIT(0),
         .pulldowns              = BIT(1) | BIT(2) | BIT(8) | BIT(15),
 };
@@ -87,7 +85,7 @@ static struct twl4030_platform_data rm680_twl_data = {
 static void __init rm680_i2c_init(void)
 {
         omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
-        omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
+        omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
 }
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index df2534de3361..020e03c95bfe 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,17 +25,18 @@
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
+
 #include <asm/system_info.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/onenand.h>
-#include <plat/gpmc-smc91x.h>
+#include <plat/omap-pm.h>
+#include "gpmc-smc91x.h"
 
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
@@ -46,6 +47,10 @@
 #include <../drivers/staging/iio/light/tsl2563.h>
 #include <linux/lis3lv02d.h>
 
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+#include <media/ir-rx51.h>
+#endif
+
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -743,7 +748,7 @@ static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module =
         .subdev_board_info = &rx51_si4713_board_info,
 };
 
-static struct platform_device rx51_si4713_dev = {
+static struct platform_device rx51_si4713_dev __initdata_or_module = {
         .name   = "radio-si4713",
         .id     = -1,
         .dev    = {
@@ -774,9 +779,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 }
 
 static struct twl4030_gpio_platform_data rx51_gpio_data = {
-        .gpio_base              = OMAP_MAX_GPIO_LINES,
-        .irq_base               = TWL4030_GPIO_IRQ_BASE,
-        .irq_end                = TWL4030_GPIO_IRQ_END,
         .pulldowns              = BIT(0) | BIT(1) | BIT(2) | BIT(3)
                                 | BIT(4) | BIT(5)
                                 | BIT(8) | BIT(9) | BIT(10) | BIT(11)
@@ -1051,7 +1053,7 @@ static int __init rx51_i2c_init(void)
         rx51_twldata.vdac->constraints.apply_uV = true;
         rx51_twldata.vdac->constraints.name = "VDAC";
 
-        omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
+        omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
         omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                               ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
 #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
@@ -1220,6 +1222,30 @@ static void __init rx51_init_tsc2005(void)
                                 gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 }
 
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+static struct lirc_rx51_platform_data rx51_lirc_data = {
+        .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
+        .pwm_timer = 9, /* Use GPT 9 for CIR */
+};
+
+static struct platform_device rx51_lirc_device = {
+        .name           = "lirc_rx51",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &rx51_lirc_data,
+        },
+};
+
+static void __init rx51_init_lirc(void)
+{
+        platform_device_register(&rx51_lirc_device);
+}
+#else
+static void __init rx51_init_lirc(void)
+{
+}
+#endif
+
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
@@ -1230,6 +1256,7 @@ void __init rx51_peripherals_init(void)
         rx51_init_wl1251();
         rx51_init_tsc2005();
         rx51_init_si4713();
+        rx51_init_lirc();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
 
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 2c1289bd5e6a..c22e111bcd00 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -17,9 +17,9 @@
 #include <asm/mach-types.h>
 #include <video/omapdss.h>
 #include <plat/vram.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 
 #include "mux.h"
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 345dd931f76f..7bbb05d9689b 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -17,14 +17,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/board-rx51.h
index b76f49e7eed5..b76f49e7eed5 100644
--- a/arch/arm/mach-omap2/include/mach/board-rx51.h
+++ b/arch/arm/mach-omap2/board-rx51.h
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index d4c8392cadb6..c4f8833b4c3c 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -15,13 +15,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/irqs.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 
@@ -32,15 +29,10 @@ static struct omap_musb_board_data musb_board_data = {
         .power          = 500,
 };
 
-static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
-};
-
 static void __init ti81xx_evm_init(void)
 {
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
-        omap_board_config = ti81xx_evm_config;
-        omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
         usb_musb_init(&musb_board_data);
 }
 
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index f64f44173061..afb2278a29f6 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -18,10 +18,13 @@
 #include <linux/regulator/machine.h>
 
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #include <mach/board-zoom.h>
 
+#include "soc.h"
+#include "common.h"
+
 #define ZOOM_SMSC911X_CS        7
 #define ZOOM_SMSC911X_GPIO      158
 #define ZOOM_QUADUART_CS        3
@@ -81,8 +84,7 @@ static inline void __init zoom_init_quaduart(void)
         quart_cs = ZOOM_QUADUART_CS;
 
         if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem"
-                                "for Quad UART(TL16CP754C)\n");
+                pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
                 return;
         }
 
@@ -104,8 +106,8 @@ static inline int omap_zoom_debugboard_detect(void)
 
         if (gpio_request_one(debug_board_detect, GPIOF_IN,
                              "Zoom debug board detect") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
-                "board detect\n", debug_board_detect);
+                pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
+                       debug_board_detect);
                 return 0;
         }
 
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 28187f134fff..b940ab2259fb 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -14,10 +14,12 @@
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <mach/board-zoom.h>
 
+#include "common.h"
+
 #define LCD_PANEL_RESET_GPIO_PROD       96
 #define LCD_PANEL_RESET_GPIO_PILOT      55
 #define LCD_PANEL_QVGA_GPIO             56
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index b797cb279618..c166fe1fdff9 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -19,6 +19,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,6 +35,7 @@
 #include "common-board-devices.h"
 
 #define OMAP_ZOOM_WLAN_PMENA_GPIO       (101)
+#define ZOOM2_HEADSET_EXTMUTE_GPIO      (153)
 #define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
 
 #define LCD_PANEL_ENABLE_GPIO           (7 + OMAP_MAX_GPIO_LINES)
@@ -193,8 +195,7 @@ static struct platform_device omap_vwlan_device = {
 };
 
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
-        /* ZOOM ref clock is 26 MHz */
-        .board_ref_clock = 1,
+        .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
 };
 
 static struct omap2_hsmmc_info mmc[] = {
@@ -244,16 +245,7 @@ static int zoom_twl_gpio_setup(struct device *dev,
         return ret;
 }
 
-/* EXTMUTE callback function */
-static void zoom2_set_hs_extmute(int mute)
-{
-        gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
-}
-
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
         .setup          = zoom_twl_gpio_setup,
 };
 
@@ -279,9 +271,9 @@ static int __init omap_i2c_init(void)
 
                 codec_data->ramp_delay_value = 3;       /* 161 ms */
                 codec_data->hs_extmute = 1;
-                codec_data->set_hs_extmute = zoom2_set_hs_extmute;
+                codec_data->hs_extmute_gpio = ZOOM2_HEADSET_EXTMUTE_GPIO;
         }
-        omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
+        omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4e7e56142e6f..4994438e1f46 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -22,7 +22,6 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/board.h>
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7234ae..c2d15212d64d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
         omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
         omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-                             OMAP24XX_CM_IDLEST_VAL, clk->name);
+                             OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
 
         /*
          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746b221a..3524f0e7b6d5 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,11 +33,11 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
         const struct prcm_config *ptr;
-        long highest_rate;
+        long highest_rate, sys_clk_rate;
 
         highest_rate = -EINVAL;
+        sys_clk_rate = __clk_get_rate(sclk);
 
         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
                 if (!(ptr->flags & cpu_mask))
                         continue;
-                if (ptr->xtal_speed != sclk->rate)
+                if (ptr->xtal_speed != sys_clk_rate)
                         continue;
 
                 highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
         const struct prcm_config *prcm;
         unsigned long found_speed = 0;
         unsigned long flags;
+        long sys_clk_rate;
+
+        sys_clk_rate = __clk_get_rate(sclk);
 
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
 
-                if (prcm->xtal_speed != sclk->rate)
+                if (prcm->xtal_speed != sys_clk_rate)
                         continue;
 
                 if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd9e7e7..7c6da2f731dc 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         struct omap_sdrc_params *sdrc_cs0;
         struct omap_sdrc_params *sdrc_cs1;
         int ret;
+        unsigned long clkrate;
 
         if (!clk || !rate)
                 return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (validrate != rate)
                 return -EINVAL;
 
-        sdrcrate = sdrc_ick_p->rate;
-        if (rate > clk->rate)
-                sdrcrate <<= ((rate / clk->rate) >> 1);
+        sdrcrate = __clk_get_rate(sdrc_ick_p);
+        clkrate = __clk_get_rate(clk);
+        if (rate > clkrate)
+                sdrcrate <<= ((rate / clkrate) >> 1);
         else
-                sdrcrate >>= ((clk->rate / rate) >> 1);
+                sdrcrate >>= ((clkrate / rate) >> 1);
 
         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
         if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         /*
          * XXX This only needs to be done when the CPU frequency changes
          */
-        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
         c += 1;  /* for safety */
         c *= SDRC_MPURATE_LOOPS;
@@ -90,28 +92,26 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (c == 0)
                 c = 1;
 
-        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-                 validrate);
-        pr_debug("clock: SDRC CS0 timing params used:"
-                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+                 clkrate, validrate);
+        pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
         if (sdrc_cs1)
-                pr_debug("clock: SDRC CS1 timing params used: "
-                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
-                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+                pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                         sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                         sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 
         if (sdrc_cs1)
                 omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
         else
                 omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b1f7f7..3ff22114d702 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 
         if (!clks->parent) {
                 /* This indicates a data problem */
-                WARN(1, "clock: Could not find parent clock %s in clksel array "
-                     "of clock %s\n", src_clk->name, clk->name);
+                WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+                     __clk_get_name(clk), __clk_get_name(src_clk));
                 return NULL;
         }
 
@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
 
         if (max_div == 0) {
                 /* This indicates an error in the clksel data */
-                WARN(1, "clock: Could not find divisor for clock %s parent %s"
-                     "\n", clk->name, src_clk->parent->name);
+                WARN(1, "clock: %s: could not find divisor for parent %s\n",
+                     __clk_get_name(clk),
+                     __clk_get_name(__clk_get_parent(src_clk)));
                 return 0;
         }
 
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        struct clk *parent;
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return 0;
 
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 
         if (!clkr->div) {
                 /* This indicates a data error */
-                WARN(1, "clock: Could not find fieldval %d for clock %s parent "
-                     "%s\n", field_val, clk->name, clk->parent->name);
+                WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
+                     __clk_get_name(clk), field_val, __clk_get_name(parent));
                 return 0;
         }
 
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        struct clk *parent;
 
         /* should never happen */
         WARN_ON(div == 0);
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return ~0;
 
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
         }
 
         if (!clkr->div) {
-                pr_err("clock: Could not find divisor %d for clock %s parent "
-                       "%s\n", div, clk->name, clk->parent->name);
+                pr_err("clock: %s: could not find divisor %d for parent %s\n",
+                       __clk_get_name(clk), div, __clk_get_name(parent));
                 return ~0;
         }
 
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
         const struct clksel *clks;
         const struct clksel_rate *clkr;
         u32 last_div = 0;
+        struct clk *parent;
+        unsigned long parent_rate;
+        const char *clk_name;
+
+        parent = __clk_get_parent(clk);
+        parent_rate = __clk_get_rate(parent);
+        clk_name = __clk_get_name(clk);
 
         if (!clk->clksel || !clk->clksel_mask)
                 return ~0;
 
         pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
 
         *new_div = 1;
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return ~0;
 
@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
                 /* Sanity check */
                 if (clkr->div <= last_div)
-                        pr_err("clock: clksel_rate table not sorted "
-                               "for clock %s", clk->name);
+                        pr_err("clock: %s: clksel_rate table not sorted\n",
+                               clk_name);
 
                 last_div = clkr->div;
 
-                test_rate = clk->parent->rate / clkr->div;
+                test_rate = parent_rate / clkr->div;
 
                 if (test_rate <= target_rate)
                         break; /* found it */
         }
 
         if (!clkr->div) {
-                pr_err("clock: Could not find divisor for target "
-                       "rate %ld for clock %s parent %s\n", target_rate,
-                       clk->name, clk->parent->name);
+                pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
+                       clk_name, target_rate, __clk_get_name(parent));
                 return ~0;
         }
 
         *new_div = clkr->div;
 
         pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-                 (clk->parent->rate / clkr->div));
+                 (parent_rate / clkr->div));
 
-        return clk->parent->rate / clkr->div;
+        return parent_rate / clkr->div;
 }
 
 /*
@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
         const struct clksel *clks;
         const struct clksel_rate *clkr;
         u32 r, found = 0;
+        struct clk *parent;
+        const char *clk_name;
 
         if (!clk->clksel || !clk->clksel_mask)
                 return;
 
+        parent = __clk_get_parent(clk);
+        clk_name = __clk_get_name(clk);
+
         r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
         r >>= __ffs(clk->clksel_mask);
 
@@ -358,14 +374,15 @@ void omap2_init_clksel_parent(struct clk *clk)
                                 continue;
 
                         if (clkr->val == r) {
-                                if (clk->parent != clks->parent) {
-                                        pr_debug("clock: inited %s parent "
-                                                 "to %s (was %s)\n",
-                                                 clk->name, clks->parent->name,
-                                                 ((clk->parent) ?
-                                                  clk->parent->name : "NULL"));
+                                if (parent != clks->parent) {
+                                        pr_debug("clock: %s: inited parent to %s (was %s)\n",
+                                                 clk_name,
+                                                 __clk_get_name(clks->parent),
+                                                 ((parent) ?
+                                                  __clk_get_name(parent) :
+                                                 "NULL"));
                                         clk_reparent(clk, clks->parent);
-                                };
+                                }
                                 found = 1;
                         }
                 }
@@ -373,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 
         /* This indicates a data error */
         WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-             clk->name, r);
+             clk_name, r);
 
         return;
 }
@@ -391,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
 {
         unsigned long rate;
         u32 div = 0;
+        struct clk *parent;
 
         div = _read_divisor(clk);
         if (div == 0)
-                return clk->rate;
+                return __clk_get_rate(clk);
 
-        rate = clk->parent->rate / div;
+        parent = __clk_get_parent(clk);
+        rate = __clk_get_rate(parent) / div;
 
-        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
-                 rate, div);
+        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+                 __clk_get_name(clk), rate, div);
 
         return rate;
 }
@@ -454,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
         _write_clksel_reg(clk, field_val);
 
-        clk->rate = clk->parent->rate / new_div;
+        clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
 
-        pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+        pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+                 __clk_get_rate(clk));
 
         return 0;
 }
@@ -498,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
         clk_reparent(clk, new_parent);
 
         /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = new_parent->rate;
+        clk->rate = __clk_get_rate(new_parent);
 
         if (parent_div > 0)
-                clk->rate /= parent_div;
+                __clk_get_rate(clk) /= parent_div;
 
         pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-                 clk->name, clk->parent->name, clk->rate);
+                 __clk_get_name(clk),
+                 __clk_get_name(__clk_get_parent(clk)),
+                 __clk_get_rate(clk));
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f91149..80411142f482 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -22,8 +22,8 @@
 #include <asm/div64.h>
 
 #include <plat/clock.h>
-#include <plat/cpu.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
         dd = clk->dpll_data;
 
         /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / n;
+        fint = __clk_get_rate(__clk_get_parent(clk)) / n;
 
         if (cpu_is_omap24xx()) {
                 /* Should not be called for OMAP2, so warn if it is called */
@@ -105,13 +105,13 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
         }
 
         if (fint < fint_min) {
-                pr_debug("rejecting n=%d due to Fint failure, "
-                         "lowering max_divider\n", n);
+                pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
+                         n);
                 dd->max_divider = n;
                 ret = DPLL_FINT_UNDERFLOW;
         } else if (fint > fint_max) {
-                pr_debug("rejecting n=%d due to Fint failure, "
-                         "boosting min_divider\n", n);
+                pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
+                         n);
                 dd->min_divider = n;
                 ret = DPLL_FINT_INVALID;
         } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
                         clk_reparent(clk, dd->clk_bypass);
-        } else if (cpu_is_omap44xx()) {
+        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                     v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         if (cpu_is_omap24xx()) {
                 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         } else if (cpu_is_omap34xx()) {
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
-        } else if (cpu_is_omap44xx()) {
+                        return __clk_get_rate(dd->clk_bypass);
+        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                     v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         }
 
         v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         dpll_div = v & dd->div1_mask;
         dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+        dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
 
         return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         unsigned long scaled_rt_rp;
         unsigned long new_rate = 0;
         struct dpll_data *dd;
+        unsigned long ref_rate;
+        const char *clk_name;
 
         if (!clk || !clk->dpll_data)
                 return ~0;
 
         dd = clk->dpll_data;
 
+        ref_rate = __clk_get_rate(dd->clk_ref);
+        clk_name = __clk_get_name(clk);
         pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
 
-        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+        scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
         scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
 
         dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                         break;
 
                 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    dd->clk_ref->rate);
+                                    ref_rate);
 
                 /* m can't be set low enough for this n - try with a larger n */
                 if (r == DPLL_MULT_UNDERFLOW)
                         continue;
 
                 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
-                         clk->name, m, n, new_rate);
+                         clk_name, m, n, new_rate);
 
                 if (target_rate == new_rate) {
                         dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         }
 
         if (target_rate != new_rate) {
-                pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
-                         target_rate);
+                pr_debug("clock: %s: cannot round to rate %ld\n",
+                         clk_name, target_rate);
                 return ~0;
         }
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565ba1a4..961ac8f7e13d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,14 +22,16 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <trace/events/power.h>
 
 #include <asm/cpu.h>
+
 #include <plat/clock.h>
-#include "clockdomain.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
 
+#include <trace/events/power.h>
+
+#include "soc.h"
+#include "clockdomain.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
@@ -76,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
         clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
 
         omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
-                             clk->name);
+                             __clk_get_name(clk));
 }
 
 /* Public functions */
@@ -92,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
 void omap2_init_clk_clkdm(struct clk *clk)
 {
         struct clockdomain *clkdm;
+        const char *clk_name;
 
         if (!clk->clkdm_name)
                 return;
 
+        clk_name = __clk_get_name(clk);
+
         clkdm = clkdm_lookup(clk->clkdm_name);
         if (clkdm) {
                 pr_debug("clock: associated clk %s to clkdm %s\n",
-                         clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
                 clk->clkdm = clkdm;
         } else {
-                pr_debug("clock: could not associate clk %s to "
-                         "clkdm %s\n", clk->name, clk->clkdm_name);
+                pr_debug("clock: could not associate clk %s to clkdm %s\n",
+                         clk_name, clk->clkdm_name);
         }
 }
 
@@ -226,8 +231,7 @@ void omap2_dflt_clk_disable(struct clk *clk)
                  * 'Independent' here refers to a clock which is not
                  * controlled by its parent.
                  */
-                printk(KERN_ERR "clock: clk_disable called on independent "
-                       "clock %s which has no enable_reg\n", clk->name);
+                pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
                 return;
         }
 
@@ -270,8 +274,7 @@ const struct clkops clkops_omap2_dflt = {
 void omap2_clk_disable(struct clk *clk)
 {
         if (clk->usecount == 0) {
-                WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
-                     "already 0?", clk->name);
+                WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
                 return;
         }
 
@@ -332,8 +335,8 @@ int omap2_clk_enable(struct clk *clk)
         if (clkdm_control && clk->clkdm) {
                 ret = clkdm_clk_enable(clk->clkdm, clk);
                 if (ret) {
-                        WARN(1, "clock: %s: could not enable clockdomain %s: "
-                             "%d\n", clk->name, clk->clkdm->name, ret);
+                        WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
+                             clk->name, clk->clkdm->name, ret);
                         goto oce_err2;
                 }
         }
@@ -501,10 +504,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 
         hfclkin_rate = clk_get_rate(hfclkin_ck);
 
-        pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
-                "%ld.%01ld/%ld/%ld MHz\n",
-                (hfclkin_rate / 1000000),
-                ((hfclkin_rate / 100000) % 10),
+        pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
                 (clk_get_rate(core_ck) / 1000000),
                 (clk_get_rate(mpu_ck) / 1000000));
 }
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 002745181ad6..c3cde1a2b6de 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -18,9 +18,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
         CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
         CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
@@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
         CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
         CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_243X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index dfda9a3f2cb2..a8e326177466 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index cacabb070e22..22404fe435e7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -17,9 +17,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
@@ -1856,6 +1856,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
+        CLK("twl",      "fck",          &osc_ck,        CK_243X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
@@ -1887,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
@@ -1926,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
@@ -1950,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
@@ -1965,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
         CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
         CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
@@ -1977,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
+        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
         CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
         CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
         CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
         CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
         CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb1_fck",         &mmchsdb1_fck,  CK_243X),
         CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb2_fck",         &mmchsdb2_fck,  CK_243X),
         CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
         CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 12500097378d..e92be1fc1a00 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,9 +22,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 25bbcc7ca4dc..114ab4b8e0e3 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -18,8 +18,8 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <plat/clkdev_omap.h>
-#include <plat/am33xx.h>
 
+#include "am33xx.h"
 #include "iomap.h"
 #include "control.h"
 #include "clock.h"
@@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
         CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck,           CK_AM33XX),
         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
@@ -1027,22 +1028,26 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
         CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
         CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
+        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
         CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
+        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
         CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
         CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
         CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
         CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
+        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck,    CK_AM33XX),
+        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
         CLK("NULL",     "mmc2_fck",             &mmc2_fck,      CK_AM33XX),
         CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
-        CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
+        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
+        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
+        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),
+        CLK(NULL,       "timer4_fck",           &timer4_fck,    CK_AM33XX),
+        CLK(NULL,       "timer5_fck",           &timer5_fck,    CK_AM33XX),
+        CLK(NULL,       "timer6_fck",           &timer6_fck,    CK_AM33XX),
+        CLK(NULL,       "timer7_fck",           &timer7_fck,    CK_AM33XX),
         CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
         CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 794d82702c85..83bb01427d40 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
 #include "prm2xxx_3xxx.h"
@@ -49,8 +49,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
          * on DPLL4.
          */
         if (omap_rev() == OMAP3430_REV_ES1_0) {
-                pr_err("clock: DPLL4 cannot change rate due to "
-                       "silicon 'Limitation 2.5' on 3430ES1.\n");
+                pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
                 return -EINVAL;
         }
 
@@ -64,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
 
         dpll5_clk = clk_get(NULL, "dpll5_ck");
         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_enable(dpll5_clk);
+        clk_prepare_enable(dpll5_clk);
 
         /* Program dpll5_m2_clk divider for no division */
         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-        clk_enable(dpll5_m2_clk);
+        clk_prepare_enable(dpll5_m2_clk);
         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 
-        clk_disable(dpll5_m2_clk);
-        clk_disable(dpll5_clk);
+        clk_disable_unprepare(dpll5_m2_clk);
+        clk_disable_unprepare(dpll5_clk);
         return;
 }
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 83bed9ad3017..1f42c9d5ecf3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -21,9 +21,9 @@
 #include <linux/list.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock3xxx.h"
@@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
  * clkdev
  */
 
-/* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
@@ -3226,6 +3225,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_3XXX),
         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
+        CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
@@ -3242,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
@@ -3262,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@@ -3271,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
@@ -3294,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
@@ -3314,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
@@ -3321,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3328,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
@@ -3368,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
@@ -3384,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
         CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
@@ -3393,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3438,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
@@ -3456,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
+        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
         CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
+        CLK(NULL,       "vpfe_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "vpfe_fck",     &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
@@ -3466,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
         CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
 };
 
 
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d7f55e43b761..d661d138f270 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -28,9 +28,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock44xx.h"
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
+        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
@@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
@@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
         CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
         CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
         CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
         CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
@@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
         CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
         CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8664f5a8bfb6..cbb879139c51 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -174,9 +174,8 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
                 if (IS_ERR(autodep->clkdm.ptr))
                         continue;
 
-                pr_debug("clockdomain: adding %s sleepdep/wkdep for "
-                         "clkdm %s\n", autodep->clkdm.ptr->name,
-                         clkdm->name);
+                pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+                         clkdm->name, autodep->clkdm.ptr->name);
 
                 clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
                 clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
@@ -205,9 +204,8 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
                 if (IS_ERR(autodep->clkdm.ptr))
                         continue;
 
-                pr_debug("clockdomain: removing %s sleepdep/wkdep for "
-                         "clkdm %s\n", autodep->clkdm.ptr->name,
-                         clkdm->name);
+                pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+                         clkdm->name, autodep->clkdm.ptr->name);
 
                 clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
                 clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
@@ -469,14 +467,14 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 ret = -EINVAL;
 
         if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of "
-                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
                 return ret;
         }
 
         if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
-                pr_debug("clockdomain: hardware will wake up %s when %s wakes "
-                         "up\n", clkdm1->name, clkdm2->name);
+                pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
 
                 ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
         }
@@ -510,14 +508,14 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 ret = -EINVAL;
 
         if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of "
-                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
                 return ret;
         }
 
         if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
-                pr_debug("clockdomain: hardware will no longer wake up %s "
-                         "after %s wakes up\n", clkdm1->name, clkdm2->name);
+                pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
 
                 ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
         }
@@ -555,8 +553,8 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 ret = -EINVAL;
 
         if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of "
-                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
                 return ret;
         }
 
@@ -613,15 +611,14 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 ret = -EINVAL;
 
         if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep "
-                         "dependency affecting %s from %s\n", clkdm1->name,
-                         clkdm2->name);
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                         clkdm1->name, clkdm2->name);
                 return ret;
         }
 
         if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
-                pr_debug("clockdomain: will prevent %s from sleeping if %s "
-                         "is active\n", clkdm1->name, clkdm2->name);
+                pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
+                         clkdm1->name, clkdm2->name);
 
                 ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
         }
@@ -657,16 +654,14 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 ret = -EINVAL;
 
         if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep "
-                         "dependency affecting %s from %s\n", clkdm1->name,
-                         clkdm2->name);
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                         clkdm1->name, clkdm2->name);
                 return ret;
         }
 
         if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
-                pr_debug("clockdomain: will no longer prevent %s from "
-                         "sleeping if %s is active\n", clkdm1->name,
-                         clkdm2->name);
+                pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
+                         clkdm1->name, clkdm2->name);
 
                 ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
         }
@@ -706,9 +701,8 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 ret = -EINVAL;
 
         if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep "
-                         "dependency affecting %s from %s\n", clkdm1->name,
-                         clkdm2->name);
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                         clkdm1->name, clkdm2->name);
                 return ret;
         }
 
@@ -755,8 +749,8 @@ int clkdm_sleep(struct clockdomain *clkdm)
                 return -EINVAL;
 
         if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-                pr_debug("clockdomain: %s does not support forcing "
-                         "sleep via software\n", clkdm->name);
+                pr_debug("clockdomain: %s does not support forcing sleep via software\n",
+                         clkdm->name);
                 return -EINVAL;
         }
 
@@ -790,8 +784,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
                 return -EINVAL;
 
         if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
-                pr_debug("clockdomain: %s does not support forcing "
-                         "wakeup via software\n", clkdm->name);
+                pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
+                         clkdm->name);
                 return -EINVAL;
         }
 
@@ -826,8 +820,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
                 return;
 
         if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
-                pr_debug("clock: automatic idle transitions cannot be enabled "
-                         "on clockdomain %s\n", clkdm->name);
+                pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
+                         clkdm->name);
                 return;
         }
 
@@ -861,8 +855,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
                 return;
 
         if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
-                pr_debug("clockdomain: automatic idle transitions cannot be "
-                         "disabled on %s\n", clkdm->name);
+                pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
+                         clkdm->name);
                 return;
         }
 
@@ -905,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm)
         return ret;
 }
 
+/**
+ * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm has the
+ * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
+ * null.  More information is available in the documentation for the
+ * CLKDM_MISSING_IDLE_REPORTING macro.
+ */
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
+{
+        if (!clkdm)
+                return false;
+
+        return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
+}
+
 /* Clockdomain-to-clock/hwmod framework interface code */
 
 static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
@@ -927,7 +938,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
         pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 
-        pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+        pr_debug("clockdomain: %s: enabled\n", clkdm->name);
 
         return 0;
 }
@@ -952,7 +963,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
         pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 
-        pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5601dc13785e..629576be7444 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -1,9 +1,7 @@
 /*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
  * OMAP2/3 clockdomain framework functions
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008, 2012 Texas Instruments, Inc.
  * Copyright (C) 2008-2011 Nokia Corporation
  *
  * Paul Walmsley
@@ -34,6 +32,20 @@
  * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
  *     active whenever the MPU is active.  True for interconnects and
  *     the WKUP clockdomains.
+ * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
+ *     clocks inside this clockdomain are not taken into account by
+ *     the PRCM when determining whether the clockdomain is idle.
+ *     Without this flag, if the clockdomain is set to
+ *     hardware-supervised idle mode, the PRCM may transition the
+ *     enclosing powerdomain to a low power state, even when devices
+ *     inside the clockdomain and powerdomain are in use.  (An example
+ *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
+ *     this flag is set, and the clockdomain does not support the
+ *     force-sleep mode, then the HW_AUTO mode will be used to put the
+ *     clockdomain to sleep.  Similarly, if the clockdomain supports
+ *     the force-wakeup mode, then it will be used whenever a clock or
+ *     IP block inside the clockdomain is active, rather than the
+ *     HW_AUTO mode.
  */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
@@ -41,6 +53,7 @@
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
 #define CLKDM_NO_AUTODEPS                       (1 << 4)
 #define CLKDM_ACTIVE_WITH_MPU                   (1 << 5)
+#define CLKDM_MISSING_IDLE_REPORTING            (1 << 6)
 
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
 void clkdm_allow_idle(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
 bool clkdm_in_hwsup(struct clockdomain *clkdm);
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
 
 int clkdm_wakeup(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index a0d68dbecfa3..70294f54e35a 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm)
                                                 clkdm->clktrctrl_mask);
 }
 
+static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+
+static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
 
 static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
 {
@@ -209,36 +222,90 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
         return 0;
 }
 
-static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
 {
-        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+
+        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
-        return 0;
 }
 
-static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
 {
-        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
-        return 0;
+
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
 }
 
-static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
+static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
 {
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_add_autodeps(clkdm);
+        bool hwsup = false;
 
-        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+                omap3_clkdm_wakeup(clkdm);
+                return 0;
+        }
+
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_add_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap3_clkdm_wakeup(clkdm);
+        }
+
+        return 0;
 }
 
-static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
+static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
 {
-        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                _enable_hwsup(clkdm);
+                return 0;
+        }
+
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
 
-        if (atomic_read(&clkdm->usecount) > 0)
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
                 _clkdm_del_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap3_clkdm_sleep(clkdm);
+        }
+
+        return 0;
 }
 
 struct clkdm_ops omap2_clkdm_operations = {
@@ -267,6 +334,6 @@ struct clkdm_ops omap3_clkdm_operations = {
         .clkdm_wakeup           = omap3_clkdm_wakeup,
         .clkdm_allow_idle       = omap3_clkdm_allow_idle,
         .clkdm_deny_idle        = omap3_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
+        .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
 };
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 762f2cc542ce..6fc6155625bc 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
         if (!clkdm->prcm_partition)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap4_clkdm_allow_idle(clkdm);
+                return 0;
+        }
+
         hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                         clkdm->cm_inst, clkdm->clkdm_offs);
 
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 56089c49142a..933a35cd124a 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
 
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
 static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
         .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .flags          = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
+                           CLKDM_MISSING_IDLE_REPORTING),
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 63d60a773d3b..b56d06b48782 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = {
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
         .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
-        .flags            = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
+        .flags            = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
+                             CLKDM_MISSING_IDLE_REPORTING),
 };
 
 static struct clockdomain l3_dma_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index 532027ee3d8d..adf7bb79b18f 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -25,263 +25,328 @@
  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
  */
 #define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
+#define AM33XX_AUTO_DPLL_MODE_WIDTH                     3
 #define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
+#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
 
 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
 
 /* Used by CM_PER_CPSW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH     1
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH             1
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
 
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
 
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
 
 /* Used by CM_PER_L3S_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
+#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
 
 /* Used by CM_PER_L4FW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
 
 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
 
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
 
 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
 
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
 
 /* Used by CM_MPU_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
+#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
 
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
 
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
 
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
 
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH                1
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2DIV_SHIFT                         3
-#define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
+#define AM33XX_CLKOUT2DIV_WIDTH                         3
+#define AM33XX_CLKOUT2DIV_MASK                          (0x7 << 3)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2EN_SHIFT                          7
+#define AM33XX_CLKOUT2EN_WIDTH                          1
 #define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2SOURCE_SHIFT                      0
-#define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
+#define AM33XX_CLKOUT2SOURCE_WIDTH                      3
+#define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
 
 /*
  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
@@ -289,6 +354,7 @@
  * CLKSEL_TIMER7_CLK
  */
 #define AM33XX_CLKSEL_SHIFT                             0
+#define AM33XX_CLKSEL_WIDTH                             1
 #define AM33XX_CLKSEL_MASK                              (0x01 << 0)
 
 /*
@@ -296,17 +362,21 @@
  * CM_CPTS_RFT_CLKSEL
  */
 #define AM33XX_CLKSEL_0_0_SHIFT                         0
+#define AM33XX_CLKSEL_0_0_WIDTH                         1
 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
 
 #define AM33XX_CLKSEL_0_1_SHIFT                         0
+#define AM33XX_CLKSEL_0_1_WIDTH                         2
 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
 
 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
 #define AM33XX_CLKSEL_0_2_SHIFT                         0
+#define AM33XX_CLKSEL_0_2_WIDTH                         3
 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
 
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
+#define AM33XX_CLKSEL_GFX_FCLK_WIDTH                    1
 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
 
 /*
@@ -318,6 +388,7 @@
  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
  */
 #define AM33XX_CLKTRCTRL_SHIFT                          0
+#define AM33XX_CLKTRCTRL_WIDTH                          2
 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
 
 /*
@@ -326,34 +397,42 @@
  * CM_SSC_DELTAMSTEP_DPLL_PER
  */
 #define AM33XX_DELTAMSTEP_SHIFT                         0
-#define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
+#define AM33XX_DELTAMSTEP_WIDTH                         20
+#define AM33XX_DELTAMSTEP_MASK                          (0xfffff << 0)
 
 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
+#define AM33XX_DPLL_BYP_CLKSEL_WIDTH                    1
 #define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH           1
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH                1
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
 
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
+#define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
 #define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH                7
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x7f << 0)
 
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH               1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH        1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
 
 /*
@@ -361,6 +440,7 @@
  * CM_DIV_M2_DPLL_PER
  */
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH              1
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -368,19 +448,22 @@
  * CM_CLKSEL_DPLL_MPU
  */
 #define AM33XX_DPLL_DIV_SHIFT                           0
+#define AM33XX_DPLL_DIV_WIDTH                           7
 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
 
 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_DIV_0_7_SHIFT                       0
-#define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
+#define AM33XX_DPLL_DIV_0_7_WIDTH                       8
+#define AM33XX_DPLL_DIV_0_7_MASK                        (0xff << 0)
 
 /*
  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH                 1
 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
 
 /*
@@ -388,6 +471,7 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_EN_SHIFT                            0
+#define AM33XX_DPLL_EN_WIDTH                            3
 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
 
 /*
@@ -395,6 +479,7 @@
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
+#define AM33XX_DPLL_LPMODE_EN_WIDTH                     1
 #define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
 
 /*
@@ -402,10 +487,12 @@
  * CM_CLKSEL_DPLL_MPU
  */
 #define AM33XX_DPLL_MULT_SHIFT                          8
+#define AM33XX_DPLL_MULT_WIDTH                          11
 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
+#define AM33XX_DPLL_MULT_PERIPH_WIDTH                   12
 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
 
 /*
@@ -413,17 +500,20 @@
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_REGM4XEN_SHIFT                      11
+#define AM33XX_DPLL_REGM4XEN_WIDTH                      1
 #define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_SD_DIV_SHIFT                        24
-#define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
+#define AM33XX_DPLL_SD_DIV_WIDTH                        8
+#define AM33XX_DPLL_SD_DIV_MASK                         (0xff << 24)
 
 /*
  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_ACK_SHIFT                       13
+#define AM33XX_DPLL_SSC_ACK_WIDTH                       1
 #define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
 
 /*
@@ -431,6 +521,7 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH                1
 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
 
 /*
@@ -438,54 +529,67 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_EN_SHIFT                        12
+#define AM33XX_DPLL_SSC_EN_WIDTH                        1
 #define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
-#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
 
 /*
@@ -522,11 +626,12 @@
  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
  */
 #define AM33XX_IDLEST_SHIFT                             16
+#define AM33XX_IDLEST_WIDTH                             2
 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
-#define AM33XX_IDLEST_VAL                               0x3
 
 /* Used by CM_MAC_CLKSEL */
 #define AM33XX_MII_CLK_SEL_SHIFT                        2
+#define AM33XX_MII_CLK_SEL_WIDTH                        1
 #define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
 
 /*
@@ -535,7 +640,8 @@
  * CM_SSC_MODFREQDIV_DPLL_PER
  */
 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
-#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
+#define AM33XX_MODFREQDIV_EXPONENT_WIDTH                3
+#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x7 << 8)
 
 /*
  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
@@ -543,7 +649,8 @@
  * CM_SSC_MODFREQDIV_DPLL_PER
  */
 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
-#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
+#define AM33XX_MODFREQDIV_MANTISSA_WIDTH                7
+#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x7f << 0)
 
 /*
  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
@@ -580,42 +687,52 @@
  * CM_CEFUSE_CEFUSE_CLKCTRL
  */
 #define AM33XX_MODULEMODE_SHIFT                         0
+#define AM33XX_MODULEMODE_WIDTH                         2
 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
+#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH                  1
 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH                1
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
 
 /* Used by CM_WKUP_GPIO0_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH             1
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
 
 /* Used by CM_PER_GPIO1_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO2_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO3_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO4_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO5_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO6_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
 
 /*
@@ -627,25 +744,30 @@
  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
  */
 #define AM33XX_STBYST_SHIFT                             18
+#define AM33XX_STBYST_WIDTH                             1
 #define AM33XX_STBYST_MASK                              (1 << 18)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
-#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
+#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x7 << 27)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
-#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
+#define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x3 << 22)
 
 /*
  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
  */
 #define AM33XX_ST_DPLL_CLK_SHIFT                        0
+#define AM33XX_ST_DPLL_CLK_WIDTH                        1
 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
+#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH                  1
 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
 
 /*
@@ -653,18 +775,22 @@
  * CM_DIV_M2_DPLL_PER
  */
 #define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
+#define AM33XX_ST_DPLL_CLKOUT_WIDTH                     1
 #define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
 
 /*
@@ -672,16 +798,20 @@
  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
  */
 #define AM33XX_ST_MN_BYPASS_SHIFT                       8
+#define AM33XX_ST_MN_BYPASS_WIDTH                       1
 #define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
-#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
+#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x7 << 24)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
-#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
+#define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x3 << 20)
 
 /* Used by CONTROL_SEC_CLK_CTRL */
+#define AM33XX_TIMER0_CLKSEL_WIDTH                      2
 #define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 766338fe4d34..59598ffd8783 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -67,6 +67,7 @@
 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
 
 /* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2_SHIFT                          0
 #define OMAP3430_ST_IVA2_MASK                           (1 << 0)
 
 /* CM_IDLEST_PLL_IVA2 */
@@ -217,6 +218,8 @@
 #define OMAP3430_ST_MAILBOXES_MASK                      (1 << 7)
 #define OMAP3430_ST_OMAPCTRL_SHIFT                      6
 #define OMAP3430_ST_OMAPCTRL_MASK                       (1 << 6)
+#define OMAP3430_ST_SAD2D_SHIFT                         3
+#define OMAP3430_ST_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_ST_SDMA_SHIFT                          2
 #define OMAP3430_ST_SDMA_MASK                           (1 << 2)
 #define OMAP3430_ST_SDRC_SHIFT                          1
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 65597a745638..4c6c2f7de65b 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP44xx Clock Management register bits
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
@@ -24,6 +24,7 @@
 
 /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
+#define OMAP4430_ABE_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
@@ -31,14 +32,17 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
+#define OMAP4430_ABE_STATDEP_WIDTH                              0x1
 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
+#define OMAP4430_ALWONCORE_DYNDEP_WIDTH                         0x1
 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
+#define OMAP4430_ALWONCORE_STATDEP_WIDTH                        0x1
 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 
 /*
@@ -47,294 +51,367 @@
  * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
+#define OMAP4430_AUTO_DPLL_MODE_WIDTH                           0x3
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
+#define OMAP4430_CEFUSE_DYNDEP_WIDTH                            0x1
 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
+#define OMAP4430_CEFUSE_STATDEP_WIDTH                           0x1
 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT                9
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
+#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
 /* Used by CM_L3_1_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_L3_2_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
 /* Used by CM_MPU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
 /* Used by CM_L4PER_CLKSTCTRL */
@@ -343,94 +420,114 @@
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH                    0x1
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
+#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT                13
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                 (1 << 13)
 
 /*
  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SHIFT                                   24
+#define OMAP4430_CLKSEL_WIDTH                                   0x1
 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 
 /*
@@ -438,50 +535,62 @@
  * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
+#define OMAP4430_CLKSEL_0_0_WIDTH                               0x1
 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
+#define OMAP4430_CLKSEL_0_1_WIDTH                               0x2
 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
+#define OMAP4430_CLKSEL_24_25_WIDTH                             0x2
 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
+#define OMAP4430_CLKSEL_60M_WIDTH                               0x1
 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                      25
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH                      0x1
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                       (1 << 25)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
+#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH                         0x1
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
+#define OMAP4430_CLKSEL_CORE_WIDTH                              0x1
 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
 /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
+#define OMAP4430_CLKSEL_CORE_1_1_WIDTH                          0x1
 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
+#define OMAP4430_CLKSEL_DIV_WIDTH                               0x1
 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                     24
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH                     0x1
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                      (1 << 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
+#define OMAP4430_CLKSEL_FCLK_WIDTH                              0x2
 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH                   0x1
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 
 /*
@@ -490,34 +599,42 @@
  * CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH      0x2
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
+#define OMAP4430_CLKSEL_L3_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
+#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH                         0x1
 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
+#define OMAP4430_CLKSEL_L4_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
+#define OMAP4430_CLKSEL_OPP_WIDTH                               0x2
 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
+#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH                       0x3
 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH                     0x3
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
+#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH                          0x1
 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 
 /*
@@ -525,18 +642,22 @@
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
+#define OMAP4430_CLKSEL_SOURCE_WIDTH                            0x2
 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
+#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH                      0x1
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
+#define OMAP4430_CLKSEL_UTMI_P1_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
+#define OMAP4430_CLKSEL_UTMI_P2_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
 /*
@@ -549,30 +670,37 @@
  * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
+#define OMAP4430_CLKTRCTRL_WIDTH                                0x2
 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
+#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH                        0x7
 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
+#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH                       0xb
 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_WIDTH                                   0x2
 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
+#define OMAP4430_D2D_DYNDEP_WIDTH                               0x1
 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
+#define OMAP4430_D2D_STATDEP_WIDTH                              0x1
 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 
 /* Used by CM_CLKSEL_DPLL_MPU */
 #define OMAP4460_DCC_COUNT_MAX_SHIFT                            24
+#define OMAP4460_DCC_COUNT_MAX_WIDTH                            0x8
 #define OMAP4460_DCC_COUNT_MAX_MASK                             (0xff << 24)
 
 /* Used by CM_CLKSEL_DPLL_MPU */
@@ -586,22 +714,27 @@
  * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
+#define OMAP4430_DELTAMSTEP_WIDTH                               0x14
 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
 /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
 #define OMAP4460_DELTAMSTEP_0_20_SHIFT                          0
+#define OMAP4460_DELTAMSTEP_0_20_WIDTH                          0x15
 #define OMAP4460_DELTAMSTEP_0_20_MASK                           (0x1fffff << 0)
 
 /* Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             0
+#define OMAP4430_DLL_OVERRIDE_WIDTH                             0x1
 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
 
 /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
+#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH                         0x1
 #define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_RESET_SHIFT                                3
+#define OMAP4430_DLL_RESET_WIDTH                                0x1
 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
@@ -610,30 +743,37 @@
  * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
+#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH                          0x1
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
 /* Used by CM_CLKSEL_DPLL_CORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH                       0x5
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
@@ -641,10 +781,12 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
+#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH                          0x5
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH                      0x7
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
@@ -652,10 +794,12 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH                     0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH              0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
@@ -663,18 +807,22 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
+#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH                        0x3
 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
+#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
+#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
@@ -683,10 +831,12 @@
  * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
+#define OMAP4430_DPLL_DIV_WIDTH                                 0x7
 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
+#define OMAP4430_DPLL_DIV_0_7_WIDTH                             0x8
 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
@@ -694,10 +844,12 @@
  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
+#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH                       0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH                   0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
@@ -706,6 +858,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
+#define OMAP4430_DPLL_EN_WIDTH                                  0x3
 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
@@ -714,6 +867,7 @@
  * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
+#define OMAP4430_DPLL_LPMODE_EN_WIDTH                           0x1
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
@@ -722,10 +876,12 @@
  * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
+#define OMAP4430_DPLL_MULT_WIDTH                                0xb
 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
+#define OMAP4430_DPLL_MULT_USB_WIDTH                            0xc
 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
@@ -734,10 +890,12 @@
  * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
+#define OMAP4430_DPLL_REGM4XEN_WIDTH                            0x1
 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
+#define OMAP4430_DPLL_SD_DIV_WIDTH                              0x8
 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
@@ -746,6 +904,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
+#define OMAP4430_DPLL_SSC_ACK_WIDTH                             0x1
 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
@@ -754,6 +913,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH                      0x1
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
@@ -762,42 +922,52 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
+#define OMAP4430_DPLL_SSC_EN_WIDTH                              0x1
 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
+#define OMAP4430_DSS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
+#define OMAP4430_DSS_STATDEP_WIDTH                              0x1
 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
+#define OMAP4430_DUCATI_DYNDEP_WIDTH                            0x1
 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
+#define OMAP4430_DUCATI_STATDEP_WIDTH                           0x1
 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
+#define OMAP4430_FREQ_UPDATE_WIDTH                              0x1
 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_WIDTH                                     0xc
 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
+#define OMAP4430_GFX_DYNDEP_WIDTH                               0x1
 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
+#define OMAP4430_GFX_STATDEP_WIDTH                              0x1
 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
+#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH                         0x1
 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
@@ -805,6 +975,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
@@ -812,6 +983,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
@@ -819,6 +991,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -826,6 +999,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
@@ -833,6 +1007,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
@@ -840,6 +1015,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
@@ -847,6 +1023,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -854,38 +1031,47 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 
 /*
@@ -893,53 +1079,48 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_IDLEST_SHIFT                                   16
+#define OMAP4430_IDLEST_WIDTH                                   0x2
 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
 /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
+#define OMAP4430_ISS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
@@ -947,10 +1128,12 @@
  * CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
+#define OMAP4430_ISS_STATDEP_WIDTH                              0x1
 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
+#define OMAP4430_IVAHD_DYNDEP_WIDTH                             0x1
 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
@@ -959,10 +1142,12 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
+#define OMAP4430_IVAHD_STATDEP_WIDTH                            0x1
 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
+#define OMAP4430_L3INIT_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
@@ -970,6 +1155,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
+#define OMAP4430_L3INIT_STATDEP_WIDTH                           0x1
 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
@@ -977,6 +1163,7 @@
  * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
+#define OMAP4430_L3_1_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
@@ -986,6 +1173,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
+#define OMAP4430_L3_1_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
@@ -995,6 +1183,7 @@
  * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
+#define OMAP4430_L3_2_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
@@ -1004,10 +1193,12 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
+#define OMAP4430_L3_2_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
 /* Used by CM_L3_1_DYNAMICDEP */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
+#define OMAP4430_L4CFG_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
@@ -1015,10 +1206,12 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
+#define OMAP4430_L4CFG_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
+#define OMAP4430_L4PER_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
@@ -1026,10 +1219,12 @@
  * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
+#define OMAP4430_L4PER_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
+#define OMAP4430_L4SEC_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
@@ -1037,10 +1232,12 @@
  * CM_SDMA_STATICDEP
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
+#define OMAP4430_L4SEC_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
+#define OMAP4430_L4WKUP_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
@@ -1048,6 +1245,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
+#define OMAP4430_L4WKUP_STATDEP_WIDTH                           0x1
 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
@@ -1055,6 +1253,7 @@
  * CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
+#define OMAP4430_MEMIF_DYNDEP_WIDTH                             0x1
 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
@@ -1064,6 +1263,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
+#define OMAP4430_MEMIF_STATDEP_WIDTH                            0x1
 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
@@ -1073,6 +1273,7 @@
  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
+#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH                      0x3
 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
@@ -1082,6 +1283,7 @@
  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
+#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH                      0x7
 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
 
 /*
@@ -1089,69 +1291,68 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_MODULEMODE_SHIFT                               0
+#define OMAP4430_MODULEMODE_WIDTH                               0x2
 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4460_MPU_DYNDEP_SHIFT                               19
+#define OMAP4460_MPU_DYNDEP_WIDTH                               0x1
 #define OMAP4460_MPU_DYNDEP_MASK                                (1 << 19)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH                      0x1
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 
 /* Used by CM_ALWON_USBPHY_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
@@ -1160,126 +1361,157 @@
  * CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
+#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
+#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH                     0x1
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH                  0x1
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH              0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
+#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                        8
+#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH                        0x1
 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
+#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_XCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
+#define OMAP4430_OVERRIDE_ENABLE_WIDTH                          0x1
 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
+#define OMAP4430_PAD_CLKS_GATE_WIDTH                            0x1
 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
+#define OMAP4430_PERF_CURRENT_WIDTH                             0x8
 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 
 /*
@@ -1288,74 +1520,85 @@
  * CM_IVA_DVFS_PERF_TESLA
  */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
+#define OMAP4430_PERF_REQ_WIDTH                                 0x8
 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
+#define OMAP4430_PHASE1_COMPLETED_WIDTH                         0x1
 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
+#define OMAP4430_PHASE2A_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
+#define OMAP4430_PHASE2B_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
+#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH                         0x2
 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
+#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH                       0x2
 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
 /* Used by CM_DYN_DEP_PRESCAL */
 #define OMAP4430_PRESCAL_SHIFT                                  0
+#define OMAP4430_PRESCAL_WIDTH                                  0x6
 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_WIDTH                                    0x5
 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
+#define OMAP4430_SAR_MODE_WIDTH                                 0x1
 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
+#define OMAP4430_SCALE_FCLK_WIDTH                               0x1
 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_WIDTH                                   0x2
 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
+#define OMAP4430_SDMA_DYNDEP_WIDTH                              0x1
 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
+#define OMAP4430_SDMA_STATDEP_WIDTH                             0x1
 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
+#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH                         0x1
 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 
 /*
  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_TESLA_TESLA_CLKCTRL
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
+#define OMAP4430_STBYST_WIDTH                                   0x1
 #define OMAP4430_STBYST_MASK                                    (1 << 18)
 
 /*
@@ -1364,10 +1607,12 @@
  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
+#define OMAP4430_ST_DPLL_CLK_WIDTH                              0x1
 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
@@ -1375,14 +1620,17 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
+#define OMAP4430_ST_DPLL_CLKOUT_WIDTH                           0x1
 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
+#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH                         0x1
 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
@@ -1390,6 +1638,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
@@ -1397,14 +1646,17 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
 
 /*
@@ -1413,18 +1665,22 @@
  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_WIDTH                             0x1
 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
+#define OMAP4430_SYS_CLKSEL_WIDTH                               0x3
 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
+#define OMAP4430_TESLA_DYNDEP_WIDTH                             0x1
 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
+#define OMAP4430_TESLA_STATDEP_WIDTH                            0x1
 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
@@ -1433,13 +1689,16 @@
  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
+#define OMAP4430_WINDOWSIZE_WIDTH                               0x4
 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_WIDTH                                  0x3
 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_WIDTH                                  0x6
 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 389f9f8b570c..7f07ab02a5b3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,8 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm.h"
@@ -36,7 +35,7 @@
 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
 
 static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
 };
 
 u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 088bbad73db5..57b2f3c2fbf3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -71,6 +71,7 @@
 #define OMAP24XX_CM_FCLKEN2                             0x0004
 #define OMAP24XX_CM_ICLKEN4                             0x001c
 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
+#define OMAP24XX_CM_IDLEST4                             0x002c
 
 #define OMAP2430_CM_IDLEST3                             0x0028
 
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index c1875862679f..48daac2581b4 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -24,9 +24,10 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <plat/mcspi.h>
-#include <plat/nand.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
+#include "common.h"
 #include "common-board-devices.h"
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
@@ -119,8 +120,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
         }
 
         if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
+                pr_info("NAND: Unable to find configuration in GPMC\n");
                 return;
         }
 
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 069f9725b1c3..17950c6e130b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,11 +17,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
-#include <plat/board.h>
-#include <plat/mux.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 1f65b1871c23..7045e4d61ac3 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -26,11 +26,18 @@
 #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #ifndef __ASSEMBLER__
 
+#include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
-#include <plat/common.h>
+
 #include <asm/proc-fns.h>
 
+#include <plat/cpu.h>
+#include <plat/serial.h>
+#include <plat/common.h>
+
+#define OMAP_INTC_START         NR_IRQS
+
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
@@ -278,6 +285,11 @@ extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
+
+extern void omap4_cpu_die(unsigned int cpu);
+
+extern struct smp_operations omap4_smp_ops;
+
 extern void omap5_secondary_startup(void);
 #endif
 
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 3223b81e7532..d1ff8399a222 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,9 +15,9 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8cdc8531b60..a89e8256fd0e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,12 +16,12 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
-#include <mach/ctrl_module_core_44xx.h>
-#include <mach/ctrl_module_wkup_44xx.h>
-#include <mach/ctrl_module_pad_core_44xx.h>
-#include <mach/ctrl_module_pad_wkup_44xx.h>
+#include "ctrl_module_core_44xx.h"
+#include "ctrl_module_wkup_44xx.h"
+#include "ctrl_module_pad_core_44xx.h"
+#include "ctrl_module_pad_wkup_44xx.h"
 
-#include <plat/am33xx.h>
+#include "am33xx.h"
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
@@ -354,6 +354,7 @@
 
 /* AM33XX CONTROL_STATUS bitfields (partial) */
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f2a49a48ef59..bc2756959be5 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -28,7 +28,6 @@
 #include <linux/cpu_pm.h>
 
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
index 01970824e0e5..01970824e0e5 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
index c88420de1151..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
index 17c9b37042c0..17c9b37042c0 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h
index a0af9baec3f7..a0af9baec3f7 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h
diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/mach-omap2/debug-devices.h
new file mode 100644
index 000000000000..a4edbd2f7484
--- /dev/null
+++ b/arch/arm/mach-omap2/debug-devices.h
@@ -0,0 +1,9 @@
+#ifndef _OMAP_DEBUG_DEVICES_H
+#define _OMAP_DEBUG_DEVICES_H
+
+#include <linux/types.h>
+
+/* for TI reference platforms sharing the same debug card */
+extern int debug_card_init(u32 addr, unsigned gpio);
+
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c00c68961bb8..c8c211731d26 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -17,21 +17,20 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 
 #include "iomap.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 
+#include "soc.h"
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
@@ -112,7 +111,7 @@ static struct resource omap2cam_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = INT_24XX_CAM_IRQ,
+                .start          = 24 + OMAP_INTC_START,
                 .flags          = IORESOURCE_IRQ,
         }
 };
@@ -201,7 +200,7 @@ static struct resource omap3isp_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = INT_34XX_CAM_IRQ,
+                .start          = 24 + OMAP_INTC_START,
                 .flags          = IORESOURCE_IRQ,
         }
 };
@@ -385,7 +384,7 @@ static inline void omap_init_hdmi_audio(void) {}
 
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
@@ -434,37 +433,24 @@ static void omap_init_mcspi(void)
 static inline void omap_init_mcspi(void) {}
 #endif
 
-static struct resource omap2_pmu_resource = {
-        .start  = 3,
-        .end    = 3,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct resource omap3_pmu_resource = {
-        .start  = INT_34XX_BENCH_MPU_EMUL,
-        .end    = INT_34XX_BENCH_MPU_EMUL,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct platform_device omap_pmu_device = {
-        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
-        .num_resources  = 1,
-};
-
-static void omap_init_pmu(void)
+/**
+ * omap_init_rng - bind the RNG hwmod to the RNG omap_device
+ *
+ * Bind the RNG hwmod to the RNG omap_device.  No return value.
+ */
+static void omap_init_rng(void)
 {
-        if (cpu_is_omap24xx())
-                omap_pmu_device.resource = &omap2_pmu_resource;
-        else if (cpu_is_omap34xx())
-                omap_pmu_device.resource = &omap3_pmu_resource;
-        else
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("rng");
+        if (!oh)
                 return;
 
-        platform_device_register(&omap_pmu_device);
+        pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-
 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 
 #ifdef CONFIG_ARCH_OMAP2
@@ -475,7 +461,7 @@ static struct resource omap2_sham_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = INT_24XX_SHA1MD5,
+                .start  = 51 + OMAP_INTC_START,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -493,7 +479,7 @@ static struct resource omap3_sham_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = INT_34XX_SHA1MD52_IRQ,
+                .start  = 49 + OMAP_INTC_START,
                 .flags  = IORESOURCE_IRQ,
         },
         {
@@ -631,6 +617,10 @@ static inline void omap_init_vout(void) {}
 
 static int __init omap2_init_devices(void)
 {
+        /* Enable dummy states for those platforms without pinctrl support */
+        if (!of_have_populated_dt())
+                pinctrl_provide_dummies();
+
         /*
          * please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
@@ -645,8 +635,8 @@ static int __init omap2_init_devices(void)
                 omap_init_mcpdm();
                 omap_init_mcspi();
         }
-        omap_init_pmu();
         omap_init_sti();
+        omap_init_rng();
         omap_init_sham();
         omap_init_aes();
         omap_init_vout();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index ee40739b55c0..1011995f150a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -76,14 +76,14 @@ struct omap_dss_hwmod_data {
         const int id;
 };
 
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
         { "dss_venc", "omapdss_venc", -1 },
 };
 
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
@@ -91,7 +91,7 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
         { "dss_dsi1", "omapdss_dsi", 0 },
 };
 
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
@@ -220,7 +220,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name,
 
         ohs[0] = oh;
         od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
-        if (!od) {
+        if (IS_ERR(od)) {
                 pr_err("Could not alloc omap_device for %s\n", pdev_name);
                 r = -ENOMEM;
                 goto err;
@@ -487,7 +487,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk)
-                        clk_enable(oc->_clk);
+                        clk_prepare_enable(oc->_clk);
 
         dispc_disable_outputs();
 
@@ -514,7 +514,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk)
-                        clk_disable(oc->_clk);
+                        clk_disable_unprepare(oc->_clk);
 
         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f6a81f..814e1808e158 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,9 +28,9 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
         const struct dpll_data *dd;
         int i = 0;
         int ret = -EINVAL;
+        const char *clk_name;
 
         dd = clk->dpll_data;
+        clk_name = __clk_get_name(clk);
 
         state <<= __ffs(dd->idlest_mask);
 
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 
         if (i == MAX_DPLL_WAIT_TRIES) {
                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-                       clk->name, (state) ? "locked" : "bypassed");
+                       clk_name, (state) ? "locked" : "bypassed");
         } else {
                 pr_debug("clock: %s transition to '%s' in %d loops\n",
-                         clk->name, (state) ? "locked" : "bypassed", i);
+                         clk_name, (state) ? "locked" : "bypassed", i);
 
                 ret = 0;
         }
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
         unsigned long fint;
         u16 f = 0;
 
-        fint = clk->dpll_data->clk_ref->rate / n;
+        fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
 
         pr_debug("clock: fint is %lu\n", fint);
 
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
         u8 state = 1;
         int r = 0;
 
-        pr_debug("clock: locking DPLL %s\n", clk->name);
+        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
 
         dd = clk->dpll_data;
         state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
                 return -EINVAL;
 
         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 clk->name);
+                 __clk_get_name(clk));
 
         ai = omap3_dpll_autoidle_read(clk);
 
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
                 return -EINVAL;
 
-        pr_debug("clock: stopping DPLL %s\n", clk->name);
+        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
 
         ai = omap3_dpll_autoidle_read(clk);
 
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
         unsigned long fint, clkinp; /* watch out for overflow */
 
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
         fint = (clkinp / n) * m;
 
         if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
         unsigned long clkinp, sd; /* watch out for overflow */
         int mod1, mod2;
 
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
 
         /*
          * target sigma-delta to near 250MHz
@@ -311,7 +313,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
          * Set jitter correction. No jitter correction for OMAP4 and 3630
          * since freqsel field is no longer present
          */
-        if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+        if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
                 v = __raw_readl(dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 {
         int r;
         struct dpll_data *dd;
+        struct clk *parent;
 
         dd = clk->dpll_data;
         if (!dd)
                 return -EINVAL;
 
-        if (clk->rate == dd->clk_bypass->rate) {
-                WARN_ON(clk->parent != dd->clk_bypass);
+        parent = __clk_get_parent(clk);
+
+        if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+                WARN_ON(parent != dd->clk_bypass);
                 r = _omap3_noncore_dpll_bypass(clk);
         } else {
-                WARN_ON(clk->parent != dd->clk_ref);
+                WARN_ON(parent != dd->clk_ref);
                 r = _omap3_noncore_dpll_lock(clk);
         }
         /*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
         struct clk *new_parent = NULL;
-        unsigned long hw_rate;
+        unsigned long hw_rate, bypass_rate;
         u16 freqsel = 0;
         struct dpll_data *dd;
         int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
         omap2_clk_enable(dd->clk_bypass);
         omap2_clk_enable(dd->clk_ref);
 
-        if (dd->clk_bypass->rate == rate &&
+        bypass_rate = __clk_get_rate(dd->clk_bypass);
+        if (bypass_rate == rate &&
             (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
 
@@ -471,7 +477,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                         return -EINVAL;
 
                 /* No freqsel on OMAP4 and OMAP3630 */
-                if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+                if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
                         freqsel = _omap3_dpll_compute_freqsel(clk,
                                                 dd->last_rounded_n);
                         if (!freqsel)
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                 }
 
                 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                         clk->name, rate);
+                         __clk_get_name(clk), rate);
 
                 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
                                                  dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
         if (!dd->autoidle_reg) {
                 pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                 return;
         }
 
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
         if (!dd->autoidle_reg) {
                 pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                 return;
         }
 
@@ -617,25 +623,30 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
         unsigned long rate;
         u32 v;
         struct clk *pclk;
+        unsigned long parent_rate;
 
         /* Walk up the parents of clk, looking for a DPLL */
-        pclk = clk->parent;
+        pclk = __clk_get_parent(clk);
         while (pclk && !pclk->dpll_data)
-                pclk = pclk->parent;
+                pclk = __clk_get_parent(pclk);
 
-        /* clk does not have a DPLL as a parent? */
-        WARN_ON(!pclk);
+        /* clk does not have a DPLL as a parent?  error in the clock data */
+        if (!pclk) {
+                WARN_ON(1);
+                return 0;
+        }
 
         dd = pclk->dpll_data;
 
         WARN_ON(!dd->enable_mask);
 
+        parent_rate = __clk_get_rate(__clk_get_parent(clk));
         v = __raw_readl(dd->control_reg) & dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
-                rate = clk->parent->rate;
+                rate = parent_rate;
         else
-                rate = clk->parent->rate * 2;
+                rate = parent_rate * 2;
         return rate;
 }
 
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 9c6a296b3dc3..09d0ccccb861 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,9 +15,9 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index a636ebc16b39..98388109f22a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -30,7 +30,7 @@
 #include <plat/omap-pm.h>
 #endif
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 static struct platform_device *omap_dsp_pdev;
 
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index e28e761b7ab9..b3566f68a559 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -21,8 +21,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ad7d489b0de..d1058f16fb40 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -60,6 +61,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
         pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
         if (!pdata->regs) {
                 pr_err("gpio%d: Memory allocation failed\n", id);
+                kfree(pdata);
                 return -ENOMEM;
         }
 
@@ -121,6 +123,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 break;
         default:
                 WARN(1, "Invalid gpio bank_type\n");
+                kfree(pdata->regs);
                 kfree(pdata);
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 386dec8d2351..4acf497faeb3 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -13,23 +13,31 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/cpu.h>
-#include <plat/nand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
 
-static struct resource gpmc_nand_resource = {
-        .flags          = IORESOURCE_MEM,
+#include "soc.h"
+
+static struct resource gpmc_nand_resource[] = {
+        {
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .flags          = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device gpmc_nand_device = {
         .name           = "omap2-nand",
         .id             = 0,
-        .num_resources  = 1,
-        .resource       = &gpmc_nand_resource,
+        .num_resources  = ARRAY_SIZE(gpmc_nand_resource),
+        .resource       = gpmc_nand_resource,
 };
 
 static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
@@ -75,6 +83,7 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
                 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
         gpmc_cs_configure(gpmc_nand_data->cs,
                         GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
+        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
         if (err)
                 return err;
@@ -90,12 +99,19 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
-                                &gpmc_nand_data->phys_base);
+                                (unsigned long *)&gpmc_nand_resource[0].start);
         if (err < 0) {
                 dev_err(dev, "Cannot request GPMC CS\n");
                 return err;
         }
 
+        gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
+                                                        NAND_IO_SIZE - 1;
+
+        gpmc_nand_resource[1].start =
+                                gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+        gpmc_nand_resource[2].start =
+                                gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
          /* Set timings in GPMC */
         err = omap2_nand_gpmc_retime(gpmc_nand_data);
         if (err < 0) {
@@ -108,6 +124,8 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
                 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
         }
 
+        gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
+
         err = platform_device_register(&gpmc_nand_device);
         if (err < 0) {
                 dev_err(dev, "Unable to register NAND device\n");
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index a0fa9bb2bda5..916716e1da3b 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,19 +15,27 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/cpu.h>
-#include <plat/onenand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
 
+#include "soc.h"
+
+#define ONENAND_IO_SIZE SZ_128K
+
 static struct omap_onenand_platform_data *gpmc_onenand_data;
 
+static struct resource gpmc_onenand_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+
 static struct platform_device gpmc_onenand_device = {
         .name           = "omap2-onenand",
         .id             = -1,
+        .num_resources  = 1,
+        .resource       = &gpmc_onenand_resource,
 };
 
 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
@@ -390,6 +398,8 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 
 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
+        int err;
+
         gpmc_onenand_data = _onenand_data;
         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
         gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
@@ -401,8 +411,19 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
 
+        err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
+                                (unsigned long *)&gpmc_onenand_resource.start);
+        if (err < 0) {
+                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                return;
+        }
+
+        gpmc_onenand_resource.end = gpmc_onenand_resource.start +
+                                                        ONENAND_IO_SIZE - 1;
+
         if (platform_device_register(&gpmc_onenand_device) < 0) {
-                printk(KERN_ERR "Unable to register OneNAND device\n");
+                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                gpmc_cs_free(gpmc_onenand_data->cs);
                 return;
         }
 }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index ba10c24f3d8d..565475310374 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,9 +17,10 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
-#include <plat/board.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
+
+#include "soc.h"
 
 static struct omap_smc91x_platform_data *gpmc_cfg;
 
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h
new file mode 100644
index 000000000000..b64fbee4d567
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smc91x.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
+
+#define GPMC_TIMINGS_SMC91C96   (1 << 4)
+#define GPMC_MUX_ADD_DATA       (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
+#define GPMC_READ_MON           (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
+#define GPMC_WRITE_MON          (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
+
+struct omap_smc91x_platform_data {
+        int     cs;
+        int     gpio_irq;
+        int     gpio_pwrdwn;
+        int     gpio_reset;
+        int     wait_pin;       /* Optional GPMC_CONFIG1_WAITPINSELECT */
+        u32     flags;
+        int     (*retime)(void);
+};
+
+#if defined(CONFIG_SMC91X) || \
+        defined(CONFIG_SMC91X_MODULE)
+
+extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
+
+#else
+
+#define board_smc91x_data       NULL
+
+static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
+{
+}
+
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index b6c77be3e8f7..249a0b440cd6 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -20,9 +20,8 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 
-#include <plat/board.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct resource gpmc_smsc911x_resources[] = {
         [0] = {
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h
new file mode 100644
index 000000000000..ea6c9c88c725
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+ *
+ * Copyright (C) 2009 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
+
+struct omap_smsc911x_platform_data {
+        int     id;
+        int     cs;
+        int     gpio_irq;
+        int     gpio_reset;
+        u32     flags;
+};
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+
+extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
+
+#else
+
+static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
+{
+}
+
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index b2b5759ab0fe..5ac5cf30406a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -24,11 +24,20 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
 
+#include <plat/cpu.h>
+#include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/omap_device.h>
+
+#include "soc.h"
+#include "common.h"
+
+#define DEVICE_NAME             "omap-gpmc"
 
 /* GPMC register offsets */
 #define GPMC_REVISION           0x00
@@ -78,6 +87,21 @@
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
 
+#define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
+#define GPMC_REVISION_MINOR(l)          (l & 0xf)
+
+#define GPMC_HAS_WR_ACCESS              0x1
+#define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+
+/* XXX: Only NAND irq has been considered,currently these are the only ones used
+ */
+#define GPMC_NR_IRQ             2
+
+struct gpmc_client_irq  {
+        unsigned                irq;
+        u32                     bitmask;
+};
+
 /* Structure to save gpmc cs context */
 struct gpmc_cs_config {
         u32 config1;
@@ -105,12 +129,19 @@ struct omap3_gpmc_regs {
         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 };
 
+static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
+static struct irq_chip gpmc_irq_chip;
+static unsigned gpmc_irq_start;
+
 static struct resource  gpmc_mem_root;
 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
-
+static struct device *gpmc_dev;
+static int gpmc_irq;
+static resource_size_t phys_base, mem_size;
+static unsigned gpmc_capability;
 static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
@@ -279,7 +310,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
         div = gpmc_cs_calc_divider(cs, t->sync_clk);
         if (div < 0)
-                return -1;
+                return div;
 
         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
@@ -300,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 
-        if (cpu_is_omap34xx()) {
+        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+        if (gpmc_capability & GPMC_HAS_WR_ACCESS)
                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-        }
 
         /* caller is expected to have initialized CONFIG1 to cover
          * at least sync vs async
@@ -413,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
         return r;
 }
 
+static int gpmc_cs_delete_mem(int cs)
+{
+        struct resource *res = &gpmc_cs_mem[cs];
+        int r;
+
+        spin_lock(&gpmc_mem_lock);
+        r = release_resource(&gpmc_cs_mem[cs]);
+        res->start = 0;
+        res->end = 0;
+        spin_unlock(&gpmc_mem_lock);
+
+        return r;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -682,7 +727,148 @@ int gpmc_prefetch_reset(int cs)
 }
 EXPORT_SYMBOL(gpmc_prefetch_reset);
 
-static void __init gpmc_mem_init(void)
+void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
+{
+        reg->gpmc_status = gpmc_base + GPMC_STATUS;
+        reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
+                                GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
+        reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
+                                GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
+        reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
+                                GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
+        reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
+        reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
+        reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
+        reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
+        reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
+        reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
+        reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
+        reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
+        reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
+}
+
+int gpmc_get_client_irq(unsigned irq_config)
+{
+        int i;
+
+        if (hweight32(irq_config) > 1)
+                return 0;
+
+        for (i = 0; i < GPMC_NR_IRQ; i++)
+                if (gpmc_client_irq[i].bitmask & irq_config)
+                        return gpmc_client_irq[i].irq;
+
+        return 0;
+}
+
+static int gpmc_irq_endis(unsigned irq, bool endis)
+{
+        int i;
+        u32 regval;
+
+        for (i = 0; i < GPMC_NR_IRQ; i++)
+                if (irq == gpmc_client_irq[i].irq) {
+                        regval = gpmc_read_reg(GPMC_IRQENABLE);
+                        if (endis)
+                                regval |= gpmc_client_irq[i].bitmask;
+                        else
+                                regval &= ~gpmc_client_irq[i].bitmask;
+                        gpmc_write_reg(GPMC_IRQENABLE, regval);
+                        break;
+                }
+
+        return 0;
+}
+
+static void gpmc_irq_disable(struct irq_data *p)
+{
+        gpmc_irq_endis(p->irq, false);
+}
+
+static void gpmc_irq_enable(struct irq_data *p)
+{
+        gpmc_irq_endis(p->irq, true);
+}
+
+static void gpmc_irq_noop(struct irq_data *data) { }
+
+static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
+
+static int gpmc_setup_irq(void)
+{
+        int i;
+        u32 regval;
+
+        if (!gpmc_irq)
+                return -EINVAL;
+
+        gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
+        if (IS_ERR_VALUE(gpmc_irq_start)) {
+                pr_err("irq_alloc_descs failed\n");
+                return gpmc_irq_start;
+        }
+
+        gpmc_irq_chip.name = "gpmc";
+        gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
+        gpmc_irq_chip.irq_enable = gpmc_irq_enable;
+        gpmc_irq_chip.irq_disable = gpmc_irq_disable;
+        gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
+        gpmc_irq_chip.irq_ack = gpmc_irq_noop;
+        gpmc_irq_chip.irq_mask = gpmc_irq_noop;
+        gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
+
+        gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
+        gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
+
+        for (i = 0; i < GPMC_NR_IRQ; i++) {
+                gpmc_client_irq[i].irq = gpmc_irq_start + i;
+                irq_set_chip_and_handler(gpmc_client_irq[i].irq,
+                                        &gpmc_irq_chip, handle_simple_irq);
+                set_irq_flags(gpmc_client_irq[i].irq,
+                                IRQF_VALID | IRQF_NOAUTOEN);
+        }
+
+        /* Disable interrupts */
+        gpmc_write_reg(GPMC_IRQENABLE, 0);
+
+        /* clear interrupts */
+        regval = gpmc_read_reg(GPMC_IRQSTATUS);
+        gpmc_write_reg(GPMC_IRQSTATUS, regval);
+
+        return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
+}
+
+static __devexit int gpmc_free_irq(void)
+{
+        int i;
+
+        if (gpmc_irq)
+                free_irq(gpmc_irq, NULL);
+
+        for (i = 0; i < GPMC_NR_IRQ; i++) {
+                irq_set_handler(gpmc_client_irq[i].irq, NULL);
+                irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
+                irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
+        }
+
+        irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
+
+        return 0;
+}
+
+static void __devexit gpmc_mem_exit(void)
+{
+        int cs;
+
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                if (!gpmc_cs_mem_enabled(cs))
+                        continue;
+                gpmc_cs_delete_mem(cs);
+        }
+
+}
+
+static void __devinit gpmc_mem_init(void)
 {
         int cs;
         unsigned long boot_rom_space = 0;
@@ -709,83 +895,120 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-static int __init gpmc_init(void)
+static __devinit int gpmc_probe(struct platform_device *pdev)
 {
-        u32 l, irq;
-        int cs, ret = -EINVAL;
-        int gpmc_irq;
-        char *ck = NULL;
-
-        if (cpu_is_omap24xx()) {
-                ck = "core_l3_ck";
-                if (cpu_is_omap2420())
-                        l = OMAP2420_GPMC_BASE;
-                else
-                        l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = INT_34XX_GPMC_IRQ;
-        } else if (cpu_is_omap34xx()) {
-                ck = "gpmc_fck";
-                l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = INT_34XX_GPMC_IRQ;
-        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
-                /* Base address and irq number are same for OMAP4/5 */
-                ck = "gpmc_ck";
-                l = OMAP44XX_GPMC_BASE;
-                gpmc_irq = OMAP44XX_IRQ_GPMC;
+        u32 l;
+        struct resource *res;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL)
+                return -ENOENT;
+
+        phys_base = res->start;
+        mem_size = resource_size(res);
+
+        gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!gpmc_base) {
+                dev_err(&pdev->dev, "error: request memory / ioremap\n");
+                return -EADDRNOTAVAIL;
         }
 
-        if (WARN_ON(!ck))
-                return ret;
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res == NULL)
+                dev_warn(&pdev->dev, "Failed to get resource: irq\n");
+        else
+                gpmc_irq = res->start;
 
-        gpmc_l3_clk = clk_get(NULL, ck);
+        gpmc_l3_clk = clk_get(&pdev->dev, "fck");
         if (IS_ERR(gpmc_l3_clk)) {
-                printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
-                BUG();
+                dev_err(&pdev->dev, "error: clk_get\n");
+                gpmc_irq = 0;
+                return PTR_ERR(gpmc_l3_clk);
         }
 
-        gpmc_base = ioremap(l, SZ_4K);
-        if (!gpmc_base) {
-                clk_put(gpmc_l3_clk);
-                printk(KERN_ERR "Could not get GPMC register memory\n");
-                BUG();
-        }
+        clk_prepare_enable(gpmc_l3_clk);
 
-        clk_enable(gpmc_l3_clk);
+        gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
-        printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-        /* Set smart idle mode and automatic L3 clock gating */
-        l = gpmc_read_reg(GPMC_SYSCONFIG);
-        l &= 0x03 << 3;
-        l |= (0x02 << 3) | (1 << 0);
-        gpmc_write_reg(GPMC_SYSCONFIG, l);
+        if (GPMC_REVISION_MAJOR(l) > 0x4)
+                gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
+                 GPMC_REVISION_MINOR(l));
+
         gpmc_mem_init();
 
-        /* initalize the irq_chained */
-        irq = OMAP_GPMC_IRQ_BASE;
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-                irq_set_chip_and_handler(irq, &dummy_irq_chip,
-                                                handle_simple_irq);
-                set_irq_flags(irq, IRQF_VALID);
-                irq++;
-        }
+        if (IS_ERR_VALUE(gpmc_setup_irq()))
+                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+
+        return 0;
+}
+
+static __devexit int gpmc_remove(struct platform_device *pdev)
+{
+        gpmc_free_irq();
+        gpmc_mem_exit();
+        gpmc_dev = NULL;
+        return 0;
+}
+
+static struct platform_driver gpmc_driver = {
+        .probe          = gpmc_probe,
+        .remove         = __devexit_p(gpmc_remove),
+        .driver         = {
+                .name   = DEVICE_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
 
-        ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
-        if (ret)
-                pr_err("gpmc: irq-%d could not claim: err %d\n",
-                                                gpmc_irq, ret);
-        return ret;
+static __init int gpmc_init(void)
+{
+        return platform_driver_register(&gpmc_driver);
 }
+
+static __exit void gpmc_exit(void)
+{
+        platform_driver_unregister(&gpmc_driver);
+
+}
+
 postcore_initcall(gpmc_init);
+module_exit(gpmc_exit);
+
+static int __init omap_gpmc_init(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char *oh_name = "gpmc";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
+
+        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
+
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+}
+postcore_initcall(omap_gpmc_init);
 
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
-        u8 cs;
+        int i;
+        u32 regval;
+
+        regval = gpmc_read_reg(GPMC_IRQSTATUS);
+
+        if (!regval)
+                return IRQ_NONE;
+
+        for (i = 0; i < GPMC_NR_IRQ; i++)
+                if (regval & gpmc_client_irq[i].bitmask)
+                        generic_handle_irq(gpmc_client_irq[i].irq);
 
-        /* check cs to invoke the irq */
-        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
-        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
-                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+        gpmc_write_reg(GPMC_IRQSTATUS, regval);
 
         return IRQ_HANDLED;
 }
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cdd6dda03828..e003f2bba30c 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -29,7 +29,7 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/hdq1w.h>
+#include "hdq1w.h"
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap2/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h
new file mode 100644
index 000000000000..0c1efc846d8d
--- /dev/null
+++ b/arch/arm/mach-omap2/hdq1w.h
@@ -0,0 +1,36 @@
+/*
+ * Shared macros and function prototypes for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
+#define ARCH_ARM_MACH_OMAP2_HDQ1W_H
+
+#include <plat/omap_hwmod.h>
+
+/*
+ * XXX A future cleanup patch should modify
+ * drivers/w1/masters/omap_hdq.c to use these macros
+ */
+#define HDQ_CTRL_STATUS_OFFSET                  0x0c
+#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT       5
+
+
+extern int omap_hdq1w_reset(struct omap_hwmod *oh);
+
+#endif
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9675d8d1822..4d3a6324155f 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -15,9 +15,10 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
-#include <plat/mux.h>
 #include <plat/omap_device.h>
 
 #include "mux.h"
@@ -522,7 +523,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
         dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 
         od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
-        if (!od) {
+        if (IS_ERR(od)) {
                 pr_err("Could not allocate od for %s\n", name);
                 goto put_pdev;
         }
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index a12e224eb97d..fc57e67b321f 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -19,7 +19,6 @@
  *
  */
 
-#include <plat/cpu.h>
 #include <plat/i2c.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 40373db649aa..cf2362ccb234 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,10 +22,10 @@
 #include <asm/cputype.h>
 
 #include "common.h"
-#include <plat/cpu.h>
 
-#include <mach/id.h>
+#include "id.h"
 
+#include "soc.h"
 #include "control.h"
 
 static unsigned int omap_revision;
@@ -161,9 +161,8 @@ void __init omap2xxx_check_revision(void)
         }
 
         if (j == ARRAY_SIZE(omap_ids)) {
-                printk(KERN_ERR "Unknown OMAP device type. "
-                                "Handling it as OMAP%04x\n",
-                                omap_ids[i].type >> 16);
+                pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
+                       omap_ids[i].type >> 16);
                 j = i;
         }
 
diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/id.h
index 02ed3aa56f1e..02ed3aa56f1e 100644
--- a/arch/arm/mach-omap2/include/mach/id.h
+++ b/arch/arm/mach-omap2/id.h
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 775fdc3b000b..2e9486940ead 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -8,5 +8,3 @@
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
 extern void __init zoom_display_init(void);
-
-#define ZOOM2_HEADSET_EXTMUTE_GPIO      153
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
index be4d290d57ee..5621cc59c9f4 100644
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
index 78edf9d33f71..54492dbf6973 100644
--- a/arch/arm/mach-omap2/include/mach/hardware.h
+++ b/arch/arm/mach-omap2/include/mach/hardware.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/hardware.h
  */
-
-#include <plat/hardware.h>
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index 44dab7725696..ba5282cafa42 100644
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/irqs.h
  */
-
-#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
deleted file mode 100644
index 323675f21b69..000000000000
--- a/arch/arm/mach-omap2/include/mach/smp.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/smp.h
- */
-
-#include <plat/smp.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981ff5c5..4234d28dc171 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,6 +33,7 @@
 #include <plat/multi.h>
 #include <plat/dma.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
@@ -523,6 +524,8 @@ void __init am33xx_init_early(void)
         am33xx_voltagedomains_init();
         am33xx_powerdomains_init();
         am33xx_clockdomains_init();
+        am33xx_hwmod_init();
+        omap_hwmod_init_postsetup();
         am33xx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index bcd83db41bbc..3926f370448f 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -23,8 +23,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 
@@ -49,6 +48,8 @@
 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
+#define INTCPS_NR_MIR_REGS      3
+#define INTCPS_NR_IRQS          96
 
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -107,9 +108,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
         unsigned long tmp;
 
         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
-        printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
-                         "(revision %ld.%ld) with %d interrupts\n",
-                         bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+        pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
+                bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 
         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
         tmp |= 1 << 1;  /* soft reset */
diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
new file mode 100644
index 000000000000..b8b5641379b0
--- /dev/null
+++ b/arch/arm/mach-omap2/l3_2xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+
+/* L3 CONNIDs */
+/* Display Sub system (DSS) */
+#define OMAP2_L3_CORE_FW_CONNID_DSS                     8
+
+#endif
diff --git a/arch/arm/mach-omap2/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h
new file mode 100644
index 000000000000..cde1938c5f82
--- /dev/null
+++ b/arch/arm/mach-omap2/l3_3xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+
+/* L3 Initiator IDs */
+/* Display Sub system (DSS) */
+#define OMAP3_L3_CORE_FW_INIT_ID_DSS                    29
+
+#endif
diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
new file mode 100644
index 000000000000..3f39cf8a35c6
--- /dev/null
+++ b/arch/arm/mach-omap2/l4_2xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+
+/* L4 CORE */
+/* Display Sub system (DSS) */
+#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION                     28
+#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION                    29
+#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION                     30
+#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION                     31
+#define OMAP2420_L4_CORE_FW_DSS_TA_REGION                       32
+
+#endif
diff --git a/arch/arm/mach-omap2/l4_3xxx.h b/arch/arm/mach-omap2/l4_3xxx.h
new file mode 100644
index 000000000000..881a858b1ffc
--- /dev/null
+++ b/arch/arm/mach-omap2/l4_3xxx.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+
+/* L4 CORE */
+#define OMAP3_L4_CORE_FW_I2C1_REGION                            21
+#define OMAP3_L4_CORE_FW_I2C1_TA_REGION                         22
+#define OMAP3_L4_CORE_FW_I2C2_REGION                            23
+#define OMAP3_L4_CORE_FW_I2C2_TA_REGION                         24
+#define OMAP3_L4_CORE_FW_I2C3_REGION                            73
+#define OMAP3_L4_CORE_FW_I2C3_TA_REGION                         74
+
+/* Display Sub system (DSS) */
+#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP                         2
+
+#define OMAP3_L4_CORE_FW_DSS_DSI_REGION                         104
+#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION                     3
+#define OMAP3_L4_CORE_FW_DSS_CORE_REGION                        4
+#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION                       4
+#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION                        5
+#define OMAP3_L4_CORE_FW_DSS_VENC_REGION                        6
+#define OMAP3_L4_CORE_FW_DSS_TA_REGION                          7
+#endif
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 6875be837d9f..0d974565f8ca 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -16,8 +16,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
+
 #include <plat/mailbox.h>
-#include <mach/irqs.h>
+
+#include "soc.h"
 
 #define MAILBOX_REVISION                0x000
 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 577cb77db26c..37f8f948047b 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -15,18 +15,15 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
-#include <mach/irqs.h>
 #include <plat/dma.h>
-#include <plat/cpu.h>
-#include <plat/mcbsp.h>
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
-#include "control.h"
-
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
  * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -34,112 +31,6 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
-/* McBSP1 internal signal muxing function for OMAP2/3 */
-static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
-                                   const char *src)
-{
-        u32 v;
-
-        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-
-        if (!strcmp(signal, "clkr")) {
-                if (!strcmp(src, "clkr"))
-                        v &= ~OMAP2_MCBSP1_CLKR_MASK;
-                else if (!strcmp(src, "clkx"))
-                        v |= OMAP2_MCBSP1_CLKR_MASK;
-                else
-                        return -EINVAL;
-        } else if (!strcmp(signal, "fsr")) {
-                if (!strcmp(src, "fsr"))
-                        v &= ~OMAP2_MCBSP1_FSR_MASK;
-                else if (!strcmp(src, "fsx"))
-                        v |= OMAP2_MCBSP1_FSR_MASK;
-                else
-                        return -EINVAL;
-        } else {
-                return -EINVAL;
-        }
-
-        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-
-        return 0;
-}
-
-/* McBSP4 internal signal muxing function for OMAP4 */
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX     (1 << 31)
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX    (1 << 30)
-static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
-                                   const char *src)
-{
-        u32 v;
-
-        /*
-         * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
-         * mux) is used */
-        v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-        if (!strcmp(signal, "clkr")) {
-                if (!strcmp(src, "clkr"))
-                        v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-                else if (!strcmp(src, "clkx"))
-                        v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-                else
-                        return -EINVAL;
-        } else if (!strcmp(signal, "fsr")) {
-                if (!strcmp(src, "fsr"))
-                        v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-                else if (!strcmp(src, "fsx"))
-                        v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-                else
-                        return -EINVAL;
-        } else {
-                return -EINVAL;
-        }
-
-        omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-        return 0;
-}
-
-/* McBSP CLKS source switching function */
-static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
-                                   const char *src)
-{
-        struct clk *fck_src;
-        char *fck_src_name;
-        int r;
-
-        if (!strcmp(src, "clks_ext"))
-                fck_src_name = "pad_fck";
-        else if (!strcmp(src, "clks_fclk"))
-                fck_src_name = "prcm_fck";
-        else
-                return -EINVAL;
-
-        fck_src = clk_get(dev, fck_src_name);
-        if (IS_ERR_OR_NULL(fck_src)) {
-                pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
-                       fck_src_name);
-                return -EINVAL;
-        }
-
-        pm_runtime_put_sync(dev);
-
-        r = clk_set_parent(clk, fck_src);
-        if (IS_ERR_VALUE(r)) {
-                pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
-                       "clks", fck_src_name);
-                clk_put(fck_src);
-                return -EINVAL;
-        }
-
-        pm_runtime_get_sync(dev);
-
-        clk_put(fck_src);
-
-        return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
         unsigned int w;
@@ -181,17 +72,11 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                 pdata->reg_size = 4;
                 pdata->has_ccr = true;
         }
-        pdata->set_clk_src = omap2_mcbsp_set_clk_src;
-
-        /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
-        if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
-                pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
 
-        /* On OMAP4 the McBSP4 port has 6 pin configuration */
-        if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
-                pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
-
-        if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+        if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
+                /* The FIFO has 128 locations */
+                pdata->buffer_size = 0x80;
+        } else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
                 if (id == 2)
                         /* The FIFO has 1024 + 256 locations */
                         pdata->buffer_size = 0x500;
@@ -227,7 +112,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 
 static int __init omap2_mcbsp_init(void)
 {
-        omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
+        if (!of_have_populated_dt())
+                omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index fb5bc6cf3773..9e57b4aadb06 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -23,6 +23,7 @@
 
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 9fe6829f4c16..701e17cba468 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,7 +486,7 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
                 default:
                         /* Nothing to be done */
                         break;
-                };
+                }
 
                 if (val >= 0) {
                         omap_mux_write(pad->partition, val,
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 414083b427df..e712d1725a8b 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -20,22 +20,17 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 
 #include "common.h"
 
 #include "powerdomain.h"
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  * Called with IRQs disabled
  */
-void __ref platform_cpu_die(unsigned int cpu)
+void __ref omap4_cpu_die(unsigned int cpu)
 {
         unsigned int boot_cpu = 0;
         void __iomem *base = omap_get_wakeupgen_base();
@@ -75,12 +70,3 @@ void __ref platform_cpu_die(unsigned int cpu)
                 pr_debug("CPU%u: spurious wakeup call\n", cpu);
         }
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 1be8bcb52e93..df298d46707c 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -14,7 +14,9 @@
 #include <linux/platform_device.h>
 
 #include <plat/iommu.h>
-#include <plat/irqs.h>
+
+#include "soc.h"
+#include "common.h"
 
 struct iommu_device {
         resource_size_t base;
@@ -29,7 +31,7 @@ static int num_iommu_devices;
 static struct iommu_device omap3_devices[] = {
         {
                 .base = 0x480bd400,
-                .irq = 24,
+                .irq = 24 + OMAP_INTC_START,
                 .pdata = {
                         .name = "isp",
                         .nr_tlb_entries = 8,
@@ -41,7 +43,7 @@ static struct iommu_device omap3_devices[] = {
 #if defined(CONFIG_OMAP_IOMMU_IVA2)
         {
                 .base = 0x5d000000,
-                .irq = 28,
+                .irq = 28 + OMAP_INTC_START,
                 .pdata = {
                         .name = "iva2",
                         .nr_tlb_entries = 32,
@@ -64,7 +66,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
 static struct iommu_device omap4_devices[] = {
         {
                 .base = OMAP4_MMU1_BASE,
-                .irq = OMAP44XX_IRQ_DUCATI_MMU,
+                .irq = 100 + OMAP44XX_IRQ_GIC_START,
                 .pdata = {
                         .name = "ducati",
                         .nr_tlb_entries = 32,
@@ -75,7 +77,7 @@ static struct iommu_device omap4_devices[] = {
         },
         {
                 .base = OMAP4_MMU2_BASE,
-                .irq = OMAP44XX_IRQ_TESLA_MMU,
+                .irq = 28 + OMAP44XX_IRQ_GIC_START,
                 .pdata = {
                         .name = "tesla",
                         .nr_tlb_entries = 32,
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 637a1bdf2ac4..ff4e6a0e9c7c 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -50,9 +50,8 @@
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <plat/omap44xx.h>
-
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d9ae4a53d818..e089e4d1ae38 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -19,7 +19,7 @@
 #include <asm/memblock.h>
 
 #include <plat/omap-secure.h>
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 
 static phys_addr_t omap_secure_memblock_base;
 
@@ -61,8 +61,8 @@ int __init omap_secure_ram_reserve_memblock(void)
 {
         u32 size = OMAP_SECURE_RAM_STORAGE;
 
-        size = ALIGN(size, SZ_1M);
-        omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
+        size = ALIGN(size, SECTION_SIZE);
+        omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index c90a43589abe..c90a43589abe 100644
--- a/arch/arm/mach-omap2/include/mach/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9a35adf91232..4d05fa8a4e48 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,11 +24,11 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 
-#include <mach/hardware.h>
-#include <mach/omap-secure.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-secure.h"
+#include "omap-wakeupgen.h"
 #include <asm/cputype.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
@@ -49,7 +49,7 @@ void __iomem *omap4_get_scu_base(void)
         return scu_base;
 }
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit omap4_secondary_init(unsigned int cpu)
 {
         /*
          * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@@ -77,7 +77,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         static struct clockdomain *cpu1_clkdm;
         static bool booted;
@@ -165,7 +165,7 @@ static void __init wakeup_secondary(void)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init omap4_smp_init_cpus(void)
 {
         unsigned int i = 0, ncores = 1, cpu_id;
 
@@ -196,7 +196,7 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
 
         /*
@@ -207,3 +207,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
                 scu_enable(scu_base);
         wakeup_secondary();
 }
+
+struct smp_operations omap4_smp_ops __initdata = {
+        .smp_init_cpus          = omap4_smp_init_cpus,
+        .smp_prepare_cpus       = omap4_smp_prepare_cpus,
+        .smp_secondary_init     = omap4_secondary_init,
+        .smp_boot_secondary     = omap4_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = omap4_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 05fdebfaa195..5d3b4f4f81ae 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -27,9 +27,10 @@
 
 #include <asm/hardware/gic.h>
 
-#include <mach/omap-wakeupgen.h>
-#include <mach/omap-secure.h>
+#include "omap-wakeupgen.h"
+#include "omap-secure.h"
 
+#include "soc.h"
 #include "omap4-sar-layout.h"
 #include "common.h"
 
@@ -46,7 +47,7 @@
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_SPINLOCK(wakeupgen_lock);
-static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_target_cpu[MAX_IRQS];
 static unsigned int irq_banks = MAX_NR_REG_BANKS;
 static unsigned int max_irqs = MAX_IRQS;
 static unsigned int omap_secure_apis;
@@ -229,13 +230,7 @@ static inline void omap4_irq_save_context(void)
         /* Save AuxBoot* registers */
         val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
         __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
-
-        /* Save SyncReq generation logic */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
         __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
 
         /* Save SyncReq generation logic */
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b0fd16f5c391..b0fd16f5c391 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
diff --git a/arch/arm/mach-omap2/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h
new file mode 100644
index 000000000000..641a2c8d2eee
--- /dev/null
+++ b/arch/arm/mach-omap2/omap24xx.h
@@ -0,0 +1,87 @@
+/*
+ * This file contains the processor specific definitions
+ * of the TI OMAP24XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP2_H
+#define __ASM_ARCH_OMAP2_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers. Note also that some of these defines are needed
+ * for omap1 to compile without adding ifdefs.
+ */
+
+#define L4_24XX_BASE            0x48000000
+#define L4_WK_243X_BASE         0x49000000
+#define L3_24XX_BASE            0x68000000
+
+/* interrupt controller */
+#define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
+#define OMAP24XX_IVA_INTC_BASE  0x40000000
+
+#define OMAP242X_CTRL_BASE      L4_24XX_BASE
+#define OMAP2420_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
+#define OMAP2420_PRCM_BASE      (L4_24XX_BASE + 0x8000)
+#define OMAP2420_CM_BASE        (L4_24XX_BASE + 0x8000)
+#define OMAP2420_PRM_BASE       OMAP2420_CM_BASE
+#define OMAP2420_SDRC_BASE      (L3_24XX_BASE + 0x9000)
+#define OMAP2420_SMS_BASE       0x68008000
+#define OMAP2420_GPMC_BASE      0x6800a000
+
+#define OMAP2430_32KSYNCT_BASE  (L4_WK_243X_BASE + 0x20000)
+#define OMAP2430_PRCM_BASE      (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_CM_BASE        (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_PRM_BASE       OMAP2430_CM_BASE
+
+#define OMAP243X_SMS_BASE       0x6C000000
+#define OMAP243X_SDRC_BASE      0x6D000000
+#define OMAP243X_GPMC_BASE      0x6E000000
+#define OMAP243X_SCM_BASE       (L4_WK_243X_BASE + 0x2000)
+#define OMAP243X_CTRL_BASE      OMAP243X_SCM_BASE
+#define OMAP243X_HS_BASE        (L4_24XX_BASE + 0x000ac000)
+
+/* DSP SS */
+#define OMAP2420_DSP_BASE       0x58000000
+#define OMAP2420_DSP_MEM_BASE   (OMAP2420_DSP_BASE + 0x0)
+#define OMAP2420_DSP_IPI_BASE   (OMAP2420_DSP_BASE + 0x1000000)
+#define OMAP2420_DSP_MMU_BASE   (OMAP2420_DSP_BASE + 0x2000000)
+
+#define OMAP243X_DSP_BASE       0x5C000000
+#define OMAP243X_DSP_MEM_BASE   (OMAP243X_DSP_BASE + 0x0)
+#define OMAP243X_DSP_MMU_BASE   (OMAP243X_DSP_BASE + 0x1000000)
+
+/* Mailbox */
+#define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
+
+/* Camera */
+#define OMAP24XX_CAMERA_BASE    (L4_24XX_BASE + 0x52000)
+
+/* Security */
+#define OMAP24XX_SEC_BASE       (L4_24XX_BASE + 0xA0000)
+#define OMAP24XX_SEC_RNG_BASE   (OMAP24XX_SEC_BASE + 0x0000)
+#define OMAP24XX_SEC_DES_BASE   (OMAP24XX_SEC_BASE + 0x2000)
+#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
+#define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
+#define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
+
+#endif /* __ASM_ARCH_OMAP2_H */
+
diff --git a/arch/arm/mach-omap2/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h
new file mode 100644
index 000000000000..c0d1b4b1653f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap34xx.h
@@ -0,0 +1,99 @@
+/*
+ * This file contains the processor specific definitions of the TI OMAP34XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_OMAP3_H
+#define __ASM_ARCH_OMAP3_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+
+#define L4_34XX_BASE            0x48000000
+#define L4_WK_34XX_BASE         0x48300000
+#define L4_PER_34XX_BASE        0x49000000
+#define L4_EMU_34XX_BASE        0x54000000
+#define L3_34XX_BASE            0x68000000
+
+#define L4_WK_AM33XX_BASE       0x44C00000
+
+#define OMAP3430_32KSYNCT_BASE  0x48320000
+#define OMAP3430_CM_BASE        0x48004800
+#define OMAP3430_PRM_BASE       0x48306800
+#define OMAP343X_SMS_BASE       0x6C000000
+#define OMAP343X_SDRC_BASE      0x6D000000
+#define OMAP34XX_GPMC_BASE      0x6E000000
+#define OMAP343X_SCM_BASE       0x48002000
+#define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
+
+#define OMAP34XX_IC_BASE        0x48200000
+
+#define OMAP3430_ISP_BASE               (L4_34XX_BASE + 0xBC000)
+#define OMAP3430_ISP_CBUFF_BASE         (OMAP3430_ISP_BASE + 0x0100)
+#define OMAP3430_ISP_CCP2_BASE          (OMAP3430_ISP_BASE + 0x0400)
+#define OMAP3430_ISP_CCDC_BASE          (OMAP3430_ISP_BASE + 0x0600)
+#define OMAP3430_ISP_HIST_BASE          (OMAP3430_ISP_BASE + 0x0A00)
+#define OMAP3430_ISP_H3A_BASE           (OMAP3430_ISP_BASE + 0x0C00)
+#define OMAP3430_ISP_PREV_BASE          (OMAP3430_ISP_BASE + 0x0E00)
+#define OMAP3430_ISP_RESZ_BASE          (OMAP3430_ISP_BASE + 0x1000)
+#define OMAP3430_ISP_SBL_BASE           (OMAP3430_ISP_BASE + 0x1200)
+#define OMAP3430_ISP_MMU_BASE           (OMAP3430_ISP_BASE + 0x1400)
+#define OMAP3430_ISP_CSI2A_REGS1_BASE   (OMAP3430_ISP_BASE + 0x1800)
+#define OMAP3430_ISP_CSIPHY2_BASE       (OMAP3430_ISP_BASE + 0x1970)
+#define OMAP3630_ISP_CSI2A_REGS2_BASE   (OMAP3430_ISP_BASE + 0x19C0)
+#define OMAP3630_ISP_CSI2C_REGS1_BASE   (OMAP3430_ISP_BASE + 0x1C00)
+#define OMAP3630_ISP_CSIPHY1_BASE       (OMAP3430_ISP_BASE + 0x1D70)
+#define OMAP3630_ISP_CSI2C_REGS2_BASE   (OMAP3430_ISP_BASE + 0x1DC0)
+
+#define OMAP3430_ISP_END                (OMAP3430_ISP_BASE         + 0x06F)
+#define OMAP3430_ISP_CBUFF_END          (OMAP3430_ISP_CBUFF_BASE   + 0x077)
+#define OMAP3430_ISP_CCP2_END           (OMAP3430_ISP_CCP2_BASE    + 0x1EF)
+#define OMAP3430_ISP_CCDC_END           (OMAP3430_ISP_CCDC_BASE    + 0x0A7)
+#define OMAP3430_ISP_HIST_END           (OMAP3430_ISP_HIST_BASE    + 0x047)
+#define OMAP3430_ISP_H3A_END            (OMAP3430_ISP_H3A_BASE     + 0x05F)
+#define OMAP3430_ISP_PREV_END           (OMAP3430_ISP_PREV_BASE    + 0x09F)
+#define OMAP3430_ISP_RESZ_END           (OMAP3430_ISP_RESZ_BASE    + 0x0AB)
+#define OMAP3430_ISP_SBL_END            (OMAP3430_ISP_SBL_BASE     + 0x0FB)
+#define OMAP3430_ISP_MMU_END            (OMAP3430_ISP_MMU_BASE     + 0x06F)
+#define OMAP3430_ISP_CSI2A_REGS1_END    (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
+#define OMAP3430_ISP_CSIPHY2_END        (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
+#define OMAP3630_ISP_CSI2A_REGS2_END    (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
+#define OMAP3630_ISP_CSI2C_REGS1_END    (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
+#define OMAP3630_ISP_CSIPHY1_END        (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
+#define OMAP3630_ISP_CSI2C_REGS2_END    (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
+
+#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
+#define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_UHH_CONFIG_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_OHCI_BASE      (L4_34XX_BASE + 0x64400)
+#define OMAP34XX_EHCI_BASE      (L4_34XX_BASE + 0x64800)
+#define OMAP34XX_SR1_BASE       0x480C9000
+#define OMAP34XX_SR2_BASE       0x480CB000
+
+#define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
+
+/* Security */
+#define OMAP34XX_SEC_BASE       (L4_34XX_BASE + 0xA0000)
+#define OMAP34XX_SEC_SHA1MD5_BASE       (OMAP34XX_SEC_BASE + 0x23000)
+#define OMAP34XX_SEC_AES_BASE   (OMAP34XX_SEC_BASE + 0x25000)
+
+#endif /* __ASM_ARCH_OMAP3_H */
+
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c29dee998a79..e1f289748c5d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,26 +16,25 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/export.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
 
-#include <plat/irqs.h>
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
 #include <plat/mmc.h>
 
-#include <mach/hardware.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 
+#include "soc.h"
 #include "common.h"
 #include "hsmmc.h"
 #include "omap4-sar-layout.h"
-#include <linux/export.h>
 
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
@@ -171,7 +170,10 @@ static int __init omap_l2_cache_init(void)
         /* Enable PL310 L2 Cache controller */
         omap_smc1(0x102, 0x1);
 
-        l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+        if (of_have_populated_dt())
+                l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+        else
+                l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
         /*
          * Override default outer_cache.disable with a OMAP4
diff --git a/arch/arm/mach-omap2/omap4-keypad.h b/arch/arm/mach-omap2/omap4-keypad.h
new file mode 100644
index 000000000000..20de0d5a7e77
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-keypad.h
@@ -0,0 +1,8 @@
+#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+
+struct omap_board_data;
+
+extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
+                                struct omap_board_data *);
+#endif
diff --git a/arch/arm/mach-omap2/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h
new file mode 100644
index 000000000000..43b927b2e2e8
--- /dev/null
+++ b/arch/arm/mach-omap2/omap44xx.h
@@ -0,0 +1,62 @@
+/*:
+ * Address mappings and base address for OMAP4 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP44XX_H
+#define __ASM_ARCH_OMAP44XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_44XX_BASE                    0x4a000000
+#define L4_WK_44XX_BASE                 0x4a300000
+#define L4_PER_44XX_BASE                0x48000000
+#define L4_EMU_44XX_BASE                0x54000000
+#define L3_44XX_BASE                    0x44000000
+#define OMAP44XX_EMIF1_BASE             0x4c000000
+#define OMAP44XX_EMIF2_BASE             0x4d000000
+#define OMAP44XX_DMM_BASE               0x4e000000
+#define OMAP4430_32KSYNCT_BASE          0x4a304000
+#define OMAP4430_CM1_BASE               0x4a004000
+#define OMAP4430_CM_BASE                OMAP4430_CM1_BASE
+#define OMAP4430_CM2_BASE               0x4a008000
+#define OMAP4430_PRM_BASE               0x4a306000
+#define OMAP4430_PRCM_MPU_BASE          0x48243000
+#define OMAP44XX_GPMC_BASE              0x50000000
+#define OMAP443X_SCM_BASE               0x4a002000
+#define OMAP443X_CTRL_BASE              0x4a100000
+#define OMAP44XX_IC_BASE                0x48200000
+#define OMAP44XX_IVA_INTC_BASE          0x40000000
+#define IRQ_SIR_IRQ                     0x0040
+#define OMAP44XX_GIC_DIST_BASE          0x48241000
+#define OMAP44XX_GIC_CPU_BASE           0x48240100
+#define OMAP44XX_IRQ_GIC_START          32
+#define OMAP44XX_SCU_BASE               0x48240000
+#define OMAP44XX_LOCAL_TWD_BASE         0x48240600
+#define OMAP44XX_L2CACHE_BASE           0x48242000
+#define OMAP44XX_WKUPGEN_BASE           0x48281000
+#define OMAP44XX_MCPDM_BASE             0x40132000
+#define OMAP44XX_SAR_RAM_BASE           0x4a326000
+
+#define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
+#define OMAP44XX_HSUSB_OTG_BASE         (L4_44XX_BASE + 0xAB000)
+
+#define OMAP4_MMU1_BASE                 0x55082000
+#define OMAP4_MMU2_BASE                 0x4A066000
+
+#define OMAP44XX_USBTLL_BASE            (L4_44XX_BASE + 0x62000)
+#define OMAP44XX_UHH_CONFIG_BASE        (L4_44XX_BASE + 0x64000)
+#define OMAP44XX_HSUSB_OHCI_BASE        (L4_44XX_BASE + 0x64800)
+#define OMAP44XX_HSUSB_EHCI_BASE        (L4_44XX_BASE + 0x64C00)
+
+#endif /* __ASM_ARCH_OMAP44XX_H */
+
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
new file mode 100644
index 000000000000..a2582bb3cab3
--- /dev/null
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -0,0 +1,32 @@
+/*:
+ * Address mappings and base address for OMAP5 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Sricharan <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_SOC_OMAP54XX_H
+#define __ASM_SOC_OMAP54XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_54XX_BASE                    0x4a000000
+#define L4_WK_54XX_BASE                 0x4ae00000
+#define L4_PER_54XX_BASE                0x48000000
+#define L3_54XX_BASE                    0x44000000
+#define OMAP54XX_32KSYNCT_BASE          0x4ae04000
+#define OMAP54XX_CM_CORE_AON_BASE       0x4a004000
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+#define OMAP54XX_PRM_BASE               0x4ae06000
+#define OMAP54XX_PRCM_MPU_BASE          0x48243000
+#define OMAP54XX_SCM_BASE               0x4a002000
+#define OMAP54XX_CTRL_BASE              0x4a002800
+
+#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e519968d..b969ab1d258b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -139,18 +139,20 @@
 #include <linux/slab.h>
 #include <linux/bootmem.h>
 
-#include "common.h"
-#include <plat/cpu.h>
-#include "clockdomain.h"
-#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
 #include <plat/prcm.h>
 
+#include "soc.h"
+#include "common.h"
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include "cm2xxx_3xxx.h"
 #include "cminst44xx.h"
+#include "cm33xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prm33xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
 #include "pm.h"
@@ -677,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
         if (!oh->main_clk)
                 return 0;
 
-        oh->_clk = omap_clk_get_by_name(oh->main_clk);
-        if (!oh->_clk) {
+        oh->_clk = clk_get(NULL, oh->main_clk);
+        if (IS_ERR(oh->_clk)) {
                 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
                            oh->name, oh->main_clk);
                 return -EINVAL;
         }
+        /*
+         * HACK: This needs a re-visit once clk_prepare() is implemented
+         * to do something meaningful. Today its just a no-op.
+         * If clk_prepare() is used at some point to do things like
+         * voltage scaling etc, then this would have to be moved to
+         * some point where subsystems like i2c and pmic become
+         * available.
+         */
+        clk_prepare(oh->_clk);
 
         if (!oh->_clk->clkdm)
-                pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
-                           oh->main_clk, oh->_clk->name);
+                pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
+                           oh->name, oh->main_clk);
 
         return ret;
 }
@@ -713,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
                 if (!os->clk)
                         continue;
 
-                c = omap_clk_get_by_name(os->clk);
-                if (!c) {
+                c = clk_get(NULL, os->clk);
+                if (IS_ERR(c)) {
                         pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
                                    oh->name, os->clk);
                         ret = -EINVAL;
                 }
                 os->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(os->_clk);
         }
 
         return ret;
@@ -740,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
         int ret = 0;
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
-                c = omap_clk_get_by_name(oc->clk);
-                if (!c) {
+                c = clk_get(NULL, oc->clk);
+                if (IS_ERR(c)) {
                         pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
                                    oh->name, oc->clk);
                         ret = -EINVAL;
                 }
                 oc->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(oc->_clk);
         }
 
         return ret;
@@ -825,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk) {
                         pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                         clk_enable(oc->_clk);
                 }
 }
@@ -840,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk) {
                         pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                         clk_disable(oc->_clk);
                 }
 }
@@ -868,6 +897,26 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Enables the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _am33xx_enable_module(struct omap_hwmod *oh)
+{
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return;
+
+        pr_debug("omap_hwmod: %s: %s: %d\n",
+                 oh->name, __func__, oh->prcm.omap4.modulemode);
+
+        am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst,
+                                oh->clkdm->clkdm_offs,
+                                oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
  * @oh: struct omap_hwmod *
  *
@@ -878,10 +927,10 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                 return -EINVAL;
 
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
                 return 0;
 
         if (oh->flags & HWMOD_NO_IDLEST)
@@ -894,6 +943,31 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _am33xx_wait_target_disable(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst,
+                                             oh->clkdm->clkdm_offs,
+                                             oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
  * @oh: struct omap_hwmod *oh
  *
@@ -1380,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name)
  */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-        if (!oh->clkdm_name)
+        if (!oh->clkdm_name) {
+                pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
                 return 0;
+        }
 
         oh->clkdm = clkdm_lookup(oh->clkdm_name);
         if (!oh->clkdm) {
@@ -1438,8 +1514,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
  * Return the bit position of the reset line that match the
  * input name. Return -ENOENT if not found.
  */
-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
-                            struct omap_hwmod_rst_info *ohri)
+static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+                             struct omap_hwmod_rst_info *ohri)
 {
         int i;
 
@@ -1475,7 +1551,7 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        u8 ret = -EINVAL;
+        int ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
@@ -1484,7 +1560,7 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
                 return -ENOSYS;
 
         ret = _lookup_hardreset(oh, name, &ohri);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 return ret;
 
         ret = soc_ops.assert_hardreset(oh, &ohri);
@@ -1509,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
         int ret = -EINVAL;
+        int hwsup = 0;
 
         if (!oh)
                 return -EINVAL;
@@ -1520,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
         if (IS_ERR_VALUE(ret))
                 return ret;
 
+        if (oh->clkdm) {
+                /*
+                 * A clockdomain must be in SW_SUP otherwise reset
+                 * might not be completed. The clockdomain can be set
+                 * in HW_AUTO only when the module become ready.
+                 */
+                hwsup = clkdm_in_hwsup(oh->clkdm);
+                ret = clkdm_hwmod_enable(oh->clkdm, oh);
+                if (ret) {
+                        WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+                             oh->name, oh->clkdm->name, ret);
+                        return ret;
+                }
+        }
+
+        _enable_clocks(oh);
+        if (soc_ops.enable_module)
+                soc_ops.enable_module(oh);
+
         ret = soc_ops.deassert_hardreset(oh, &ohri);
+
+        if (soc_ops.disable_module)
+                soc_ops.disable_module(oh);
+        _disable_clocks(oh);
+
         if (ret == -EBUSY)
                 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
+        if (!ret) {
+                /*
+                 * Set the clockdomain to HW_AUTO, assuming that the
+                 * previous state was HW_AUTO.
+                 */
+                if (oh->clkdm && hwsup)
+                        clkdm_allow_idle(oh->clkdm);
+        } else {
+                if (oh->clkdm)
+                        clkdm_hwmod_disable(oh->clkdm, oh);
+        }
+
         return ret;
 }
 
@@ -1542,7 +1655,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        u8 ret = -EINVAL;
+        int ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
@@ -1551,37 +1664,63 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
                 return -ENOSYS;
 
         ret = _lookup_hardreset(oh, name, &ohri);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 return ret;
 
         return soc_ops.is_hardreset_asserted(oh, &ohri);
 }
 
 /**
- * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
  * @oh: struct omap_hwmod *
  *
- * If any hardreset line associated with @oh is asserted, then return true.
- * Otherwise, if @oh has no hardreset lines associated with it, or if
- * no hardreset lines associated with @oh are asserted, then return false.
+ * If all hardreset lines associated with @oh are asserted, then return true.
+ * Otherwise, if part of @oh is out hardreset or if no hardreset lines
+ * associated with @oh are asserted, then return false.
  * This function is used to avoid executing some parts of the IP block
- * enable/disable sequence if a hardreset line is set.
+ * enable/disable sequence if its hardreset line is set.
  */
-static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
 {
-        int i;
+        int i, rst_cnt = 0;
 
         if (oh->rst_lines_cnt == 0)
                 return false;
 
         for (i = 0; i < oh->rst_lines_cnt; i++)
                 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
-                        return true;
+                        rst_cnt++;
+
+        if (oh->rst_lines_cnt == rst_cnt)
+                return true;
 
         return false;
 }
 
 /**
+ * _are_any_hardreset_lines_asserted - return true if any part of @oh is
+ * hard-reset
+ * @oh: struct omap_hwmod *
+ *
+ * If any hardreset lines associated with @oh are asserted, then
+ * return true.  Otherwise, if no hardreset lines associated with @oh
+ * are asserted, or if @oh has no hardreset lines, then return false.
+ * This function is used to avoid executing some parts of the IP block
+ * enable/disable sequence if any hardreset line is set.
+ */
+static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+{
+        int rst_cnt = 0;
+        int i;
+
+        for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++)
+                if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
+                        rst_cnt++;
+
+        return (rst_cnt) ? true : false;
+}
+
+/**
  * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
  * @oh: struct omap_hwmod *
  *
@@ -1595,6 +1734,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return -EINVAL;
 
+        /*
+         * Since integration code might still be doing something, only
+         * disable if all lines are under hardreset.
+         */
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
+
         pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
 
         omap4_cminst_module_disable(oh->clkdm->prcm_partition,
@@ -1602,10 +1748,37 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
                                     oh->clkdm->clkdm_offs,
                                     oh->prcm.omap4.clkctrl_offs);
 
+        v = _omap4_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+
+        return 0;
+}
+
+/**
+ * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ */
+static int _am33xx_disable_module(struct omap_hwmod *oh)
+{
+        int v;
+
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
+
         if (_are_any_hardreset_lines_asserted(oh))
                 return 0;
 
-        v = _omap4_wait_target_disable(oh);
+        am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
+                                 oh->prcm.omap4.clkctrl_offs);
+
+        v = _am33xx_wait_target_disable(oh);
         if (v)
                 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
                         oh->name);
@@ -1641,8 +1814,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
 
         /* clocks must be on for this operation */
         if (oh->_state != _HWMOD_STATE_ENABLED) {
-                pr_warning("omap_hwmod: %s: reset can only be entered from "
-                           "enabled state\n", oh->name);
+                pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
+                        oh->name);
                 return -EINVAL;
         }
 
@@ -1830,7 +2003,7 @@ static int _enable(struct omap_hwmod *oh)
         }
 
         /*
-         * If an IP block contains HW reset lines and any of them are
+         * If an IP block contains HW reset lines and all of them are
          * asserted, we let integration code associated with that
          * block handle the enable.  We've received very little
          * information on what those driver authors need, and until
@@ -1838,7 +2011,7 @@ static int _enable(struct omap_hwmod *oh)
          * posted to the public lists, this is probably the best we
          * can do.
          */
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         /* Mux pins for device runtime if populated */
@@ -1857,7 +2030,8 @@ static int _enable(struct omap_hwmod *oh)
                  * completely the module. The clockdomain can be set
                  * in HW_AUTO only when the module become ready.
                  */
-                hwsup = clkdm_in_hwsup(oh->clkdm);
+                hwsup = clkdm_in_hwsup(oh->clkdm) &&
+                        !clkdm_missing_idle_reporting(oh->clkdm);
                 r = clkdm_hwmod_enable(oh->clkdm, oh);
                 if (r) {
                         WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1889,6 +2063,7 @@ static int _enable(struct omap_hwmod *oh)
                         _enable_sysc(oh);
                 }
         } else {
+                _omap4_disable_module(oh);
                 _disable_clocks(oh);
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
                          oh->name, r);
@@ -1918,7 +2093,7 @@ static int _idle(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         if (oh->class->sysc)
@@ -2006,7 +2181,7 @@ static int _shutdown(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
@@ -2530,10 +2705,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                 return -EINVAL;
 
-        if (oh->flags & HWMOD_NO_IDLEST)
+        if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
                 return 0;
 
         if (!_find_mpu_rt_port(oh))
@@ -2548,6 +2723,33 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh || !oh->clkdm)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status */
+
+        return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst,
+                                              oh->clkdm->clkdm_offs,
+                                              oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
  * @oh: struct omap_hwmod * to assert hardreset
  * @ohri: hardreset line data
@@ -2678,6 +2880,72 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
                                 oh->prcm.omap4.rstctrl_offs);
 }
 
+/**
+ * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_assert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from am33xx_prminst_assert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+
+{
+        return am33xx_prm_assert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
+/**
+ * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_deassert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from am33xx_prminst_deassert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        if (ohri->st_shift)
+                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+                       oh->name, ohri->name);
+
+        return am33xx_prm_deassert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs,
+                                oh->prcm.omap4.rstst_offs);
+}
+
+/**
+ * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_is_hardreset_asserted() with parameters
+ * extracted from the hwmod @oh and the hardreset line data @ohri.
+ * Only intended for use as an soc_ops function pointer.  Passes along
+ * the return value from am33xx_prminst_is_hardreset_asserted().  XXX
+ * This function is scheduled for removal when the PRM code is moved
+ * into drivers/.
+ */
+static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        return am33xx_prm_is_hardreset_asserted(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
 /* Public functions */
 
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -3158,6 +3426,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }
 
 /**
+ * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the array of struct resource to fill
+ *
+ * Fill the struct resource array @res with dma resource data from the
+ * omap_hwmod @oh.  Intended to be called by code that registers
+ * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
+{
+        int i, sdma_reqs_cnt;
+        int r = 0;
+
+        sdma_reqs_cnt = _count_sdma_reqs(oh);
+        for (i = 0; i < sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->flags = IORESOURCE_DMA;
+                r++;
+        }
+
+        return r;
+}
+
+/**
  * omap_hwmod_get_resource_byname - fetch IP block integration data by name
  * @oh: struct omap_hwmod * to operate on
  * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
@@ -3677,6 +3972,14 @@ void __init omap_hwmod_init(void)
                 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
                 soc_ops.init_clkdm = _init_clkdm;
+        } else if (soc_is_am33xx()) {
+                soc_ops.enable_module = _am33xx_enable_module;
+                soc_ops.disable_module = _am33xx_disable_module;
+                soc_ops.wait_target_ready = _am33xx_wait_target_ready;
+                soc_ops.assert_hardreset = _am33xx_assert_hardreset;
+                soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
         } else {
                 WARN(1, "omap_hwmod: unknown SoC type\n");
         }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 50cfab61b0e2..b5db6007c523 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -12,17 +12,15 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
-#include <plat/l3_2xxx.h>
-#include <plat/l4_2xxx.h>
+#include "l3_2xxx.h"
+#include "l4_2xxx.h"
 #include <plat/mmc.h>
 
 #include "omap_hwmod_common_data.h"
@@ -162,9 +160,9 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 
 /* mailbox */
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-        { .name = "dsp", .irq = 26 },
-        { .name = "iva", .irq = 34 },
-        { .irq = -1 }
+        { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
+        { .name = "iva", .irq = 34 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2420_mailbox_hwmod = {
@@ -199,9 +197,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-        { .name = "tx", .irq = 59 },
-        { .name = "rx", .irq = 60 },
-        { .irq = -1 }
+        { .name = "tx", .irq = 59 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 60 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
@@ -225,9 +223,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-        { .name = "tx", .irq = 62 },
-        { .name = "rx", .irq = 63 },
-        { .irq = -1 }
+        { .name = "tx", .irq = 62 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 63 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
@@ -265,8 +263,8 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 
 /* msdi1 */
 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
-        { .irq = 83 },
-        { .irq = -1 }
+        { .irq = 83 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
@@ -538,6 +536,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6800a000,
+                .pa_end         = 0x6800afff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
@@ -546,6 +553,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2420_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2xxx_l3_main__l4_core,
         &omap2xxx_mpu__l3_main,
@@ -587,8 +602,10 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2420_l4_core__mcbsp1,
         &omap2420_l4_core__mcbsp2,
         &omap2420_l4_core__msdi1,
+        &omap2xxx_l4_core__rng,
         &omap2420_l4_core__hdq1w,
         &omap2420_l4_wkup__counter_32k,
+        &omap2420_l3__gpmc,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 58b5bc196d32..c455e41b0237 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,21 +12,19 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/mmc.h>
-#include <plat/l3_2xxx.h>
+#include "l3_2xxx.h"
 
+#include "soc.h"
 #include "omap_hwmod_common_data.h"
-
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "wd_timer.h"
@@ -133,8 +131,8 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
 
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
-        { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
-        { .irq = -1 }
+        { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_gpio5_hwmod = {
@@ -173,8 +171,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 
 /* mailbox */
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
-        { .irq = 26 },
-        { .irq = -1 }
+        { .irq = 26 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mailbox_hwmod = {
@@ -195,8 +193,8 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
 
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
-        { .irq = 91 },
-        { .irq = -1 }
+        { .irq = 91 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -250,9 +248,9 @@ static struct omap_hwmod_class usbotg_class = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
 
-        { .name = "mc", .irq = 92 },
-        { .name = "dma", .irq = 93 },
-        { .irq = -1 }
+        { .name = "mc", .irq = 92 + OMAP_INTC_START, },
+        { .name = "dma", .irq = 93 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
@@ -303,11 +301,11 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
-        { .name = "tx",         .irq = 59 },
-        { .name = "rx",         .irq = 60 },
-        { .name = "ovr",        .irq = 61 },
-        { .name = "common",     .irq = 64 },
-        { .irq = -1 }
+        { .name = "tx",         .irq = 59 + OMAP_INTC_START, },
+        { .name = "rx",         .irq = 60 + OMAP_INTC_START, },
+        { .name = "ovr",        .irq = 61 + OMAP_INTC_START, },
+        { .name = "common",     .irq = 64 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
@@ -331,10 +329,10 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
-        { .name = "tx",         .irq = 62 },
-        { .name = "rx",         .irq = 63 },
-        { .name = "common",     .irq = 16 },
-        { .irq = -1 }
+        { .name = "tx",         .irq = 62 + OMAP_INTC_START, },
+        { .name = "rx",         .irq = 63 + OMAP_INTC_START, },
+        { .name = "common",     .irq = 16 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
@@ -358,10 +356,10 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
 
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
-        { .name = "tx",         .irq = 89 },
-        { .name = "rx",         .irq = 90 },
-        { .name = "common",     .irq = 17 },
-        { .irq = -1 }
+        { .name = "tx",         .irq = 89 + OMAP_INTC_START, },
+        { .name = "rx",         .irq = 90 + OMAP_INTC_START, },
+        { .name = "common",     .irq = 17 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
@@ -385,10 +383,10 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
 
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
-        { .name = "tx",         .irq = 54 },
-        { .name = "rx",         .irq = 55 },
-        { .name = "common",     .irq = 18 },
-        { .irq = -1 }
+        { .name = "tx",         .irq = 54 + OMAP_INTC_START, },
+        { .name = "rx",         .irq = 55 + OMAP_INTC_START, },
+        { .name = "common",     .irq = 18 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
@@ -418,10 +416,10 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
 
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
-        { .name = "tx",         .irq = 81 },
-        { .name = "rx",         .irq = 82 },
-        { .name = "common",     .irq = 19 },
-        { .irq = -1 }
+        { .name = "tx",         .irq = 81 + OMAP_INTC_START, },
+        { .name = "rx",         .irq = 82 + OMAP_INTC_START, },
+        { .name = "common",     .irq = 19 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
@@ -468,8 +466,8 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 
 /* MMC/SD/SDIO1 */
 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
-        { .irq = 83 },
-        { .irq = -1 }
+        { .irq = 83 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
@@ -509,8 +507,8 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
 
 /* MMC/SD/SDIO2 */
 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
-        { .irq = 86 },
-        { .irq = -1 }
+        { .irq = 86 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
@@ -890,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
@@ -898,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2430_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2xxx_l3_main__l4_core,
         &omap2xxx_mpu__l3_main,
@@ -947,7 +962,9 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2430_l4_core__mcbsp4,
         &omap2430_l4_core__mcbsp5,
         &omap2430_l4_core__hdq1w,
+        &omap2xxx_l4_core__rng,
         &omap2430_l4_wkup__counter_32k,
+        &omap2430_l3__gpmc,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 102d76e9e9ea..8851bbb6bb24 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -13,9 +13,7 @@
 #include <plat/serial.h>
 #include <plat/dma.h>
 #include <plat/common.h>
-#include <plat/hdq1w.h>
-
-#include <mach/irqs.h>
+#include "hdq1w.h"
 
 #include "omap_hwmod_common_data.h"
 
@@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = {
 /* Common MPU IRQ line data */
 
 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
-        { .irq = 37, },
-        { .irq = -1 }
+        { .irq = 37 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
-        { .irq = 38, },
-        { .irq = -1 }
+        { .irq = 38 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
-        { .irq = 39, },
-        { .irq = -1 }
+        { .irq = 39 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
-        { .irq = 40, },
-        { .irq = -1 }
+        { .irq = 40 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
-        { .irq = 41, },
-        { .irq = -1 }
+        { .irq = 41 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
-        { .irq = 42, },
-        { .irq = -1 }
+        { .irq = 42 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
-        { .irq = 43, },
-        { .irq = -1 }
+        { .irq = 43 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
-        { .irq = 44, },
-        { .irq = -1 }
+        { .irq = 44 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
-        { .irq = 45, },
-        { .irq = -1 }
+        { .irq = 45 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
-        { .irq = 46, },
-        { .irq = -1 }
+        { .irq = 46 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
-        { .irq = 47, },
-        { .irq = -1 }
+        { .irq = 47 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
-        { .irq = INT_24XX_UART1_IRQ, },
-        { .irq = -1 }
+        { .irq = 72 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
-        { .irq = INT_24XX_UART2_IRQ, },
-        { .irq = -1 }
+        { .irq = 73 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
-        { .irq = INT_24XX_UART3_IRQ, },
-        { .irq = -1 }
+        { .irq = 74 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
-        { .irq = 25 },
-        { .irq = -1 }
+        { .irq = 25 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C1_IRQ, },
-        { .irq = -1 }
+        { .irq = 56 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C2_IRQ, },
-        { .irq = -1 }
+        { .irq = 57 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
-        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
-        { .irq = -1 }
+        { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
-        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
-        { .irq = -1 }
+        { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
-        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
-        { .irq = -1 }
+        { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
-        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
-        { .irq = -1 }
+        { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
-        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
-        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
-        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
-        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-        { .irq = -1 }
+        { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
-        { .irq = 65 },
-        { .irq = -1 }
+        { .irq = 65 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
-        { .irq = 66 },
-        { .irq = -1 }
+        { .irq = 66 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
@@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = {
 };
 
 struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
-        { .irq = 58, },
-        { .irq = -1 }
+        { .irq = 58 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5178e40e84f9..1a1287d62648 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,8 +15,8 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/l3_2xxx.h>
-#include <plat/l4_2xxx.h>
+#include "l3_2xxx.h"
+#include "l4_2xxx.h"
 
 #include "omap_hwmod_common_data.h"
 
@@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
+        {
+                .pa_start       = 0x480a0000,
+                .pa_end         = 0x480a004f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /*
  * Common interconnect data
  */
@@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> rng */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_rng_hwmod,
+        .clk            = "rng_ick",
+        .addr           = omap2_rng_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index afad69c6ba6e..bd9220ed5ab9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,12 +10,10 @@
  */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
-#include <plat/mcspi.h>
-
-#include <mach/irqs.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
@@ -23,8 +21,8 @@
 #include "wd_timer.h"
 
 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
-        { .irq = 48, },
-        { .irq = -1 }
+        { .irq = 48 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
@@ -175,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap2xxx_gpmc_sysc,
+};
+
+/*
  * IP blocks
  */
 
@@ -200,8 +218,14 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 };
 
 /* MPU */
+static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 + OMAP_INTC_START },
+        { .irq = -1 }
+};
+
 struct omap_hwmod omap2xxx_mpu_hwmod = {
         .name           = "mpu",
+        .mpu_irqs       = omap2xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "mpu_ck",
 };
@@ -222,6 +246,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
 /* timer1 */
 
 struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -310,6 +339,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -328,6 +358,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -346,6 +377,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -364,6 +396,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -726,7 +759,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
         .dev_attr       = &omap_mcspi2_dev_attr,
 };
 
-
 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
         .name   = "counter",
 };
@@ -745,3 +777,77 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
         },
         .class          = &omap2xxx_counter_hwmod_class,
 };
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap2xxx_gpmc_hwmod_class,
+        .mpu_irqs       = omap2xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+        .prcm           = {
+                .omap2  = {
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP24XX_EN_GPMC_MASK,
+                        .module_offs = CORE_MOD,
+                },
+        },
+};
+
+/* RNG */
+
+static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
+        .rev_offs       = 0x3c,
+        .sysc_offs      = 0x40,
+        .syss_offs      = 0x44,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2_rng_hwmod_class = {
+        .name           = "rng",
+        .sysc           = &omap2_rng_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
+        { .irq = 52 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_rng_hwmod = {
+        .name           = "rng",
+        .mpu_irqs       = omap2_rng_mpu_irqs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_RNG_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
+                },
+        },
+        /*
+         * XXX The first read from the SYSSTATUS register of the RNG
+         * after the SYSCONFIG SOFTRESET bit is set triggers an
+         * imprecise external abort.  It's unclear why this happens.
+         * Until this is analyzed, skip the IP block reset.
+         */
+        .flags          = HWMOD_INIT_NO_RESET,
+        .class          = &omap2_rng_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 000000000000..59d5c1cd316d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/i2c.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+        .name           = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+        .name           = "emif_fw",
+        .class          = &am33xx_emif_fw_hwmod_class,
+        .clkdm_name     = "l4fw_clkdm",
+        .main_clk       = "l4fw_gclk",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+        .rev_offs       = 0x0000,
+};
+
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+        .name           = "emif",
+        .sysc           = &am33xx_emif_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+        { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+        .name           = "emif",
+        .class          = &am33xx_emif_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_emif_irqs,
+        .main_clk       = "dpll_ddr_m2_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+        .name           = "l3",
+};
+
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+        { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
+        { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+        .name           = "l3_main",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_l3_main_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+        .name           = "l3_s",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+        .name           = "l4",
+};
+
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+        .name           = "l4_ls",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+        .name           = "l4_hs",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4hs_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l4hs_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+        .name           = "l4_fw",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4fw_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+        { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
+        { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
+        { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
+        { .name = "bench", .irq = 3 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &am33xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_mpu_irqs,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+        .name           = "wkup_m3",
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+        { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+        { .name = "txev", .irq = 78 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+/* wkup_m3  */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+        .name           = "wkup_m3",
+        .class          = &am33xx_wkup_m3_hwmod_class,
+        .clkdm_name     = "l4_wkup_aon_clkdm",
+        .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
+        .mpu_irqs       = am33xx_wkup_m3_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_wkup_m3_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+        .name   = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+        { .name = "pruss", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+        { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
+        { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
+        { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
+        { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
+        { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
+        { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
+        { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
+        { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+        .name           = "pruss",
+        .class          = &am33xx_pruss_hwmod_class,
+        .clkdm_name     = "pruss_ocp_clkdm",
+        .mpu_irqs       = am33xx_pruss_irqs,
+        .main_clk       = "pruss_ocp_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_pruss_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+        .name   = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+        { .name = "gfx", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+        { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_gfx_hwmod = {
+        .name           = "gfx",
+        .class          = &am33xx_gfx_hwmod_class,
+        .clkdm_name     = "gfx_l3_clkdm",
+        .mpu_irqs       = am33xx_gfx_irqs,
+        .main_clk       = "gfx_fck_div_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_gfx_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+        .name   = "prcm",
+};
+
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+        .name           = "prcm",
+        .class          = &am33xx_prcm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+        .name           = "adc_tsc",
+        .sysc           = &am33xx_adc_tsc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+        { .irq = 16 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+        .name           = "adc_tsc",
+        .class          = &am33xx_adc_tsc_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_adc_tsc_irqs,
+        .main_clk       = "adc_tsc_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ *   properly adapted to omap_hwmod / omap_device
+ *
+ *    - cEFUSE (doesn't fall under any ocp_if)
+ *    - clkdiv32k
+ *    - debugss
+ *    - ocmc ram
+ *    - ocp watch point
+ *    - aes0
+ *    - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+        .name           = "cefuse",
+};
+
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+        .name           = "cefuse",
+        .class          = &am33xx_cefuse_hwmod_class,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .main_clk       = "cefuse_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+        .name           = "clkdiv32k",
+};
+
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+        .name           = "clkdiv32k",
+        .class          = &am33xx_clkdiv32k_hwmod_class,
+        .clkdm_name     = "clk_24mhz_clkdm",
+        .main_clk       = "clkdiv32k_ick",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+        .name           = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &am33xx_debugss_hwmod_class,
+        .clkdm_name     = "l3_aon_clkdm",
+        .main_clk       = "debugss_ick",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+        .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+        .name           = "ocmcram",
+        .class          = &am33xx_ocmcram_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+        .name           = "ocpwp",
+};
+
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+        .name           = "ocpwp",
+        .class          = &am33xx_ocpwp_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+        .name           = "aes",
+};
+
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+        { .irq = 102 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+        .name           = "aes0",
+        .class          = &am33xx_aes_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_aes0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+        .name           = "sha0",
+};
+
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+        { .irq = 108 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+        .name           = "sha0",
+        .class          = &am33xx_sha0_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_sha0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+#endif
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+        .name           = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+        { .irq = 120 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+        .name           = "smartreflex0",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_smartreflex0_irqs,
+        .main_clk       = "smartreflex0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+        { .irq = 121 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+        .name           = "smartreflex1",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_smartreflex1_irqs,
+        .main_clk       = "smartreflex1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+        .name           = "control",
+};
+
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+        { .irq = 8 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+        .name           = "control",
+        .class          = &am33xx_control_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_control_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x8,
+        .syss_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+                           MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+        .name           = "cpgmac0",
+        .sysc           = &am33xx_cpgmac_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+        { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
+        { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
+        { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
+        { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+        .name           = "cpgmac0",
+        .class          = &am33xx_cpgmac0_hwmod_class,
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .mpu_irqs       = am33xx_cpgmac0_irqs,
+        .main_clk       = "cpsw_125mhz_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+        .name = "d_can",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+        { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
+        { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+        .name           = "d_can0",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_dcan0_irqs,
+        .main_clk       = "dcan0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+        { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
+        { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+        .name           = "d_can1",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_dcan1_irqs,
+        .main_clk       = "dcan1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+        .name           = "elm",
+        .sysc           = &am33xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+        { .irq = 4 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &am33xx_elm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_elm_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                        MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+        .name           = "epwmss",
+        .sysc           = &am33xx_epwmss_sysc,
+};
+
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+        { .name = "int", .irq = 86 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+        .name           = "ehrpwm0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm0_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+        { .name = "int", .irq = 87 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+        .name           = "ehrpwm1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+        { .name = "int", .irq = 39 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+        .name           = "ehrpwm2",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm2_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+        { .irq = 31 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+        .name           = "ecap0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ecap0_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+        { .irq = 47 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+        .name           = "ecap1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ecap1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+        { .irq = 61 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+        .name           = "ecap2",
+        .mpu_irqs       = am33xx_ecap2_irqs,
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+        .name           = "gpio",
+        .sysc           = &am33xx_gpio_sysc,
+        .rev            = 2,
+};
+
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+        { .irq = 96 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+        .name           = "gpio1",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio0_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio0_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+        { .irq = 98 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+        .name           = "gpio2",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+        { .irq = 32 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+        .name           = "gpio3",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio2_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+        { .irq = 62 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+        .name           = "gpio4",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio3_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+        .name           = "gpmc",
+        .sysc           = &gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+        { .irq = 100 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &am33xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_gpmc_irqs,
+        .main_clk       = "l3s_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &am33xx_i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_2,
+        .reset          = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = 70 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .sdma_reqs      = i2c1_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = 71 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .sdma_reqs      = i2c2_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+        { .irq = 30 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = i2c3_mpu_irqs,
+        .sdma_reqs      = i2c3_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x54,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+        .name           = "lcdc",
+        .sysc           = &lcdc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+        { .irq = 36 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+        .name           = "lcdc",
+        .class          = &am33xx_lcdc_hwmod_class,
+        .clkdm_name     = "lcdc_clkdm",
+        .mpu_irqs       = am33xx_lcdc_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "lcd_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &am33xx_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+        { .irq = 77 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &am33xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mailbox_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+        .name           = "mcasp",
+        .sysc           = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+        { .name = "ax", .irq = 80 + OMAP_INTC_START, },
+        { .name = "ar", .irq = 81 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 8, },
+        { .name = "rx", .dma_req = 9, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+        .name           = "mcasp0",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mcasp0_irqs,
+        .sdma_reqs      = am33xx_mcasp0_edma_reqs,
+        .main_clk       = "mcasp0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+        { .name = "ax", .irq = 82 + OMAP_INTC_START, },
+        { .name = "ar", .irq = 83 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 10, },
+        { .name = "rx", .dma_req = 11, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+        .name           = "mcasp1",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mcasp1_irqs,
+        .sdma_reqs      = am33xx_mcasp1_edma_reqs,
+        .main_clk       = "mcasp1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+        .name           = "mmc",
+        .sysc           = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+        { .irq = 64 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 24, },
+        { .name = "rx", .dma_req = 25, },
+        { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+        .name           = "mmc1",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mmc0_irqs,
+        .sdma_reqs      = am33xx_mmc0_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+        { .irq = 28 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 2, },
+        { .name = "rx", .dma_req = 3, },
+        { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+        .name           = "mmc2",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mmc1_irqs,
+        .sdma_reqs      = am33xx_mmc1_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+        { .irq = 29 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 64, },
+        { .name = "rx", .dma_req = 65, },
+        { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+        .name           = "mmc3",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mmc2_irqs,
+        .sdma_reqs      = am33xx_mmc2_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+        .rev_offs       = 0x0074,
+        .sysc_offs      = 0x0078,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
+                          SIDLE_SMART | SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+        .name           = "rtc",
+        .sysc           = &am33xx_rtc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+        { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
+        { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+        .name           = "rtc",
+        .class          = &am33xx_rtc_hwmod_class,
+        .clkdm_name     = "l4_rtc_clkdm",
+        .mpu_irqs       = am33xx_rtc_irqs,
+        .main_clk       = "clk_32768_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0110,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+        .name           = "mcspi",
+        .sysc           = &am33xx_mcspi_sysc,
+        .rev            = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+        { .irq = 65 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+        { .name = "rx0", .dma_req = 17 },
+        { .name = "tx0", .dma_req = 16 },
+        { .name = "rx1", .dma_req = 19 },
+        { .name = "tx1", .dma_req = 18 },
+        { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+        .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+        .name           = "spi0",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_spi0_irqs,
+        .sdma_reqs      = am33xx_mcspi0_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+        { .irq = 125 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+        { .name = "rx0", .dma_req = 43 },
+        { .name = "tx0", .dma_req = 42 },
+        { .name = "rx1", .dma_req = 45 },
+        { .name = "tx1", .dma_req = 44 },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_spi1_hwmod = {
+        .name           = "spi1",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_spi1_irqs,
+        .sdma_reqs      = am33xx_mcspi1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+        .name           = "spinlock",
+};
+
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &am33xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer1ms_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+        { .irq = 67 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &am33xx_timer1ms_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_timer1_irqs,
+        .main_clk       = "timer1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+        { .irq = 68 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer2_irqs,
+        .main_clk       = "timer2_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+        { .irq = 69 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer3_irqs,
+        .main_clk       = "timer3_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+        { .irq = 92 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer4_irqs,
+        .main_clk       = "timer4_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+        { .irq = 93 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer5_irqs,
+        .main_clk       = "timer5_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+        { .irq = 94 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer6_irqs,
+        .main_clk       = "timer6_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+        { .irq = 95 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer7_irqs,
+        .main_clk       = "timer7_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+        .name           = "tpcc",
+};
+
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+        { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
+        { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
+        { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+        .name           = "tpcc",
+        .class          = &am33xx_tpcc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tpcc_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+        .name           = "tptc",
+        .sysc           = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+        { .irq = 112 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+        .name           = "tptc0",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+        { .irq = 113 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+        .name           = "tptc1",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc1_irqs,
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+        { .irq = 114 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+        .name           = "tptc2",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc2_irqs,
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name           = "uart",
+        .sysc           = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 26, },
+        { .name = "rx", .dma_req = 27, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+        { .irq = 72 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &uart_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_uart1_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+        { .irq = 73 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart2_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+        { .name = "tx", .dma_req = 30, },
+        { .name = "rx", .dma_req = 31, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+        { .irq = 74 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart3_irqs,
+        .sdma_reqs      = uart3_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+        { .irq = 44 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart4_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+        { .irq = 45 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart5_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+        { .irq = 46 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart6_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &am33xx_wd_timer_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .main_clk       = "wdt1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+        .name           = "usbotg",
+        .sysc           = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+        { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
+        { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
+        { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
+        { .irq = -1 + OMAP_INTC_START, },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+        .name           = "usb_otg_hs",
+        .class          = &am33xx_usbotg_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_usbss_mpu_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "usbotg_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+        .master         = &am33xx_l4_fw_hwmod,
+        .slave          = &am33xx_emif_fw_hwmod,
+        .clk            = "l4fw_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+        {
+                .pa_start       = 0x4c000000,
+                .pa_end         = 0x4c000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_emif_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_emif_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l4_hs_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_s_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_ls_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_fw_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_instr_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_prcm_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+        .master         = &am33xx_pruss_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+        .master         = &am33xx_wkup_m3_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+        .master         = &am33xx_gfx_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+        {
+                .name           = "umem",
+                .pa_start       = 0x44d00000,
+                .pa_end         = 0x44d00000 + SZ_16K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "dmem",
+                .pa_start       = 0x44d80000,
+                .pa_end         = 0x44d80000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wkup_m3_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_wkup_m3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+        {
+                .pa_start       = 0x4a300000,
+                .pa_end         = 0x4a300000 + SZ_512K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+        .master         = &am33xx_l4_hs_hwmod,
+        .slave          = &am33xx_pruss_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_pruss_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+        {
+                .pa_start       = 0x56000000,
+                .pa_end         = 0x56000000 + SZ_16M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_gfx_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_gfx_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+        {
+                .pa_start       = 0x44e37000,
+                .pa_end         = 0x44e37000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex0_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_smartreflex0_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+        {
+                .pa_start       = 0x44e39000,
+                .pa_end         = 0x44e39000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_smartreflex1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+        {
+                .pa_start       = 0x44e10000,
+                .pa_end         = 0x44e10000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_control_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_control_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+        {
+                .pa_start       = 0x44e3e000,
+                .pa_end         = 0x44e3e000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_rtc_hwmod,
+        .clk            = "clkdiv32k_ick",
+        .addr           = am33xx_rtc_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+        {
+                .pa_start       = 0x481CC000,
+                .pa_end         = 0x481CC000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_dcan0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+        {
+                .pa_start       = 0x481D0000,
+                .pa_end         = 0x481D0000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_dcan1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4804C000,
+                .pa_end         = 0x4804C000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x481AC000,
+                .pa_end         = 0x481AC000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x481AE000,
+                .pa_end         = 0x481AE000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x44E0B000,
+                .pa_end         = 0x44E0B000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_i2c1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_i2c1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+        {
+                .pa_start       = 0x44E07000,
+                .pa_end         = 0x44E07000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_gpio0_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_gpio0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+        {
+                .pa_start       = 0x44E0D000,
+                .pa_end         = 0x44E0D000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_adc_tsc_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_adc_tsc_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+        /* cpsw ss */
+        {
+                .pa_start       = 0x4a100000,
+                .pa_end         = 0x4a100000 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        /* cpsw wr */
+        {
+                .pa_start       = 0x4a101200,
+                .pa_end         = 0x4a101200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+        .master         = &am33xx_l4_hs_hwmod,
+        .slave          = &am33xx_cpgmac0_hwmod,
+        .clk            = "cpsw_125mhz_gclk",
+        .addr           = am33xx_cpgmac0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_elm_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_elm_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48300200,
+                .pa_end         = 0x48300200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48302200,
+                .pa_end         = 0x48302200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48304200,
+                .pa_end         = 0x48304200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48300100,
+                .pa_end         = 0x48300100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48302100,
+                .pa_end         = 0x48302100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48304100,
+                .pa_end         = 0x48304100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x50000000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_gpmc_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_gpmc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x4802A000,
+                .pa_end         = 0x4802A000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_i2c2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x4819C000,
+                .pa_end         = 0x4819C000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_i2c3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+        {
+                .pa_start       = 0x4830E000,
+                .pa_end         = 0x4830E000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_lcdc_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_lcdc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x480C8000,
+                .pa_end         = 0x480C8000 + (SZ_4K - 1),
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mailbox_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mailbox_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x480Ca000,
+                .pa_end         = 0x480Ca000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spinlock_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_spinlock_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+        {
+                .pa_start       = 0x48038000,
+                .pa_end         = 0x48038000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+        {
+                .pa_start       = 0x46000000,
+                .pa_end         = 0x46000000 + SZ_4M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mcasp0_data_addr_space,
+        .user           = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+        {
+                .pa_start       = 0x4803C000,
+                .pa_end         = 0x4803C000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+        {
+                .pa_start       = 0x46400000,
+                .pa_end         = 0x46400000 + SZ_4M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mcasp1_data_addr_space,
+        .user           = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+        {
+                .pa_start       = 0x48060100,
+                .pa_end         = 0x48060100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x481d8100,
+                .pa_end         = 0x481d8100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x47810100,
+                .pa_end         = 0x47810100 + SZ_64K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mmc2_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mmc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+        {
+                .pa_start       = 0x48030000,
+                .pa_end         = 0x48030000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcspi0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x481A0000,
+                .pa_end         = 0x481A0000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcspi1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+        {
+                .pa_start       = 0x44E31000,
+                .pa_end         = 0x44E31000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_timer1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_timer1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x48040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x48042000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x48044000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer4_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer4_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer5_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer5_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+        {
+                .pa_start       = 0x48048000,
+                .pa_end         = 0x48048000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer6_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer6_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+        {
+                .pa_start       = 0x4804A000,
+                .pa_end         = 0x4804A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer7_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer7_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+        {
+                .pa_start       = 0x49000000,
+                .pa_end         = 0x49000000 + SZ_32K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tpcc_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tpcc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+        {
+                .pa_start       = 0x49800000,
+                .pa_end         = 0x49800000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc0_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+        {
+                .pa_start       = 0x49900000,
+                .pa_end         = 0x49900000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc1_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+        {
+                .pa_start       = 0x49a00000,
+                .pa_end         = 0x49a00000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc2_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+        {
+                .pa_start       = 0x44E09000,
+                .pa_end         = 0x44E09000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_uart1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_uart1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+        {
+                .pa_start       = 0x48022000,
+                .pa_end         = 0x48022000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+        {
+                .pa_start       = 0x48024000,
+                .pa_end         = 0x48024000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+        {
+                .pa_start       = 0x481A6000,
+                .pa_end         = 0x481A6000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart4_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart4_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+        {
+                .pa_start       = 0x481A8000,
+                .pa_end         = 0x481A8000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart5_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart5_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+        {
+                .pa_start       = 0x481aa000,
+                .pa_end         = 0x481aa000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart6_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart6_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+        {
+                .pa_start       = 0x44e35000,
+                .pa_end         = 0x44e35000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wd_timer1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_wd_timer1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+        {
+                .name           = "usbss",
+                .pa_start       = 0x47400000,
+                .pa_end         = 0x47400000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "musb0",
+                .pa_start       = 0x47401000,
+                .pa_end         = 0x47401000 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "musb1",
+                .pa_start       = 0x47401800,
+                .pa_end         = 0x47401800 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_usbss_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_usbss_addr_space,
+        .user           = OCP_USER_MPU,
+        .flags          = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+        &am33xx_l4_fw__emif_fw,
+        &am33xx_l3_main__emif,
+        &am33xx_mpu__l3_main,
+        &am33xx_mpu__prcm,
+        &am33xx_l3_s__l4_ls,
+        &am33xx_l3_s__l4_wkup,
+        &am33xx_l3_s__l4_fw,
+        &am33xx_l3_main__l4_hs,
+        &am33xx_l3_main__l3_s,
+        &am33xx_l3_main__l3_instr,
+        &am33xx_l3_main__gfx,
+        &am33xx_l3_s__l3_main,
+        &am33xx_pruss__l3_main,
+        &am33xx_wkup_m3__l4_wkup,
+        &am33xx_gfx__l3_main,
+        &am33xx_l4_wkup__wkup_m3,
+        &am33xx_l4_wkup__control,
+        &am33xx_l4_wkup__smartreflex0,
+        &am33xx_l4_wkup__smartreflex1,
+        &am33xx_l4_wkup__uart1,
+        &am33xx_l4_wkup__timer1,
+        &am33xx_l4_wkup__rtc,
+        &am33xx_l4_wkup__i2c1,
+        &am33xx_l4_wkup__gpio0,
+        &am33xx_l4_wkup__adc_tsc,
+        &am33xx_l4_wkup__wd_timer1,
+        &am33xx_l4_hs__pruss,
+        &am33xx_l4_per__dcan0,
+        &am33xx_l4_per__dcan1,
+        &am33xx_l4_per__gpio1,
+        &am33xx_l4_per__gpio2,
+        &am33xx_l4_per__gpio3,
+        &am33xx_l4_per__i2c2,
+        &am33xx_l4_per__i2c3,
+        &am33xx_l4_per__mailbox,
+        &am33xx_l4_ls__mcasp0,
+        &am33xx_l3_s__mcasp0_data,
+        &am33xx_l4_ls__mcasp1,
+        &am33xx_l3_s__mcasp1_data,
+        &am33xx_l4_ls__mmc0,
+        &am33xx_l4_ls__mmc1,
+        &am33xx_l3_s__mmc2,
+        &am33xx_l4_ls__timer2,
+        &am33xx_l4_ls__timer3,
+        &am33xx_l4_ls__timer4,
+        &am33xx_l4_ls__timer5,
+        &am33xx_l4_ls__timer6,
+        &am33xx_l4_ls__timer7,
+        &am33xx_l3_main__tpcc,
+        &am33xx_l4_ls__uart2,
+        &am33xx_l4_ls__uart3,
+        &am33xx_l4_ls__uart4,
+        &am33xx_l4_ls__uart5,
+        &am33xx_l4_ls__uart6,
+        &am33xx_l4_ls__spinlock,
+        &am33xx_l4_ls__elm,
+        &am33xx_l4_ls__ehrpwm0,
+        &am33xx_l4_ls__ehrpwm1,
+        &am33xx_l4_ls__ehrpwm2,
+        &am33xx_l4_ls__ecap0,
+        &am33xx_l4_ls__ecap1,
+        &am33xx_l4_ls__ecap2,
+        &am33xx_l3_s__gpmc,
+        &am33xx_l3_main__lcdc,
+        &am33xx_l4_ls__mcspi0,
+        &am33xx_l4_ls__mcspi1,
+        &am33xx_l3_main__tptc0,
+        &am33xx_l3_main__tptc1,
+        &am33xx_l3_main__tptc2,
+        &am33xx_l3_s__usbss,
+        &am33xx_l4_hs__cpgmac0,
+        NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c9e38200216b..f67b7ee07dd4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -15,26 +15,27 @@
  * XXX these should be marked initdata for multi-OMAP kernels
  */
 #include <linux/power/smartreflex.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
-#include <plat/l3_3xxx.h>
-#include <plat/l4_3xxx.h>
+#include "l3_3xxx.h"
+#include "l4_3xxx.h"
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mmc.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
+#include <plat/iommu.h>
 
+#include "am35xx.h"
+
+#include "soc.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
-#include <mach/am35xx.h>
 
 /*
  * OMAP3xxx hardware module integration data
@@ -51,9 +52,9 @@
 
 /* L3 */
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
-        { .irq = INT_34XX_L3_DBG_IRQ },
-        { .irq = INT_34XX_L3_APP_IRQ },
-        { .irq = -1 }
+        { .irq = 9 + OMAP_INTC_START, },
+        { .irq = 10 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
@@ -92,17 +93,23 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
 };
 
 /* MPU */
+static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 + OMAP_INTC_START },
+        { .irq = -1 }
+};
+
 static struct omap_hwmod omap3xxx_mpu_hwmod = {
         .name           = "mpu",
+        .mpu_irqs       = omap3xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "arm_fck",
 };
 
 /* IVA2 (IVA2) */
 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
-        { .name = "logic", .rst_shift = 0 },
-        { .name = "seq0", .rst_shift = 1 },
-        { .name = "seq1", .rst_shift = 2 },
+        { .name = "logic", .rst_shift = 0, .st_shift = 8 },
+        { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
+        { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 };
 
 static struct omap_hwmod omap3xxx_iva_hwmod = {
@@ -112,6 +119,33 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .rst_lines      = omap3xxx_iva_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
         .main_clk       = "iva2_ck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430_IVA2_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
+                }
+        },
+};
+
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+
+static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
+        .name   = "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod omap3xxx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &omap3xxx_debugss_hwmod_class,
+        .clkdm_name     = "emu_clkdm",
+        .main_clk       = "emu_src_ck",
+        .flags          = HWMOD_NO_IDLEST,
 };
 
 /* timer class */
@@ -161,6 +195,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
         .name           = "timer1",
@@ -244,6 +288,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -261,6 +306,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -278,6 +324,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -295,7 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -355,8 +402,8 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
 
 /* timer12 */
 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
-        { .irq = 95, },
-        { .irq = -1 }
+        { .irq = 95 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_timer12_hwmod = {
@@ -490,8 +537,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
 
 /* UART4 */
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
-        { .irq = INT_36XX_UART4_IRQ, },
-        { .irq = -1 }
+        { .irq = 80 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
@@ -518,8 +565,8 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 };
 
 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
-        { .irq = INT_35XX_UART4_IRQ, },
-        { .irq = -1 }
+        { .irq = 84 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
@@ -674,8 +721,8 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
-        { .irq = 25 },
-        { .irq = -1 }
+        { .irq = 25 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 /* dss_dsi1 */
@@ -804,8 +851,8 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-        { .irq = INT_34XX_I2C3_IRQ, },
-        { .irq = -1 }
+        { .irq = 61 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
@@ -963,8 +1010,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 
 /* gpio5 */
 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
-        { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
-        { .irq = -1 }
+        { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -993,8 +1040,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 
 /* gpio6 */
 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
-        { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
-        { .irq = -1 }
+        { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -1098,10 +1145,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
-        { .name = "common", .irq = 16 },
-        { .name = "tx", .irq = 59 },
-        { .name = "rx", .irq = 60 },
-        { .irq = -1 }
+        { .name = "common", .irq = 16 + OMAP_INTC_START, },
+        { .name = "tx", .irq = 59 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 60 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
@@ -1125,10 +1172,10 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
-        { .name = "common", .irq = 17 },
-        { .name = "tx", .irq = 62 },
-        { .name = "rx", .irq = 63 },
-        { .irq = -1 }
+        { .name = "common", .irq = 17 + OMAP_INTC_START, },
+        { .name = "tx", .irq = 62 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 63 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
@@ -1157,10 +1204,10 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
 
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
-        { .name = "common", .irq = 22 },
-        { .name = "tx", .irq = 89 },
-        { .name = "rx", .irq = 90 },
-        { .irq = -1 }
+        { .name = "common", .irq = 22 + OMAP_INTC_START, },
+        { .name = "tx", .irq = 89 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 90 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
@@ -1189,10 +1236,10 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
 
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
-        { .name = "common", .irq = 23 },
-        { .name = "tx", .irq = 54 },
-        { .name = "rx", .irq = 55 },
-        { .irq = -1 }
+        { .name = "common", .irq = 23 + OMAP_INTC_START, },
+        { .name = "tx", .irq = 54 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 55 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
@@ -1222,10 +1269,10 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
 
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
-        { .name = "common", .irq = 27 },
-        { .name = "tx", .irq = 81 },
-        { .name = "rx", .irq = 82 },
-        { .irq = -1 }
+        { .name = "common", .irq = 27 + OMAP_INTC_START, },
+        { .name = "tx", .irq = 81 + OMAP_INTC_START, },
+        { .name = "rx", .irq = 82 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
@@ -1267,8 +1314,8 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
 
 /* mcbsp2_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
-        { .name = "irq", .irq = 4 },
-        { .irq = -1 }
+        { .name = "irq", .irq = 4 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
@@ -1289,8 +1336,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
 
 /* mcbsp3_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
-        { .name = "irq", .irq = 5 },
-        { .irq = -1 }
+        { .name = "irq", .irq = 5 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
@@ -1352,8 +1399,8 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
-        { .irq = 18 },
-        { .irq = -1 }
+        { .irq = 18 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap34xx_sr1_hwmod = {
@@ -1397,8 +1444,8 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
-        { .irq = 19 },
-        { .irq = -1 }
+        { .irq = 19 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap34xx_sr2_hwmod = {
@@ -1458,8 +1505,8 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
-        { .irq = 26 },
-        { .irq = -1 }
+        { .irq = 26 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
@@ -1549,8 +1596,8 @@ static struct omap_hwmod omap34xx_mcspi2 = {
 
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
-        { .name = "irq", .irq = 91 }, /* 91 */
-        { .irq = -1 }
+        { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -1585,8 +1632,8 @@ static struct omap_hwmod omap34xx_mcspi3 = {
 
 /* mcspi4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
-        { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
-        { .irq = -1 }
+        { .name = "irq", .irq = 48 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
@@ -1638,9 +1685,9 @@ static struct omap_hwmod_class usbotg_class = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
 
-        { .name = "mc", .irq = 92 },
-        { .name = "dma", .irq = 93 },
-        { .irq = -1 }
+        { .name = "mc", .irq = 92 + OMAP_INTC_START, },
+        { .name = "dma", .irq = 93 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
@@ -1670,8 +1717,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
 
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
-        { .name = "mc", .irq = 71 },
-        { .irq = -1 }
+        { .name = "mc", .irq = 71 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -1706,8 +1753,8 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
 /* MMC/SD/SDIO1 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
-        { .irq = 83, },
-        { .irq = -1 }
+        { .irq = 83 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
@@ -1773,8 +1820,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
 /* MMC/SD/SDIO2 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
-        { .irq = INT_24XX_MMC2_IRQ, },
-        { .irq = -1 }
+        { .irq = 86 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
@@ -1834,8 +1881,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
 /* MMC/SD/SDIO3 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
-        { .irq = 94, },
-        { .irq = -1 }
+        { .irq = 94 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
@@ -1893,9 +1940,9 @@ static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
-        { .name = "ohci-irq", .irq = 76 },
-        { .name = "ehci-irq", .irq = 77 },
-        { .irq = -1 }
+        { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
+        { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
@@ -1987,8 +2034,8 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
-        { .name = "tll-irq", .irq = 78 },
-        { .irq = -1 }
+        { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
@@ -2024,6 +2071,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
         .class          = &omap2_hdq1w_class,
 };
 
+/* SAD2D */
+static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
+        { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
+        { .name = "rst_modem_sw", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_class omap3xxx_sad2d_class = {
+        .name                   = "sad2d",
+};
+
+static struct omap_hwmod omap3xxx_sad2d_hwmod = {
+        .name           = "sad2d",
+        .rst_lines      = omap3xxx_sad2d_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
+        .main_clk       = "sad2d_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SAD2D_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_sad2d_class,
+};
+
 /*
  * '32K sync counter' class
  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
@@ -2059,6 +2133,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap3xxx_gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap3xxx_gpmc_hwmod_class,
+        .clkdm_name     = "core_l3_clkdm",
+        .mpu_irqs       = omap3xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+};
+
+/*
  * interfaces
  */
 
@@ -2093,6 +2210,23 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
         .user   = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
+        {
+                .pa_start       = 0x54000000,
+                .pa_end         = 0x547fffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3 -> debugss */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_debugss_hwmod,
+        .addr           = omap3xxx_l4_emu_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 /* DSS -> l3 */
 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
         .master         = &omap3430es1_dss_core_hwmod,
@@ -2128,6 +2262,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
         .user           = OCP_USER_MPU,
 };
 
+/* l3_core -> sad2d interface */
+static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
+        .master         = &omap3xxx_sad2d_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -2814,6 +2956,122 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+
+/* mmu isp */
+
+static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 8,
+};
+
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
+        { .irq = 24 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
+        {
+                .pa_start       = 0x480bd400,
+                .pa_end         = 0x480bd47f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> mmu isp */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmu_isp_hwmod,
+        .addr           = omap3xxx_mmu_isp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
+        .name           = "mmu_isp",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_isp_irqs,
+        .main_clk       = "cam_ick",
+        .dev_attr       = &mmu_isp_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+
+/* mmu iva */
+
+static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
+        .da_start       = 0x11000000,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
+        { .irq = 28 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
+        { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
+        {
+                .pa_start       = 0x5d000000,
+                .pa_end         = 0x5d00007f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3_main -> iva mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_mmu_iva_hwmod,
+        .addr           = omap3xxx_mmu_iva_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
+        .name           = "mmu_iva",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_iva_irqs,
+        .rst_lines      = omap3xxx_mmu_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
+        .main_clk       = "iva2_ck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430_IVA2_MOD,
+                },
+        },
+        .dev_attr       = &mmu_iva_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+#endif
+
 /* l4_per -> gpio4 */
 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
         {
@@ -3159,6 +3417,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
         .master         = &omap3xxx_l4_wkup_hwmod,
         .slave          = &omap3xxx_counter_32k_hwmod,
@@ -3214,11 +3481,11 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
 };
 
 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
-        { .name = "rxthresh",   .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
-        { .name = "rx_pulse",   .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
-        { .name = "tx_pulse",   .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
-        { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
-        { .irq = -1 }
+        { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
+        { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
+        { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
+        { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
+        { .irq = -1 },
 };
 
 static struct omap_hwmod_class am35xx_emac_class = {
@@ -3268,10 +3535,19 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
         .user           = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_gpmc_hwmod,
+        .clk            = "core_l3_ick",
+        .addr           = omap3xxx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
         &omap3xxx_mpu__l3_main,
+        &omap3xxx_l3_main__l4_debugss,
         &omap3xxx_l4_core__l4_wkup,
         &omap3xxx_l4_core__mmc3,
         &omap3_l4_core__uart1,
@@ -3313,6 +3589,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap34xx_l4_core__mcspi3,
         &omap34xx_l4_core__mcspi4,
         &omap3xxx_l4_wkup__counter_32k,
+        &omap3xxx_l3_main__gpmc,
         NULL,
 };
 
@@ -3362,6 +3639,11 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
         &omap34xx_l4_core__sr2,
         &omap3xxx_l4_core__mailbox,
         &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
         NULL
 };
 
@@ -3382,6 +3664,11 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_core__es3plus_mmc1,
         &omap3xxx_l4_core__es3plus_mmc2,
         &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
         NULL
 };
 
@@ -3396,6 +3683,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_core__usb_tll_hs,
         &omap3xxx_l4_core__es3plus_mmc1,
         &omap3xxx_l4_core__es3plus_mmc2,
+        &omap3xxx_l4_core__hdq1w,
         &am35xx_mdio__l3,
         &am35xx_l4_core__mdio,
         &am35xx_emac__l3,
@@ -3450,7 +3738,7 @@ int __init omap3xxx_hwmod_init(void)
         } else {
                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                 return -EINVAL;
-        };
+        }
 
         r = omap_hwmod_register_links(h);
         if (r < 0)
@@ -3467,7 +3755,7 @@ int __init omap3xxx_hwmod_init(void)
                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                    rev == OMAP3430_REV_ES3_1_2) {
                 h = omap3430es2plus_hwmod_ocp_ifs;
-        };
+        }
 
         if (h) {
                 r = omap_hwmod_register_links(h);
@@ -3482,7 +3770,7 @@ int __init omap3xxx_hwmod_init(void)
         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                    rev == OMAP3430_REV_ES3_1_2) {
                 h = omap3430_es3plus_hwmod_ocp_ifs;
-        };
+        }
 
         if (h)
                 r = omap_hwmod_register_links(h);
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 242aee498ceb..652d0285bd6d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -19,18 +19,18 @@
  */
 
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/dma.h>
-#include <plat/mcspi.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
+#include <plat/iommu.h>
 
 #include "omap_hwmod_common_data.h"
 #include "cm1_44xx.h"
@@ -203,6 +203,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
+                        .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
                 },
         },
 };
@@ -259,6 +262,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
         .name           = "mpu_private",
         .class          = &omap44xx_mpu_bus_hwmod_class,
         .clkdm_name     = "mpuss_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -343,6 +351,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
@@ -447,6 +456,11 @@ static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_pad_core */
@@ -454,6 +468,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
         .name           = "ctrl_module_pad_core",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_wkup */
@@ -461,6 +480,11 @@ static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
         .name           = "ctrl_module_wkup",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_pad_wkup */
@@ -468,6 +492,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
         .name           = "ctrl_module_pad_wkup",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -612,7 +641,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
         { .name = "dsp", .rst_shift = 0 },
-        { .name = "mmu_cache", .rst_shift = 1 },
 };
 
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1324,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
         .name           = "gpmc",
         .class          = &omap44xx_gpmc_hwmod_class,
         .clkdm_name     = "l3_2_clkdm",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_gpmc_irqs,
         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
@@ -1632,7 +1668,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
         { .name = "cpu0", .rst_shift = 0 },
         { .name = "cpu1", .rst_shift = 1 },
-        { .name = "mmu_cache", .rst_shift = 2 },
 };
 
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2439,6 +2474,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
 };
 
 /*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+
+/* mmu ipu */
+
+static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
+        { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
+        {
+                .pa_start       = 0x55082000,
+                .pa_end         = 0x550820ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3_main_2 -> mmu_ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_mmu_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_mmu_ipu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
+        .name           = "mmu_ipu",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
+        .mpu_irqs       = omap44xx_mmu_ipu_irqs,
+        .rst_lines      = omap44xx_mmu_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
+        .main_clk       = "ducati_clk_mux_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_ipu_dev_attr,
+};
+
+/* mmu dsp */
+
+static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
+        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
+        {
+                .pa_start       = 0x4a066000,
+                .pa_end         = 0x4a0660ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mmu_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmu_dsp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
+        .name           = "mmu_dsp",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "tesla_clkdm",
+        .mpu_irqs       = omap44xx_mmu_dsp_irqs,
+        .rst_lines      = omap44xx_mmu_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
+        .main_clk       = "dpll_iva_m4x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_dsp_dev_attr,
+};
+
+/*
  * 'mpu' class
  * mpu sub-system
  */
@@ -2449,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 
 /* mpu */
 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
+        { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
@@ -2498,19 +2666,27 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
  * protocol
  */
 
+static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
         .name   = "ocp2scp",
+        .sysc   = &omap44xx_ocp2scp_sysc,
 };
 
 /* ocp2scp_usb_phy */
-static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
-        { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
-};
-
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
         .class          = &omap44xx_ocp2scp_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "ocp2scp_usb_phy_phy_48m",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -2518,8 +2694,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .opt_clks       = ocp2scp_usb_phy_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
@@ -2537,18 +2711,36 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
         .name           = "prcm_mpu",
         .class          = &omap44xx_prcm_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* cm_core_aon */
 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
         .name           = "cm_core_aon",
         .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* cm_core */
 static struct omap_hwmod omap44xx_cm_core_hwmod = {
         .name           = "cm_core",
         .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* prm */
@@ -2584,6 +2776,11 @@ static struct omap_hwmod omap44xx_scrm_hwmod = {
         .name           = "scrm",
         .class          = &omap44xx_scrm_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -2902,6 +3099,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3006,6 +3213,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer6 */
@@ -3028,6 +3236,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer7 */
@@ -3049,6 +3258,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer8 */
@@ -3070,7 +3280,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
 };
 
 /* timer9 */
@@ -4210,7 +4420,7 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 };
 
 /* dsp -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
         .master         = &omap44xx_dsp_hwmod,
         .slave          = &omap44xx_sl2if_hwmod,
         .clk            = "dpll_iva_m5x2_ck",
@@ -4828,7 +5038,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
 };
 
 /* iva -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
         .master         = &omap44xx_iva_hwmod,
         .slave          = &omap44xx_sl2if_hwmod,
         .clk            = "dpll_iva_m5x2_ck",
@@ -5059,6 +5269,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
 
 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
         {
+                .name           = "mpu",
                 .pa_start       = 0x40132000,
                 .pa_end         = 0x4013207f,
                 .flags          = ADDR_TYPE_RT
@@ -5077,6 +5288,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
 
 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
         {
+                .name           = "dma",
                 .pa_start       = 0x49032000,
                 .pa_end         = 0x4903207f,
                 .flags          = ADDR_TYPE_RT
@@ -5263,11 +5475,21 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
+        {
+                .pa_start       = 0x4a0ad000,
+                .pa_end         = 0x4a0ad01f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
         .clk            = "l4_div_ck",
+        .addr           = omap44xx_ocp2scp_usb_phy_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5362,7 +5584,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
 };
 
 /* l3_main_2 -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_sl2if_hwmod,
         .clk            = "l3_div_ck",
@@ -5887,7 +6109,13 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
         {
                 .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab003,
+                .pa_end         = 0x4a0ab7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                /* XXX: Remove this once control module driver is in place */
+                .pa_start       = 0x4a00233c,
+                .pa_end         = 0x4a00233f,
                 .flags          = ADDR_TYPE_RT
         },
         { }
@@ -6032,7 +6260,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_abe__dmic,
         &omap44xx_l4_abe__dmic_dma,
         &omap44xx_dsp__iva,
-        &omap44xx_dsp__sl2if,
+        /* &omap44xx_dsp__sl2if, */
         &omap44xx_l4_cfg__dsp,
         &omap44xx_l3_main_2__dss,
         &omap44xx_l4_per__dss,
@@ -6068,7 +6296,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__i2c4,
         &omap44xx_l3_main_2__ipu,
         &omap44xx_l3_main_2__iss,
-        &omap44xx_iva__sl2if,
+        /* &omap44xx_iva__sl2if, */
         &omap44xx_l3_main_2__iva,
         &omap44xx_l4_wkup__kbd,
         &omap44xx_l4_cfg__mailbox,
@@ -6092,6 +6320,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__mmc3,
         &omap44xx_l4_per__mmc4,
         &omap44xx_l4_per__mmc5,
+        &omap44xx_l3_main_2__mmu_ipu,
+        &omap44xx_l4_cfg__mmu_dsp,
         &omap44xx_l3_main_2__ocmc_ram,
         &omap44xx_l4_cfg__ocp2scp_usb_phy,
         &omap44xx_mpu_private__prcm_mpu,
@@ -6099,7 +6329,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_cfg__cm_core,
         &omap44xx_l4_wkup__prm,
         &omap44xx_l4_wkup__scrm,
-        &omap44xx_l3_main_2__sl2if,
+        /* &omap44xx_l3_main_2__sl2if, */
         &omap44xx_l4_abe__slimbus1,
         &omap44xx_l4_abe__slimbus1_dma,
         &omap44xx_l4_per__slimbus2,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index e7e8eeae95e5..2bc8f1705d4a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -2,9 +2,8 @@
  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
  *
  * Copyright (C) 2010-2011 Nokia Corporation
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
  * Paul Walmsley
- *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Benoît Cousson
  *
  * This program is free software; you can redistribute it and/or modify
@@ -16,6 +15,7 @@
 
 #include <plat/omap_hwmod.h>
 
+#include "common.h"
 #include "display.h"
 
 /* Common address space across OMAP2xxx */
@@ -76,6 +76,8 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+extern struct omap_hwmod omap2xxx_gpmc_hwmod;
+extern struct omap_hwmod omap2xxx_rng_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -102,6 +104,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
deleted file mode 100644
index d15225ff5c49..000000000000
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * OMAP4XXX L3 Interconnect error handling driver
- *
- * Copyright (C) 2011 Texas Corporation
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#include "omap_l3_noc.h"
-
-/*
- * Interrupt Handler for L3 error detection.
- *      1) Identify the L3 clockdomain partition to which the error belongs to.
- *      2) Identify the slave where the error information is logged
- *      3) Print the logged information.
- *      4) Add dump stack to provide kernel trace.
- *
- * Two Types of errors :
- *      1) Custom errors in L3 :
- *              Target like DMM/FW/EMIF generates SRESP=ERR error
- *      2) Standard L3 error:
- *              - Unsupported CMD.
- *                      L3 tries to access target while it is idle
- *              - OCP disconnect.
- *              - Address hole error:
- *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
- *                      do not have connectivity, the error is logged in
- *                      their default target which is DMM2.
- *
- *      On High Secure devices, firewall errors are possible and those
- *      can be trapped as well. But the trapping is implemented as part
- *      secure software and hence need not be implemented here.
- */
-static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
-{
-
-        struct omap4_l3 *l3 = _l3;
-        int inttype, i, k;
-        int err_src = 0;
-        u32 std_err_main, err_reg, clear, masterid;
-        void __iomem *base, *l3_targ_base;
-        char *target_name, *master_name = "UN IDENTIFIED";
-
-        /* Get the Type of interrupt */
-        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
-
-        for (i = 0; i < L3_MODULES; i++) {
-                /*
-                 * Read the regerr register of the clock domain
-                 * to determine the source
-                 */
-                base = l3->l3_base[i];
-                err_reg = __raw_readl(base + l3_flagmux[i] +
-                                        + L3_FLAGMUX_REGERR0 + (inttype << 3));
-
-                /* Get the corresponding error and analyse */
-                if (err_reg) {
-                        /* Identify the source from control status register */
-                        err_src = __ffs(err_reg);
-
-                        /* Read the stderrlog_main_source from clk domain */
-                        l3_targ_base = base + *(l3_targ[i] + err_src);
-                        std_err_main =  __raw_readl(l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                        masterid = __raw_readl(l3_targ_base +
-                                        L3_TARG_STDERRLOG_MSTADDR);
-
-                        switch (std_err_main & CUSTOM_ERROR) {
-                        case STANDARD_ERROR:
-                                target_name =
-                                        l3_targ_inst_name[i][err_src];
-                                WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
-                                        target_name,
-                                        __raw_readl(l3_targ_base +
-                                                L3_TARG_STDERRLOG_SLVOFSLSB));
-                                /* clear the std error log*/
-                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                                break;
-
-                        case CUSTOM_ERROR:
-                                target_name =
-                                        l3_targ_inst_name[i][err_src];
-                                for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
-                                        if (masterid == l3_masters[k].id)
-                                                master_name =
-                                                        l3_masters[k].name;
-                                }
-                                WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
-                                        master_name, target_name);
-                                /* clear the std error log*/
-                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                                break;
-
-                        default:
-                                /* Nothing to be handled here as of now */
-                                break;
-                        }
-                /* Error found so break the for loop */
-                break;
-                }
-        }
-        return IRQ_HANDLED;
-}
-
-static int __devinit omap4_l3_probe(struct platform_device *pdev)
-{
-        static struct omap4_l3 *l3;
-        struct resource *res;
-        int ret;
-
-        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, l3);
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 0\n");
-                ret = -ENODEV;
-                goto err0;
-        }
-
-        l3->l3_base[0] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[0]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 1\n");
-                ret = -ENODEV;
-                goto err1;
-        }
-
-        l3->l3_base[1] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[1]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 2\n");
-                ret = -ENODEV;
-                goto err2;
-        }
-
-        l3->l3_base[2] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[2]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err2;
-        }
-
-        /*
-         * Setup interrupt Handlers
-         */
-        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(l3->debug_irq,
-                        l3_interrupt_handler,
-                        IRQF_DISABLED, "l3-dbg-irq", l3);
-        if (ret) {
-                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                                OMAP44XX_IRQ_L3_DBG);
-                goto err3;
-        }
-
-        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(l3->app_irq,
-                        l3_interrupt_handler,
-                        IRQF_DISABLED, "l3-app-irq", l3);
-        if (ret) {
-                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                                OMAP44XX_IRQ_L3_APP);
-                goto err4;
-        }
-
-        return 0;
-
-err4:
-        free_irq(l3->debug_irq, l3);
-err3:
-        iounmap(l3->l3_base[2]);
-err2:
-        iounmap(l3->l3_base[1]);
-err1:
-        iounmap(l3->l3_base[0]);
-err0:
-        kfree(l3);
-        return ret;
-}
-
-static int __devexit omap4_l3_remove(struct platform_device *pdev)
-{
-        struct omap4_l3 *l3 = platform_get_drvdata(pdev);
-
-        free_irq(l3->app_irq, l3);
-        free_irq(l3->debug_irq, l3);
-        iounmap(l3->l3_base[0]);
-        iounmap(l3->l3_base[1]);
-        iounmap(l3->l3_base[2]);
-        kfree(l3);
-
-        return 0;
-}
-
-#if defined(CONFIG_OF)
-static const struct of_device_id l3_noc_match[] = {
-        {.compatible = "ti,omap4-l3-noc", },
-        {},
-};
-MODULE_DEVICE_TABLE(of, l3_noc_match);
-#else
-#define l3_noc_match NULL
-#endif
-
-static struct platform_driver omap4_l3_driver = {
-        .probe          = omap4_l3_probe,
-        .remove         = __devexit_p(omap4_l3_remove),
-        .driver         = {
-                .name           = "omap_l3_noc",
-                .owner          = THIS_MODULE,
-                .of_match_table = l3_noc_match,
-        },
-};
-
-static int __init omap4_l3_init(void)
-{
-        return platform_driver_register(&omap4_l3_driver);
-}
-postcore_initcall_sync(omap4_l3_init);
-
-static void __exit omap4_l3_exit(void)
-{
-        platform_driver_unregister(&omap4_l3_driver);
-}
-module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
deleted file mode 100644
index a6ce34dc4814..000000000000
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * OMAP4XXX L3 Interconnect  error handling driver header
- *
- * Copyright (C) 2011 Texas Corporation
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-
-#define L3_MODULES                      3
-#define CLEAR_STDERR_LOG                (1 << 31)
-#define CUSTOM_ERROR                    0x2
-#define STANDARD_ERROR                  0x0
-#define INBAND_ERROR                    0x0
-#define L3_APPLICATION_ERROR            0x0
-#define L3_DEBUG_ERROR                  0x1
-
-/* L3 TARG register offsets */
-#define L3_TARG_STDERRLOG_MAIN          0x48
-#define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
-#define L3_TARG_STDERRLOG_MSTADDR       0x68
-#define L3_FLAGMUX_REGERR0              0xc
-
-#define NUM_OF_L3_MASTERS       (sizeof(l3_masters)/sizeof(l3_masters[0]))
-
-static u32 l3_flagmux[L3_MODULES] = {
-        0x500,
-        0x1000,
-        0X0200
-};
-
-/* L3 Target standard Error register offsets */
-static u32 l3_targ_inst_clk1[] = {
-        0x100, /* DMM1 */
-        0x200, /* DMM2 */
-        0x300, /* ABE */
-        0x400, /* L4CFG */
-        0x600,  /* CLK2 PWR DISC */
-        0x0,    /* Host CLK1 */
-        0x900   /* L4 Wakeup */
-};
-
-static u32 l3_targ_inst_clk2[] = {
-        0x500, /* CORTEX M3 */
-        0x300, /* DSS */
-        0x100, /* GPMC */
-        0x400, /* ISS */
-        0x700, /* IVAHD */
-        0xD00, /* missing in TRM  corresponds to AES1*/
-        0x900, /* L4 PER0*/
-        0x200, /* OCMRAM */
-        0x100, /* missing in TRM corresponds to GPMC sERROR*/
-        0x600, /* SGX */
-        0x800, /* SL2 */
-        0x1600, /* C2C */
-        0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
-        0xF00, /* missing in TRM corrsponds to SHA1*/
-        0xE00, /* missing in TRM corresponds to AES2*/
-        0xC00, /* L4 PER3 */
-        0xA00, /* L4 PER1*/
-        0xB00, /* L4 PER2*/
-        0x0, /* HOST CLK2 */
-        0x1800, /* CAL */
-        0x1700 /* LLI */
-};
-
-static u32 l3_targ_inst_clk3[] = {
-        0x0100  /* EMUSS */,
-        0x0300, /* DEBUGSS_CT_TBR */
-        0x0 /* HOST CLK3 */
-};
-
-static struct l3_masters_data {
-        u32 id;
-        char name[10];
-} l3_masters[] = {
-        { 0x0 , "MPU"},
-        { 0x10, "CS_ADP"},
-        { 0x14, "xxx"},
-        { 0x20, "DSP"},
-        { 0x30, "IVAHD"},
-        { 0x40, "ISS"},
-        { 0x44, "DucatiM3"},
-        { 0x48, "FaceDetect"},
-        { 0x50, "SDMA_Rd"},
-        { 0x54, "SDMA_Wr"},
-        { 0x58, "xxx"},
-        { 0x5C, "xxx"},
-        { 0x60, "SGX"},
-        { 0x70, "DSS"},
-        { 0x80, "C2C"},
-        { 0x88, "xxx"},
-        { 0x8C, "xxx"},
-        { 0x90, "HSI"},
-        { 0xA0, "MMC1"},
-        { 0xA4, "MMC2"},
-        { 0xA8, "MMC6"},
-        { 0xB0, "UNIPRO1"},
-        { 0xC0, "USBHOSTHS"},
-        { 0xC4, "USBOTGHS"},
-        { 0xC8, "USBHOSTFS"}
-};
-
-static char *l3_targ_inst_name[L3_MODULES][21] = {
-        {
-                "DMM1",
-                "DMM2",
-                "ABE",
-                "L4CFG",
-                "CLK2 PWR DISC",
-                "HOST CLK1",
-                "L4 WAKEUP"
-        },
-        {
-                "CORTEX M3" ,
-                "DSS ",
-                "GPMC ",
-                "ISS ",
-                "IVAHD ",
-                "AES1",
-                "L4 PER0",
-                "OCMRAM ",
-                "GPMC sERROR",
-                "SGX ",
-                "SL2 ",
-                "C2C ",
-                "PWR DISC CLK1",
-                "SHA1",
-                "AES2",
-                "L4 PER3",
-                "L4 PER1",
-                "L4 PER2",
-                "HOST CLK2",
-                "CAL",
-                "LLI"
-        },
-        {
-                "EMUSS",
-                "DEBUG SOURCE",
-                "HOST CLK3"
-        },
-};
-
-static u32 *l3_targ[L3_MODULES] = {
-        l3_targ_inst_clk1,
-        l3_targ_inst_clk2,
-        l3_targ_inst_clk3,
-};
-
-struct omap4_l3 {
-        struct device *dev;
-        struct clk *ick;
-
-        /* memory base */
-        void __iomem *l3_base[L3_MODULES];
-
-        int debug_irq;
-        int app_irq;
-};
-#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
deleted file mode 100644
index acc216491b8a..000000000000
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * OMAP3XXX L3 Interconnect Driver
- *
- * Copyright (C) 2011 Texas Corporation
- *      Felipe Balbi <balbi@ti.com>
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include "omap_l3_smx.h"
-
-static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
-{
-        return __raw_readll(base + reg);
-}
-
-static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
-{
-        __raw_writell(value, base + reg);
-}
-
-static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
-{
-        return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
-}
-
-static inline u32 omap3_l3_decode_addr(u64 error_addr)
-{
-        return error_addr & 0xffffffff;
-}
-
-static inline unsigned omap3_l3_decode_cmd(u64 error)
-{
-        return (error & 0x07) >> L3_ERROR_LOG_CMD;
-}
-
-static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
-{
-        return (error & 0xff00) >> L3_ERROR_LOG_INITID;
-}
-
-static inline unsigned omap3_l3_decode_req_info(u64 error)
-{
-        return (error >> 32) & 0xffff;
-}
-
-static char *omap3_l3_code_string(u8 code)
-{
-        switch (code) {
-        case OMAP_L3_CODE_NOERROR:
-                return "No Error";
-        case OMAP_L3_CODE_UNSUP_CMD:
-                return "Unsupported Command";
-        case OMAP_L3_CODE_ADDR_HOLE:
-                return "Address Hole";
-        case OMAP_L3_CODE_PROTECT_VIOLATION:
-                return "Protection Violation";
-        case OMAP_L3_CODE_IN_BAND_ERR:
-                return "In-band Error";
-        case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
-                return "Request Timeout Not Accepted";
-        case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
-                return "Request Timeout, no response";
-        default:
-                return "UNKNOWN error";
-        }
-}
-
-static char *omap3_l3_initiator_string(u8 initid)
-{
-        switch (initid) {
-        case OMAP_L3_LCD:
-                return "LCD";
-        case OMAP_L3_SAD2D:
-                return "SAD2D";
-        case OMAP_L3_IA_MPU_SS_1:
-        case OMAP_L3_IA_MPU_SS_2:
-        case OMAP_L3_IA_MPU_SS_3:
-        case OMAP_L3_IA_MPU_SS_4:
-        case OMAP_L3_IA_MPU_SS_5:
-                return "MPU";
-        case OMAP_L3_IA_IVA_SS_1:
-        case OMAP_L3_IA_IVA_SS_2:
-        case OMAP_L3_IA_IVA_SS_3:
-                return "IVA_SS";
-        case OMAP_L3_IA_IVA_SS_DMA_1:
-        case OMAP_L3_IA_IVA_SS_DMA_2:
-        case OMAP_L3_IA_IVA_SS_DMA_3:
-        case OMAP_L3_IA_IVA_SS_DMA_4:
-        case OMAP_L3_IA_IVA_SS_DMA_5:
-        case OMAP_L3_IA_IVA_SS_DMA_6:
-                return "IVA_SS_DMA";
-        case OMAP_L3_IA_SGX:
-                return "SGX";
-        case OMAP_L3_IA_CAM_1:
-        case OMAP_L3_IA_CAM_2:
-        case OMAP_L3_IA_CAM_3:
-                return "CAM";
-        case OMAP_L3_IA_DAP:
-                return "DAP";
-        case OMAP_L3_SDMA_WR_1:
-        case OMAP_L3_SDMA_WR_2:
-                return "SDMA_WR";
-        case OMAP_L3_SDMA_RD_1:
-        case OMAP_L3_SDMA_RD_2:
-        case OMAP_L3_SDMA_RD_3:
-        case OMAP_L3_SDMA_RD_4:
-                return "SDMA_RD";
-        case OMAP_L3_USBOTG:
-                return "USB_OTG";
-        case OMAP_L3_USBHOST:
-                return "USB_HOST";
-        default:
-                return "UNKNOWN Initiator";
-        }
-}
-
-/*
- * omap3_l3_block_irq - handles a register block's irq
- * @l3: struct omap3_l3 *
- * @base: register block base address
- * @error: L3_ERROR_LOG register of our block
- *
- * Called in hard-irq context. Caller should take care of locking
- *
- * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
- * Analysis Sequence, we are following that sequence here, please
- * refer to that Figure for more information on the subject.
- */
-static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
-                                        u64 error, int error_addr)
-{
-        u8 code = omap3_l3_decode_error_code(error);
-        u8 initid = omap3_l3_decode_initid(error);
-        u8 multi = error & L3_ERROR_LOG_MULTI;
-        u32 address = omap3_l3_decode_addr(error_addr);
-
-        pr_err("%s seen by %s %s at address %x\n",
-                        omap3_l3_code_string(code),
-                        omap3_l3_initiator_string(initid),
-                        multi ? "Multiple Errors" : "", address);
-        WARN_ON(1);
-
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
-{
-        struct omap3_l3 *l3 = _l3;
-        u64 status, clear;
-        u64 error;
-        u64 error_addr;
-        u64 err_source = 0;
-        void __iomem *base;
-        int int_type;
-        irqreturn_t ret = IRQ_NONE;
-
-        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
-        if (!int_type) {
-                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
-                /*
-                 * if we have a timeout error, there's nothing we can
-                 * do besides rebooting the board. So let's BUG on any
-                 * of such errors and handle the others. timeout error
-                 * is severe and not expected to occur.
-                 */
-                BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
-        } else {
-                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
-                /* No timeout error for debug sources */
-        }
-
-        /* identify the error source */
-        err_source = __ffs(status);
-
-        base = l3->rt + omap3_l3_bases[int_type][err_source];
-        error = omap3_l3_readll(base, L3_ERROR_LOG);
-        if (error) {
-                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
-                ret |= omap3_l3_block_irq(l3, error, error_addr);
-        }
-
-        /* Clear the status register */
-        clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
-                L3_AGENT_STATUS_CLEAR_TA;
-        omap3_l3_writell(base, L3_AGENT_STATUS, clear);
-
-        /* clear the error log register */
-        omap3_l3_writell(base, L3_ERROR_LOG, error);
-
-        return ret;
-}
-
-static int __init omap3_l3_probe(struct platform_device *pdev)
-{
-        struct omap3_l3 *l3;
-        struct resource *res;
-        int ret;
-
-        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, l3);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource\n");
-                ret = -ENODEV;
-                goto err0;
-        }
-        l3->rt = ioremap(res->start, resource_size(res));
-        if (!l3->rt) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-
-        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                "l3-debug-irq", l3);
-        if (ret) {
-                dev_err(&pdev->dev, "couldn't request debug irq\n");
-                goto err1;
-        }
-
-        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(l3->app_irq, omap3_l3_app_irq,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                "l3-app-irq", l3);
-        if (ret) {
-                dev_err(&pdev->dev, "couldn't request app irq\n");
-                goto err2;
-        }
-
-        return 0;
-
-err2:
-        free_irq(l3->debug_irq, l3);
-err1:
-        iounmap(l3->rt);
-err0:
-        kfree(l3);
-        return ret;
-}
-
-static int __exit omap3_l3_remove(struct platform_device *pdev)
-{
-        struct omap3_l3         *l3 = platform_get_drvdata(pdev);
-
-        free_irq(l3->app_irq, l3);
-        free_irq(l3->debug_irq, l3);
-        iounmap(l3->rt);
-        kfree(l3);
-
-        return 0;
-}
-
-static struct platform_driver omap3_l3_driver = {
-        .remove         = __exit_p(omap3_l3_remove),
-        .driver         = {
-        .name   = "omap_l3_smx",
-        },
-};
-
-static int __init omap3_l3_init(void)
-{
-        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
-}
-postcore_initcall_sync(omap3_l3_init);
-
-static void __exit omap3_l3_exit(void)
-{
-        platform_driver_unregister(&omap3_l3_driver);
-}
-module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
deleted file mode 100644
index 4f3cebca4179..000000000000
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * OMAP3XXX L3 Interconnect Driver header
- *
- * Copyright (C) 2011 Texas Corporation
- *      Felipe Balbi <balbi@ti.com>
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-
-/* Register definitions. All 64-bit wide */
-#define L3_COMPONENT                    0x000
-#define L3_CORE                         0x018
-#define L3_AGENT_CONTROL                0x020
-#define L3_AGENT_STATUS                 0x028
-#define L3_ERROR_LOG                    0x058
-
-#define L3_ERROR_LOG_MULTI              (1 << 31)
-#define L3_ERROR_LOG_SECONDARY          (1 << 30)
-
-#define L3_ERROR_LOG_ADDR               0x060
-
-/* Register definitions for Sideband Interconnect */
-#define L3_SI_CONTROL                   0x020
-#define L3_SI_FLAG_STATUS_0             0x510
-
-static const u64 shift = 1;
-
-#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
-#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
-#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
-#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
-#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
-#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
-#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
-#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
-#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
-#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
-#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
-#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
-#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
-#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
-#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
-#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
-#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
-#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
-#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
-#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
-#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
-#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
-#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
-#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
-#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
-#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
-#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
-#define L3_STATUS_0_IVATA_REQ           (shift << 54)
-#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
-#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
-#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
-#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
-#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
-#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
-#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
-
-#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
-                                        | L3_STATUS_0_MPUIA_RSP         \
-                                        | L3_STATUS_0_IVAIA_BRST        \
-                                        | L3_STATUS_0_IVAIA_RSP         \
-                                        | L3_STATUS_0_SGXIA_BRST        \
-                                        | L3_STATUS_0_SGXIA_RSP         \
-                                        | L3_STATUS_0_CAMIA_BRST        \
-                                        | L3_STATUS_0_CAMIA_RSP         \
-                                        | L3_STATUS_0_DISPIA_BRST       \
-                                        | L3_STATUS_0_DISPIA_RSP        \
-                                        | L3_STATUS_0_DMARDIA_BRST      \
-                                        | L3_STATUS_0_DMARDIA_RSP       \
-                                        | L3_STATUS_0_DMAWRIA_BRST      \
-                                        | L3_STATUS_0_DMAWRIA_RSP       \
-                                        | L3_STATUS_0_USBOTGIA_BRST     \
-                                        | L3_STATUS_0_USBOTGIA_RSP      \
-                                        | L3_STATUS_0_USBHOSTIA_BRST    \
-                                        | L3_STATUS_0_SMSTA_REQ         \
-                                        | L3_STATUS_0_GPMCTA_REQ        \
-                                        | L3_STATUS_0_OCMRAMTA_REQ      \
-                                        | L3_STATUS_0_OCMROMTA_REQ      \
-                                        | L3_STATUS_0_IVATA_REQ         \
-                                        | L3_STATUS_0_SGXTA_REQ         \
-                                        | L3_STATUS_0_L4CORETA_REQ      \
-                                        | L3_STATUS_0_L4PERTA_REQ       \
-                                        | L3_STATUS_0_L4EMUTA_REQ       \
-                                        | L3_STATUS_0_MAD2DTA_REQ)
-
-#define L3_SI_FLAG_STATUS_1             0x530
-
-#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
-#define L3_STATUS_1_DAPIA0              (1 << 3)
-#define L3_STATUS_1_DAPIA1              (1 << 4)
-#define L3_STATUS_1_IVAIA               (1 << 6)
-
-#define L3_PM_ERROR_LOG                 0x020
-#define L3_PM_CONTROL                   0x028
-#define L3_PM_ERROR_CLEAR_SINGLE        0x030
-#define L3_PM_ERROR_CLEAR_MULTI         0x038
-#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
-#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
-#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
-#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
-
-/* L3 error log bit fields. Common for IA and TA */
-#define L3_ERROR_LOG_CODE               24
-#define L3_ERROR_LOG_INITID             8
-#define L3_ERROR_LOG_CMD                0
-
-/* L3 agent status bit fields. */
-#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
-#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
-
-#define OMAP34xx_IRQ_L3_APP             10
-#define L3_APPLICATION_ERROR            0x0
-#define L3_DEBUG_ERROR                  0x1
-
-enum omap3_l3_initiator_id {
-        /* LCD has 1 ID */
-        OMAP_L3_LCD = 29,
-        /* SAD2D has 1 ID */
-        OMAP_L3_SAD2D = 28,
-        /* MPU has 5 IDs */
-        OMAP_L3_IA_MPU_SS_1 = 27,
-        OMAP_L3_IA_MPU_SS_2 = 26,
-        OMAP_L3_IA_MPU_SS_3 = 25,
-        OMAP_L3_IA_MPU_SS_4 = 24,
-        OMAP_L3_IA_MPU_SS_5 = 23,
-        /* IVA2.2 SS has 3 IDs*/
-        OMAP_L3_IA_IVA_SS_1 = 22,
-        OMAP_L3_IA_IVA_SS_2 = 21,
-        OMAP_L3_IA_IVA_SS_3 = 20,
-        /* IVA 2.2 SS DMA has 6 IDS */
-        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
-        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
-        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
-        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
-        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
-        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
-        /* SGX has 1 ID */
-        OMAP_L3_IA_SGX = 13,
-        /* CAM has 3 ID */
-        OMAP_L3_IA_CAM_1 = 12,
-        OMAP_L3_IA_CAM_2 = 11,
-        OMAP_L3_IA_CAM_3 = 10,
-        /* DAP has 1 ID */
-        OMAP_L3_IA_DAP = 9,
-        /* SDMA WR has 2 IDs */
-        OMAP_L3_SDMA_WR_1 = 8,
-        OMAP_L3_SDMA_WR_2 = 7,
-        /* SDMA RD has 4 IDs */
-        OMAP_L3_SDMA_RD_1 = 6,
-        OMAP_L3_SDMA_RD_2 = 5,
-        OMAP_L3_SDMA_RD_3 = 4,
-        OMAP_L3_SDMA_RD_4 = 3,
-        /* HSUSB OTG has 1 ID */
-        OMAP_L3_USBOTG = 2,
-        /* HSUSB HOST has 1 ID */
-        OMAP_L3_USBHOST = 1,
-};
-
-enum omap3_l3_code {
-        OMAP_L3_CODE_NOERROR = 0,
-        OMAP_L3_CODE_UNSUP_CMD = 1,
-        OMAP_L3_CODE_ADDR_HOLE = 2,
-        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
-        OMAP_L3_CODE_IN_BAND_ERR = 4,
-        /* codes 5 and 6 are reserved */
-        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
-        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
-        /* codes 9 - 15 are also reserved */
-};
-
-struct omap3_l3 {
-        struct device *dev;
-        struct clk *ick;
-
-        /* memory base*/
-        void __iomem *rt;
-
-        int debug_irq;
-        int app_irq;
-
-        /* true when and inband functional error occurs */
-        unsigned inband:1;
-};
-
-/* offsets for l3 agents in order with the Flag status register */
-static unsigned int omap3_l3_app_bases[] = {
-        /* MPU IA */
-        0x1400,
-        0x1400,
-        0x1400,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        /* IVA 2.2 IA */
-        0x1800,
-        0x1800,
-        0x1800,
-        /* SGX IA */
-        0x1c00,
-        0x1c00,
-        /* RESERVED */
-        0,
-        /* CAMERA IA */
-        0x5800,
-        0x5800,
-        0x5800,
-        /* DISPLAY IA */
-        0x5400,
-        0x5400,
-        /* RESERVED */
-        0,
-        /*SDMA RD IA */
-        0x4c00,
-        0x4c00,
-        /* RESERVED */
-        0,
-        /* SDMA WR IA */
-        0x5000,
-        0x5000,
-        /* RESERVED */
-        0,
-        /* USB OTG IA */
-        0x4400,
-        0x4400,
-        0x4400,
-        /* USB HOST IA */
-        0x4000,
-        0x4000,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        0,
-        /* SAD2D IA */
-        0x3000,
-        0x3000,
-        0x3000,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        /* SMA TA */
-        0x2000,
-        /* GPMC TA */
-        0x2400,
-        /* OCM RAM TA */
-        0x2800,
-        /* OCM ROM TA */
-        0x2C00,
-        /* L4 CORE TA */
-        0x6800,
-        /* L4 PER TA */
-        0x6c00,
-        /* IVA 2.2 TA */
-        0x6000,
-        /* SGX TA */
-        0x6400,
-        /* L4 EMU TA */
-        0x7000,
-        /* GPMC TA */
-        0x2400,
-        /* L4 CORE TA */
-        0x6800,
-        /* L4 PER TA */
-        0x6c00,
-        /* L4 EMU TA */
-        0x7000,
-        /* MAD2D TA */
-        0x3400,
-        /* RESERVED */
-        0,
-        0,
-};
-
-static unsigned int omap3_l3_debug_bases[] = {
-        /* MPU DATA IA */
-        0x1400,
-        /* RESERVED */
-        0,
-        0,
-        /* DAP IA */
-        0x5c00,
-        0x5c00,
-        /* RESERVED */
-        0,
-        /* IVA 2.2 IA */
-        0x1800,
-        /* REST RESERVED */
-};
-
-static u32 *omap3_l3_bases[] = {
-        omap3_l3_app_bases,
-        omap3_l3_debug_bases,
-};
-
-/*
- * REVISIT define __raw_readll/__raw_writell here, but move them to
- * <asm/io.h> at some point
- */
-#define __raw_writell(v, a)     (__chk_io_ptr(a), \
-                                *(volatile u64 __force *)(a) = (v))
-#define __raw_readll(a)         (__chk_io_ptr(a), \
-                                *(volatile u64 __force *)(a))
-
-#endif
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d52651a05daa..d992db8ff0b0 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -29,145 +29,9 @@
 #include <linux/usb.h>
 
 #include <plat/usb.h>
-#include "control.h"
-
-/* OMAP control module register for UTMI PHY */
-#define CONTROL_DEV_CONF                0x300
-#define PHY_PD                          0x1
-
-#define USBOTGHS_CONTROL                0x33c
-#define AVALID                          BIT(0)
-#define BVALID                          BIT(1)
-#define VBUSVALID                       BIT(2)
-#define SESSEND                         BIT(3)
-#define IDDIG                           BIT(4)
-
-static struct clk *phyclk, *clk48m, *clk32k;
-static void __iomem *ctrl_base;
-static int usbotghs_control;
-
-int omap4430_phy_init(struct device *dev)
-{
-        ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
-        if (!ctrl_base) {
-                pr_err("control module ioremap failed\n");
-                return -ENOMEM;
-        }
-        /* Power down the phy */
-        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-        if (!dev) {
-                iounmap(ctrl_base);
-                return 0;
-        }
-
-        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
-        if (IS_ERR(phyclk)) {
-                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
-                iounmap(ctrl_base);
-                return PTR_ERR(phyclk);
-        }
-
-        clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
-        if (IS_ERR(clk48m)) {
-                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
-                clk_put(phyclk);
-                iounmap(ctrl_base);
-                return PTR_ERR(clk48m);
-        }
-
-        clk32k = clk_get(dev, "usb_phy_cm_clk32k");
-        if (IS_ERR(clk32k)) {
-                dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
-                clk_put(phyclk);
-                clk_put(clk48m);
-                iounmap(ctrl_base);
-                return PTR_ERR(clk32k);
-        }
-        return 0;
-}
-
-int omap4430_phy_set_clk(struct device *dev, int on)
-{
-        static int state;
-
-        if (on && !state) {
-                /* Enable the phy clocks */
-                clk_enable(phyclk);
-                clk_enable(clk48m);
-                clk_enable(clk32k);
-                state = 1;
-        } else if (state) {
-                /* Disable the phy clocks */
-                clk_disable(phyclk);
-                clk_disable(clk48m);
-                clk_disable(clk32k);
-                state = 0;
-        }
-        return 0;
-}
-
-int omap4430_phy_power(struct device *dev, int ID, int on)
-{
-        if (on) {
-                if (ID)
-                        /* enable VBUS valid, IDDIG groung */
-                        __raw_writel(AVALID | VBUSVALID, ctrl_base +
-                                                        USBOTGHS_CONTROL);
-                else
-                        /*
-                         * Enable VBUS Valid, AValid and IDDIG
-                         * high impedance
-                         */
-                        __raw_writel(IDDIG | AVALID | VBUSVALID,
-                                                ctrl_base + USBOTGHS_CONTROL);
-        } else {
-                /* Enable session END and IDIG to high impedance. */
-                __raw_writel(SESSEND | IDDIG, ctrl_base +
-                                        USBOTGHS_CONTROL);
-        }
-        return 0;
-}
-
-int omap4430_phy_suspend(struct device *dev, int suspend)
-{
-        if (suspend) {
-                /* Disable the clocks */
-                omap4430_phy_set_clk(dev, 0);
-                /* Power down the phy */
-                __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-                /* save the context */
-                usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
-        } else {
-                /* Enable the internel phy clcoks */
-                omap4430_phy_set_clk(dev, 1);
-                /* power on the phy */
-                if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
-                        __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-                        mdelay(200);
-                }
-
-                /* restore the context */
-                __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
-        }
-
-        return 0;
-}
-
-int omap4430_phy_exit(struct device *dev)
-{
-        if (ctrl_base)
-                iounmap(ctrl_base);
-        if (phyclk)
-                clk_put(phyclk);
-        if (clk48m)
-                clk_put(clk48m);
-        if (clk32k)
-                clk_put(clk32k);
 
-        return 0;
-}
+#include "soc.h"
+#include "control.h"
 
 void am35x_musb_reset(void)
 {
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index d8f6dbf45d16..58e16aef40bb 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -18,6 +18,7 @@
  */
 #include <linux/module.h>
 #include <linux/opp.h>
+#include <linux/cpu.h>
 
 #include <plat/omap_device.h>
 
@@ -62,27 +63,34 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                                 __func__, i);
                         return -EINVAL;
                 }
-                oh = omap_hwmod_lookup(opp_def->hwmod_name);
-                if (!oh || !oh->od) {
-                        pr_debug("%s: no hwmod or odev for %s, [%d] "
-                                "cannot add OPPs.\n", __func__,
-                                opp_def->hwmod_name, i);
-                        continue;
+
+                if (!strncmp(opp_def->hwmod_name, "mpu", 3)) {
+                        /* 
+                         * All current OMAPs share voltage rail and
+                         * clock source, so CPU0 is used to represent
+                         * the MPU-SS.
+                         */
+                        dev = get_cpu_device(0);
+                } else {
+                        oh = omap_hwmod_lookup(opp_def->hwmod_name);
+                        if (!oh || !oh->od) {
+                                pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
+                                         __func__, opp_def->hwmod_name, i);
+                                continue;
+                        }
+                        dev = &oh->od->pdev->dev;
                 }
-                dev = &oh->od->pdev->dev;
 
                 r = opp_add(dev, opp_def->freq, opp_def->u_volt);
                 if (r) {
-                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
-                                "result=%d\n",
-                               __func__, opp_def->freq,
-                               opp_def->hwmod_name, i, r);
+                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
+                                __func__, opp_def->freq,
+                                opp_def->hwmod_name, i, r);
                 } else {
                         if (!opp_def->default_available)
                                 r = opp_disable(dev, opp_def->freq);
                         if (r)
-                                dev_err(dev, "%s: disable %ld failed for %s "
-                                        "[%d] result=%d\n",
+                                dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
                                         __func__, opp_def->freq,
                                         opp_def->hwmod_name, i, r);
                 }
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index 5037e76e4e23..a9e8cf21705d 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -28,7 +28,7 @@
  *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
  */
 
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 
 #include "opp2xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index 750805c528d8..0e75ec3e114b 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -26,7 +26,7 @@
  * This is technically part of the OMAP2xxx clock code.
  */
 
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 
 #include "opp2xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index d95f3f945d4a..75cef5f67a8a 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,8 +19,6 @@
  */
 #include <linux/module.h>
 
-#include <plat/cpu.h>
-
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index c95415da23c2..a9fd6d5fe79e 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -20,8 +20,7 @@
  */
 #include <linux/module.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd901596..46092cd806fa 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -28,7 +28,6 @@
 #include <linux/slab.h>
 
 #include <plat/clock.h>
-#include <plat/board.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include <plat/dmtimer.h>
@@ -169,7 +168,7 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
         default:
                 return single_open(file, pm_dbg_show_timers,
                         &inode->i_private);
-        };
+        }
 }
 
 static const struct file_operations debug_fops = {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5cede0f50..ea61c32957bd 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -16,6 +16,7 @@
 #include <linux/opp.h>
 #include <linux/export.h>
 #include <linux/suspend.h>
+#include <linux/cpu.h>
 
 #include <asm/system_misc.h>
 
@@ -80,7 +81,8 @@ static void __init omap2_init_processor_devices(void)
 
 int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+        if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
+            !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
                 clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                  atomic_read(&clkdm->usecount) == 0)
@@ -168,7 +170,15 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
                 goto exit;
         }
 
-        dev = omap_device_get_by_hwmod_name(oh_name);
+        if (!strncmp(oh_name, "mpu", 3))
+                /* 
+                 * All current OMAPs share voltage rail and clock
+                 * source, so CPU0 is used to represent the MPU-SS.
+                 */
+                dev = get_cpu_device(0);
+        else
+                dev = omap_device_get_by_hwmod_name(oh_name);
+
         if (IS_ERR(dev)) {
                 pr_err("%s: Unable to get dev pointer for hwmod %s\n",
                         __func__, oh_name);
@@ -176,7 +186,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
         }
 
         voltdm = voltdm_lookup(vdd_name);
-        if (IS_ERR(voltdm)) {
+        if (!voltdm) {
                 pr_err("%s: unable to get vdd pointer for vdd_%s\n",
                         __func__, vdd_name);
                 goto exit;
@@ -188,7 +198,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
                 goto exit;
         }
 
-        freq = clk->rate;
+        freq = clk_get_rate(clk);
         clk_put(clk);
 
         rcu_read_lock();
@@ -203,8 +213,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
         bootup_volt = opp_get_voltage(opp);
         rcu_read_unlock();
         if (!bootup_volt) {
-                pr_err("%s: unable to find voltage corresponding "
-                        "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+                pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
+                       __func__, vdd_name);
                 goto exit;
         }
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2edeffc923a6..8af6cd6ac331 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -29,6 +29,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -38,9 +39,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/dma.h>
-#include <plat/board.h>
-
-#include <mach/irqs.h>
 
 #include "common.h"
 #include "prm2xxx_3xxx.h"
@@ -352,16 +350,6 @@ int __init omap2_pm_init(void)
 
         prcm_setup_regs();
 
-        /* Hack to prevent MPU retention when STI console is enabled. */
-        {
-                const struct omap_sti_console_config *sti;
-
-                sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
-                                      struct omap_sti_console_config);
-                if (sti != NULL && sti->enable)
-                        sti_console_enabled = 1;
-        }
-
         /*
          * We copy the assembler sleep/wakeup routines to SRAM.
          * These routines need to be in SRAM as that's the only
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 05bd8f02723f..ba670db1fd37 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,6 +28,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
@@ -389,9 +391,8 @@ restore:
         list_for_each_entry(pwrst, &pwrst_list, node) {
                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                 if (state > pwrst->next_state) {
-                        pr_info("Powerdomain (%s) didn't enter "
-                                "target state %d\n",
-                               pwrst->pwrdm->name, pwrst->next_state);
+                        pr_info("Powerdomain (%s) didn't enter target state %d\n",
+                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -731,8 +732,7 @@ int __init omap3_pm_init(void)
                 omap3_secure_ram_storage =
                         kmalloc(0x803F, GFP_KERNEL);
                 if (!omap3_secure_ram_storage)
-                        pr_err("Memory allocation failed when "
-                               "allocating for secure sram context\n");
+                        pr_err("Memory allocation failed when allocating for secure sram context\n");
 
                 local_irq_disable();
                 local_fiq_disable();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea24174f5707..04922d149068 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -69,9 +69,8 @@ static int omap4_pm_suspend(void)
         list_for_each_entry(pwrst, &pwrst_list, node) {
                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                 if (state > pwrst->next_state) {
-                        pr_info("Powerdomain (%s) didn't enter "
-                               "target state %d\n",
-                               pwrst->pwrdm->name, pwrst->next_state);
+                        pr_info("Powerdomain (%s) didn't enter target state %d\n",
+                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -189,8 +188,7 @@ int __init omap4_pm_init(void)
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
         if (ret) {
-                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
-                                "wakeup dependency\n");
+                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
                 goto err2;
         }
 
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
new file mode 100644
index 000000000000..2a791766283d
--- /dev/null
+++ b/arch/arm/mach-omap2/pmu.c
@@ -0,0 +1,95 @@
+/*
+ * OMAP2 ARM Performance Monitoring Unit (PMU) Support
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Contacts:
+ * Jon Hunter <jon-hunter@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/pm_runtime.h>
+
+#include <asm/pmu.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static char *omap2_pmu_oh_names[] = {"mpu"};
+static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
+static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"};
+static struct platform_device *omap_pmu_dev;
+
+/**
+ * omap2_init_pmu - creates and registers PMU platform device
+ * @oh_num:     Number of OMAP HWMODs required to create PMU device
+ * @oh_names:   Array of OMAP HWMODS names required to create PMU device
+ *
+ * Uses OMAP HWMOD framework to create and register an ARM PMU device
+ * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3
+ * and OMAP4 devices.
+ */
+static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
+{
+        int i;
+        struct omap_hwmod *oh[3];
+        char *dev_name = "arm-pmu";
+
+        if ((!oh_num) || (oh_num > 3))
+                return -EINVAL;
+
+        for (i = 0; i < oh_num; i++) {
+                oh[i] = omap_hwmod_lookup(oh_names[i]);
+                if (!oh[i]) {
+                        pr_err("Could not look up %s hwmod\n", oh_names[i]);
+                        return -ENODEV;
+                }
+        }
+
+        omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0,
+                                            NULL, 0, 0);
+        WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
+             dev_name);
+
+        if (IS_ERR(omap_pmu_dev))
+                return PTR_ERR(omap_pmu_dev);
+
+        pm_runtime_enable(&omap_pmu_dev->dev);
+
+        return 0;
+}
+
+static int __init omap_init_pmu(void)
+{
+        unsigned oh_num;
+        char **oh_names;
+
+        /*
+         * To create an ARM-PMU device the following HWMODs
+         * are required for the various OMAP2+ devices.
+         *
+         * OMAP24xx:    mpu
+         * OMAP3xxx:    mpu, debugss
+         * OMAP4430:    l3_main_3, l3_instr, debugss
+         * OMAP4460/70: mpu, debugss
+         */
+        if (cpu_is_omap443x()) {
+                oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
+                oh_names = omap4430_pmu_oh_names;
+                /* XXX Remove the next two lines when CTI driver available */
+                pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
+                return 0;
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
+                oh_names = omap3_pmu_oh_names;
+        } else {
+                oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
+                oh_names = omap2_pmu_oh_names;
+        }
+
+        return omap2_init_pmu(oh_num, oh_names);
+}
+subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 69b36e185e9b..1678a3284233 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -28,11 +28,13 @@
 #include "prm44xx.h"
 
 #include <asm/cpu.h>
-#include <plat/cpu.h>
+
+#include <plat/prcm.h>
+
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/prcm.h>
 
+#include "soc.h"
 #include "pm.h"
 
 #define PWRDM_TRACE_STATES_FLAG (1<<31)
@@ -339,8 +341,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         if (!pwrdm || !clkdm)
                 return -EINVAL;
 
-        pr_debug("powerdomain: associating clockdomain %s with powerdomain "
-                 "%s\n", clkdm->name, pwrdm->name);
+        pr_debug("powerdomain: %s: associating clockdomain %s\n",
+                 pwrdm->name, clkdm->name);
 
         for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
                 if (!pwrdm->pwrdm_clkdms[i])
@@ -354,8 +356,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         }
 
         if (i == PWRDM_MAX_CLKDMS) {
-                pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
-                         "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+                pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
+                         pwrdm->name, clkdm->name);
                 WARN_ON(1);
                 ret = -ENOMEM;
                 goto pac_exit;
@@ -387,16 +389,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         if (!pwrdm || !clkdm)
                 return -EINVAL;
 
-        pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
-                 "%s\n", clkdm->name, pwrdm->name);
+        pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
+                 pwrdm->name, clkdm->name);
 
         for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
                 if (pwrdm->pwrdm_clkdms[i] == clkdm)
                         break;
 
         if (i == PWRDM_MAX_CLKDMS) {
-                pr_debug("powerdomain: clkdm %s not associated with pwrdm "
-                         "%s ?!\n", clkdm->name, pwrdm->name);
+                pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
+                         pwrdm->name, clkdm->name);
                 ret = -ENOENT;
                 goto pdc_exit;
         }
@@ -485,7 +487,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
         if (!(pwrdm->pwrsts & (1 << pwrst)))
                 return -EINVAL;
 
-        pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+        pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
                  pwrdm->name, pwrst);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
@@ -587,7 +589,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
         if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
                 return -EINVAL;
 
-        pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+        pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
                  pwrdm->name, pwrst);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
@@ -624,8 +626,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
                 return -EINVAL;
 
-        pr_debug("powerdomain: setting next memory powerstate for domain %s "
-                 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+        pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
+                 pwrdm->name, bank, pwrst);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
                 ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
@@ -662,8 +664,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
                 return -EINVAL;
 
-        pr_debug("powerdomain: setting next memory powerstate for domain %s "
-                 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+        pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
+                 pwrdm->name, bank, pwrst);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
                 ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
@@ -841,7 +843,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
          * warn & fail if it is not ON.
          */
 
-        pr_debug("powerdomain: clearing previous power state reg for %s\n",
+        pr_debug("powerdomain: %s: clearing previous power state reg\n",
                  pwrdm->name);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
@@ -871,8 +873,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
         if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
                 return ret;
 
-        pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
-                 pwrdm->name);
+        pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
                 ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
@@ -901,8 +902,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
         if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
                 return ret;
 
-        pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
-                 pwrdm->name);
+        pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
 
         if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
                 ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 0f0a9f1592fe..3950ccfe5f4a 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -122,8 +122,8 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
                         udelay(1);
 
         if (c > PWRDM_TRANSITION_BAILOUT) {
-                printk(KERN_ERR "powerdomain: waited too long for "
-                        "powerdomain %s to complete transition\n", pwrdm->name);
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
                 return -EAGAIN;
         }
 
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index 601325b852a4..aceb4f464c9b 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -1,7 +1,7 @@
 /*
  * OMAP4 powerdomain control
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
@@ -151,6 +151,34 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
         return v;
 }
 
+/**
+ * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
+ * @pwrdm: struct powerdomain * to read the state for
+ *
+ * Reads the previous logic powerstate for a powerdomain. This
+ * function must determine the previous logic powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next retention logic state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether the logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_logic_retst(pwrdm);
+}
+
 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
         u32 m, v;
@@ -179,6 +207,35 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
         return v;
 }
 
+/**
+ * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
+ * @pwrdm: struct powerdomain * to read mem powerstate for
+ * @bank: memory bank index
+ *
+ * Reads the previous memory powerstate for a powerdomain. This
+ * function must determine the previous memory powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next memory retention state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
+}
+
 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
         u32 c = 0;
@@ -198,8 +255,8 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
                 udelay(1);
 
         if (c > PWRDM_TRANSITION_BAILOUT) {
-                printk(KERN_ERR "powerdomain: waited too long for "
-                       "powerdomain %s to complete transition\n", pwrdm->name);
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
                 return -EAGAIN;
         }
 
@@ -217,9 +274,11 @@ struct pwrdm_ops omap4_pwrdm_operations = {
         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index bb883e463078..8b23d234fb55 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -15,11 +15,9 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
-
 #include "prcm-common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index e5f0503a68b0..72df97482cc0 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -109,6 +109,8 @@
 #define OMAP2430_EN_MDM_INTC_MASK                       (1 << 11)
 #define OMAP2430_EN_USBHS_SHIFT                         6
 #define OMAP2430_EN_USBHS_MASK                          (1 << 6)
+#define OMAP24XX_EN_GPMC_SHIFT                          1
+#define OMAP24XX_EN_GPMC_MASK                           (1 << 1)
 
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 #define OMAP2420_ST_MMC_SHIFT                           26
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 053e24ed3c48..0f51e034e0aa 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -27,7 +27,6 @@
 
 #include "common.h"
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
@@ -140,11 +139,11 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                           MAX_MODULE_ENABLE_WAIT, i);
 
         if (i < MAX_MODULE_ENABLE_WAIT)
-                pr_debug("cm: Module associated with clock %s ready after %d "
-                         "loops\n", name, i);
+                pr_debug("cm: Module associated with clock %s ready after %d loops\n",
+                         name, i);
         else
-                pr_err("cm: Module associated with clock %s didn't enable in "
-                       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+                pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
+                       name, MAX_MODULE_ENABLE_WAIT);
 
         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 };
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index a0309dea6794..9529984d8d2b 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -17,11 +17,10 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "common.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
+#include "soc.h"
+#include "common.h"
 #include "vp.h"
 
 #include "prm2xxx_3xxx.h"
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
         .nr_regs                = 1,
         .irqs                   = omap3_prcm_irqs,
         .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
-        .irq                    = INT_34XX_PRCM_MPU_IRQ,
+        .irq                    = 11 + OMAP_INTC_START,
         .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
         .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
         .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index bb727c2d9337..f0c4d5f4a174 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,10 +17,9 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
-#include <plat/irqs.h>
 #include <plat/prcm.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "vp.h"
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
         .nr_regs                = 2,
         .irqs                   = omap4_prcm_irqs,
         .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
-        .irq                    = OMAP44XX_IRQ_PRCM,
+        .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
         .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 03b126d9ad94..6b4d332be2f6 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -26,7 +26,6 @@
 
 #include <plat/common.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 1133bb2f632b..73e55e485329 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,11 +24,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c752d70..0405c8190803 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -29,11 +29,11 @@
 
 #include <plat/omap-serial.h>
 #include "common.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/serial.h>
 
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
@@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
 };
 
 #ifdef CONFIG_PM
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct omap_device *od = to_omap_device(pdev);
 
         if (!od)
@@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
  * in Smartidle Mode When Configured for DMA Operations.
  * WA: configure uart in force idle mode.
  */
-static void omap_uart_set_noidle(struct platform_device *pdev)
+static void omap_uart_set_noidle(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct omap_device *od = to_omap_device(pdev);
 
         omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
 }
 
-static void omap_uart_set_smartidle(struct platform_device *pdev)
+static void omap_uart_set_smartidle(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct omap_device *od = to_omap_device(pdev);
         u8 idlemode;
 
@@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev)
 }
 
 #else
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {}
-static void omap_uart_set_noidle(struct platform_device *pdev) {}
-static void omap_uart_set_smartidle(struct platform_device *pdev) {}
+static void omap_uart_set_noidle(struct device *dev) {}
+static void omap_uart_set_smartidle(struct device *dev) {}
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_OMAP_MUX
@@ -229,9 +232,8 @@ static int __init omap_serial_early_init(void)
 
                         if (console_loglevel >= 10) {
                                 uart_debug = true;
-                                pr_info("%s used as console in debug mode"
-                                                " uart%d clocks will not be"
-                                                " gated", uart_name, uart->num);
+                                pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
+                                        uart_name, uart->num);
                         }
 
                         if (cmdline_find_option("no_console_suspend"))
@@ -304,6 +306,9 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
         omap_up.dma_rx_timeout = info->dma_rx_timeout;
         omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
         omap_up.autosuspend_timeout = info->autosuspend_timeout;
+        omap_up.DTR_gpio = info->DTR_gpio;
+        omap_up.DTR_inverted = info->DTR_inverted;
+        omap_up.DTR_present = info->DTR_present;
 
         pdata = &omap_up;
         pdata_size = sizeof(struct omap_uart_port_info);
@@ -313,8 +318,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 
         pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
                                  NULL, 0, false);
-        WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
-             name, oh->name);
+        if (IS_ERR(pdev)) {
+                WARN(1, "Could not build omap_device for %s: %s.\n", name,
+                     oh->name);
+                return;
+        }
 
         if ((console_uart_id == bdata->id) && no_console_suspend)
                 omap_device_disable_idle_on_suspend(pdev);
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index d4bf904d84ab..ce0ccd26efbd 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -28,8 +28,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <plat/omap24xx.h>
-
+#include "omap24xx.h"
 #include "sdrc.h"
 
 /* First address of reserved address space?  apparently valid for OMAP2 & 3 */
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 1f62f23673fb..506987979c1c 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,9 +26,9 @@
 
 #include <asm/assembler.h>
 
-#include <plat/hardware.h>
 #include <plat/sram.h>
 
+#include "omap34xx.h"
 #include "iomap.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 91e71d8f46f0..88ff83a0942e 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -14,10 +14,10 @@
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <plat/omap44xx.h>
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
new file mode 100644
index 000000000000..fc9b96daf851
--- /dev/null
+++ b/arch/arm/mach-omap2/soc.h
@@ -0,0 +1,7 @@
+#include <plat/cpu.h>
+#include "omap24xx.h"
+#include "omap34xx.h"
+#include "omap44xx.h"
+#include "ti81xx.h"
+#include "am33xx.h"
+#include "omap54xx.h"
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65f4e4e..f8217a5a4a26 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -104,16 +104,15 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
         sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
         if (!sr_data) {
-                pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
-                        __func__, oh->name);
+                pr_err("%s: Unable to allocate memory for %s sr_data\n",
+                       __func__, oh->name);
                 return -ENOMEM;
         }
 
         sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
         if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
-                pr_err("%s: No voltage domain specified for %s."
-                                "Cannot initialize\n", __func__,
-                                        oh->name);
+                pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+                       __func__, oh->name);
                 goto exit;
         }
 
@@ -123,7 +122,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
         sr_data->senp_mod = 0x1;
 
         sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
-        if (IS_ERR(sr_data->voltdm)) {
+        if (!sr_data->voltdm) {
                 pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
                         __func__, sr_dev_attr->sensor_voltdm_name);
                 goto exit;
@@ -131,8 +130,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
         omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
         if (!volt_data) {
-                pr_warning("%s: No Voltage table registered fo VDD%d."
-                        "Something really wrong\n\n", __func__, i + 1);
+                pr_err("%s: No Voltage table registered for VDD%d\n",
+                       __func__, i + 1);
                 goto exit;
         }
 
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index ee0bfcc1410f..8f7326cd435b 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -32,8 +32,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index d4d39ef04769..b140d6578529 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -32,8 +32,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index df5a21322b0a..2d0ceaa23fb8 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -29,8 +29,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
new file mode 100644
index 000000000000..8f9843f78422
--- /dev/null
+++ b/arch/arm/mach-omap2/ti81xx.h
@@ -0,0 +1,27 @@
+/*
+ * This file contains the address data for various TI81XX modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TI81XX_H
+#define __ASM_ARCH_TI81XX_H
+
+#define L4_SLOW_TI81XX_BASE     0x48000000
+
+#define TI81XX_SCM_BASE         0x48140000
+#define TI81XX_CTRL_BASE        TI81XX_SCM_BASE
+#define TI81XX_PRCM_BASE        0x48180000
+
+#define TI81XX_ARM_INTC_BASE    0x48200000
+
+#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41ec6c6..44f9aa7ec0c0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -36,16 +36,20 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <asm/mach/time.h>
-#include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
-#include "common.h"
+
+#include <asm/arch_timer.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/dmtimer.h>
 #include <plat/omap-pm.h>
 
+#include "soc.h"
+#include "common.h"
 #include "powerdomain.h"
 
 /* Parent clocks, eventually these will come from the clock framework */
@@ -69,6 +73,11 @@
 #define OMAP3_SECURE_TIMER      1
 #endif
 
+#define REALTIME_COUNTER_BASE                           0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET                    0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
+#define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
+
 /* Clockevent code */
 
 static struct omap_dm_timer clkev;
@@ -211,7 +220,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
         BUG_ON(res);
 
-        omap2_gp_timer_irq.dev_id = (void *)&clkev;
+        omap2_gp_timer_irq.dev_id = &clkev;
         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 
         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
@@ -260,6 +269,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
         return 0;
 }
 
+#ifdef CONFIG_OMAP_32K_TIMER
 /* Setup free-running counter for clocksource */
 static int __init omap2_sync32k_clocksource_init(void)
 {
@@ -299,6 +309,12 @@ static int __init omap2_sync32k_clocksource_init(void)
 
         return ret;
 }
+#else
+static inline int omap2_sync32k_clocksource_init(void)
+{
+        return -ENODEV;
+}
+#endif
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                                                 const char *fck_source)
@@ -339,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id,
                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
 
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+        void __iomem *base;
+        static struct clk *sys_clk;
+        unsigned long rate;
+        unsigned int reg, num, den;
+
+        base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+        if (!base) {
+                pr_err("%s: ioremap failed\n", __func__);
+                return;
+        }
+        sys_clk = clk_get(NULL, "sys_clkin_ck");
+        if (IS_ERR(sys_clk)) {
+                pr_err("%s: failed to get system clock handle\n", __func__);
+                iounmap(base);
+                return;
+        }
+
+        rate = clk_get_rate(sys_clk);
+        /* Numerator/denumerator values refer TRM Realtime Counter section */
+        switch (rate) {
+        case 1200000:
+                num = 64;
+                den = 125;
+                break;
+        case 1300000:
+                num = 768;
+                den = 1625;
+                break;
+        case 19200000:
+                num = 8;
+                den = 25;
+                break;
+        case 2600000:
+                num = 384;
+                den = 1625;
+                break;
+        case 2700000:
+                num = 256;
+                den = 1125;
+                break;
+        case 38400000:
+        default:
+                /* Program it for 38.4 MHz */
+                num = 4;
+                den = 25;
+                break;
+        }
+
+        /* Program numerator and denumerator registers */
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= num;
+        __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= den;
+        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+
+        iounmap(base);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
+
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
                                 clksrc_nr, clksrc_src)                  \
 static void __init omap##name##_timer_init(void)                        \
@@ -373,8 +467,7 @@ OMAP_SYS_TIMER(3_am33xx)
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
-                              OMAP44XX_LOCAL_TWD_BASE,
-                              OMAP44XX_IRQ_LOCALTIMER);
+                              OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
 #endif
 
 static void __init omap4_timer_init(void)
@@ -386,6 +479,11 @@ static void __init omap4_timer_init(void)
         if (omap_rev() != OMAP4430_REV_ES1_0) {
                 int err;
 
+                if (of_have_populated_dt()) {
+                        twd_local_timer_of_register();
+                        return;
+                }
+
                 err = twd_local_timer_register(&twd_local_timer);
                 if (err)
                         pr_err("twd_local_timer_register failed %d\n", err);
@@ -396,7 +494,18 @@ OMAP_SYS_TIMER(4)
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+        int err;
+
+        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+        realtime_counter_init();
+
+        err = arch_timer_of_register();
+        if (err)
+                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+}
 OMAP_SYS_TIMER(5)
 #endif
 
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 9bf8a89e78c6..635e109f5ad3 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -29,6 +29,7 @@
 #include <plat/i2c.h>
 #include <plat/usb.h>
 
+#include "soc.h"
 #include "twl-common.h"
 #include "pm.h"
 #include "voltage.h"
@@ -39,16 +40,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
         .flags          = I2C_CLIENT_WAKE,
 };
 
-static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
-        {
-                .addr           = 0x48,
-                .flags          = I2C_CLIENT_WAKE,
-        },
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-        },
-};
-
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
@@ -78,30 +69,25 @@ void __init omap_pmic_init(int bus, u32 clkrate,
 
 void __init omap4_pmic_init(const char *pmic_type,
                     struct twl4030_platform_data *pmic_data,
-                    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+                    struct i2c_board_info *devices, int nr_devices)
 {
         /* PMIC part*/
         omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-        strncpy(omap4_i2c1_board_info[0].type, pmic_type,
-                sizeof(omap4_i2c1_board_info[0].type));
-        omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
-        omap4_i2c1_board_info[0].platform_data = pmic_data;
-
-        /* TWL6040 audio IC part */
-        omap4_i2c1_board_info[1].irq = twl6040_irq;
-        omap4_i2c1_board_info[1].platform_data = twl6040_data;
-
-        omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+        omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
 
+        /* Register additional devices on i2c1 bus if needed */
+        if (devices)
+                i2c_register_board_info(1, devices, nr_devices);
 }
 
 void __init omap_pmic_late_init(void)
 {
-        /* Init the OMAP TWL parameters (if PMIC has been registered) */
-        if (pmic_i2c_board_info.irq)
-                omap3_twl_init();
-        if (omap4_i2c1_board_info[0].irq)
-                omap4_twl_init();
+        /* Init the OMAP TWL parameters (if PMIC has been registerd) */
+        if (!pmic_i2c_board_info.irq)
+                return;
+
+        omap3_twl_init();
+        omap4_twl_init();
 }
 
 #if defined(CONFIG_ARCH_OMAP3)
@@ -172,7 +158,7 @@ static struct regulator_init_data omap3_vpll2_idata = {
 };
 
 static struct regulator_consumer_supply omap3_vdd1_supply[] = {
-        REGULATOR_SUPPLY("vcc", "mpu.0"),
+        REGULATOR_SUPPLY("vcc", "cpu0"),
 };
 
 static struct regulator_consumer_supply omap3_vdd2_supply[] = {
@@ -251,11 +237,6 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 
 #if defined(CONFIG_ARCH_OMAP4)
 static struct twl4030_usb_data omap4_usb_pdata = {
-        .phy_init       = omap4430_phy_init,
-        .phy_exit       = omap4430_phy_exit,
-        .phy_power      = omap4430_phy_power,
-        .phy_set_clock  = omap4430_phy_set_clk,
-        .phy_suspend    = omap4430_phy_suspend,
 };
 
 static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = {
@@ -544,3 +525,30 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                 pmic_data->v2v1 = &omap4_v2v1_idata;
 }
 #endif /* CONFIG_ARCH_OMAP4 */
+
+#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \
+        defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
+#include <linux/platform_data/omap-twl4030.h>
+
+static struct omap_tw4030_pdata omap_twl4030_audio_data;
+
+static struct platform_device audio_device = {
+        .name           = "omap-twl4030",
+        .id             = -1,
+        .dev = {
+                .platform_data = &omap_twl4030_audio_data,
+        },
+};
+
+void __init omap_twl4030_audio_init(char *card_name)
+{
+        omap_twl4030_audio_data.card_name = card_name;
+        platform_device_register(&audio_device);
+}
+
+#else /* SOC_OMAP_TWL4030 */
+void __init omap_twl4030_audio_init(char *card_name)
+{
+        return;
+}
+#endif /* SOC_OMAP_TWL4030 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 8fe71cfd002c..dcfbad5ac471 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -1,7 +1,7 @@
 #ifndef __OMAP_PMIC_COMMON__
 #define __OMAP_PMIC_COMMON__
 
-#include <plat/irqs.h>
+#include "common.h"
 
 #define TWL_COMMON_PDATA_USB            (1 << 0)
 #define TWL_COMMON_PDATA_BCI            (1 << 1)
@@ -32,6 +32,7 @@
 
 struct twl4030_platform_data;
 struct twl6040_platform_data;
+struct i2c_board_info;
 
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
                     struct twl4030_platform_data *pmic_data);
@@ -40,18 +41,18 @@ void omap_pmic_late_init(void);
 static inline void omap2_pmic_init(const char *pmic_type,
                                    struct twl4030_platform_data *pmic_data)
 {
-        omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+        omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
 }
 
 static inline void omap3_pmic_init(const char *pmic_type,
                                    struct twl4030_platform_data *pmic_data)
 {
-        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+        omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
 }
 
 void omap4_pmic_init(const char *pmic_type,
                     struct twl4030_platform_data *pmic_data,
-                    struct twl6040_platform_data *audio_data, int twl6040_irq);
+                    struct i2c_board_info *devices, int nr_devices);
 
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                            u32 pdata_flags, u32 regulators_flags);
@@ -59,4 +60,6 @@ void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                            u32 pdata_flags, u32 regulators_flags);
 
+void omap_twl4030_audio_init(char *card_name);
+
 #endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index dde8a11f47d5..3c434498e12e 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -25,8 +25,6 @@
 
 #include <asm/io.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
@@ -35,10 +33,12 @@
 #ifdef CONFIG_MFD_OMAP_USB_HOST
 
 #define OMAP_USBHS_DEVICE       "usbhs_omap"
+#define OMAP_USBTLL_DEVICE      "usbhs_tll"
 #define USBHS_UHH_HWMODNAME     "usb_host_hs"
 #define USBHS_TLL_HWMODNAME     "usb_tll_hs"
 
 static struct usbhs_omap_platform_data          usbhs_data;
+static struct usbtll_omap_platform_data         usbtll_data;
 static struct ehci_hcd_omap_platform_data       ehci_data;
 static struct ohci_hcd_omap_platform_data       ohci_data;
 
@@ -487,13 +487,14 @@ void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
-        struct omap_hwmod       *oh[2];
+        struct omap_hwmod       *uhh_hwm, *tll_hwm;
         struct platform_device  *pdev;
         int                     bus_id = -1;
         int                     i;
 
         for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
                 usbhs_data.port_mode[i] = pdata->port_mode[i];
+                usbtll_data.port_mode[i] = pdata->port_mode[i];
                 ohci_data.port_mode[i] = pdata->port_mode[i];
                 ehci_data.port_mode[i] = pdata->port_mode[i];
                 ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
@@ -512,25 +513,35 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
                 setup_4430ohci_io_mux(pdata->port_mode);
         }
 
-        oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
-        if (!oh[0]) {
+        uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
+        if (!uhh_hwm) {
                 pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
                 return;
         }
 
-        oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
-        if (!oh[1]) {
+        tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
+        if (!tll_hwm) {
                 pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
                 return;
         }
 
-        pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
-                                (void *)&usbhs_data, sizeof(usbhs_data),
+        pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
+                                &usbtll_data, sizeof(usbtll_data),
                                 omap_uhhtll_latency,
                                 ARRAY_SIZE(omap_uhhtll_latency), false);
         if (IS_ERR(pdev)) {
-                pr_err("Could not build hwmod devices %s,%s\n",
-                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+                pr_err("Could not build hwmod device %s\n",
+                       USBHS_TLL_HWMODNAME);
+                return;
+        }
+
+        pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
+                                &usbhs_data, sizeof(usbhs_data),
+                                omap_uhhtll_latency,
+                                ARRAY_SIZE(omap_uhhtll_latency), false);
+        if (IS_ERR(pdev)) {
+                pr_err("Could not build hwmod devices %s\n",
+                       USBHS_UHH_HWMODNAME);
                 return;
         }
 }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index c4a576856661..51da21cb78f1 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -23,14 +23,13 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
-
 #include <linux/usb/musb.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/am35xx.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
+
+#include "am35xx.h"
+
 #include "mux.h"
 
 static struct musb_hdrc_config musb_config = {
@@ -117,7 +116,4 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
         dev->dma_mask = &musb_dmamask;
         dev->coherent_dma_mask = musb_dmamask;
         put_device(dev);
-
-        if (cpu_is_omap44xx())
-                omap4430_phy_init(dev);
 }
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 84da34f9a7cf..880249b17012 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -12,8 +12,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "voltage.h"
 #include "vc.h"
 #include "prm-regbits-34xx.h"
@@ -116,9 +115,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
         }
 
         if (!voltdm->pmic->uv_to_vsel) {
-                pr_err("%s: PMIC function to convert voltage in uV to"
-                        "vsel not registered. Hence unable to scale voltage"
-                        "for vdd_%s\n", __func__, voltdm->name);
+                pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
+                       __func__, voltdm->name);
                 return -ENODATA;
         }
 
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 4dc60e83e00d..3ac8fe1d8213 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -195,8 +195,8 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
                         return &voltdm->volt_data[i];
         }
 
-        pr_notice("%s: Unable to match the current voltage with the voltage"
-                "table for vdd_%s\n", __func__, voltdm->name);
+        pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n",
+                  __func__, voltdm->name);
 
         return ERR_PTR(-ENODATA);
 }
@@ -249,8 +249,8 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
                 voltdm->scale = omap_vc_bypass_scale;
                 return;
         default:
-                pr_warning("%s: Trying to change the method of voltage scaling"
-                        "to an unsupported one!\n", __func__);
+                pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
+                        __func__);
         }
 }
 
@@ -331,8 +331,8 @@ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
         if (!voltdm || !pwrdm)
                 return -EINVAL;
 
-        pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
-                 "%s\n", pwrdm->name, voltdm->name);
+        pr_debug("voltagedomain: %s: associating powerdomain %s\n",
+                 voltdm->name, pwrdm->name);
 
         list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
 
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 0ac2caf15941..7283b7ed7de8 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -16,7 +16,7 @@
 
 #include <linux/err.h>
 
-#include <plat/voltage.h>
+#include <linux/platform_data/voltage-omap.h>
 
 #include "vc.h"
 #include "vp.h"
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index d0103c80d040..63afbfed3cbc 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -18,9 +18,8 @@
 #include <linux/err.h>
 #include <linux/init.h>
 
+#include "soc.h"
 #include "common.h"
-#include <plat/cpu.h>
-
 #include "prm-regbits-34xx.h"
 #include "omap_opp_data.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index f95c1bad9dc6..85241b828c02 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -138,8 +138,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
                 udelay(1);
         }
         if (timeout >= VP_TRANXDONE_TIMEOUT) {
-                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
-                        "Voltage change aborted", __func__, voltdm->name);
+                pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
+                        __func__, voltdm->name);
                 return -ETIMEDOUT;
         }
 
@@ -157,9 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
         omap_test_timeout(vp->common->ops->check_txdone(vp->id),
                           VP_TRANXDONE_TIMEOUT, timeout);
         if (timeout >= VP_TRANXDONE_TIMEOUT)
-                pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
-                        "TRANXDONE never got set after the voltage update\n",
-                        __func__, voltdm->name);
+                pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n",
+                       __func__, voltdm->name);
 
         omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 
@@ -176,8 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
         }
 
         if (timeout >= VP_TRANXDONE_TIMEOUT)
-                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
-                        "to clear the TRANXDONE status\n",
+                pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n",
                         __func__, voltdm->name);
 
         /* Clear force bit */
@@ -257,8 +255,8 @@ void omap_vp_disable(struct voltagedomain *voltdm)
 
         /* If VP is already disabled, do nothing. Return */
         if (!vp->enabled) {
-                pr_warning("%s: Trying to disable VP for vdd_%s when"
-                        "it is already disabled\n", __func__, voltdm->name);
+                pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n",
+                        __func__, voltdm->name);
                 return;
         }