diff options
Diffstat (limited to 'arch/arm/mach-mv78xx0/include/mach/mv78xx0.h')
| -rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 105 |
1 files changed, 52 insertions, 53 deletions
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0b..46200a183cf2 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
| @@ -29,28 +29,27 @@ | |||
| 29 | * | 29 | * |
| 30 | * virt phys size | 30 | * virt phys size |
| 31 | * fe400000 f102x000 16K core-specific peripheral registers | 31 | * fe400000 f102x000 16K core-specific peripheral registers |
| 32 | * fe700000 f0800000 1M PCIe #0 I/O space | 32 | * fee00000 f0800000 64K PCIe #0 I/O space |
| 33 | * fe800000 f0900000 1M PCIe #1 I/O space | 33 | * fee10000 f0900000 64K PCIe #1 I/O space |
| 34 | * fe900000 f0a00000 1M PCIe #2 I/O space | 34 | * fee20000 f0a00000 64K PCIe #2 I/O space |
| 35 | * fea00000 f0b00000 1M PCIe #3 I/O space | 35 | * fee30000 f0b00000 64K PCIe #3 I/O space |
| 36 | * feb00000 f0c00000 1M PCIe #4 I/O space | 36 | * fee40000 f0c00000 64K PCIe #4 I/O space |
| 37 | * fec00000 f0d00000 1M PCIe #5 I/O space | 37 | * fee50000 f0d00000 64K PCIe #5 I/O space |
| 38 | * fed00000 f0e00000 1M PCIe #6 I/O space | 38 | * fee60000 f0e00000 64K PCIe #6 I/O space |
| 39 | * fee00000 f0f00000 1M PCIe #7 I/O space | 39 | * fee70000 f0f00000 64K PCIe #7 I/O space |
| 40 | * fef00000 f1000000 1M on-chip peripheral registers | 40 | * fd000000 f1000000 1M on-chip peripheral registers |
| 41 | */ | 41 | */ |
| 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 | 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
| 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 | 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
| 44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 | 44 | #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) |
| 45 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 | 45 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 |
| 46 | #define MV78XX0_CORE_REGS_SIZE SZ_16K | 46 | #define MV78XX0_CORE_REGS_SIZE SZ_16K |
| 47 | 47 | ||
| 48 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) | 48 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) |
| 49 | #define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) | ||
| 50 | #define MV78XX0_PCIE_IO_SIZE SZ_1M | 49 | #define MV78XX0_PCIE_IO_SIZE SZ_1M |
| 51 | 50 | ||
| 52 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 | 51 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 |
| 53 | #define MV78XX0_REGS_VIRT_BASE 0xfef00000 | 52 | #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) |
| 54 | #define MV78XX0_REGS_SIZE SZ_1M | 53 | #define MV78XX0_REGS_SIZE SZ_1M |
| 55 | 54 | ||
| 56 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 | 55 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 |
| @@ -65,47 +64,47 @@ | |||
| 65 | /* | 64 | /* |
| 66 | * Register Map | 65 | * Register Map |
| 67 | */ | 66 | */ |
| 68 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) | 67 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) |
| 69 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) | 68 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) |
| 70 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) | 69 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) |
| 71 | 70 | ||
| 72 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) | 71 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) |
| 73 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) | 72 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) |
| 74 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) | 73 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) |
| 75 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) | 74 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) |
| 76 | #define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) | 75 | #define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) |
| 77 | #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | 76 | #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) |
| 78 | #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) | 77 | #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) |
| 79 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 78 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) |
| 80 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 79 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) |
| 81 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 80 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) |
| 82 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | 81 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) |
| 83 | #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) | 82 | #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) |
| 84 | #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) | 83 | #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) |
| 85 | #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) | 84 | #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) |
| 86 | #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) | 85 | #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) |
| 87 | 86 | ||
| 88 | #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) | 87 | #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) |
| 89 | #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) | 88 | #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) |
| 90 | 89 | ||
| 91 | #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) | 90 | #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) |
| 92 | #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) | 91 | #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) |
| 93 | #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) | 92 | #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) |
| 94 | #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) | 93 | #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) |
| 95 | 94 | ||
| 96 | #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) | 95 | #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) |
| 97 | #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) | 96 | #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) |
| 98 | #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) | 97 | #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) |
| 99 | 98 | ||
| 100 | #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) | 99 | #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) |
| 101 | #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) | 100 | #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) |
| 102 | 101 | ||
| 103 | #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) | 102 | #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) |
| 104 | #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) | 103 | #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) |
| 105 | #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) | 104 | #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) |
| 106 | #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) | 105 | #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) |
| 107 | 106 | ||
| 108 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) | 107 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) |
| 109 | 108 | ||
| 110 | /* | 109 | /* |
| 111 | * Supported devices and revisions. | 110 | * Supported devices and revisions. |