diff options
Diffstat (limited to 'arch/arm/mach-mv78xx0/include/mach/bridge-regs.h')
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index eb187e0e059b..5f03484584d4 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | |||
@@ -11,18 +11,18 @@ | |||
11 | 11 | ||
12 | #include <mach/mv78xx0.h> | 12 | #include <mach/mv78xx0.h> |
13 | 13 | ||
14 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | 14 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
15 | #define L2_WRITETHROUGH 0x00020000 | 15 | #define L2_WRITETHROUGH 0x00020000 |
16 | 16 | ||
17 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | 17 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
18 | #define SOFT_RESET_OUT_EN 0x00000004 | 18 | #define SOFT_RESET_OUT_EN 0x00000004 |
19 | 19 | ||
20 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | 20 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
21 | #define SOFT_RESET 0x00000001 | 21 | #define SOFT_RESET 0x00000001 |
22 | 22 | ||
23 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | 23 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
24 | 24 | ||
25 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | 25 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
26 | #define IRQ_CAUSE_ERR_OFF 0x0000 | 26 | #define IRQ_CAUSE_ERR_OFF 0x0000 |
27 | #define IRQ_CAUSE_LOW_OFF 0x0004 | 27 | #define IRQ_CAUSE_LOW_OFF 0x0004 |
28 | #define IRQ_CAUSE_HIGH_OFF 0x0008 | 28 | #define IRQ_CAUSE_HIGH_OFF 0x0008 |
@@ -30,7 +30,7 @@ | |||
30 | #define IRQ_MASK_LOW_OFF 0x0010 | 30 | #define IRQ_MASK_LOW_OFF 0x0010 |
31 | #define IRQ_MASK_HIGH_OFF 0x0014 | 31 | #define IRQ_MASK_HIGH_OFF 0x0014 |
32 | 32 | ||
33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | 33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
34 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) | 34 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
35 | 35 | ||
36 | #endif | 36 | #endif |