diff options
Diffstat (limited to 'arch/arm/mach-mmp/pxa168.c')
-rw-r--r-- | arch/arm/mach-mmp/pxa168.c | 58 |
1 files changed, 5 insertions, 53 deletions
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 62d787c34475..b7f074f15498 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c | |||
@@ -18,8 +18,8 @@ | |||
18 | 18 | ||
19 | #include <asm/mach/time.h> | 19 | #include <asm/mach/time.h> |
20 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
21 | #include <mach/addr-map.h> | ||
22 | #include <mach/cputype.h> | 21 | #include <mach/cputype.h> |
22 | #include <mach/addr-map.h> | ||
23 | #include <mach/regs-apbc.h> | 23 | #include <mach/regs-apbc.h> |
24 | #include <mach/regs-apmu.h> | 24 | #include <mach/regs-apmu.h> |
25 | #include <mach/irqs.h> | 25 | #include <mach/irqs.h> |
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void) | |||
50 | icu_init_irq(); | 50 | icu_init_irq(); |
51 | } | 51 | } |
52 | 52 | ||
53 | /* APB peripheral clocks */ | ||
54 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); | ||
55 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); | ||
56 | static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); | ||
57 | static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); | ||
58 | static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); | ||
59 | static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); | ||
60 | static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); | ||
61 | static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); | ||
62 | static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); | ||
63 | static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); | ||
64 | static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); | ||
65 | static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); | ||
66 | static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); | ||
67 | static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); | ||
68 | static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000); | ||
69 | static APBC_CLK(keypad, PXA168_KPC, 0, 32000); | ||
70 | static APBC_CLK(rtc, PXA168_RTC, 8, 32768); | ||
71 | |||
72 | static APMU_CLK(nand, NAND, 0x19b, 156000000); | ||
73 | static APMU_CLK(lcd, LCD, 0x7f, 312000000); | ||
74 | static APMU_CLK(eth, ETH, 0x09, 0); | ||
75 | static APMU_CLK(usb, USB, 0x12, 0); | ||
76 | |||
77 | /* device and clock bindings */ | ||
78 | static struct clk_lookup pxa168_clkregs[] = { | ||
79 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
80 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
81 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | ||
82 | INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), | ||
83 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), | ||
84 | INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), | ||
85 | INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), | ||
86 | INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), | ||
87 | INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), | ||
88 | INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), | ||
89 | INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), | ||
90 | INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), | ||
91 | INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), | ||
92 | INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), | ||
93 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | ||
94 | INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), | ||
95 | INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), | ||
96 | INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), | ||
97 | INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), | ||
98 | INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), | ||
99 | INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), | ||
100 | }; | ||
101 | |||
102 | static int __init pxa168_init(void) | 53 | static int __init pxa168_init(void) |
103 | { | 54 | { |
104 | if (cpu_is_pxa168()) { | 55 | if (cpu_is_pxa168()) { |
105 | mfp_init_base(MFPR_VIRT_BASE); | 56 | mfp_init_base(MFPR_VIRT_BASE); |
106 | mfp_init_addr(pxa168_mfp_addr_map); | 57 | mfp_init_addr(pxa168_mfp_addr_map); |
107 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); | 58 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); |
108 | clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); | 59 | pxa168_clk_init(); |
109 | } | 60 | } |
110 | 61 | ||
111 | return 0; | 62 | return 0; |
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init); | |||
114 | 65 | ||
115 | /* system timer - clock enabled, 3.25MHz */ | 66 | /* system timer - clock enabled, 3.25MHz */ |
116 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | 67 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) |
68 | #define APBC_TIMERS APBC_REG(0x34) | ||
117 | 69 | ||
118 | static void __init pxa168_timer_init(void) | 70 | static void __init pxa168_timer_init(void) |
119 | { | 71 | { |
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void) | |||
121 | * ourselves instead of using clk_* API. Clock rate is defined | 73 | * ourselves instead of using clk_* API. Clock rate is defined |
122 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running | 74 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running |
123 | */ | 75 | */ |
124 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); | 76 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); |
125 | 77 | ||
126 | /* 3.25MHz, bus/functional clock enabled, release reset */ | 78 | /* 3.25MHz, bus/functional clock enabled, release reset */ |
127 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); | 79 | __raw_writel(TIMER_CLK_RST, APBC_TIMERS); |
128 | 80 | ||
129 | timer_init(IRQ_PXA168_TIMER1); | 81 | timer_init(IRQ_PXA168_TIMER1); |
130 | } | 82 | } |