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-rw-r--r--arch/arm/mach-exynos/Kconfig52
-rw-r--r--arch/arm/mach-exynos/Makefile10
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1581
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h30
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c50
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c34
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1247
-rw-r--r--arch/arm/mach-exynos/clock.c1562
-rw-r--r--arch/arm/mach-exynos/common.c534
-rw-r--r--arch/arm/mach-exynos/common.h40
-rw-r--r--arch/arm/mach-exynos/cpuidle.c151
-rw-r--r--arch/arm/mach-exynos/dev-ahci.c4
-rw-r--r--arch/arm/mach-exynos/dev-audio.c4
-rw-r--r--arch/arm/mach-exynos/dev-pd.c139
-rw-r--r--arch/arm/mach-exynos/dev-uart.c78
-rw-r--r--arch/arm/mach-exynos/dma.c153
-rw-r--r--arch/arm/mach-exynos/hotplug.c1
-rw-r--r--arch/arm/mach-exynos/include/mach/cpufreq.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S9
-rw-r--r--arch/arm/mach-exynos/include/mach/entry-macro.S16
-rw-r--r--arch/arm/mach-exynos/include/mach/exynos4-clock.h43
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h239
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h595
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h55
-rw-r--r--arch/arm/mach-exynos/include/mach/pmu.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h478
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h17
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c16
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c78
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c103
-rw-r--r--arch/arm/mach-exynos/mach-origen.c53
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c15
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c105
-rw-r--r--arch/arm/mach-exynos/mct.c62
-rw-r--r--arch/arm/mach-exynos/platsmp.c10
-rw-r--r--arch/arm/mach-exynos/pm.c57
-rw-r--r--arch/arm/mach-exynos/pm_domains.c201
-rw-r--r--arch/arm/mach-exynos/setup-i2c0.c9
41 files changed, 5282 insertions, 2594 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5d602f68a0e8..0491ceef1cda 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
11 11
12menu "SAMSUNG EXYNOS SoCs Support" 12menu "SAMSUNG EXYNOS SoCs Support"
13 13
14choice
15 prompt "EXYNOS System Type"
16 default ARCH_EXYNOS4
17
18config ARCH_EXYNOS4 14config ARCH_EXYNOS4
19 bool "SAMSUNG EXYNOS4" 15 bool "SAMSUNG EXYNOS4"
16 default y
20 select HAVE_SMP 17 select HAVE_SMP
21 select MIGHT_HAVE_CACHE_L2X0 18 select MIGHT_HAVE_CACHE_L2X0
22 help 19 help
23 Samsung EXYNOS4 SoCs based systems 20 Samsung EXYNOS4 SoCs based systems
24 21
25endchoice 22config ARCH_EXYNOS5
23 bool "SAMSUNG EXYNOS5"
24 select HAVE_SMP
25 help
26 Samsung EXYNOS5 (Cortex-A15) SoC based systems
26 27
27comment "EXYNOS SoCs" 28comment "EXYNOS SoCs"
28 29
@@ -34,6 +35,7 @@ config CPU_EXYNOS4210
34 select ARM_CPU_SUSPEND if PM 35 select ARM_CPU_SUSPEND if PM
35 select S5P_PM if PM 36 select S5P_PM if PM
36 select S5P_SLEEP if PM 37 select S5P_SLEEP if PM
38 select PM_GENERIC_DOMAINS
37 help 39 help
38 Enable EXYNOS4210 CPU support 40 Enable EXYNOS4210 CPU support
39 41
@@ -41,6 +43,7 @@ config SOC_EXYNOS4212
41 bool "SAMSUNG EXYNOS4212" 43 bool "SAMSUNG EXYNOS4212"
42 default y 44 default y
43 depends on ARCH_EXYNOS4 45 depends on ARCH_EXYNOS4
46 select SAMSUNG_DMADEV
44 select S5P_PM if PM 47 select S5P_PM if PM
45 select S5P_SLEEP if PM 48 select S5P_SLEEP if PM
46 help 49 help
@@ -50,9 +53,17 @@ config SOC_EXYNOS4412
50 bool "SAMSUNG EXYNOS4412" 53 bool "SAMSUNG EXYNOS4412"
51 default y 54 default y
52 depends on ARCH_EXYNOS4 55 depends on ARCH_EXYNOS4
56 select SAMSUNG_DMADEV
53 help 57 help
54 Enable EXYNOS4412 SoC support 58 Enable EXYNOS4412 SoC support
55 59
60config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250"
62 default y
63 depends on ARCH_EXYNOS5
64 help
65 Enable EXYNOS5250 SoC support
66
56config EXYNOS4_MCT 67config EXYNOS4_MCT
57 bool 68 bool
58 default y 69 default y
@@ -74,11 +85,6 @@ config EXYNOS4_SETUP_FIMD0
74 help 85 help
75 Common setup code for FIMD0. 86 Common setup code for FIMD0.
76 87
77config EXYNOS4_DEV_PD
78 bool
79 help
80 Compile in platform device definitions for Power Domain
81
82config EXYNOS4_DEV_SYSMMU 88config EXYNOS4_DEV_SYSMMU
83 bool 89 bool
84 help 90 help
@@ -183,7 +189,9 @@ config MACH_SMDKV310
183 select S5P_DEV_FIMC1 189 select S5P_DEV_FIMC1
184 select S5P_DEV_FIMC2 190 select S5P_DEV_FIMC2
185 select S5P_DEV_FIMC3 191 select S5P_DEV_FIMC3
192 select S5P_DEV_G2D
186 select S5P_DEV_I2C_HDMIPHY 193 select S5P_DEV_I2C_HDMIPHY
194 select S5P_DEV_JPEG
187 select S5P_DEV_MFC 195 select S5P_DEV_MFC
188 select S5P_DEV_TV 196 select S5P_DEV_TV
189 select S5P_DEV_USB_EHCI 197 select S5P_DEV_USB_EHCI
@@ -195,7 +203,6 @@ config MACH_SMDKV310
195 select EXYNOS4_DEV_AHCI 203 select EXYNOS4_DEV_AHCI
196 select SAMSUNG_DEV_KEYPAD 204 select SAMSUNG_DEV_KEYPAD
197 select EXYNOS4_DEV_DMA 205 select EXYNOS4_DEV_DMA
198 select EXYNOS4_DEV_PD
199 select SAMSUNG_DEV_PWM 206 select SAMSUNG_DEV_PWM
200 select EXYNOS4_DEV_USB_OHCI 207 select EXYNOS4_DEV_USB_OHCI
201 select EXYNOS4_DEV_SYSMMU 208 select EXYNOS4_DEV_SYSMMU
@@ -230,7 +237,9 @@ config MACH_UNIVERSAL_C210
230 select S5P_DEV_FIMC1 237 select S5P_DEV_FIMC1
231 select S5P_DEV_FIMC2 238 select S5P_DEV_FIMC2
232 select S5P_DEV_FIMC3 239 select S5P_DEV_FIMC3
240 select S5P_DEV_G2D
233 select S5P_DEV_CSIS0 241 select S5P_DEV_CSIS0
242 select S5P_DEV_JPEG
234 select S5P_DEV_FIMD0 243 select S5P_DEV_FIMD0
235 select S3C_DEV_HSMMC 244 select S3C_DEV_HSMMC
236 select S3C_DEV_HSMMC2 245 select S3C_DEV_HSMMC2
@@ -243,7 +252,6 @@ config MACH_UNIVERSAL_C210
243 select S5P_DEV_ONENAND 252 select S5P_DEV_ONENAND
244 select S5P_DEV_TV 253 select S5P_DEV_TV
245 select EXYNOS4_DEV_DMA 254 select EXYNOS4_DEV_DMA
246 select EXYNOS4_DEV_PD
247 select EXYNOS4_SETUP_FIMD0 255 select EXYNOS4_SETUP_FIMD0
248 select EXYNOS4_SETUP_I2C1 256 select EXYNOS4_SETUP_I2C1
249 select EXYNOS4_SETUP_I2C3 257 select EXYNOS4_SETUP_I2C3
@@ -268,21 +276,24 @@ config MACH_NURI
268 select S3C_DEV_I2C1 276 select S3C_DEV_I2C1
269 select S3C_DEV_I2C3 277 select S3C_DEV_I2C3
270 select S3C_DEV_I2C5 278 select S3C_DEV_I2C5
279 select S3C_DEV_I2C6
271 select S5P_DEV_CSIS0 280 select S5P_DEV_CSIS0
281 select S5P_DEV_JPEG
272 select S5P_DEV_FIMC0 282 select S5P_DEV_FIMC0
273 select S5P_DEV_FIMC1 283 select S5P_DEV_FIMC1
274 select S5P_DEV_FIMC2 284 select S5P_DEV_FIMC2
275 select S5P_DEV_FIMC3 285 select S5P_DEV_FIMC3
286 select S5P_DEV_G2D
276 select S5P_DEV_MFC 287 select S5P_DEV_MFC
277 select S5P_DEV_USB_EHCI 288 select S5P_DEV_USB_EHCI
278 select S5P_SETUP_MIPIPHY 289 select S5P_SETUP_MIPIPHY
279 select EXYNOS4_DEV_DMA 290 select EXYNOS4_DEV_DMA
280 select EXYNOS4_DEV_PD
281 select EXYNOS4_SETUP_FIMC 291 select EXYNOS4_SETUP_FIMC
282 select EXYNOS4_SETUP_FIMD0 292 select EXYNOS4_SETUP_FIMD0
283 select EXYNOS4_SETUP_I2C1 293 select EXYNOS4_SETUP_I2C1
284 select EXYNOS4_SETUP_I2C3 294 select EXYNOS4_SETUP_I2C3
285 select EXYNOS4_SETUP_I2C5 295 select EXYNOS4_SETUP_I2C5
296 select EXYNOS4_SETUP_I2C6
286 select EXYNOS4_SETUP_SDHCI 297 select EXYNOS4_SETUP_SDHCI
287 select EXYNOS4_SETUP_USB_PHY 298 select EXYNOS4_SETUP_USB_PHY
288 select S5P_SETUP_MIPIPHY 299 select S5P_SETUP_MIPIPHY
@@ -303,14 +314,15 @@ config MACH_ORIGEN
303 select S5P_DEV_FIMC2 314 select S5P_DEV_FIMC2
304 select S5P_DEV_FIMC3 315 select S5P_DEV_FIMC3
305 select S5P_DEV_FIMD0 316 select S5P_DEV_FIMD0
317 select S5P_DEV_G2D
306 select S5P_DEV_I2C_HDMIPHY 318 select S5P_DEV_I2C_HDMIPHY
319 select S5P_DEV_JPEG
307 select S5P_DEV_MFC 320 select S5P_DEV_MFC
308 select S5P_DEV_TV 321 select S5P_DEV_TV
309 select S5P_DEV_USB_EHCI 322 select S5P_DEV_USB_EHCI
310 select SAMSUNG_DEV_BACKLIGHT 323 select SAMSUNG_DEV_BACKLIGHT
311 select SAMSUNG_DEV_PWM 324 select SAMSUNG_DEV_PWM
312 select EXYNOS4_DEV_DMA 325 select EXYNOS4_DEV_DMA
313 select EXYNOS4_DEV_PD
314 select EXYNOS4_DEV_USB_OHCI 326 select EXYNOS4_DEV_USB_OHCI
315 select EXYNOS4_SETUP_FIMD0 327 select EXYNOS4_SETUP_FIMD0
316 select EXYNOS4_SETUP_SDHCI 328 select EXYNOS4_SETUP_SDHCI
@@ -333,6 +345,7 @@ config MACH_SMDK4212
333 select SAMSUNG_DEV_BACKLIGHT 345 select SAMSUNG_DEV_BACKLIGHT
334 select SAMSUNG_DEV_KEYPAD 346 select SAMSUNG_DEV_KEYPAD
335 select SAMSUNG_DEV_PWM 347 select SAMSUNG_DEV_PWM
348 select EXYNOS4_DEV_DMA
336 select EXYNOS4_SETUP_I2C1 349 select EXYNOS4_SETUP_I2C1
337 select EXYNOS4_SETUP_I2C3 350 select EXYNOS4_SETUP_I2C3
338 select EXYNOS4_SETUP_I2C7 351 select EXYNOS4_SETUP_I2C7
@@ -351,7 +364,7 @@ config MACH_SMDK4412
351 Machine support for Samsung SMDK4412 364 Machine support for Samsung SMDK4412
352endif 365endif
353 366
354comment "Flattened Device Tree based board for Exynos4 based SoC" 367comment "Flattened Device Tree based board for EXYNOS SoCs"
355 368
356config MACH_EXYNOS4_DT 369config MACH_EXYNOS4_DT
357 bool "Samsung Exynos4 Machine using device tree" 370 bool "Samsung Exynos4 Machine using device tree"
@@ -365,6 +378,15 @@ config MACH_EXYNOS4_DT
365 Note: This is under development and not all peripherals can be supported 378 Note: This is under development and not all peripherals can be supported
366 with this machine file. 379 with this machine file.
367 380
381config MACH_EXYNOS5_DT
382 bool "SAMSUNG EXYNOS5 Machine using device tree"
383 select SOC_EXYNOS5250
384 select USE_OF
385 select ARM_AMBA
386 help
387 Machine support for Samsung Exynos4 machine with device tree enabled.
388 Select this if a fdt blob is available for the EXYNOS4 SoC based board.
389
368if ARCH_EXYNOS4 390if ARCH_EXYNOS4
369 391
370comment "Configuration for HSMMC 8-bit bus width" 392comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202cdfdb6..8631840d1b5e 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,11 +12,14 @@ obj- :=
12 12
13# Core 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
17obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 18obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 19obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18 20
19obj-$(CONFIG_PM) += pm.o 21obj-$(CONFIG_PM) += pm.o
22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 23obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 24
22obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o 25obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
@@ -40,18 +43,19 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
40obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o 43obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
41 44
42obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o 45obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
46obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
43 47
44# device support 48# device support
45 49
50obj-y += dev-uart.o
46obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
47obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
48obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
49obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 53obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
50obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 54obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
51obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
52obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
53 57
54obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o 58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
55obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 59obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
56obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 60obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
57obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 61obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 000000000000..df54c2a92225
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1581 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28
29#include "common.h"
30#include "clock-exynos4.h"
31
32#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95};
96#endif
97
98static struct clk exynos4_clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m",
100 .rate = 27000000,
101};
102
103static struct clk exynos4_clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy",
105};
106
107static struct clk exynos4_clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0",
109 .rate = 27000000,
110};
111
112static struct clk exynos4_clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1",
114};
115
116static struct clk dummy_apb_pclk = {
117 .name = "apb_pclk",
118 .id = -1,
119};
120
121static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122{
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124}
125
126static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127{
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129}
130
131static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132{
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134}
135
136int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137{
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139}
140
141static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142{
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144}
145
146static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147{
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149}
150
151static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152{
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154}
155
156static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157{
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159}
160
161static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162{
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164}
165
166static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167{
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169}
170
171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172{
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174}
175
176static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177{
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179}
180
181int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182{
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184}
185
186int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187{
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189}
190
191static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192{
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194}
195
196static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197{
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199}
200
201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202{
203 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204}
205
206static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
207{
208 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
209}
210
211/* Core list of CMU_CPU side */
212
213static struct clksrc_clk exynos4_clk_mout_apll = {
214 .clk = {
215 .name = "mout_apll",
216 },
217 .sources = &clk_src_apll,
218 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
219};
220
221static struct clksrc_clk exynos4_clk_sclk_apll = {
222 .clk = {
223 .name = "sclk_apll",
224 .parent = &exynos4_clk_mout_apll.clk,
225 },
226 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
227};
228
229static struct clksrc_clk exynos4_clk_mout_epll = {
230 .clk = {
231 .name = "mout_epll",
232 },
233 .sources = &clk_src_epll,
234 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
235};
236
237struct clksrc_clk exynos4_clk_mout_mpll = {
238 .clk = {
239 .name = "mout_mpll",
240 },
241 .sources = &clk_src_mpll,
242
243 /* reg_src will be added in each SoCs' clock */
244};
245
246static struct clk *exynos4_clkset_moutcore_list[] = {
247 [0] = &exynos4_clk_mout_apll.clk,
248 [1] = &exynos4_clk_mout_mpll.clk,
249};
250
251static struct clksrc_sources exynos4_clkset_moutcore = {
252 .sources = exynos4_clkset_moutcore_list,
253 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
254};
255
256static struct clksrc_clk exynos4_clk_moutcore = {
257 .clk = {
258 .name = "moutcore",
259 },
260 .sources = &exynos4_clkset_moutcore,
261 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
262};
263
264static struct clksrc_clk exynos4_clk_coreclk = {
265 .clk = {
266 .name = "core_clk",
267 .parent = &exynos4_clk_moutcore.clk,
268 },
269 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
270};
271
272static struct clksrc_clk exynos4_clk_armclk = {
273 .clk = {
274 .name = "armclk",
275 .parent = &exynos4_clk_coreclk.clk,
276 },
277};
278
279static struct clksrc_clk exynos4_clk_aclk_corem0 = {
280 .clk = {
281 .name = "aclk_corem0",
282 .parent = &exynos4_clk_coreclk.clk,
283 },
284 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
285};
286
287static struct clksrc_clk exynos4_clk_aclk_cores = {
288 .clk = {
289 .name = "aclk_cores",
290 .parent = &exynos4_clk_coreclk.clk,
291 },
292 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
293};
294
295static struct clksrc_clk exynos4_clk_aclk_corem1 = {
296 .clk = {
297 .name = "aclk_corem1",
298 .parent = &exynos4_clk_coreclk.clk,
299 },
300 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
301};
302
303static struct clksrc_clk exynos4_clk_periphclk = {
304 .clk = {
305 .name = "periphclk",
306 .parent = &exynos4_clk_coreclk.clk,
307 },
308 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
309};
310
311/* Core list of CMU_CORE side */
312
313static struct clk *exynos4_clkset_corebus_list[] = {
314 [0] = &exynos4_clk_mout_mpll.clk,
315 [1] = &exynos4_clk_sclk_apll.clk,
316};
317
318struct clksrc_sources exynos4_clkset_mout_corebus = {
319 .sources = exynos4_clkset_corebus_list,
320 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
321};
322
323static struct clksrc_clk exynos4_clk_mout_corebus = {
324 .clk = {
325 .name = "mout_corebus",
326 },
327 .sources = &exynos4_clkset_mout_corebus,
328 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
329};
330
331static struct clksrc_clk exynos4_clk_sclk_dmc = {
332 .clk = {
333 .name = "sclk_dmc",
334 .parent = &exynos4_clk_mout_corebus.clk,
335 },
336 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
337};
338
339static struct clksrc_clk exynos4_clk_aclk_cored = {
340 .clk = {
341 .name = "aclk_cored",
342 .parent = &exynos4_clk_sclk_dmc.clk,
343 },
344 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
345};
346
347static struct clksrc_clk exynos4_clk_aclk_corep = {
348 .clk = {
349 .name = "aclk_corep",
350 .parent = &exynos4_clk_aclk_cored.clk,
351 },
352 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
353};
354
355static struct clksrc_clk exynos4_clk_aclk_acp = {
356 .clk = {
357 .name = "aclk_acp",
358 .parent = &exynos4_clk_mout_corebus.clk,
359 },
360 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
361};
362
363static struct clksrc_clk exynos4_clk_pclk_acp = {
364 .clk = {
365 .name = "pclk_acp",
366 .parent = &exynos4_clk_aclk_acp.clk,
367 },
368 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
369};
370
371/* Core list of CMU_TOP side */
372
373struct clk *exynos4_clkset_aclk_top_list[] = {
374 [0] = &exynos4_clk_mout_mpll.clk,
375 [1] = &exynos4_clk_sclk_apll.clk,
376};
377
378static struct clksrc_sources exynos4_clkset_aclk = {
379 .sources = exynos4_clkset_aclk_top_list,
380 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
381};
382
383static struct clksrc_clk exynos4_clk_aclk_200 = {
384 .clk = {
385 .name = "aclk_200",
386 },
387 .sources = &exynos4_clkset_aclk,
388 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
389 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
390};
391
392static struct clksrc_clk exynos4_clk_aclk_100 = {
393 .clk = {
394 .name = "aclk_100",
395 },
396 .sources = &exynos4_clkset_aclk,
397 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
398 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
399};
400
401static struct clksrc_clk exynos4_clk_aclk_160 = {
402 .clk = {
403 .name = "aclk_160",
404 },
405 .sources = &exynos4_clkset_aclk,
406 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
407 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
408};
409
410struct clksrc_clk exynos4_clk_aclk_133 = {
411 .clk = {
412 .name = "aclk_133",
413 },
414 .sources = &exynos4_clkset_aclk,
415 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
416 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
417};
418
419static struct clk *exynos4_clkset_vpllsrc_list[] = {
420 [0] = &clk_fin_vpll,
421 [1] = &exynos4_clk_sclk_hdmi27m,
422};
423
424static struct clksrc_sources exynos4_clkset_vpllsrc = {
425 .sources = exynos4_clkset_vpllsrc_list,
426 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
427};
428
429static struct clksrc_clk exynos4_clk_vpllsrc = {
430 .clk = {
431 .name = "vpll_src",
432 .enable = exynos4_clksrc_mask_top_ctrl,
433 .ctrlbit = (1 << 0),
434 },
435 .sources = &exynos4_clkset_vpllsrc,
436 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
437};
438
439static struct clk *exynos4_clkset_sclk_vpll_list[] = {
440 [0] = &exynos4_clk_vpllsrc.clk,
441 [1] = &clk_fout_vpll,
442};
443
444static struct clksrc_sources exynos4_clkset_sclk_vpll = {
445 .sources = exynos4_clkset_sclk_vpll_list,
446 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
447};
448
449static struct clksrc_clk exynos4_clk_sclk_vpll = {
450 .clk = {
451 .name = "sclk_vpll",
452 },
453 .sources = &exynos4_clkset_sclk_vpll,
454 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
455};
456
457static struct clk exynos4_init_clocks_off[] = {
458 {
459 .name = "timers",
460 .parent = &exynos4_clk_aclk_100.clk,
461 .enable = exynos4_clk_ip_peril_ctrl,
462 .ctrlbit = (1<<24),
463 }, {
464 .name = "csis",
465 .devname = "s5p-mipi-csis.0",
466 .enable = exynos4_clk_ip_cam_ctrl,
467 .ctrlbit = (1 << 4),
468 }, {
469 .name = "csis",
470 .devname = "s5p-mipi-csis.1",
471 .enable = exynos4_clk_ip_cam_ctrl,
472 .ctrlbit = (1 << 5),
473 }, {
474 .name = "jpeg",
475 .id = 0,
476 .enable = exynos4_clk_ip_cam_ctrl,
477 .ctrlbit = (1 << 6),
478 }, {
479 .name = "fimc",
480 .devname = "exynos4-fimc.0",
481 .enable = exynos4_clk_ip_cam_ctrl,
482 .ctrlbit = (1 << 0),
483 }, {
484 .name = "fimc",
485 .devname = "exynos4-fimc.1",
486 .enable = exynos4_clk_ip_cam_ctrl,
487 .ctrlbit = (1 << 1),
488 }, {
489 .name = "fimc",
490 .devname = "exynos4-fimc.2",
491 .enable = exynos4_clk_ip_cam_ctrl,
492 .ctrlbit = (1 << 2),
493 }, {
494 .name = "fimc",
495 .devname = "exynos4-fimc.3",
496 .enable = exynos4_clk_ip_cam_ctrl,
497 .ctrlbit = (1 << 3),
498 }, {
499 .name = "hsmmc",
500 .devname = "s3c-sdhci.0",
501 .parent = &exynos4_clk_aclk_133.clk,
502 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 5),
504 }, {
505 .name = "hsmmc",
506 .devname = "s3c-sdhci.1",
507 .parent = &exynos4_clk_aclk_133.clk,
508 .enable = exynos4_clk_ip_fsys_ctrl,
509 .ctrlbit = (1 << 6),
510 }, {
511 .name = "hsmmc",
512 .devname = "s3c-sdhci.2",
513 .parent = &exynos4_clk_aclk_133.clk,
514 .enable = exynos4_clk_ip_fsys_ctrl,
515 .ctrlbit = (1 << 7),
516 }, {
517 .name = "hsmmc",
518 .devname = "s3c-sdhci.3",
519 .parent = &exynos4_clk_aclk_133.clk,
520 .enable = exynos4_clk_ip_fsys_ctrl,
521 .ctrlbit = (1 << 8),
522 }, {
523 .name = "dwmmc",
524 .parent = &exynos4_clk_aclk_133.clk,
525 .enable = exynos4_clk_ip_fsys_ctrl,
526 .ctrlbit = (1 << 9),
527 }, {
528 .name = "dac",
529 .devname = "s5p-sdo",
530 .enable = exynos4_clk_ip_tv_ctrl,
531 .ctrlbit = (1 << 2),
532 }, {
533 .name = "mixer",
534 .devname = "s5p-mixer",
535 .enable = exynos4_clk_ip_tv_ctrl,
536 .ctrlbit = (1 << 1),
537 }, {
538 .name = "vp",
539 .devname = "s5p-mixer",
540 .enable = exynos4_clk_ip_tv_ctrl,
541 .ctrlbit = (1 << 0),
542 }, {
543 .name = "hdmi",
544 .devname = "exynos4-hdmi",
545 .enable = exynos4_clk_ip_tv_ctrl,
546 .ctrlbit = (1 << 3),
547 }, {
548 .name = "hdmiphy",
549 .devname = "exynos4-hdmi",
550 .enable = exynos4_clk_hdmiphy_ctrl,
551 .ctrlbit = (1 << 0),
552 }, {
553 .name = "dacphy",
554 .devname = "s5p-sdo",
555 .enable = exynos4_clk_dac_ctrl,
556 .ctrlbit = (1 << 0),
557 }, {
558 .name = "adc",
559 .enable = exynos4_clk_ip_peril_ctrl,
560 .ctrlbit = (1 << 15),
561 }, {
562 .name = "keypad",
563 .enable = exynos4_clk_ip_perir_ctrl,
564 .ctrlbit = (1 << 16),
565 }, {
566 .name = "rtc",
567 .enable = exynos4_clk_ip_perir_ctrl,
568 .ctrlbit = (1 << 15),
569 }, {
570 .name = "watchdog",
571 .parent = &exynos4_clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_perir_ctrl,
573 .ctrlbit = (1 << 14),
574 }, {
575 .name = "usbhost",
576 .enable = exynos4_clk_ip_fsys_ctrl ,
577 .ctrlbit = (1 << 12),
578 }, {
579 .name = "otg",
580 .enable = exynos4_clk_ip_fsys_ctrl,
581 .ctrlbit = (1 << 13),
582 }, {
583 .name = "spi",
584 .devname = "s3c64xx-spi.0",
585 .enable = exynos4_clk_ip_peril_ctrl,
586 .ctrlbit = (1 << 16),
587 }, {
588 .name = "spi",
589 .devname = "s3c64xx-spi.1",
590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 17),
592 }, {
593 .name = "spi",
594 .devname = "s3c64xx-spi.2",
595 .enable = exynos4_clk_ip_peril_ctrl,
596 .ctrlbit = (1 << 18),
597 }, {
598 .name = "iis",
599 .devname = "samsung-i2s.0",
600 .enable = exynos4_clk_ip_peril_ctrl,
601 .ctrlbit = (1 << 19),
602 }, {
603 .name = "iis",
604 .devname = "samsung-i2s.1",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 20),
607 }, {
608 .name = "iis",
609 .devname = "samsung-i2s.2",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 21),
612 }, {
613 .name = "ac97",
614 .devname = "samsung-ac97",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 27),
617 }, {
618 .name = "fimg2d",
619 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 0),
621 }, {
622 .name = "mfc",
623 .devname = "s5p-mfc",
624 .enable = exynos4_clk_ip_mfc_ctrl,
625 .ctrlbit = (1 << 0),
626 }, {
627 .name = "i2c",
628 .devname = "s3c2440-i2c.0",
629 .parent = &exynos4_clk_aclk_100.clk,
630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 6),
632 }, {
633 .name = "i2c",
634 .devname = "s3c2440-i2c.1",
635 .parent = &exynos4_clk_aclk_100.clk,
636 .enable = exynos4_clk_ip_peril_ctrl,
637 .ctrlbit = (1 << 7),
638 }, {
639 .name = "i2c",
640 .devname = "s3c2440-i2c.2",
641 .parent = &exynos4_clk_aclk_100.clk,
642 .enable = exynos4_clk_ip_peril_ctrl,
643 .ctrlbit = (1 << 8),
644 }, {
645 .name = "i2c",
646 .devname = "s3c2440-i2c.3",
647 .parent = &exynos4_clk_aclk_100.clk,
648 .enable = exynos4_clk_ip_peril_ctrl,
649 .ctrlbit = (1 << 9),
650 }, {
651 .name = "i2c",
652 .devname = "s3c2440-i2c.4",
653 .parent = &exynos4_clk_aclk_100.clk,
654 .enable = exynos4_clk_ip_peril_ctrl,
655 .ctrlbit = (1 << 10),
656 }, {
657 .name = "i2c",
658 .devname = "s3c2440-i2c.5",
659 .parent = &exynos4_clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl,
661 .ctrlbit = (1 << 11),
662 }, {
663 .name = "i2c",
664 .devname = "s3c2440-i2c.6",
665 .parent = &exynos4_clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl,
667 .ctrlbit = (1 << 12),
668 }, {
669 .name = "i2c",
670 .devname = "s3c2440-i2c.7",
671 .parent = &exynos4_clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl,
673 .ctrlbit = (1 << 13),
674 }, {
675 .name = "i2c",
676 .devname = "s3c2440-hdmiphy-i2c",
677 .parent = &exynos4_clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 14),
680 }, {
681 .name = "SYSMMU_MDMA",
682 .enable = exynos4_clk_ip_image_ctrl,
683 .ctrlbit = (1 << 5),
684 }, {
685 .name = "SYSMMU_FIMC0",
686 .enable = exynos4_clk_ip_cam_ctrl,
687 .ctrlbit = (1 << 7),
688 }, {
689 .name = "SYSMMU_FIMC1",
690 .enable = exynos4_clk_ip_cam_ctrl,
691 .ctrlbit = (1 << 8),
692 }, {
693 .name = "SYSMMU_FIMC2",
694 .enable = exynos4_clk_ip_cam_ctrl,
695 .ctrlbit = (1 << 9),
696 }, {
697 .name = "SYSMMU_FIMC3",
698 .enable = exynos4_clk_ip_cam_ctrl,
699 .ctrlbit = (1 << 10),
700 }, {
701 .name = "SYSMMU_JPEG",
702 .enable = exynos4_clk_ip_cam_ctrl,
703 .ctrlbit = (1 << 11),
704 }, {
705 .name = "SYSMMU_FIMD0",
706 .enable = exynos4_clk_ip_lcd0_ctrl,
707 .ctrlbit = (1 << 4),
708 }, {
709 .name = "SYSMMU_FIMD1",
710 .enable = exynos4_clk_ip_lcd1_ctrl,
711 .ctrlbit = (1 << 4),
712 }, {
713 .name = "SYSMMU_PCIe",
714 .enable = exynos4_clk_ip_fsys_ctrl,
715 .ctrlbit = (1 << 18),
716 }, {
717 .name = "SYSMMU_G2D",
718 .enable = exynos4_clk_ip_image_ctrl,
719 .ctrlbit = (1 << 3),
720 }, {
721 .name = "SYSMMU_ROTATOR",
722 .enable = exynos4_clk_ip_image_ctrl,
723 .ctrlbit = (1 << 4),
724 }, {
725 .name = "SYSMMU_TV",
726 .enable = exynos4_clk_ip_tv_ctrl,
727 .ctrlbit = (1 << 4),
728 }, {
729 .name = "SYSMMU_MFC_L",
730 .enable = exynos4_clk_ip_mfc_ctrl,
731 .ctrlbit = (1 << 1),
732 }, {
733 .name = "SYSMMU_MFC_R",
734 .enable = exynos4_clk_ip_mfc_ctrl,
735 .ctrlbit = (1 << 2),
736 }
737};
738
739static struct clk exynos4_init_clocks_on[] = {
740 {
741 .name = "uart",
742 .devname = "s5pv210-uart.0",
743 .enable = exynos4_clk_ip_peril_ctrl,
744 .ctrlbit = (1 << 0),
745 }, {
746 .name = "uart",
747 .devname = "s5pv210-uart.1",
748 .enable = exynos4_clk_ip_peril_ctrl,
749 .ctrlbit = (1 << 1),
750 }, {
751 .name = "uart",
752 .devname = "s5pv210-uart.2",
753 .enable = exynos4_clk_ip_peril_ctrl,
754 .ctrlbit = (1 << 2),
755 }, {
756 .name = "uart",
757 .devname = "s5pv210-uart.3",
758 .enable = exynos4_clk_ip_peril_ctrl,
759 .ctrlbit = (1 << 3),
760 }, {
761 .name = "uart",
762 .devname = "s5pv210-uart.4",
763 .enable = exynos4_clk_ip_peril_ctrl,
764 .ctrlbit = (1 << 4),
765 }, {
766 .name = "uart",
767 .devname = "s5pv210-uart.5",
768 .enable = exynos4_clk_ip_peril_ctrl,
769 .ctrlbit = (1 << 5),
770 }
771};
772
773static struct clk exynos4_clk_pdma0 = {
774 .name = "dma",
775 .devname = "dma-pl330.0",
776 .enable = exynos4_clk_ip_fsys_ctrl,
777 .ctrlbit = (1 << 0),
778};
779
780static struct clk exynos4_clk_pdma1 = {
781 .name = "dma",
782 .devname = "dma-pl330.1",
783 .enable = exynos4_clk_ip_fsys_ctrl,
784 .ctrlbit = (1 << 1),
785};
786
787static struct clk exynos4_clk_mdma1 = {
788 .name = "dma",
789 .devname = "dma-pl330.2",
790 .enable = exynos4_clk_ip_image_ctrl,
791 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
792};
793
794static struct clk exynos4_clk_fimd0 = {
795 .name = "fimd",
796 .devname = "exynos4-fb.0",
797 .enable = exynos4_clk_ip_lcd0_ctrl,
798 .ctrlbit = (1 << 0),
799};
800
801struct clk *exynos4_clkset_group_list[] = {
802 [0] = &clk_ext_xtal_mux,
803 [1] = &clk_xusbxti,
804 [2] = &exynos4_clk_sclk_hdmi27m,
805 [3] = &exynos4_clk_sclk_usbphy0,
806 [4] = &exynos4_clk_sclk_usbphy1,
807 [5] = &exynos4_clk_sclk_hdmiphy,
808 [6] = &exynos4_clk_mout_mpll.clk,
809 [7] = &exynos4_clk_mout_epll.clk,
810 [8] = &exynos4_clk_sclk_vpll.clk,
811};
812
813struct clksrc_sources exynos4_clkset_group = {
814 .sources = exynos4_clkset_group_list,
815 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
816};
817
818static struct clk *exynos4_clkset_mout_g2d0_list[] = {
819 [0] = &exynos4_clk_mout_mpll.clk,
820 [1] = &exynos4_clk_sclk_apll.clk,
821};
822
823static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
824 .sources = exynos4_clkset_mout_g2d0_list,
825 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
826};
827
828static struct clksrc_clk exynos4_clk_mout_g2d0 = {
829 .clk = {
830 .name = "mout_g2d0",
831 },
832 .sources = &exynos4_clkset_mout_g2d0,
833 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
834};
835
836static struct clk *exynos4_clkset_mout_g2d1_list[] = {
837 [0] = &exynos4_clk_mout_epll.clk,
838 [1] = &exynos4_clk_sclk_vpll.clk,
839};
840
841static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
842 .sources = exynos4_clkset_mout_g2d1_list,
843 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
844};
845
846static struct clksrc_clk exynos4_clk_mout_g2d1 = {
847 .clk = {
848 .name = "mout_g2d1",
849 },
850 .sources = &exynos4_clkset_mout_g2d1,
851 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
852};
853
854static struct clk *exynos4_clkset_mout_g2d_list[] = {
855 [0] = &exynos4_clk_mout_g2d0.clk,
856 [1] = &exynos4_clk_mout_g2d1.clk,
857};
858
859static struct clksrc_sources exynos4_clkset_mout_g2d = {
860 .sources = exynos4_clkset_mout_g2d_list,
861 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
862};
863
864static struct clk *exynos4_clkset_mout_mfc0_list[] = {
865 [0] = &exynos4_clk_mout_mpll.clk,
866 [1] = &exynos4_clk_sclk_apll.clk,
867};
868
869static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
870 .sources = exynos4_clkset_mout_mfc0_list,
871 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
872};
873
874static struct clksrc_clk exynos4_clk_mout_mfc0 = {
875 .clk = {
876 .name = "mout_mfc0",
877 },
878 .sources = &exynos4_clkset_mout_mfc0,
879 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
880};
881
882static struct clk *exynos4_clkset_mout_mfc1_list[] = {
883 [0] = &exynos4_clk_mout_epll.clk,
884 [1] = &exynos4_clk_sclk_vpll.clk,
885};
886
887static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
888 .sources = exynos4_clkset_mout_mfc1_list,
889 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
890};
891
892static struct clksrc_clk exynos4_clk_mout_mfc1 = {
893 .clk = {
894 .name = "mout_mfc1",
895 },
896 .sources = &exynos4_clkset_mout_mfc1,
897 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
898};
899
900static struct clk *exynos4_clkset_mout_mfc_list[] = {
901 [0] = &exynos4_clk_mout_mfc0.clk,
902 [1] = &exynos4_clk_mout_mfc1.clk,
903};
904
905static struct clksrc_sources exynos4_clkset_mout_mfc = {
906 .sources = exynos4_clkset_mout_mfc_list,
907 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
908};
909
910static struct clk *exynos4_clkset_sclk_dac_list[] = {
911 [0] = &exynos4_clk_sclk_vpll.clk,
912 [1] = &exynos4_clk_sclk_hdmiphy,
913};
914
915static struct clksrc_sources exynos4_clkset_sclk_dac = {
916 .sources = exynos4_clkset_sclk_dac_list,
917 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
918};
919
920static struct clksrc_clk exynos4_clk_sclk_dac = {
921 .clk = {
922 .name = "sclk_dac",
923 .enable = exynos4_clksrc_mask_tv_ctrl,
924 .ctrlbit = (1 << 8),
925 },
926 .sources = &exynos4_clkset_sclk_dac,
927 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
928};
929
930static struct clksrc_clk exynos4_clk_sclk_pixel = {
931 .clk = {
932 .name = "sclk_pixel",
933 .parent = &exynos4_clk_sclk_vpll.clk,
934 },
935 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
936};
937
938static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
939 [0] = &exynos4_clk_sclk_pixel.clk,
940 [1] = &exynos4_clk_sclk_hdmiphy,
941};
942
943static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
944 .sources = exynos4_clkset_sclk_hdmi_list,
945 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
946};
947
948static struct clksrc_clk exynos4_clk_sclk_hdmi = {
949 .clk = {
950 .name = "sclk_hdmi",
951 .enable = exynos4_clksrc_mask_tv_ctrl,
952 .ctrlbit = (1 << 0),
953 },
954 .sources = &exynos4_clkset_sclk_hdmi,
955 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
956};
957
958static struct clk *exynos4_clkset_sclk_mixer_list[] = {
959 [0] = &exynos4_clk_sclk_dac.clk,
960 [1] = &exynos4_clk_sclk_hdmi.clk,
961};
962
963static struct clksrc_sources exynos4_clkset_sclk_mixer = {
964 .sources = exynos4_clkset_sclk_mixer_list,
965 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
966};
967
968static struct clksrc_clk exynos4_clk_sclk_mixer = {
969 .clk = {
970 .name = "sclk_mixer",
971 .enable = exynos4_clksrc_mask_tv_ctrl,
972 .ctrlbit = (1 << 4),
973 },
974 .sources = &exynos4_clkset_sclk_mixer,
975 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
976};
977
978static struct clksrc_clk *exynos4_sclk_tv[] = {
979 &exynos4_clk_sclk_dac,
980 &exynos4_clk_sclk_pixel,
981 &exynos4_clk_sclk_hdmi,
982 &exynos4_clk_sclk_mixer,
983};
984
985static struct clksrc_clk exynos4_clk_dout_mmc0 = {
986 .clk = {
987 .name = "dout_mmc0",
988 },
989 .sources = &exynos4_clkset_group,
990 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
991 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
992};
993
994static struct clksrc_clk exynos4_clk_dout_mmc1 = {
995 .clk = {
996 .name = "dout_mmc1",
997 },
998 .sources = &exynos4_clkset_group,
999 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
1000 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1001};
1002
1003static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1004 .clk = {
1005 .name = "dout_mmc2",
1006 },
1007 .sources = &exynos4_clkset_group,
1008 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1009 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1010};
1011
1012static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1013 .clk = {
1014 .name = "dout_mmc3",
1015 },
1016 .sources = &exynos4_clkset_group,
1017 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1018 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1019};
1020
1021static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1022 .clk = {
1023 .name = "dout_mmc4",
1024 },
1025 .sources = &exynos4_clkset_group,
1026 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1027 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1028};
1029
1030static struct clksrc_clk exynos4_clksrcs[] = {
1031 {
1032 .clk = {
1033 .name = "sclk_pwm",
1034 .enable = exynos4_clksrc_mask_peril0_ctrl,
1035 .ctrlbit = (1 << 24),
1036 },
1037 .sources = &exynos4_clkset_group,
1038 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1039 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1040 }, {
1041 .clk = {
1042 .name = "sclk_csis",
1043 .devname = "s5p-mipi-csis.0",
1044 .enable = exynos4_clksrc_mask_cam_ctrl,
1045 .ctrlbit = (1 << 24),
1046 },
1047 .sources = &exynos4_clkset_group,
1048 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1049 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1050 }, {
1051 .clk = {
1052 .name = "sclk_csis",
1053 .devname = "s5p-mipi-csis.1",
1054 .enable = exynos4_clksrc_mask_cam_ctrl,
1055 .ctrlbit = (1 << 28),
1056 },
1057 .sources = &exynos4_clkset_group,
1058 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1059 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1060 }, {
1061 .clk = {
1062 .name = "sclk_cam0",
1063 .enable = exynos4_clksrc_mask_cam_ctrl,
1064 .ctrlbit = (1 << 16),
1065 },
1066 .sources = &exynos4_clkset_group,
1067 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1068 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1069 }, {
1070 .clk = {
1071 .name = "sclk_cam1",
1072 .enable = exynos4_clksrc_mask_cam_ctrl,
1073 .ctrlbit = (1 << 20),
1074 },
1075 .sources = &exynos4_clkset_group,
1076 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1077 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1078 }, {
1079 .clk = {
1080 .name = "sclk_fimc",
1081 .devname = "exynos4-fimc.0",
1082 .enable = exynos4_clksrc_mask_cam_ctrl,
1083 .ctrlbit = (1 << 0),
1084 },
1085 .sources = &exynos4_clkset_group,
1086 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1087 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1088 }, {
1089 .clk = {
1090 .name = "sclk_fimc",
1091 .devname = "exynos4-fimc.1",
1092 .enable = exynos4_clksrc_mask_cam_ctrl,
1093 .ctrlbit = (1 << 4),
1094 },
1095 .sources = &exynos4_clkset_group,
1096 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1097 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1098 }, {
1099 .clk = {
1100 .name = "sclk_fimc",
1101 .devname = "exynos4-fimc.2",
1102 .enable = exynos4_clksrc_mask_cam_ctrl,
1103 .ctrlbit = (1 << 8),
1104 },
1105 .sources = &exynos4_clkset_group,
1106 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1107 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1108 }, {
1109 .clk = {
1110 .name = "sclk_fimc",
1111 .devname = "exynos4-fimc.3",
1112 .enable = exynos4_clksrc_mask_cam_ctrl,
1113 .ctrlbit = (1 << 12),
1114 },
1115 .sources = &exynos4_clkset_group,
1116 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1117 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1118 }, {
1119 .clk = {
1120 .name = "sclk_fimd",
1121 .devname = "exynos4-fb.0",
1122 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1123 .ctrlbit = (1 << 0),
1124 },
1125 .sources = &exynos4_clkset_group,
1126 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1127 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1128 }, {
1129 .clk = {
1130 .name = "sclk_fimg2d",
1131 },
1132 .sources = &exynos4_clkset_mout_g2d,
1133 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1134 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1135 }, {
1136 .clk = {
1137 .name = "sclk_mfc",
1138 .devname = "s5p-mfc",
1139 },
1140 .sources = &exynos4_clkset_mout_mfc,
1141 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1142 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1143 }, {
1144 .clk = {
1145 .name = "sclk_dwmmc",
1146 .parent = &exynos4_clk_dout_mmc4.clk,
1147 .enable = exynos4_clksrc_mask_fsys_ctrl,
1148 .ctrlbit = (1 << 16),
1149 },
1150 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1151 }
1152};
1153
1154static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1155 .clk = {
1156 .name = "uclk1",
1157 .devname = "exynos4210-uart.0",
1158 .enable = exynos4_clksrc_mask_peril0_ctrl,
1159 .ctrlbit = (1 << 0),
1160 },
1161 .sources = &exynos4_clkset_group,
1162 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1163 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1164};
1165
1166static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1167 .clk = {
1168 .name = "uclk1",
1169 .devname = "exynos4210-uart.1",
1170 .enable = exynos4_clksrc_mask_peril0_ctrl,
1171 .ctrlbit = (1 << 4),
1172 },
1173 .sources = &exynos4_clkset_group,
1174 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1175 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1176};
1177
1178static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1179 .clk = {
1180 .name = "uclk1",
1181 .devname = "exynos4210-uart.2",
1182 .enable = exynos4_clksrc_mask_peril0_ctrl,
1183 .ctrlbit = (1 << 8),
1184 },
1185 .sources = &exynos4_clkset_group,
1186 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1187 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1188};
1189
1190static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1191 .clk = {
1192 .name = "uclk1",
1193 .devname = "exynos4210-uart.3",
1194 .enable = exynos4_clksrc_mask_peril0_ctrl,
1195 .ctrlbit = (1 << 12),
1196 },
1197 .sources = &exynos4_clkset_group,
1198 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1199 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1200};
1201
1202static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1203 .clk = {
1204 .name = "sclk_mmc",
1205 .devname = "s3c-sdhci.0",
1206 .parent = &exynos4_clk_dout_mmc0.clk,
1207 .enable = exynos4_clksrc_mask_fsys_ctrl,
1208 .ctrlbit = (1 << 0),
1209 },
1210 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1211};
1212
1213static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1214 .clk = {
1215 .name = "sclk_mmc",
1216 .devname = "s3c-sdhci.1",
1217 .parent = &exynos4_clk_dout_mmc1.clk,
1218 .enable = exynos4_clksrc_mask_fsys_ctrl,
1219 .ctrlbit = (1 << 4),
1220 },
1221 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1222};
1223
1224static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1225 .clk = {
1226 .name = "sclk_mmc",
1227 .devname = "s3c-sdhci.2",
1228 .parent = &exynos4_clk_dout_mmc2.clk,
1229 .enable = exynos4_clksrc_mask_fsys_ctrl,
1230 .ctrlbit = (1 << 8),
1231 },
1232 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1233};
1234
1235static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1236 .clk = {
1237 .name = "sclk_mmc",
1238 .devname = "s3c-sdhci.3",
1239 .parent = &exynos4_clk_dout_mmc3.clk,
1240 .enable = exynos4_clksrc_mask_fsys_ctrl,
1241 .ctrlbit = (1 << 12),
1242 },
1243 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1244};
1245
1246static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1247 .clk = {
1248 .name = "sclk_spi",
1249 .devname = "s3c64xx-spi.0",
1250 .enable = exynos4_clksrc_mask_peril1_ctrl,
1251 .ctrlbit = (1 << 16),
1252 },
1253 .sources = &exynos4_clkset_group,
1254 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1255 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1256};
1257
1258static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1259 .clk = {
1260 .name = "sclk_spi",
1261 .devname = "s3c64xx-spi.1",
1262 .enable = exynos4_clksrc_mask_peril1_ctrl,
1263 .ctrlbit = (1 << 20),
1264 },
1265 .sources = &exynos4_clkset_group,
1266 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1267 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1268};
1269
1270static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1271 .clk = {
1272 .name = "sclk_spi",
1273 .devname = "s3c64xx-spi.2",
1274 .enable = exynos4_clksrc_mask_peril1_ctrl,
1275 .ctrlbit = (1 << 24),
1276 },
1277 .sources = &exynos4_clkset_group,
1278 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1279 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1280};
1281
1282/* Clock initialization code */
1283static struct clksrc_clk *exynos4_sysclks[] = {
1284 &exynos4_clk_mout_apll,
1285 &exynos4_clk_sclk_apll,
1286 &exynos4_clk_mout_epll,
1287 &exynos4_clk_mout_mpll,
1288 &exynos4_clk_moutcore,
1289 &exynos4_clk_coreclk,
1290 &exynos4_clk_armclk,
1291 &exynos4_clk_aclk_corem0,
1292 &exynos4_clk_aclk_cores,
1293 &exynos4_clk_aclk_corem1,
1294 &exynos4_clk_periphclk,
1295 &exynos4_clk_mout_corebus,
1296 &exynos4_clk_sclk_dmc,
1297 &exynos4_clk_aclk_cored,
1298 &exynos4_clk_aclk_corep,
1299 &exynos4_clk_aclk_acp,
1300 &exynos4_clk_pclk_acp,
1301 &exynos4_clk_vpllsrc,
1302 &exynos4_clk_sclk_vpll,
1303 &exynos4_clk_aclk_200,
1304 &exynos4_clk_aclk_100,
1305 &exynos4_clk_aclk_160,
1306 &exynos4_clk_aclk_133,
1307 &exynos4_clk_dout_mmc0,
1308 &exynos4_clk_dout_mmc1,
1309 &exynos4_clk_dout_mmc2,
1310 &exynos4_clk_dout_mmc3,
1311 &exynos4_clk_dout_mmc4,
1312 &exynos4_clk_mout_mfc0,
1313 &exynos4_clk_mout_mfc1,
1314};
1315
1316static struct clk *exynos4_clk_cdev[] = {
1317 &exynos4_clk_pdma0,
1318 &exynos4_clk_pdma1,
1319 &exynos4_clk_mdma1,
1320 &exynos4_clk_fimd0,
1321};
1322
1323static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1324 &exynos4_clk_sclk_uart0,
1325 &exynos4_clk_sclk_uart1,
1326 &exynos4_clk_sclk_uart2,
1327 &exynos4_clk_sclk_uart3,
1328 &exynos4_clk_sclk_mmc0,
1329 &exynos4_clk_sclk_mmc1,
1330 &exynos4_clk_sclk_mmc2,
1331 &exynos4_clk_sclk_mmc3,
1332 &exynos4_clk_sclk_spi0,
1333 &exynos4_clk_sclk_spi1,
1334 &exynos4_clk_sclk_spi2,
1335
1336};
1337
1338static struct clk_lookup exynos4_clk_lookup[] = {
1339 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1340 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1341 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1342 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1343 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1344 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1345 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1346 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1347 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1348 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1349 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1350 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1351 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1352 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1353 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1354};
1355
1356static int xtal_rate;
1357
1358static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1359{
1360 if (soc_is_exynos4210())
1361 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1362 pll_4508);
1363 else if (soc_is_exynos4212() || soc_is_exynos4412())
1364 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1365 else
1366 return 0;
1367}
1368
1369static struct clk_ops exynos4_fout_apll_ops = {
1370 .get_rate = exynos4_fout_apll_get_rate,
1371};
1372
1373static u32 exynos4_vpll_div[][8] = {
1374 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1375 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1376};
1377
1378static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1379{
1380 return clk->rate;
1381}
1382
1383static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1384{
1385 unsigned int vpll_con0, vpll_con1 = 0;
1386 unsigned int i;
1387
1388 /* Return if nothing changed */
1389 if (clk->rate == rate)
1390 return 0;
1391
1392 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1393 vpll_con0 &= ~(0x1 << 27 | \
1394 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1395 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1396 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1397
1398 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1399 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1400 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1401 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1402
1403 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1404 if (exynos4_vpll_div[i][0] == rate) {
1405 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1406 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1407 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1408 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1409 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1410 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1411 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1412 break;
1413 }
1414 }
1415
1416 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1417 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1418 __func__);
1419 return -EINVAL;
1420 }
1421
1422 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1423 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1424
1425 /* Wait for VPLL lock */
1426 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1427 continue;
1428
1429 clk->rate = rate;
1430 return 0;
1431}
1432
1433static struct clk_ops exynos4_vpll_ops = {
1434 .get_rate = exynos4_vpll_get_rate,
1435 .set_rate = exynos4_vpll_set_rate,
1436};
1437
1438void __init_or_cpufreq exynos4_setup_clocks(void)
1439{
1440 struct clk *xtal_clk;
1441 unsigned long apll = 0;
1442 unsigned long mpll = 0;
1443 unsigned long epll = 0;
1444 unsigned long vpll = 0;
1445 unsigned long vpllsrc;
1446 unsigned long xtal;
1447 unsigned long armclk;
1448 unsigned long sclk_dmc;
1449 unsigned long aclk_200;
1450 unsigned long aclk_100;
1451 unsigned long aclk_160;
1452 unsigned long aclk_133;
1453 unsigned int ptr;
1454
1455 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1456
1457 xtal_clk = clk_get(NULL, "xtal");
1458 BUG_ON(IS_ERR(xtal_clk));
1459
1460 xtal = clk_get_rate(xtal_clk);
1461
1462 xtal_rate = xtal;
1463
1464 clk_put(xtal_clk);
1465
1466 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1467
1468 if (soc_is_exynos4210()) {
1469 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1470 pll_4508);
1471 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1472 pll_4508);
1473 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1474 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1475
1476 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1477 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1478 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1479 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1480 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1481 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1482 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1483 __raw_readl(EXYNOS4_EPLL_CON1));
1484
1485 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1486 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1487 __raw_readl(EXYNOS4_VPLL_CON1));
1488 } else {
1489 /* nothing */
1490 }
1491
1492 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1493 clk_fout_mpll.rate = mpll;
1494 clk_fout_epll.rate = epll;
1495 clk_fout_vpll.ops = &exynos4_vpll_ops;
1496 clk_fout_vpll.rate = vpll;
1497
1498 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1499 apll, mpll, epll, vpll);
1500
1501 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1502 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1503
1504 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1505 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1506 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1507 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1508
1509 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1510 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1511 armclk, sclk_dmc, aclk_200,
1512 aclk_100, aclk_160, aclk_133);
1513
1514 clk_f.rate = armclk;
1515 clk_h.rate = sclk_dmc;
1516 clk_p.rate = aclk_100;
1517
1518 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1519 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1520}
1521
1522static struct clk *exynos4_clks[] __initdata = {
1523 &exynos4_clk_sclk_hdmi27m,
1524 &exynos4_clk_sclk_hdmiphy,
1525 &exynos4_clk_sclk_usbphy0,
1526 &exynos4_clk_sclk_usbphy1,
1527};
1528
1529#ifdef CONFIG_PM_SLEEP
1530static int exynos4_clock_suspend(void)
1531{
1532 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1533 return 0;
1534}
1535
1536static void exynos4_clock_resume(void)
1537{
1538 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1539}
1540
1541#else
1542#define exynos4_clock_suspend NULL
1543#define exynos4_clock_resume NULL
1544#endif
1545
1546static struct syscore_ops exynos4_clock_syscore_ops = {
1547 .suspend = exynos4_clock_suspend,
1548 .resume = exynos4_clock_resume,
1549};
1550
1551void __init exynos4_register_clocks(void)
1552{
1553 int ptr;
1554
1555 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1556
1557 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1558 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1559
1560 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1561 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1562
1563 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1564 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1565
1566 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1567 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1568
1569 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1570 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1571 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1572
1573 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1574 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1575 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1576
1577 register_syscore_ops(&exynos4_clock_syscore_ops);
1578 s3c24xx_register_clock(&dummy_apb_pclk);
1579
1580 s3c_pwmclk_init();
1581}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 000000000000..cb71c29c14d1
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Header file for exynos4 clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_CLOCK_H
13#define __ASM_ARCH_CLOCK_H __FILE__
14
15#include <linux/clk.h>
16
17extern struct clksrc_clk exynos4_clk_aclk_133;
18extern struct clksrc_clk exynos4_clk_mout_mpll;
19
20extern struct clksrc_sources exynos4_clkset_mout_corebus;
21extern struct clksrc_sources exynos4_clkset_group;
22
23extern struct clk *exynos4_clkset_aclk_top_list[];
24extern struct clk *exynos4_clkset_group_list[];
25
26extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
27extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
28extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
29
30#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index a5823a7f249e..3b131e4b6ef5 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4210.c 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 3 * http://www.samsung.com
6 * 4 *
7 * EXYNOS4210 - Clock support 5 * EXYNOS4210 - Clock support
@@ -28,20 +26,22 @@
28#include <mach/hardware.h> 26#include <mach/hardware.h>
29#include <mach/map.h> 27#include <mach/map.h>
30#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
31#include <mach/exynos4-clock.h>
32 29
33#include "common.h" 30#include "common.h"
31#include "clock-exynos4.h"
34 32
33#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4210_clock_save[] = { 34static struct sleep_save exynos4210_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKSRC_LCD1), 36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKDIV_IMAGE), 37 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
39 SAVE_ITEM(S5P_CLKDIV_LCD1), 38 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
40 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), 39 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
41 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210), 40 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
42 SAVE_ITEM(S5P_CLKGATE_IP_LCD1), 41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
43 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), 42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
44}; 43};
44#endif
45 45
46static struct clksrc_clk *sysclks[] = { 46static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */ 47 /* nothing here yet */
@@ -49,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
49 49
50static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 50static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
51{ 51{
52 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); 52 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
53} 53}
54 54
55static struct clksrc_clk clksrcs[] = { 55static struct clksrc_clk clksrcs[] = {
@@ -60,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
60 .enable = exynos4_clksrc_mask_fsys_ctrl, 60 .enable = exynos4_clksrc_mask_fsys_ctrl,
61 .ctrlbit = (1 << 24), 61 .ctrlbit = (1 << 24),
62 }, 62 },
63 .sources = &clkset_mout_corebus, 63 .sources = &exynos4_clkset_mout_corebus,
64 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, 64 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
65 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, 65 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
66 }, { 66 }, {
67 .clk = { 67 .clk = {
68 .name = "sclk_fimd", 68 .name = "sclk_fimd",
@@ -70,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
70 .enable = exynos4_clksrc_mask_lcd1_ctrl, 70 .enable = exynos4_clksrc_mask_lcd1_ctrl,
71 .ctrlbit = (1 << 0), 71 .ctrlbit = (1 << 0),
72 }, 72 },
73 .sources = &clkset_group, 73 .sources = &exynos4_clkset_group,
74 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, 74 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
75 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, 75 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
76 }, 76 },
77}; 77};
78 78
@@ -80,13 +80,13 @@ static struct clk init_clocks_off[] = {
80 { 80 {
81 .name = "sataphy", 81 .name = "sataphy",
82 .id = -1, 82 .id = -1,
83 .parent = &clk_aclk_133.clk, 83 .parent = &exynos4_clk_aclk_133.clk,
84 .enable = exynos4_clk_ip_fsys_ctrl, 84 .enable = exynos4_clk_ip_fsys_ctrl,
85 .ctrlbit = (1 << 3), 85 .ctrlbit = (1 << 3),
86 }, { 86 }, {
87 .name = "sata", 87 .name = "sata",
88 .id = -1, 88 .id = -1,
89 .parent = &clk_aclk_133.clk, 89 .parent = &exynos4_clk_aclk_133.clk,
90 .enable = exynos4_clk_ip_fsys_ctrl, 90 .enable = exynos4_clk_ip_fsys_ctrl,
91 .ctrlbit = (1 << 10), 91 .ctrlbit = (1 << 10),
92 }, { 92 }, {
@@ -115,7 +115,7 @@ static void exynos4210_clock_resume(void)
115#define exynos4210_clock_resume NULL 115#define exynos4210_clock_resume NULL
116#endif 116#endif
117 117
118struct syscore_ops exynos4210_clock_syscore_ops = { 118static struct syscore_ops exynos4210_clock_syscore_ops = {
119 .suspend = exynos4210_clock_suspend, 119 .suspend = exynos4210_clock_suspend,
120 .resume = exynos4210_clock_resume, 120 .resume = exynos4210_clock_resume,
121}; 121};
@@ -124,9 +124,9 @@ void __init exynos4210_register_clocks(void)
124{ 124{
125 int ptr; 125 int ptr;
126 126
127 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU; 127 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
128 clk_mout_mpll.reg_src.shift = 8; 128 exynos4_clk_mout_mpll.reg_src.shift = 8;
129 clk_mout_mpll.reg_src.size = 1; 129 exynos4_clk_mout_mpll.reg_src.size = 1;
130 130
131 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 131 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
132 s3c_register_clksrc(sysclks[ptr], 1); 132 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 26a668b0d101..3ecc01e06f74 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4212.c 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 3 * http://www.samsung.com
6 * 4 *
7 * EXYNOS4212 - Clock support 5 * EXYNOS4212 - Clock support
@@ -28,20 +26,22 @@
28#include <mach/hardware.h> 26#include <mach/hardware.h>
29#include <mach/map.h> 27#include <mach/map.h>
30#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
31#include <mach/exynos4-clock.h>
32 29
33#include "common.h" 30#include "common.h"
31#include "clock-exynos4.h"
34 32
33#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4212_clock_save[] = { 34static struct sleep_save exynos4212_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE), 36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), 37 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
39 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), 38 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
40}; 39};
40#endif
41 41
42static struct clk *clk_src_mpll_user_list[] = { 42static struct clk *clk_src_mpll_user_list[] = {
43 [0] = &clk_fin_mpll, 43 [0] = &clk_fin_mpll,
44 [1] = &clk_mout_mpll.clk, 44 [1] = &exynos4_clk_mout_mpll.clk,
45}; 45};
46 46
47static struct clksrc_sources clk_src_mpll_user = { 47static struct clksrc_sources clk_src_mpll_user = {
@@ -54,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
54 .name = "mout_mpll_user", 54 .name = "mout_mpll_user",
55 }, 55 },
56 .sources = &clk_src_mpll_user, 56 .sources = &clk_src_mpll_user,
57 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 }, 57 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
58}; 58};
59 59
60static struct clksrc_clk *sysclks[] = { 60static struct clksrc_clk *sysclks[] = {
@@ -87,7 +87,7 @@ static void exynos4212_clock_resume(void)
87#define exynos4212_clock_resume NULL 87#define exynos4212_clock_resume NULL
88#endif 88#endif
89 89
90struct syscore_ops exynos4212_clock_syscore_ops = { 90static struct syscore_ops exynos4212_clock_syscore_ops = {
91 .suspend = exynos4212_clock_suspend, 91 .suspend = exynos4212_clock_suspend,
92 .resume = exynos4212_clock_resume, 92 .resume = exynos4212_clock_resume,
93}; 93};
@@ -97,15 +97,15 @@ void __init exynos4212_register_clocks(void)
97 int ptr; 97 int ptr;
98 98
99 /* usbphy1 is removed */ 99 /* usbphy1 is removed */
100 clkset_group_list[4] = NULL; 100 exynos4_clkset_group_list[4] = NULL;
101 101
102 /* mout_mpll_user is used */ 102 /* mout_mpll_user is used */
103 clkset_group_list[6] = &clk_mout_mpll_user.clk; 103 exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
104 clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; 104 exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
105 105
106 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC; 106 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
107 clk_mout_mpll.reg_src.shift = 12; 107 exynos4_clk_mout_mpll.reg_src.shift = 12;
108 clk_mout_mpll.reg_src.size = 1; 108 exynos4_clk_mout_mpll.reg_src.size = 1;
109 109
110 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 110 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
111 s3c_register_clksrc(sysclks[ptr], 1); 111 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 000000000000..d013982d0f8e
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28
29#include "common.h"
30
31#ifdef CONFIG_PM_SLEEP
32static struct sleep_save exynos5_clock_save[] = {
33 /* will be implemented */
34};
35#endif
36
37static struct clk exynos5_clk_sclk_dptxphy = {
38 .name = "sclk_dptx",
39};
40
41static struct clk exynos5_clk_sclk_hdmi24m = {
42 .name = "sclk_hdmi24m",
43 .rate = 24000000,
44};
45
46static struct clk exynos5_clk_sclk_hdmi27m = {
47 .name = "sclk_hdmi27m",
48 .rate = 27000000,
49};
50
51static struct clk exynos5_clk_sclk_hdmiphy = {
52 .name = "sclk_hdmiphy",
53};
54
55static struct clk exynos5_clk_sclk_usbphy = {
56 .name = "sclk_usbphy",
57 .rate = 48000000,
58};
59
60static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
61{
62 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
63}
64
65static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
66{
67 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
68}
69
70static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
71{
72 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
73}
74
75static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
76{
77 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
78}
79
80static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
81{
82 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
83}
84
85static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
86{
87 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
88}
89
90static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
91{
92 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
93}
94
95static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
96{
97 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
98}
99
100static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
101{
102 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
103}
104
105static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
106{
107 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
108}
109
110static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
111{
112 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
113}
114
115static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
116{
117 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
118}
119
120static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
123}
124
125static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
128}
129
130/* Core list of CMU_CPU side */
131
132static struct clksrc_clk exynos5_clk_mout_apll = {
133 .clk = {
134 .name = "mout_apll",
135 },
136 .sources = &clk_src_apll,
137 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
138};
139
140static struct clksrc_clk exynos5_clk_sclk_apll = {
141 .clk = {
142 .name = "sclk_apll",
143 .parent = &exynos5_clk_mout_apll.clk,
144 },
145 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
146};
147
148static struct clksrc_clk exynos5_clk_mout_bpll = {
149 .clk = {
150 .name = "mout_bpll",
151 },
152 .sources = &clk_src_bpll,
153 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
154};
155
156static struct clk *exynos5_clk_src_bpll_user_list[] = {
157 [0] = &clk_fin_mpll,
158 [1] = &exynos5_clk_mout_bpll.clk,
159};
160
161static struct clksrc_sources exynos5_clk_src_bpll_user = {
162 .sources = exynos5_clk_src_bpll_user_list,
163 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
164};
165
166static struct clksrc_clk exynos5_clk_mout_bpll_user = {
167 .clk = {
168 .name = "mout_bpll_user",
169 },
170 .sources = &exynos5_clk_src_bpll_user,
171 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
172};
173
174static struct clksrc_clk exynos5_clk_mout_cpll = {
175 .clk = {
176 .name = "mout_cpll",
177 },
178 .sources = &clk_src_cpll,
179 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
180};
181
182static struct clksrc_clk exynos5_clk_mout_epll = {
183 .clk = {
184 .name = "mout_epll",
185 },
186 .sources = &clk_src_epll,
187 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
188};
189
190struct clksrc_clk exynos5_clk_mout_mpll = {
191 .clk = {
192 .name = "mout_mpll",
193 },
194 .sources = &clk_src_mpll,
195 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
196};
197
198static struct clk *exynos_clkset_vpllsrc_list[] = {
199 [0] = &clk_fin_vpll,
200 [1] = &exynos5_clk_sclk_hdmi27m,
201};
202
203static struct clksrc_sources exynos5_clkset_vpllsrc = {
204 .sources = exynos_clkset_vpllsrc_list,
205 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
206};
207
208static struct clksrc_clk exynos5_clk_vpllsrc = {
209 .clk = {
210 .name = "vpll_src",
211 .enable = exynos5_clksrc_mask_top_ctrl,
212 .ctrlbit = (1 << 0),
213 },
214 .sources = &exynos5_clkset_vpllsrc,
215 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
216};
217
218static struct clk *exynos5_clkset_sclk_vpll_list[] = {
219 [0] = &exynos5_clk_vpllsrc.clk,
220 [1] = &clk_fout_vpll,
221};
222
223static struct clksrc_sources exynos5_clkset_sclk_vpll = {
224 .sources = exynos5_clkset_sclk_vpll_list,
225 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
226};
227
228static struct clksrc_clk exynos5_clk_sclk_vpll = {
229 .clk = {
230 .name = "sclk_vpll",
231 },
232 .sources = &exynos5_clkset_sclk_vpll,
233 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
234};
235
236static struct clksrc_clk exynos5_clk_sclk_pixel = {
237 .clk = {
238 .name = "sclk_pixel",
239 .parent = &exynos5_clk_sclk_vpll.clk,
240 },
241 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
242};
243
244static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
245 [0] = &exynos5_clk_sclk_pixel.clk,
246 [1] = &exynos5_clk_sclk_hdmiphy,
247};
248
249static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
250 .sources = exynos5_clkset_sclk_hdmi_list,
251 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
252};
253
254static struct clksrc_clk exynos5_clk_sclk_hdmi = {
255 .clk = {
256 .name = "sclk_hdmi",
257 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
258 .ctrlbit = (1 << 20),
259 },
260 .sources = &exynos5_clkset_sclk_hdmi,
261 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
262};
263
264static struct clksrc_clk *exynos5_sclk_tv[] = {
265 &exynos5_clk_sclk_pixel,
266 &exynos5_clk_sclk_hdmi,
267};
268
269static struct clk *exynos5_clk_src_mpll_user_list[] = {
270 [0] = &clk_fin_mpll,
271 [1] = &exynos5_clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources exynos5_clk_src_mpll_user = {
275 .sources = exynos5_clk_src_mpll_user_list,
276 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
277};
278
279static struct clksrc_clk exynos5_clk_mout_mpll_user = {
280 .clk = {
281 .name = "mout_mpll_user",
282 },
283 .sources = &exynos5_clk_src_mpll_user,
284 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
285};
286
287static struct clk *exynos5_clkset_mout_cpu_list[] = {
288 [0] = &exynos5_clk_mout_apll.clk,
289 [1] = &exynos5_clk_mout_mpll.clk,
290};
291
292static struct clksrc_sources exynos5_clkset_mout_cpu = {
293 .sources = exynos5_clkset_mout_cpu_list,
294 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
295};
296
297static struct clksrc_clk exynos5_clk_mout_cpu = {
298 .clk = {
299 .name = "mout_cpu",
300 },
301 .sources = &exynos5_clkset_mout_cpu,
302 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
303};
304
305static struct clksrc_clk exynos5_clk_dout_armclk = {
306 .clk = {
307 .name = "dout_armclk",
308 .parent = &exynos5_clk_mout_cpu.clk,
309 },
310 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
311};
312
313static struct clksrc_clk exynos5_clk_dout_arm2clk = {
314 .clk = {
315 .name = "dout_arm2clk",
316 .parent = &exynos5_clk_dout_armclk.clk,
317 },
318 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
319};
320
321static struct clk exynos5_clk_armclk = {
322 .name = "armclk",
323 .parent = &exynos5_clk_dout_arm2clk.clk,
324};
325
326/* Core list of CMU_CDREX side */
327
328static struct clk *exynos5_clkset_cdrex_list[] = {
329 [0] = &exynos5_clk_mout_mpll.clk,
330 [1] = &exynos5_clk_mout_bpll.clk,
331};
332
333static struct clksrc_sources exynos5_clkset_cdrex = {
334 .sources = exynos5_clkset_cdrex_list,
335 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
336};
337
338static struct clksrc_clk exynos5_clk_cdrex = {
339 .clk = {
340 .name = "clk_cdrex",
341 },
342 .sources = &exynos5_clkset_cdrex,
343 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
344 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
345};
346
347static struct clksrc_clk exynos5_clk_aclk_acp = {
348 .clk = {
349 .name = "aclk_acp",
350 .parent = &exynos5_clk_mout_mpll.clk,
351 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
353};
354
355static struct clksrc_clk exynos5_clk_pclk_acp = {
356 .clk = {
357 .name = "pclk_acp",
358 .parent = &exynos5_clk_aclk_acp.clk,
359 },
360 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
361};
362
363/* Core list of CMU_TOP side */
364
365struct clk *exynos5_clkset_aclk_top_list[] = {
366 [0] = &exynos5_clk_mout_mpll_user.clk,
367 [1] = &exynos5_clk_mout_bpll_user.clk,
368};
369
370struct clksrc_sources exynos5_clkset_aclk = {
371 .sources = exynos5_clkset_aclk_top_list,
372 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
373};
374
375static struct clksrc_clk exynos5_clk_aclk_400 = {
376 .clk = {
377 .name = "aclk_400",
378 },
379 .sources = &exynos5_clkset_aclk,
380 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
381 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
382};
383
384struct clk *exynos5_clkset_aclk_333_166_list[] = {
385 [0] = &exynos5_clk_mout_cpll.clk,
386 [1] = &exynos5_clk_mout_mpll_user.clk,
387};
388
389struct clksrc_sources exynos5_clkset_aclk_333_166 = {
390 .sources = exynos5_clkset_aclk_333_166_list,
391 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
392};
393
394static struct clksrc_clk exynos5_clk_aclk_333 = {
395 .clk = {
396 .name = "aclk_333",
397 },
398 .sources = &exynos5_clkset_aclk_333_166,
399 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
400 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
401};
402
403static struct clksrc_clk exynos5_clk_aclk_166 = {
404 .clk = {
405 .name = "aclk_166",
406 },
407 .sources = &exynos5_clkset_aclk_333_166,
408 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
409 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
410};
411
412static struct clksrc_clk exynos5_clk_aclk_266 = {
413 .clk = {
414 .name = "aclk_266",
415 .parent = &exynos5_clk_mout_mpll_user.clk,
416 },
417 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
418};
419
420static struct clksrc_clk exynos5_clk_aclk_200 = {
421 .clk = {
422 .name = "aclk_200",
423 },
424 .sources = &exynos5_clkset_aclk,
425 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
426 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
427};
428
429static struct clksrc_clk exynos5_clk_aclk_66_pre = {
430 .clk = {
431 .name = "aclk_66_pre",
432 .parent = &exynos5_clk_mout_mpll_user.clk,
433 },
434 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
435};
436
437static struct clksrc_clk exynos5_clk_aclk_66 = {
438 .clk = {
439 .name = "aclk_66",
440 .parent = &exynos5_clk_aclk_66_pre.clk,
441 },
442 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
443};
444
445static struct clk exynos5_init_clocks_off[] = {
446 {
447 .name = "timers",
448 .parent = &exynos5_clk_aclk_66.clk,
449 .enable = exynos5_clk_ip_peric_ctrl,
450 .ctrlbit = (1 << 24),
451 }, {
452 .name = "rtc",
453 .parent = &exynos5_clk_aclk_66.clk,
454 .enable = exynos5_clk_ip_peris_ctrl,
455 .ctrlbit = (1 << 20),
456 }, {
457 .name = "hsmmc",
458 .devname = "s3c-sdhci.0",
459 .parent = &exynos5_clk_aclk_200.clk,
460 .enable = exynos5_clk_ip_fsys_ctrl,
461 .ctrlbit = (1 << 12),
462 }, {
463 .name = "hsmmc",
464 .devname = "s3c-sdhci.1",
465 .parent = &exynos5_clk_aclk_200.clk,
466 .enable = exynos5_clk_ip_fsys_ctrl,
467 .ctrlbit = (1 << 13),
468 }, {
469 .name = "hsmmc",
470 .devname = "s3c-sdhci.2",
471 .parent = &exynos5_clk_aclk_200.clk,
472 .enable = exynos5_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 14),
474 }, {
475 .name = "hsmmc",
476 .devname = "s3c-sdhci.3",
477 .parent = &exynos5_clk_aclk_200.clk,
478 .enable = exynos5_clk_ip_fsys_ctrl,
479 .ctrlbit = (1 << 15),
480 }, {
481 .name = "dwmci",
482 .parent = &exynos5_clk_aclk_200.clk,
483 .enable = exynos5_clk_ip_fsys_ctrl,
484 .ctrlbit = (1 << 16),
485 }, {
486 .name = "sata",
487 .devname = "ahci",
488 .enable = exynos5_clk_ip_fsys_ctrl,
489 .ctrlbit = (1 << 6),
490 }, {
491 .name = "sata_phy",
492 .enable = exynos5_clk_ip_fsys_ctrl,
493 .ctrlbit = (1 << 24),
494 }, {
495 .name = "sata_phy_i2c",
496 .enable = exynos5_clk_ip_fsys_ctrl,
497 .ctrlbit = (1 << 25),
498 }, {
499 .name = "mfc",
500 .devname = "s5p-mfc",
501 .enable = exynos5_clk_ip_mfc_ctrl,
502 .ctrlbit = (1 << 0),
503 }, {
504 .name = "hdmi",
505 .devname = "exynos4-hdmi",
506 .enable = exynos5_clk_ip_disp1_ctrl,
507 .ctrlbit = (1 << 6),
508 }, {
509 .name = "mixer",
510 .devname = "s5p-mixer",
511 .enable = exynos5_clk_ip_disp1_ctrl,
512 .ctrlbit = (1 << 5),
513 }, {
514 .name = "jpeg",
515 .enable = exynos5_clk_ip_gen_ctrl,
516 .ctrlbit = (1 << 2),
517 }, {
518 .name = "dsim0",
519 .enable = exynos5_clk_ip_disp1_ctrl,
520 .ctrlbit = (1 << 3),
521 }, {
522 .name = "iis",
523 .devname = "samsung-i2s.1",
524 .enable = exynos5_clk_ip_peric_ctrl,
525 .ctrlbit = (1 << 20),
526 }, {
527 .name = "iis",
528 .devname = "samsung-i2s.2",
529 .enable = exynos5_clk_ip_peric_ctrl,
530 .ctrlbit = (1 << 21),
531 }, {
532 .name = "pcm",
533 .devname = "samsung-pcm.1",
534 .enable = exynos5_clk_ip_peric_ctrl,
535 .ctrlbit = (1 << 22),
536 }, {
537 .name = "pcm",
538 .devname = "samsung-pcm.2",
539 .enable = exynos5_clk_ip_peric_ctrl,
540 .ctrlbit = (1 << 23),
541 }, {
542 .name = "spdif",
543 .devname = "samsung-spdif",
544 .enable = exynos5_clk_ip_peric_ctrl,
545 .ctrlbit = (1 << 26),
546 }, {
547 .name = "ac97",
548 .devname = "samsung-ac97",
549 .enable = exynos5_clk_ip_peric_ctrl,
550 .ctrlbit = (1 << 27),
551 }, {
552 .name = "usbhost",
553 .enable = exynos5_clk_ip_fsys_ctrl ,
554 .ctrlbit = (1 << 18),
555 }, {
556 .name = "usbotg",
557 .enable = exynos5_clk_ip_fsys_ctrl,
558 .ctrlbit = (1 << 7),
559 }, {
560 .name = "gps",
561 .enable = exynos5_clk_ip_gps_ctrl,
562 .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)),
563 }, {
564 .name = "nfcon",
565 .enable = exynos5_clk_ip_fsys_ctrl,
566 .ctrlbit = (1 << 22),
567 }, {
568 .name = "iop",
569 .enable = exynos5_clk_ip_fsys_ctrl,
570 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
571 }, {
572 .name = "core_iop",
573 .enable = exynos5_clk_ip_core_ctrl,
574 .ctrlbit = ((1 << 21) | (1 << 3)),
575 }, {
576 .name = "mcu_iop",
577 .enable = exynos5_clk_ip_fsys_ctrl,
578 .ctrlbit = (1 << 0),
579 }, {
580 .name = "i2c",
581 .devname = "s3c2440-i2c.0",
582 .parent = &exynos5_clk_aclk_66.clk,
583 .enable = exynos5_clk_ip_peric_ctrl,
584 .ctrlbit = (1 << 6),
585 }, {
586 .name = "i2c",
587 .devname = "s3c2440-i2c.1",
588 .parent = &exynos5_clk_aclk_66.clk,
589 .enable = exynos5_clk_ip_peric_ctrl,
590 .ctrlbit = (1 << 7),
591 }, {
592 .name = "i2c",
593 .devname = "s3c2440-i2c.2",
594 .parent = &exynos5_clk_aclk_66.clk,
595 .enable = exynos5_clk_ip_peric_ctrl,
596 .ctrlbit = (1 << 8),
597 }, {
598 .name = "i2c",
599 .devname = "s3c2440-i2c.3",
600 .parent = &exynos5_clk_aclk_66.clk,
601 .enable = exynos5_clk_ip_peric_ctrl,
602 .ctrlbit = (1 << 9),
603 }, {
604 .name = "i2c",
605 .devname = "s3c2440-i2c.4",
606 .parent = &exynos5_clk_aclk_66.clk,
607 .enable = exynos5_clk_ip_peric_ctrl,
608 .ctrlbit = (1 << 10),
609 }, {
610 .name = "i2c",
611 .devname = "s3c2440-i2c.5",
612 .parent = &exynos5_clk_aclk_66.clk,
613 .enable = exynos5_clk_ip_peric_ctrl,
614 .ctrlbit = (1 << 11),
615 }, {
616 .name = "i2c",
617 .devname = "s3c2440-i2c.6",
618 .parent = &exynos5_clk_aclk_66.clk,
619 .enable = exynos5_clk_ip_peric_ctrl,
620 .ctrlbit = (1 << 12),
621 }, {
622 .name = "i2c",
623 .devname = "s3c2440-i2c.7",
624 .parent = &exynos5_clk_aclk_66.clk,
625 .enable = exynos5_clk_ip_peric_ctrl,
626 .ctrlbit = (1 << 13),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-hdmiphy-i2c",
630 .parent = &exynos5_clk_aclk_66.clk,
631 .enable = exynos5_clk_ip_peric_ctrl,
632 .ctrlbit = (1 << 14),
633 }
634};
635
636static struct clk exynos5_init_clocks_on[] = {
637 {
638 .name = "uart",
639 .devname = "s5pv210-uart.0",
640 .enable = exynos5_clk_ip_peric_ctrl,
641 .ctrlbit = (1 << 0),
642 }, {
643 .name = "uart",
644 .devname = "s5pv210-uart.1",
645 .enable = exynos5_clk_ip_peric_ctrl,
646 .ctrlbit = (1 << 1),
647 }, {
648 .name = "uart",
649 .devname = "s5pv210-uart.2",
650 .enable = exynos5_clk_ip_peric_ctrl,
651 .ctrlbit = (1 << 2),
652 }, {
653 .name = "uart",
654 .devname = "s5pv210-uart.3",
655 .enable = exynos5_clk_ip_peric_ctrl,
656 .ctrlbit = (1 << 3),
657 }, {
658 .name = "uart",
659 .devname = "s5pv210-uart.4",
660 .enable = exynos5_clk_ip_peric_ctrl,
661 .ctrlbit = (1 << 4),
662 }, {
663 .name = "uart",
664 .devname = "s5pv210-uart.5",
665 .enable = exynos5_clk_ip_peric_ctrl,
666 .ctrlbit = (1 << 5),
667 }
668};
669
670static struct clk exynos5_clk_pdma0 = {
671 .name = "dma",
672 .devname = "dma-pl330.0",
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 1),
675};
676
677static struct clk exynos5_clk_pdma1 = {
678 .name = "dma",
679 .devname = "dma-pl330.1",
680 .enable = exynos5_clk_ip_fsys_ctrl,
681 .ctrlbit = (1 << 1),
682};
683
684static struct clk exynos5_clk_mdma1 = {
685 .name = "dma",
686 .devname = "dma-pl330.2",
687 .enable = exynos5_clk_ip_gen_ctrl,
688 .ctrlbit = (1 << 4),
689};
690
691struct clk *exynos5_clkset_group_list[] = {
692 [0] = &clk_ext_xtal_mux,
693 [1] = NULL,
694 [2] = &exynos5_clk_sclk_hdmi24m,
695 [3] = &exynos5_clk_sclk_dptxphy,
696 [4] = &exynos5_clk_sclk_usbphy,
697 [5] = &exynos5_clk_sclk_hdmiphy,
698 [6] = &exynos5_clk_mout_mpll_user.clk,
699 [7] = &exynos5_clk_mout_epll.clk,
700 [8] = &exynos5_clk_sclk_vpll.clk,
701 [9] = &exynos5_clk_mout_cpll.clk,
702};
703
704struct clksrc_sources exynos5_clkset_group = {
705 .sources = exynos5_clkset_group_list,
706 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
707};
708
709/* Possible clock sources for aclk_266_gscl_sub Mux */
710static struct clk *clk_src_gscl_266_list[] = {
711 [0] = &clk_ext_xtal_mux,
712 [1] = &exynos5_clk_aclk_266.clk,
713};
714
715static struct clksrc_sources clk_src_gscl_266 = {
716 .sources = clk_src_gscl_266_list,
717 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
718};
719
720static struct clksrc_clk exynos5_clk_dout_mmc0 = {
721 .clk = {
722 .name = "dout_mmc0",
723 },
724 .sources = &exynos5_clkset_group,
725 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
726 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
727};
728
729static struct clksrc_clk exynos5_clk_dout_mmc1 = {
730 .clk = {
731 .name = "dout_mmc1",
732 },
733 .sources = &exynos5_clkset_group,
734 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
735 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
736};
737
738static struct clksrc_clk exynos5_clk_dout_mmc2 = {
739 .clk = {
740 .name = "dout_mmc2",
741 },
742 .sources = &exynos5_clkset_group,
743 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
744 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
745};
746
747static struct clksrc_clk exynos5_clk_dout_mmc3 = {
748 .clk = {
749 .name = "dout_mmc3",
750 },
751 .sources = &exynos5_clkset_group,
752 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
753 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
754};
755
756static struct clksrc_clk exynos5_clk_dout_mmc4 = {
757 .clk = {
758 .name = "dout_mmc4",
759 },
760 .sources = &exynos5_clkset_group,
761 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
762 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
763};
764
765static struct clksrc_clk exynos5_clk_sclk_uart0 = {
766 .clk = {
767 .name = "uclk1",
768 .devname = "exynos4210-uart.0",
769 .enable = exynos5_clksrc_mask_peric0_ctrl,
770 .ctrlbit = (1 << 0),
771 },
772 .sources = &exynos5_clkset_group,
773 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
774 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
775};
776
777static struct clksrc_clk exynos5_clk_sclk_uart1 = {
778 .clk = {
779 .name = "uclk1",
780 .devname = "exynos4210-uart.1",
781 .enable = exynos5_clksrc_mask_peric0_ctrl,
782 .ctrlbit = (1 << 4),
783 },
784 .sources = &exynos5_clkset_group,
785 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
786 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
787};
788
789static struct clksrc_clk exynos5_clk_sclk_uart2 = {
790 .clk = {
791 .name = "uclk1",
792 .devname = "exynos4210-uart.2",
793 .enable = exynos5_clksrc_mask_peric0_ctrl,
794 .ctrlbit = (1 << 8),
795 },
796 .sources = &exynos5_clkset_group,
797 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
798 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
799};
800
801static struct clksrc_clk exynos5_clk_sclk_uart3 = {
802 .clk = {
803 .name = "uclk1",
804 .devname = "exynos4210-uart.3",
805 .enable = exynos5_clksrc_mask_peric0_ctrl,
806 .ctrlbit = (1 << 12),
807 },
808 .sources = &exynos5_clkset_group,
809 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
810 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
811};
812
813static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
814 .clk = {
815 .name = "sclk_mmc",
816 .devname = "s3c-sdhci.0",
817 .parent = &exynos5_clk_dout_mmc0.clk,
818 .enable = exynos5_clksrc_mask_fsys_ctrl,
819 .ctrlbit = (1 << 0),
820 },
821 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
822};
823
824static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
825 .clk = {
826 .name = "sclk_mmc",
827 .devname = "s3c-sdhci.1",
828 .parent = &exynos5_clk_dout_mmc1.clk,
829 .enable = exynos5_clksrc_mask_fsys_ctrl,
830 .ctrlbit = (1 << 4),
831 },
832 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
833};
834
835static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
836 .clk = {
837 .name = "sclk_mmc",
838 .devname = "s3c-sdhci.2",
839 .parent = &exynos5_clk_dout_mmc2.clk,
840 .enable = exynos5_clksrc_mask_fsys_ctrl,
841 .ctrlbit = (1 << 8),
842 },
843 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
844};
845
846static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
847 .clk = {
848 .name = "sclk_mmc",
849 .devname = "s3c-sdhci.3",
850 .parent = &exynos5_clk_dout_mmc3.clk,
851 .enable = exynos5_clksrc_mask_fsys_ctrl,
852 .ctrlbit = (1 << 12),
853 },
854 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
855};
856
857static struct clksrc_clk exynos5_clksrcs[] = {
858 {
859 .clk = {
860 .name = "sclk_dwmci",
861 .parent = &exynos5_clk_dout_mmc4.clk,
862 .enable = exynos5_clksrc_mask_fsys_ctrl,
863 .ctrlbit = (1 << 16),
864 },
865 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
866 }, {
867 .clk = {
868 .name = "sclk_fimd",
869 .devname = "s3cfb.1",
870 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
871 .ctrlbit = (1 << 0),
872 },
873 .sources = &exynos5_clkset_group,
874 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
875 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
876 }, {
877 .clk = {
878 .name = "aclk_266_gscl",
879 },
880 .sources = &clk_src_gscl_266,
881 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
882 }, {
883 .clk = {
884 .name = "sclk_g3d",
885 .devname = "mali-t604.0",
886 .enable = exynos5_clk_block_ctrl,
887 .ctrlbit = (1 << 1),
888 },
889 .sources = &exynos5_clkset_aclk,
890 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
891 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
892 }, {
893 .clk = {
894 .name = "sclk_gscl_wrap",
895 .devname = "s5p-mipi-csis.0",
896 .enable = exynos5_clksrc_mask_gscl_ctrl,
897 .ctrlbit = (1 << 24),
898 },
899 .sources = &exynos5_clkset_group,
900 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
901 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
902 }, {
903 .clk = {
904 .name = "sclk_gscl_wrap",
905 .devname = "s5p-mipi-csis.1",
906 .enable = exynos5_clksrc_mask_gscl_ctrl,
907 .ctrlbit = (1 << 28),
908 },
909 .sources = &exynos5_clkset_group,
910 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
911 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
912 }, {
913 .clk = {
914 .name = "sclk_cam0",
915 .enable = exynos5_clksrc_mask_gscl_ctrl,
916 .ctrlbit = (1 << 16),
917 },
918 .sources = &exynos5_clkset_group,
919 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
920 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
921 }, {
922 .clk = {
923 .name = "sclk_cam1",
924 .enable = exynos5_clksrc_mask_gscl_ctrl,
925 .ctrlbit = (1 << 20),
926 },
927 .sources = &exynos5_clkset_group,
928 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
929 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
930 }, {
931 .clk = {
932 .name = "sclk_jpeg",
933 .parent = &exynos5_clk_mout_cpll.clk,
934 },
935 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
936 },
937};
938
939/* Clock initialization code */
940static struct clksrc_clk *exynos5_sysclks[] = {
941 &exynos5_clk_mout_apll,
942 &exynos5_clk_sclk_apll,
943 &exynos5_clk_mout_bpll,
944 &exynos5_clk_mout_bpll_user,
945 &exynos5_clk_mout_cpll,
946 &exynos5_clk_mout_epll,
947 &exynos5_clk_mout_mpll,
948 &exynos5_clk_mout_mpll_user,
949 &exynos5_clk_vpllsrc,
950 &exynos5_clk_sclk_vpll,
951 &exynos5_clk_mout_cpu,
952 &exynos5_clk_dout_armclk,
953 &exynos5_clk_dout_arm2clk,
954 &exynos5_clk_cdrex,
955 &exynos5_clk_aclk_400,
956 &exynos5_clk_aclk_333,
957 &exynos5_clk_aclk_266,
958 &exynos5_clk_aclk_200,
959 &exynos5_clk_aclk_166,
960 &exynos5_clk_aclk_66_pre,
961 &exynos5_clk_aclk_66,
962 &exynos5_clk_dout_mmc0,
963 &exynos5_clk_dout_mmc1,
964 &exynos5_clk_dout_mmc2,
965 &exynos5_clk_dout_mmc3,
966 &exynos5_clk_dout_mmc4,
967 &exynos5_clk_aclk_acp,
968 &exynos5_clk_pclk_acp,
969};
970
971static struct clk *exynos5_clk_cdev[] = {
972 &exynos5_clk_pdma0,
973 &exynos5_clk_pdma1,
974 &exynos5_clk_mdma1,
975};
976
977static struct clksrc_clk *exynos5_clksrc_cdev[] = {
978 &exynos5_clk_sclk_uart0,
979 &exynos5_clk_sclk_uart1,
980 &exynos5_clk_sclk_uart2,
981 &exynos5_clk_sclk_uart3,
982 &exynos5_clk_sclk_mmc0,
983 &exynos5_clk_sclk_mmc1,
984 &exynos5_clk_sclk_mmc2,
985 &exynos5_clk_sclk_mmc3,
986};
987
988static struct clk_lookup exynos5_clk_lookup[] = {
989 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
990 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
991 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
992 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
993 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
994 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
995 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
996 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
997 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
998 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
999 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1000};
1001
1002static unsigned long exynos5_epll_get_rate(struct clk *clk)
1003{
1004 return clk->rate;
1005}
1006
1007static struct clk *exynos5_clks[] __initdata = {
1008 &exynos5_clk_sclk_hdmi27m,
1009 &exynos5_clk_sclk_hdmiphy,
1010 &clk_fout_bpll,
1011 &clk_fout_cpll,
1012 &exynos5_clk_armclk,
1013};
1014
1015static u32 epll_div[][6] = {
1016 { 192000000, 0, 48, 3, 1, 0 },
1017 { 180000000, 0, 45, 3, 1, 0 },
1018 { 73728000, 1, 73, 3, 3, 47710 },
1019 { 67737600, 1, 90, 4, 3, 20762 },
1020 { 49152000, 0, 49, 3, 3, 9961 },
1021 { 45158400, 0, 45, 3, 3, 10381 },
1022 { 180633600, 0, 45, 3, 1, 10381 },
1023};
1024
1025static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1026{
1027 unsigned int epll_con, epll_con_k;
1028 unsigned int i;
1029 unsigned int tmp;
1030 unsigned int epll_rate;
1031 unsigned int locktime;
1032 unsigned int lockcnt;
1033
1034 /* Return if nothing changed */
1035 if (clk->rate == rate)
1036 return 0;
1037
1038 if (clk->parent)
1039 epll_rate = clk_get_rate(clk->parent);
1040 else
1041 epll_rate = clk_ext_xtal_mux.rate;
1042
1043 if (epll_rate != 24000000) {
1044 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1045 return -EINVAL;
1046 }
1047
1048 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1049 epll_con &= ~(0x1 << 27 | \
1050 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1051 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1052 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1053
1054 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1055 if (epll_div[i][0] == rate) {
1056 epll_con_k = epll_div[i][5] << 0;
1057 epll_con |= epll_div[i][1] << 27;
1058 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1059 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1060 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1061 break;
1062 }
1063 }
1064
1065 if (i == ARRAY_SIZE(epll_div)) {
1066 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1067 __func__);
1068 return -EINVAL;
1069 }
1070
1071 epll_rate /= 1000000;
1072
1073 /* 3000 max_cycls : specification data */
1074 locktime = 3000 / epll_rate * epll_div[i][3];
1075 lockcnt = locktime * 10000 / (10000 / epll_rate);
1076
1077 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1078
1079 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1080 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1081
1082 do {
1083 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1084 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1085
1086 clk->rate = rate;
1087
1088 return 0;
1089}
1090
1091static struct clk_ops exynos5_epll_ops = {
1092 .get_rate = exynos5_epll_get_rate,
1093 .set_rate = exynos5_epll_set_rate,
1094};
1095
1096static int xtal_rate;
1097
1098static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1099{
1100 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1101}
1102
1103static struct clk_ops exynos5_fout_apll_ops = {
1104 .get_rate = exynos5_fout_apll_get_rate,
1105};
1106
1107#ifdef CONFIG_PM
1108static int exynos5_clock_suspend(void)
1109{
1110 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1111
1112 return 0;
1113}
1114
1115static void exynos5_clock_resume(void)
1116{
1117 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1118}
1119#else
1120#define exynos5_clock_suspend NULL
1121#define exynos5_clock_resume NULL
1122#endif
1123
1124struct syscore_ops exynos5_clock_syscore_ops = {
1125 .suspend = exynos5_clock_suspend,
1126 .resume = exynos5_clock_resume,
1127};
1128
1129void __init_or_cpufreq exynos5_setup_clocks(void)
1130{
1131 struct clk *xtal_clk;
1132 unsigned long apll;
1133 unsigned long bpll;
1134 unsigned long cpll;
1135 unsigned long mpll;
1136 unsigned long epll;
1137 unsigned long vpll;
1138 unsigned long vpllsrc;
1139 unsigned long xtal;
1140 unsigned long armclk;
1141 unsigned long mout_cdrex;
1142 unsigned long aclk_400;
1143 unsigned long aclk_333;
1144 unsigned long aclk_266;
1145 unsigned long aclk_200;
1146 unsigned long aclk_166;
1147 unsigned long aclk_66;
1148 unsigned int ptr;
1149
1150 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1151
1152 xtal_clk = clk_get(NULL, "xtal");
1153 BUG_ON(IS_ERR(xtal_clk));
1154
1155 xtal = clk_get_rate(xtal_clk);
1156
1157 xtal_rate = xtal;
1158
1159 clk_put(xtal_clk);
1160
1161 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1162
1163 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1164 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1165 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1166 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1167 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1168 __raw_readl(EXYNOS5_EPLL_CON1));
1169
1170 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1171 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1172 __raw_readl(EXYNOS5_VPLL_CON1));
1173
1174 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1175 clk_fout_bpll.rate = bpll;
1176 clk_fout_cpll.rate = cpll;
1177 clk_fout_mpll.rate = mpll;
1178 clk_fout_epll.rate = epll;
1179 clk_fout_vpll.rate = vpll;
1180
1181 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1182 "M=%ld, E=%ld V=%ld",
1183 apll, bpll, cpll, mpll, epll, vpll);
1184
1185 armclk = clk_get_rate(&exynos5_clk_armclk);
1186 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1187
1188 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1189 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1190 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1191 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1192 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1193 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1194
1195 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1196 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1197 "ACLK166=%ld, ACLK66=%ld\n",
1198 armclk, mout_cdrex, aclk_400,
1199 aclk_333, aclk_266, aclk_200,
1200 aclk_166, aclk_66);
1201
1202
1203 clk_fout_epll.ops = &exynos5_epll_ops;
1204
1205 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1206 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1207 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1208
1209 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1210 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1211
1212 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1213 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1214
1215 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1216 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1217}
1218
1219void __init exynos5_register_clocks(void)
1220{
1221 int ptr;
1222
1223 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1224
1225 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1226 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1227
1228 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1229 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1230
1231 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1232 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1233
1234 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1235 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1236
1237 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1238 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1239 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1240
1241 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1242 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1243 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1244
1245 register_syscore_ops(&exynos5_clock_syscore_ops);
1246 s3c_pwmclk_init();
1247}
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644
index 5a8c42e90005..000000000000
--- a/arch/arm/mach-exynos/clock.c
+++ /dev/null
@@ -1,1562 +0,0 @@
1/* linux/arch/arm/mach-exynos4/clock.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/pm.h>
25
26#include <mach/map.h>
27#include <mach/regs-clock.h>
28#include <mach/sysmmu.h>
29#include <mach/exynos4-clock.h>
30
31#include "common.h"
32
33static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(S5P_CLKSRC_TOP0),
39 SAVE_ITEM(S5P_CLKSRC_TOP1),
40 SAVE_ITEM(S5P_CLKSRC_CAM),
41 SAVE_ITEM(S5P_CLKSRC_TV),
42 SAVE_ITEM(S5P_CLKSRC_MFC),
43 SAVE_ITEM(S5P_CLKSRC_G3D),
44 SAVE_ITEM(S5P_CLKSRC_LCD0),
45 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
46 SAVE_ITEM(S5P_CLKSRC_FSYS),
47 SAVE_ITEM(S5P_CLKSRC_PERIL0),
48 SAVE_ITEM(S5P_CLKSRC_PERIL1),
49 SAVE_ITEM(S5P_CLKDIV_CAM),
50 SAVE_ITEM(S5P_CLKDIV_TV),
51 SAVE_ITEM(S5P_CLKDIV_MFC),
52 SAVE_ITEM(S5P_CLKDIV_G3D),
53 SAVE_ITEM(S5P_CLKDIV_LCD0),
54 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
55 SAVE_ITEM(S5P_CLKDIV_FSYS0),
56 SAVE_ITEM(S5P_CLKDIV_FSYS1),
57 SAVE_ITEM(S5P_CLKDIV_FSYS2),
58 SAVE_ITEM(S5P_CLKDIV_FSYS3),
59 SAVE_ITEM(S5P_CLKDIV_PERIL0),
60 SAVE_ITEM(S5P_CLKDIV_PERIL1),
61 SAVE_ITEM(S5P_CLKDIV_PERIL2),
62 SAVE_ITEM(S5P_CLKDIV_PERIL3),
63 SAVE_ITEM(S5P_CLKDIV_PERIL4),
64 SAVE_ITEM(S5P_CLKDIV_PERIL5),
65 SAVE_ITEM(S5P_CLKDIV_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
67 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
68 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
69 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(S5P_CLKDIV2_RATIO),
75 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
77 SAVE_ITEM(S5P_CLKGATE_IP_TV),
78 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
79 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
80 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
81 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
82 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
83 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
84 SAVE_ITEM(S5P_CLKGATE_BLOCK),
85 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
86 SAVE_ITEM(S5P_CLKSRC_DMC),
87 SAVE_ITEM(S5P_CLKDIV_DMC0),
88 SAVE_ITEM(S5P_CLKDIV_DMC1),
89 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
90 SAVE_ITEM(S5P_CLKSRC_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU),
92 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
94 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
95};
96
97struct clk clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m",
99 .rate = 27000000,
100};
101
102struct clk clk_sclk_hdmiphy = {
103 .name = "sclk_hdmiphy",
104};
105
106struct clk clk_sclk_usbphy0 = {
107 .name = "sclk_usbphy0",
108 .rate = 27000000,
109};
110
111struct clk clk_sclk_usbphy1 = {
112 .name = "sclk_usbphy1",
113};
114
115static struct clk dummy_apb_pclk = {
116 .name = "apb_pclk",
117 .id = -1,
118};
119
120static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
123}
124
125static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
128}
129
130static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
131{
132 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
133}
134
135int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
138}
139
140static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
143}
144
145static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
148}
149
150static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
151{
152 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
153}
154
155static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
156{
157 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
158}
159
160static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
161{
162 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
163}
164
165static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
166{
167 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
168}
169
170static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
171{
172 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
173}
174
175static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
176{
177 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
178}
179
180int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
181{
182 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
183}
184
185int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
186{
187 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
188}
189
190static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
191{
192 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
193}
194
195static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
198}
199
200static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
203}
204
205static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
206{
207 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
208}
209
210/* Core list of CMU_CPU side */
211
212static struct clksrc_clk clk_mout_apll = {
213 .clk = {
214 .name = "mout_apll",
215 },
216 .sources = &clk_src_apll,
217 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
218};
219
220struct clksrc_clk clk_sclk_apll = {
221 .clk = {
222 .name = "sclk_apll",
223 .parent = &clk_mout_apll.clk,
224 },
225 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
226};
227
228struct clksrc_clk clk_mout_epll = {
229 .clk = {
230 .name = "mout_epll",
231 },
232 .sources = &clk_src_epll,
233 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
234};
235
236struct clksrc_clk clk_mout_mpll = {
237 .clk = {
238 .name = "mout_mpll",
239 },
240 .sources = &clk_src_mpll,
241
242 /* reg_src will be added in each SoCs' clock */
243};
244
245static struct clk *clkset_moutcore_list[] = {
246 [0] = &clk_mout_apll.clk,
247 [1] = &clk_mout_mpll.clk,
248};
249
250static struct clksrc_sources clkset_moutcore = {
251 .sources = clkset_moutcore_list,
252 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
253};
254
255static struct clksrc_clk clk_moutcore = {
256 .clk = {
257 .name = "moutcore",
258 },
259 .sources = &clkset_moutcore,
260 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
261};
262
263static struct clksrc_clk clk_coreclk = {
264 .clk = {
265 .name = "core_clk",
266 .parent = &clk_moutcore.clk,
267 },
268 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
269};
270
271static struct clksrc_clk clk_armclk = {
272 .clk = {
273 .name = "armclk",
274 .parent = &clk_coreclk.clk,
275 },
276};
277
278static struct clksrc_clk clk_aclk_corem0 = {
279 .clk = {
280 .name = "aclk_corem0",
281 .parent = &clk_coreclk.clk,
282 },
283 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
284};
285
286static struct clksrc_clk clk_aclk_cores = {
287 .clk = {
288 .name = "aclk_cores",
289 .parent = &clk_coreclk.clk,
290 },
291 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
292};
293
294static struct clksrc_clk clk_aclk_corem1 = {
295 .clk = {
296 .name = "aclk_corem1",
297 .parent = &clk_coreclk.clk,
298 },
299 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
300};
301
302static struct clksrc_clk clk_periphclk = {
303 .clk = {
304 .name = "periphclk",
305 .parent = &clk_coreclk.clk,
306 },
307 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
308};
309
310/* Core list of CMU_CORE side */
311
312struct clk *clkset_corebus_list[] = {
313 [0] = &clk_mout_mpll.clk,
314 [1] = &clk_sclk_apll.clk,
315};
316
317struct clksrc_sources clkset_mout_corebus = {
318 .sources = clkset_corebus_list,
319 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
320};
321
322static struct clksrc_clk clk_mout_corebus = {
323 .clk = {
324 .name = "mout_corebus",
325 },
326 .sources = &clkset_mout_corebus,
327 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
328};
329
330static struct clksrc_clk clk_sclk_dmc = {
331 .clk = {
332 .name = "sclk_dmc",
333 .parent = &clk_mout_corebus.clk,
334 },
335 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
336};
337
338static struct clksrc_clk clk_aclk_cored = {
339 .clk = {
340 .name = "aclk_cored",
341 .parent = &clk_sclk_dmc.clk,
342 },
343 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
344};
345
346static struct clksrc_clk clk_aclk_corep = {
347 .clk = {
348 .name = "aclk_corep",
349 .parent = &clk_aclk_cored.clk,
350 },
351 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
352};
353
354static struct clksrc_clk clk_aclk_acp = {
355 .clk = {
356 .name = "aclk_acp",
357 .parent = &clk_mout_corebus.clk,
358 },
359 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
360};
361
362static struct clksrc_clk clk_pclk_acp = {
363 .clk = {
364 .name = "pclk_acp",
365 .parent = &clk_aclk_acp.clk,
366 },
367 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
368};
369
370/* Core list of CMU_TOP side */
371
372struct clk *clkset_aclk_top_list[] = {
373 [0] = &clk_mout_mpll.clk,
374 [1] = &clk_sclk_apll.clk,
375};
376
377struct clksrc_sources clkset_aclk = {
378 .sources = clkset_aclk_top_list,
379 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
380};
381
382static struct clksrc_clk clk_aclk_200 = {
383 .clk = {
384 .name = "aclk_200",
385 },
386 .sources = &clkset_aclk,
387 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
388 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
389};
390
391static struct clksrc_clk clk_aclk_100 = {
392 .clk = {
393 .name = "aclk_100",
394 },
395 .sources = &clkset_aclk,
396 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
397 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
398};
399
400static struct clksrc_clk clk_aclk_160 = {
401 .clk = {
402 .name = "aclk_160",
403 },
404 .sources = &clkset_aclk,
405 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
406 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
407};
408
409struct clksrc_clk clk_aclk_133 = {
410 .clk = {
411 .name = "aclk_133",
412 },
413 .sources = &clkset_aclk,
414 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
415 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
416};
417
418static struct clk *clkset_vpllsrc_list[] = {
419 [0] = &clk_fin_vpll,
420 [1] = &clk_sclk_hdmi27m,
421};
422
423static struct clksrc_sources clkset_vpllsrc = {
424 .sources = clkset_vpllsrc_list,
425 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
426};
427
428static struct clksrc_clk clk_vpllsrc = {
429 .clk = {
430 .name = "vpll_src",
431 .enable = exynos4_clksrc_mask_top_ctrl,
432 .ctrlbit = (1 << 0),
433 },
434 .sources = &clkset_vpllsrc,
435 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
436};
437
438static struct clk *clkset_sclk_vpll_list[] = {
439 [0] = &clk_vpllsrc.clk,
440 [1] = &clk_fout_vpll,
441};
442
443static struct clksrc_sources clkset_sclk_vpll = {
444 .sources = clkset_sclk_vpll_list,
445 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
446};
447
448struct clksrc_clk clk_sclk_vpll = {
449 .clk = {
450 .name = "sclk_vpll",
451 },
452 .sources = &clkset_sclk_vpll,
453 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
454};
455
456static struct clk init_clocks_off[] = {
457 {
458 .name = "timers",
459 .parent = &clk_aclk_100.clk,
460 .enable = exynos4_clk_ip_peril_ctrl,
461 .ctrlbit = (1<<24),
462 }, {
463 .name = "csis",
464 .devname = "s5p-mipi-csis.0",
465 .enable = exynos4_clk_ip_cam_ctrl,
466 .ctrlbit = (1 << 4),
467 }, {
468 .name = "csis",
469 .devname = "s5p-mipi-csis.1",
470 .enable = exynos4_clk_ip_cam_ctrl,
471 .ctrlbit = (1 << 5),
472 }, {
473 .name = "fimc",
474 .devname = "exynos4-fimc.0",
475 .enable = exynos4_clk_ip_cam_ctrl,
476 .ctrlbit = (1 << 0),
477 }, {
478 .name = "fimc",
479 .devname = "exynos4-fimc.1",
480 .enable = exynos4_clk_ip_cam_ctrl,
481 .ctrlbit = (1 << 1),
482 }, {
483 .name = "fimc",
484 .devname = "exynos4-fimc.2",
485 .enable = exynos4_clk_ip_cam_ctrl,
486 .ctrlbit = (1 << 2),
487 }, {
488 .name = "fimc",
489 .devname = "exynos4-fimc.3",
490 .enable = exynos4_clk_ip_cam_ctrl,
491 .ctrlbit = (1 << 3),
492 }, {
493 .name = "fimd",
494 .devname = "exynos4-fb.0",
495 .enable = exynos4_clk_ip_lcd0_ctrl,
496 .ctrlbit = (1 << 0),
497 }, {
498 .name = "hsmmc",
499 .devname = "s3c-sdhci.0",
500 .parent = &clk_aclk_133.clk,
501 .enable = exynos4_clk_ip_fsys_ctrl,
502 .ctrlbit = (1 << 5),
503 }, {
504 .name = "hsmmc",
505 .devname = "s3c-sdhci.1",
506 .parent = &clk_aclk_133.clk,
507 .enable = exynos4_clk_ip_fsys_ctrl,
508 .ctrlbit = (1 << 6),
509 }, {
510 .name = "hsmmc",
511 .devname = "s3c-sdhci.2",
512 .parent = &clk_aclk_133.clk,
513 .enable = exynos4_clk_ip_fsys_ctrl,
514 .ctrlbit = (1 << 7),
515 }, {
516 .name = "hsmmc",
517 .devname = "s3c-sdhci.3",
518 .parent = &clk_aclk_133.clk,
519 .enable = exynos4_clk_ip_fsys_ctrl,
520 .ctrlbit = (1 << 8),
521 }, {
522 .name = "dwmmc",
523 .parent = &clk_aclk_133.clk,
524 .enable = exynos4_clk_ip_fsys_ctrl,
525 .ctrlbit = (1 << 9),
526 }, {
527 .name = "dac",
528 .devname = "s5p-sdo",
529 .enable = exynos4_clk_ip_tv_ctrl,
530 .ctrlbit = (1 << 2),
531 }, {
532 .name = "mixer",
533 .devname = "s5p-mixer",
534 .enable = exynos4_clk_ip_tv_ctrl,
535 .ctrlbit = (1 << 1),
536 }, {
537 .name = "vp",
538 .devname = "s5p-mixer",
539 .enable = exynos4_clk_ip_tv_ctrl,
540 .ctrlbit = (1 << 0),
541 }, {
542 .name = "hdmi",
543 .devname = "exynos4-hdmi",
544 .enable = exynos4_clk_ip_tv_ctrl,
545 .ctrlbit = (1 << 3),
546 }, {
547 .name = "hdmiphy",
548 .devname = "exynos4-hdmi",
549 .enable = exynos4_clk_hdmiphy_ctrl,
550 .ctrlbit = (1 << 0),
551 }, {
552 .name = "dacphy",
553 .devname = "s5p-sdo",
554 .enable = exynos4_clk_dac_ctrl,
555 .ctrlbit = (1 << 0),
556 }, {
557 .name = "adc",
558 .enable = exynos4_clk_ip_peril_ctrl,
559 .ctrlbit = (1 << 15),
560 }, {
561 .name = "keypad",
562 .enable = exynos4_clk_ip_perir_ctrl,
563 .ctrlbit = (1 << 16),
564 }, {
565 .name = "rtc",
566 .enable = exynos4_clk_ip_perir_ctrl,
567 .ctrlbit = (1 << 15),
568 }, {
569 .name = "watchdog",
570 .parent = &clk_aclk_100.clk,
571 .enable = exynos4_clk_ip_perir_ctrl,
572 .ctrlbit = (1 << 14),
573 }, {
574 .name = "usbhost",
575 .enable = exynos4_clk_ip_fsys_ctrl ,
576 .ctrlbit = (1 << 12),
577 }, {
578 .name = "otg",
579 .enable = exynos4_clk_ip_fsys_ctrl,
580 .ctrlbit = (1 << 13),
581 }, {
582 .name = "spi",
583 .devname = "s3c64xx-spi.0",
584 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 16),
586 }, {
587 .name = "spi",
588 .devname = "s3c64xx-spi.1",
589 .enable = exynos4_clk_ip_peril_ctrl,
590 .ctrlbit = (1 << 17),
591 }, {
592 .name = "spi",
593 .devname = "s3c64xx-spi.2",
594 .enable = exynos4_clk_ip_peril_ctrl,
595 .ctrlbit = (1 << 18),
596 }, {
597 .name = "iis",
598 .devname = "samsung-i2s.0",
599 .enable = exynos4_clk_ip_peril_ctrl,
600 .ctrlbit = (1 << 19),
601 }, {
602 .name = "iis",
603 .devname = "samsung-i2s.1",
604 .enable = exynos4_clk_ip_peril_ctrl,
605 .ctrlbit = (1 << 20),
606 }, {
607 .name = "iis",
608 .devname = "samsung-i2s.2",
609 .enable = exynos4_clk_ip_peril_ctrl,
610 .ctrlbit = (1 << 21),
611 }, {
612 .name = "ac97",
613 .devname = "samsung-ac97",
614 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 27),
616 }, {
617 .name = "fimg2d",
618 .enable = exynos4_clk_ip_image_ctrl,
619 .ctrlbit = (1 << 0),
620 }, {
621 .name = "mfc",
622 .devname = "s5p-mfc",
623 .enable = exynos4_clk_ip_mfc_ctrl,
624 .ctrlbit = (1 << 0),
625 }, {
626 .name = "i2c",
627 .devname = "s3c2440-i2c.0",
628 .parent = &clk_aclk_100.clk,
629 .enable = exynos4_clk_ip_peril_ctrl,
630 .ctrlbit = (1 << 6),
631 }, {
632 .name = "i2c",
633 .devname = "s3c2440-i2c.1",
634 .parent = &clk_aclk_100.clk,
635 .enable = exynos4_clk_ip_peril_ctrl,
636 .ctrlbit = (1 << 7),
637 }, {
638 .name = "i2c",
639 .devname = "s3c2440-i2c.2",
640 .parent = &clk_aclk_100.clk,
641 .enable = exynos4_clk_ip_peril_ctrl,
642 .ctrlbit = (1 << 8),
643 }, {
644 .name = "i2c",
645 .devname = "s3c2440-i2c.3",
646 .parent = &clk_aclk_100.clk,
647 .enable = exynos4_clk_ip_peril_ctrl,
648 .ctrlbit = (1 << 9),
649 }, {
650 .name = "i2c",
651 .devname = "s3c2440-i2c.4",
652 .parent = &clk_aclk_100.clk,
653 .enable = exynos4_clk_ip_peril_ctrl,
654 .ctrlbit = (1 << 10),
655 }, {
656 .name = "i2c",
657 .devname = "s3c2440-i2c.5",
658 .parent = &clk_aclk_100.clk,
659 .enable = exynos4_clk_ip_peril_ctrl,
660 .ctrlbit = (1 << 11),
661 }, {
662 .name = "i2c",
663 .devname = "s3c2440-i2c.6",
664 .parent = &clk_aclk_100.clk,
665 .enable = exynos4_clk_ip_peril_ctrl,
666 .ctrlbit = (1 << 12),
667 }, {
668 .name = "i2c",
669 .devname = "s3c2440-i2c.7",
670 .parent = &clk_aclk_100.clk,
671 .enable = exynos4_clk_ip_peril_ctrl,
672 .ctrlbit = (1 << 13),
673 }, {
674 .name = "i2c",
675 .devname = "s3c2440-hdmiphy-i2c",
676 .parent = &clk_aclk_100.clk,
677 .enable = exynos4_clk_ip_peril_ctrl,
678 .ctrlbit = (1 << 14),
679 }, {
680 .name = "SYSMMU_MDMA",
681 .enable = exynos4_clk_ip_image_ctrl,
682 .ctrlbit = (1 << 5),
683 }, {
684 .name = "SYSMMU_FIMC0",
685 .enable = exynos4_clk_ip_cam_ctrl,
686 .ctrlbit = (1 << 7),
687 }, {
688 .name = "SYSMMU_FIMC1",
689 .enable = exynos4_clk_ip_cam_ctrl,
690 .ctrlbit = (1 << 8),
691 }, {
692 .name = "SYSMMU_FIMC2",
693 .enable = exynos4_clk_ip_cam_ctrl,
694 .ctrlbit = (1 << 9),
695 }, {
696 .name = "SYSMMU_FIMC3",
697 .enable = exynos4_clk_ip_cam_ctrl,
698 .ctrlbit = (1 << 10),
699 }, {
700 .name = "SYSMMU_JPEG",
701 .enable = exynos4_clk_ip_cam_ctrl,
702 .ctrlbit = (1 << 11),
703 }, {
704 .name = "SYSMMU_FIMD0",
705 .enable = exynos4_clk_ip_lcd0_ctrl,
706 .ctrlbit = (1 << 4),
707 }, {
708 .name = "SYSMMU_FIMD1",
709 .enable = exynos4_clk_ip_lcd1_ctrl,
710 .ctrlbit = (1 << 4),
711 }, {
712 .name = "SYSMMU_PCIe",
713 .enable = exynos4_clk_ip_fsys_ctrl,
714 .ctrlbit = (1 << 18),
715 }, {
716 .name = "SYSMMU_G2D",
717 .enable = exynos4_clk_ip_image_ctrl,
718 .ctrlbit = (1 << 3),
719 }, {
720 .name = "SYSMMU_ROTATOR",
721 .enable = exynos4_clk_ip_image_ctrl,
722 .ctrlbit = (1 << 4),
723 }, {
724 .name = "SYSMMU_TV",
725 .enable = exynos4_clk_ip_tv_ctrl,
726 .ctrlbit = (1 << 4),
727 }, {
728 .name = "SYSMMU_MFC_L",
729 .enable = exynos4_clk_ip_mfc_ctrl,
730 .ctrlbit = (1 << 1),
731 }, {
732 .name = "SYSMMU_MFC_R",
733 .enable = exynos4_clk_ip_mfc_ctrl,
734 .ctrlbit = (1 << 2),
735 }
736};
737
738static struct clk init_clocks[] = {
739 {
740 .name = "uart",
741 .devname = "s5pv210-uart.0",
742 .enable = exynos4_clk_ip_peril_ctrl,
743 .ctrlbit = (1 << 0),
744 }, {
745 .name = "uart",
746 .devname = "s5pv210-uart.1",
747 .enable = exynos4_clk_ip_peril_ctrl,
748 .ctrlbit = (1 << 1),
749 }, {
750 .name = "uart",
751 .devname = "s5pv210-uart.2",
752 .enable = exynos4_clk_ip_peril_ctrl,
753 .ctrlbit = (1 << 2),
754 }, {
755 .name = "uart",
756 .devname = "s5pv210-uart.3",
757 .enable = exynos4_clk_ip_peril_ctrl,
758 .ctrlbit = (1 << 3),
759 }, {
760 .name = "uart",
761 .devname = "s5pv210-uart.4",
762 .enable = exynos4_clk_ip_peril_ctrl,
763 .ctrlbit = (1 << 4),
764 }, {
765 .name = "uart",
766 .devname = "s5pv210-uart.5",
767 .enable = exynos4_clk_ip_peril_ctrl,
768 .ctrlbit = (1 << 5),
769 }
770};
771
772static struct clk clk_pdma0 = {
773 .name = "dma",
774 .devname = "dma-pl330.0",
775 .enable = exynos4_clk_ip_fsys_ctrl,
776 .ctrlbit = (1 << 0),
777};
778
779static struct clk clk_pdma1 = {
780 .name = "dma",
781 .devname = "dma-pl330.1",
782 .enable = exynos4_clk_ip_fsys_ctrl,
783 .ctrlbit = (1 << 1),
784};
785
786struct clk *clkset_group_list[] = {
787 [0] = &clk_ext_xtal_mux,
788 [1] = &clk_xusbxti,
789 [2] = &clk_sclk_hdmi27m,
790 [3] = &clk_sclk_usbphy0,
791 [4] = &clk_sclk_usbphy1,
792 [5] = &clk_sclk_hdmiphy,
793 [6] = &clk_mout_mpll.clk,
794 [7] = &clk_mout_epll.clk,
795 [8] = &clk_sclk_vpll.clk,
796};
797
798struct clksrc_sources clkset_group = {
799 .sources = clkset_group_list,
800 .nr_sources = ARRAY_SIZE(clkset_group_list),
801};
802
803static struct clk *clkset_mout_g2d0_list[] = {
804 [0] = &clk_mout_mpll.clk,
805 [1] = &clk_sclk_apll.clk,
806};
807
808static struct clksrc_sources clkset_mout_g2d0 = {
809 .sources = clkset_mout_g2d0_list,
810 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
811};
812
813static struct clksrc_clk clk_mout_g2d0 = {
814 .clk = {
815 .name = "mout_g2d0",
816 },
817 .sources = &clkset_mout_g2d0,
818 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
819};
820
821static struct clk *clkset_mout_g2d1_list[] = {
822 [0] = &clk_mout_epll.clk,
823 [1] = &clk_sclk_vpll.clk,
824};
825
826static struct clksrc_sources clkset_mout_g2d1 = {
827 .sources = clkset_mout_g2d1_list,
828 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
829};
830
831static struct clksrc_clk clk_mout_g2d1 = {
832 .clk = {
833 .name = "mout_g2d1",
834 },
835 .sources = &clkset_mout_g2d1,
836 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
837};
838
839static struct clk *clkset_mout_g2d_list[] = {
840 [0] = &clk_mout_g2d0.clk,
841 [1] = &clk_mout_g2d1.clk,
842};
843
844static struct clksrc_sources clkset_mout_g2d = {
845 .sources = clkset_mout_g2d_list,
846 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
847};
848
849static struct clk *clkset_mout_mfc0_list[] = {
850 [0] = &clk_mout_mpll.clk,
851 [1] = &clk_sclk_apll.clk,
852};
853
854static struct clksrc_sources clkset_mout_mfc0 = {
855 .sources = clkset_mout_mfc0_list,
856 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
857};
858
859static struct clksrc_clk clk_mout_mfc0 = {
860 .clk = {
861 .name = "mout_mfc0",
862 },
863 .sources = &clkset_mout_mfc0,
864 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
865};
866
867static struct clk *clkset_mout_mfc1_list[] = {
868 [0] = &clk_mout_epll.clk,
869 [1] = &clk_sclk_vpll.clk,
870};
871
872static struct clksrc_sources clkset_mout_mfc1 = {
873 .sources = clkset_mout_mfc1_list,
874 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
875};
876
877static struct clksrc_clk clk_mout_mfc1 = {
878 .clk = {
879 .name = "mout_mfc1",
880 },
881 .sources = &clkset_mout_mfc1,
882 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
883};
884
885static struct clk *clkset_mout_mfc_list[] = {
886 [0] = &clk_mout_mfc0.clk,
887 [1] = &clk_mout_mfc1.clk,
888};
889
890static struct clksrc_sources clkset_mout_mfc = {
891 .sources = clkset_mout_mfc_list,
892 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
893};
894
895static struct clk *clkset_sclk_dac_list[] = {
896 [0] = &clk_sclk_vpll.clk,
897 [1] = &clk_sclk_hdmiphy,
898};
899
900static struct clksrc_sources clkset_sclk_dac = {
901 .sources = clkset_sclk_dac_list,
902 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
903};
904
905static struct clksrc_clk clk_sclk_dac = {
906 .clk = {
907 .name = "sclk_dac",
908 .enable = exynos4_clksrc_mask_tv_ctrl,
909 .ctrlbit = (1 << 8),
910 },
911 .sources = &clkset_sclk_dac,
912 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
913};
914
915static struct clksrc_clk clk_sclk_pixel = {
916 .clk = {
917 .name = "sclk_pixel",
918 .parent = &clk_sclk_vpll.clk,
919 },
920 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
921};
922
923static struct clk *clkset_sclk_hdmi_list[] = {
924 [0] = &clk_sclk_pixel.clk,
925 [1] = &clk_sclk_hdmiphy,
926};
927
928static struct clksrc_sources clkset_sclk_hdmi = {
929 .sources = clkset_sclk_hdmi_list,
930 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
931};
932
933static struct clksrc_clk clk_sclk_hdmi = {
934 .clk = {
935 .name = "sclk_hdmi",
936 .enable = exynos4_clksrc_mask_tv_ctrl,
937 .ctrlbit = (1 << 0),
938 },
939 .sources = &clkset_sclk_hdmi,
940 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
941};
942
943static struct clk *clkset_sclk_mixer_list[] = {
944 [0] = &clk_sclk_dac.clk,
945 [1] = &clk_sclk_hdmi.clk,
946};
947
948static struct clksrc_sources clkset_sclk_mixer = {
949 .sources = clkset_sclk_mixer_list,
950 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
951};
952
953static struct clksrc_clk clk_sclk_mixer = {
954 .clk = {
955 .name = "sclk_mixer",
956 .enable = exynos4_clksrc_mask_tv_ctrl,
957 .ctrlbit = (1 << 4),
958 },
959 .sources = &clkset_sclk_mixer,
960 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
961};
962
963static struct clksrc_clk *sclk_tv[] = {
964 &clk_sclk_dac,
965 &clk_sclk_pixel,
966 &clk_sclk_hdmi,
967 &clk_sclk_mixer,
968};
969
970static struct clksrc_clk clk_dout_mmc0 = {
971 .clk = {
972 .name = "dout_mmc0",
973 },
974 .sources = &clkset_group,
975 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
976 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
977};
978
979static struct clksrc_clk clk_dout_mmc1 = {
980 .clk = {
981 .name = "dout_mmc1",
982 },
983 .sources = &clkset_group,
984 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
985 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
986};
987
988static struct clksrc_clk clk_dout_mmc2 = {
989 .clk = {
990 .name = "dout_mmc2",
991 },
992 .sources = &clkset_group,
993 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
994 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
995};
996
997static struct clksrc_clk clk_dout_mmc3 = {
998 .clk = {
999 .name = "dout_mmc3",
1000 },
1001 .sources = &clkset_group,
1002 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1003 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1004};
1005
1006static struct clksrc_clk clk_dout_mmc4 = {
1007 .clk = {
1008 .name = "dout_mmc4",
1009 },
1010 .sources = &clkset_group,
1011 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1012 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1013};
1014
1015static struct clksrc_clk clksrcs[] = {
1016 {
1017 .clk = {
1018 .name = "sclk_pwm",
1019 .enable = exynos4_clksrc_mask_peril0_ctrl,
1020 .ctrlbit = (1 << 24),
1021 },
1022 .sources = &clkset_group,
1023 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1024 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1025 }, {
1026 .clk = {
1027 .name = "sclk_csis",
1028 .devname = "s5p-mipi-csis.0",
1029 .enable = exynos4_clksrc_mask_cam_ctrl,
1030 .ctrlbit = (1 << 24),
1031 },
1032 .sources = &clkset_group,
1033 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1034 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1035 }, {
1036 .clk = {
1037 .name = "sclk_csis",
1038 .devname = "s5p-mipi-csis.1",
1039 .enable = exynos4_clksrc_mask_cam_ctrl,
1040 .ctrlbit = (1 << 28),
1041 },
1042 .sources = &clkset_group,
1043 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1044 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1045 }, {
1046 .clk = {
1047 .name = "sclk_cam0",
1048 .enable = exynos4_clksrc_mask_cam_ctrl,
1049 .ctrlbit = (1 << 16),
1050 },
1051 .sources = &clkset_group,
1052 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1053 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1054 }, {
1055 .clk = {
1056 .name = "sclk_cam1",
1057 .enable = exynos4_clksrc_mask_cam_ctrl,
1058 .ctrlbit = (1 << 20),
1059 },
1060 .sources = &clkset_group,
1061 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1062 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1063 }, {
1064 .clk = {
1065 .name = "sclk_fimc",
1066 .devname = "exynos4-fimc.0",
1067 .enable = exynos4_clksrc_mask_cam_ctrl,
1068 .ctrlbit = (1 << 0),
1069 },
1070 .sources = &clkset_group,
1071 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1072 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1073 }, {
1074 .clk = {
1075 .name = "sclk_fimc",
1076 .devname = "exynos4-fimc.1",
1077 .enable = exynos4_clksrc_mask_cam_ctrl,
1078 .ctrlbit = (1 << 4),
1079 },
1080 .sources = &clkset_group,
1081 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1082 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1083 }, {
1084 .clk = {
1085 .name = "sclk_fimc",
1086 .devname = "exynos4-fimc.2",
1087 .enable = exynos4_clksrc_mask_cam_ctrl,
1088 .ctrlbit = (1 << 8),
1089 },
1090 .sources = &clkset_group,
1091 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1092 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1093 }, {
1094 .clk = {
1095 .name = "sclk_fimc",
1096 .devname = "exynos4-fimc.3",
1097 .enable = exynos4_clksrc_mask_cam_ctrl,
1098 .ctrlbit = (1 << 12),
1099 },
1100 .sources = &clkset_group,
1101 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1102 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1103 }, {
1104 .clk = {
1105 .name = "sclk_fimd",
1106 .devname = "exynos4-fb.0",
1107 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1108 .ctrlbit = (1 << 0),
1109 },
1110 .sources = &clkset_group,
1111 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1112 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1113 }, {
1114 .clk = {
1115 .name = "sclk_fimg2d",
1116 },
1117 .sources = &clkset_mout_g2d,
1118 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1119 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1120 }, {
1121 .clk = {
1122 .name = "sclk_mfc",
1123 .devname = "s5p-mfc",
1124 },
1125 .sources = &clkset_mout_mfc,
1126 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1127 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1128 }, {
1129 .clk = {
1130 .name = "sclk_dwmmc",
1131 .parent = &clk_dout_mmc4.clk,
1132 .enable = exynos4_clksrc_mask_fsys_ctrl,
1133 .ctrlbit = (1 << 16),
1134 },
1135 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1136 }
1137};
1138
1139static struct clksrc_clk clk_sclk_uart0 = {
1140 .clk = {
1141 .name = "uclk1",
1142 .devname = "exynos4210-uart.0",
1143 .enable = exynos4_clksrc_mask_peril0_ctrl,
1144 .ctrlbit = (1 << 0),
1145 },
1146 .sources = &clkset_group,
1147 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1148 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1149};
1150
1151static struct clksrc_clk clk_sclk_uart1 = {
1152 .clk = {
1153 .name = "uclk1",
1154 .devname = "exynos4210-uart.1",
1155 .enable = exynos4_clksrc_mask_peril0_ctrl,
1156 .ctrlbit = (1 << 4),
1157 },
1158 .sources = &clkset_group,
1159 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1160 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1161};
1162
1163static struct clksrc_clk clk_sclk_uart2 = {
1164 .clk = {
1165 .name = "uclk1",
1166 .devname = "exynos4210-uart.2",
1167 .enable = exynos4_clksrc_mask_peril0_ctrl,
1168 .ctrlbit = (1 << 8),
1169 },
1170 .sources = &clkset_group,
1171 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1172 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1173};
1174
1175static struct clksrc_clk clk_sclk_uart3 = {
1176 .clk = {
1177 .name = "uclk1",
1178 .devname = "exynos4210-uart.3",
1179 .enable = exynos4_clksrc_mask_peril0_ctrl,
1180 .ctrlbit = (1 << 12),
1181 },
1182 .sources = &clkset_group,
1183 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1184 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1185};
1186
1187static struct clksrc_clk clk_sclk_mmc0 = {
1188 .clk = {
1189 .name = "sclk_mmc",
1190 .devname = "s3c-sdhci.0",
1191 .parent = &clk_dout_mmc0.clk,
1192 .enable = exynos4_clksrc_mask_fsys_ctrl,
1193 .ctrlbit = (1 << 0),
1194 },
1195 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1196};
1197
1198static struct clksrc_clk clk_sclk_mmc1 = {
1199 .clk = {
1200 .name = "sclk_mmc",
1201 .devname = "s3c-sdhci.1",
1202 .parent = &clk_dout_mmc1.clk,
1203 .enable = exynos4_clksrc_mask_fsys_ctrl,
1204 .ctrlbit = (1 << 4),
1205 },
1206 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1207};
1208
1209static struct clksrc_clk clk_sclk_mmc2 = {
1210 .clk = {
1211 .name = "sclk_mmc",
1212 .devname = "s3c-sdhci.2",
1213 .parent = &clk_dout_mmc2.clk,
1214 .enable = exynos4_clksrc_mask_fsys_ctrl,
1215 .ctrlbit = (1 << 8),
1216 },
1217 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1218};
1219
1220static struct clksrc_clk clk_sclk_mmc3 = {
1221 .clk = {
1222 .name = "sclk_mmc",
1223 .devname = "s3c-sdhci.3",
1224 .parent = &clk_dout_mmc3.clk,
1225 .enable = exynos4_clksrc_mask_fsys_ctrl,
1226 .ctrlbit = (1 << 12),
1227 },
1228 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1229};
1230
1231static struct clksrc_clk clk_sclk_spi0 = {
1232 .clk = {
1233 .name = "sclk_spi",
1234 .devname = "s3c64xx-spi.0",
1235 .enable = exynos4_clksrc_mask_peril1_ctrl,
1236 .ctrlbit = (1 << 16),
1237 },
1238 .sources = &clkset_group,
1239 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1240 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1241};
1242
1243static struct clksrc_clk clk_sclk_spi1 = {
1244 .clk = {
1245 .name = "sclk_spi",
1246 .devname = "s3c64xx-spi.1",
1247 .enable = exynos4_clksrc_mask_peril1_ctrl,
1248 .ctrlbit = (1 << 20),
1249 },
1250 .sources = &clkset_group,
1251 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1252 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1253};
1254
1255static struct clksrc_clk clk_sclk_spi2 = {
1256 .clk = {
1257 .name = "sclk_spi",
1258 .devname = "s3c64xx-spi.2",
1259 .enable = exynos4_clksrc_mask_peril1_ctrl,
1260 .ctrlbit = (1 << 24),
1261 },
1262 .sources = &clkset_group,
1263 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1265};
1266
1267/* Clock initialization code */
1268static struct clksrc_clk *sysclks[] = {
1269 &clk_mout_apll,
1270 &clk_sclk_apll,
1271 &clk_mout_epll,
1272 &clk_mout_mpll,
1273 &clk_moutcore,
1274 &clk_coreclk,
1275 &clk_armclk,
1276 &clk_aclk_corem0,
1277 &clk_aclk_cores,
1278 &clk_aclk_corem1,
1279 &clk_periphclk,
1280 &clk_mout_corebus,
1281 &clk_sclk_dmc,
1282 &clk_aclk_cored,
1283 &clk_aclk_corep,
1284 &clk_aclk_acp,
1285 &clk_pclk_acp,
1286 &clk_vpllsrc,
1287 &clk_sclk_vpll,
1288 &clk_aclk_200,
1289 &clk_aclk_100,
1290 &clk_aclk_160,
1291 &clk_aclk_133,
1292 &clk_dout_mmc0,
1293 &clk_dout_mmc1,
1294 &clk_dout_mmc2,
1295 &clk_dout_mmc3,
1296 &clk_dout_mmc4,
1297 &clk_mout_mfc0,
1298 &clk_mout_mfc1,
1299};
1300
1301static struct clk *clk_cdev[] = {
1302 &clk_pdma0,
1303 &clk_pdma1,
1304};
1305
1306static struct clksrc_clk *clksrc_cdev[] = {
1307 &clk_sclk_uart0,
1308 &clk_sclk_uart1,
1309 &clk_sclk_uart2,
1310 &clk_sclk_uart3,
1311 &clk_sclk_mmc0,
1312 &clk_sclk_mmc1,
1313 &clk_sclk_mmc2,
1314 &clk_sclk_mmc3,
1315 &clk_sclk_spi0,
1316 &clk_sclk_spi1,
1317 &clk_sclk_spi2,
1318
1319};
1320
1321static struct clk_lookup exynos4_clk_lookup[] = {
1322 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1323 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1324 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1325 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1326 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1327 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1328 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1329 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1330 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1331 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1332 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1333 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1334 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1335};
1336
1337static int xtal_rate;
1338
1339static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1340{
1341 if (soc_is_exynos4210())
1342 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1343 pll_4508);
1344 else if (soc_is_exynos4212() || soc_is_exynos4412())
1345 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1346 else
1347 return 0;
1348}
1349
1350static struct clk_ops exynos4_fout_apll_ops = {
1351 .get_rate = exynos4_fout_apll_get_rate,
1352};
1353
1354static u32 vpll_div[][8] = {
1355 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1356 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1357};
1358
1359static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1360{
1361 return clk->rate;
1362}
1363
1364static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1365{
1366 unsigned int vpll_con0, vpll_con1 = 0;
1367 unsigned int i;
1368
1369 /* Return if nothing changed */
1370 if (clk->rate == rate)
1371 return 0;
1372
1373 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1374 vpll_con0 &= ~(0x1 << 27 | \
1375 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1376 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1377 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1378
1379 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1380 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1381 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1382 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1383
1384 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1385 if (vpll_div[i][0] == rate) {
1386 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1387 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1388 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1389 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1390 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1391 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1392 vpll_con0 |= vpll_div[i][7] << 27;
1393 break;
1394 }
1395 }
1396
1397 if (i == ARRAY_SIZE(vpll_div)) {
1398 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1399 __func__);
1400 return -EINVAL;
1401 }
1402
1403 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1404 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1405
1406 /* Wait for VPLL lock */
1407 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1408 continue;
1409
1410 clk->rate = rate;
1411 return 0;
1412}
1413
1414static struct clk_ops exynos4_vpll_ops = {
1415 .get_rate = exynos4_vpll_get_rate,
1416 .set_rate = exynos4_vpll_set_rate,
1417};
1418
1419void __init_or_cpufreq exynos4_setup_clocks(void)
1420{
1421 struct clk *xtal_clk;
1422 unsigned long apll = 0;
1423 unsigned long mpll = 0;
1424 unsigned long epll = 0;
1425 unsigned long vpll = 0;
1426 unsigned long vpllsrc;
1427 unsigned long xtal;
1428 unsigned long armclk;
1429 unsigned long sclk_dmc;
1430 unsigned long aclk_200;
1431 unsigned long aclk_100;
1432 unsigned long aclk_160;
1433 unsigned long aclk_133;
1434 unsigned int ptr;
1435
1436 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1437
1438 xtal_clk = clk_get(NULL, "xtal");
1439 BUG_ON(IS_ERR(xtal_clk));
1440
1441 xtal = clk_get_rate(xtal_clk);
1442
1443 xtal_rate = xtal;
1444
1445 clk_put(xtal_clk);
1446
1447 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1448
1449 if (soc_is_exynos4210()) {
1450 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1451 pll_4508);
1452 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1453 pll_4508);
1454 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1455 __raw_readl(S5P_EPLL_CON1), pll_4600);
1456
1457 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1458 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1459 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1460 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1461 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1462 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1463 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1464 __raw_readl(S5P_EPLL_CON1));
1465
1466 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1467 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1468 __raw_readl(S5P_VPLL_CON1));
1469 } else {
1470 /* nothing */
1471 }
1472
1473 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1474 clk_fout_mpll.rate = mpll;
1475 clk_fout_epll.rate = epll;
1476 clk_fout_vpll.ops = &exynos4_vpll_ops;
1477 clk_fout_vpll.rate = vpll;
1478
1479 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1480 apll, mpll, epll, vpll);
1481
1482 armclk = clk_get_rate(&clk_armclk.clk);
1483 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1484
1485 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1486 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1487 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1488 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1489
1490 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1491 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1492 armclk, sclk_dmc, aclk_200,
1493 aclk_100, aclk_160, aclk_133);
1494
1495 clk_f.rate = armclk;
1496 clk_h.rate = sclk_dmc;
1497 clk_p.rate = aclk_100;
1498
1499 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1500 s3c_set_clksrc(&clksrcs[ptr], true);
1501}
1502
1503static struct clk *clks[] __initdata = {
1504 &clk_sclk_hdmi27m,
1505 &clk_sclk_hdmiphy,
1506 &clk_sclk_usbphy0,
1507 &clk_sclk_usbphy1,
1508};
1509
1510#ifdef CONFIG_PM_SLEEP
1511static int exynos4_clock_suspend(void)
1512{
1513 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1514 return 0;
1515}
1516
1517static void exynos4_clock_resume(void)
1518{
1519 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1520}
1521
1522#else
1523#define exynos4_clock_suspend NULL
1524#define exynos4_clock_resume NULL
1525#endif
1526
1527struct syscore_ops exynos4_clock_syscore_ops = {
1528 .suspend = exynos4_clock_suspend,
1529 .resume = exynos4_clock_resume,
1530};
1531
1532void __init exynos4_register_clocks(void)
1533{
1534 int ptr;
1535
1536 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1537
1538 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1539 s3c_register_clksrc(sysclks[ptr], 1);
1540
1541 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1542 s3c_register_clksrc(sclk_tv[ptr], 1);
1543
1544 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1545 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1546
1547 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1548 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1549
1550 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1551 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1552 s3c_disable_clocks(clk_cdev[ptr], 1);
1553
1554 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1555 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1556 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1557
1558 register_syscore_ops(&exynos4_clock_syscore_ops);
1559 s3c24xx_register_clock(&dummy_apb_pclk);
1560
1561 s3c_pwmclk_init();
1562}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index c59e18871006..e6cc50e94a58 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -26,10 +26,12 @@
26#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/mach/irq.h> 28#include <asm/mach/irq.h>
29#include <asm/cacheflush.h>
29 30
30#include <mach/regs-irq.h> 31#include <mach/regs-irq.h>
31#include <mach/regs-pmu.h> 32#include <mach/regs-pmu.h>
32#include <mach/regs-gpio.h> 33#include <mach/regs-gpio.h>
34#include <mach/pmu.h>
33 35
34#include <plat/cpu.h> 36#include <plat/cpu.h>
35#include <plat/clock.h> 37#include <plat/clock.h>
@@ -45,10 +47,20 @@
45#include <plat/regs-serial.h> 47#include <plat/regs-serial.h>
46 48
47#include "common.h" 49#include "common.h"
50#define L2_AUX_VAL 0x7C470001
51#define L2_AUX_MASK 0xC200ffff
48 52
49static const char name_exynos4210[] = "EXYNOS4210"; 53static const char name_exynos4210[] = "EXYNOS4210";
50static const char name_exynos4212[] = "EXYNOS4212"; 54static const char name_exynos4212[] = "EXYNOS4212";
51static const char name_exynos4412[] = "EXYNOS4412"; 55static const char name_exynos4412[] = "EXYNOS4412";
56static const char name_exynos5250[] = "EXYNOS5250";
57
58static void exynos4_map_io(void);
59static void exynos5_map_io(void);
60static void exynos4_init_clocks(int xtal);
61static void exynos5_init_clocks(int xtal);
62static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
63static int exynos_init(void);
52 64
53static struct cpu_table cpu_ids[] __initdata = { 65static struct cpu_table cpu_ids[] __initdata = {
54 { 66 {
@@ -56,7 +68,7 @@ static struct cpu_table cpu_ids[] __initdata = {
56 .idmask = EXYNOS4_CPU_MASK, 68 .idmask = EXYNOS4_CPU_MASK,
57 .map_io = exynos4_map_io, 69 .map_io = exynos4_map_io,
58 .init_clocks = exynos4_init_clocks, 70 .init_clocks = exynos4_init_clocks,
59 .init_uarts = exynos4_init_uarts, 71 .init_uarts = exynos_init_uarts,
60 .init = exynos_init, 72 .init = exynos_init,
61 .name = name_exynos4210, 73 .name = name_exynos4210,
62 }, { 74 }, {
@@ -64,7 +76,7 @@ static struct cpu_table cpu_ids[] __initdata = {
64 .idmask = EXYNOS4_CPU_MASK, 76 .idmask = EXYNOS4_CPU_MASK,
65 .map_io = exynos4_map_io, 77 .map_io = exynos4_map_io,
66 .init_clocks = exynos4_init_clocks, 78 .init_clocks = exynos4_init_clocks,
67 .init_uarts = exynos4_init_uarts, 79 .init_uarts = exynos_init_uarts,
68 .init = exynos_init, 80 .init = exynos_init,
69 .name = name_exynos4212, 81 .name = name_exynos4212,
70 }, { 82 }, {
@@ -72,9 +84,17 @@ static struct cpu_table cpu_ids[] __initdata = {
72 .idmask = EXYNOS4_CPU_MASK, 84 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io, 85 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks, 86 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts, 87 .init_uarts = exynos_init_uarts,
76 .init = exynos_init, 88 .init = exynos_init,
77 .name = name_exynos4412, 89 .name = name_exynos4412,
90 }, {
91 .idcode = EXYNOS5250_SOC_ID,
92 .idmask = EXYNOS5_SOC_MASK,
93 .map_io = exynos5_map_io,
94 .init_clocks = exynos5_init_clocks,
95 .init_uarts = exynos_init_uarts,
96 .init = exynos_init,
97 .name = name_exynos5250,
78 }, 98 },
79}; 99};
80 100
@@ -83,10 +103,14 @@ static struct cpu_table cpu_ids[] __initdata = {
83static struct map_desc exynos_iodesc[] __initdata = { 103static struct map_desc exynos_iodesc[] __initdata = {
84 { 104 {
85 .virtual = (unsigned long)S5P_VA_CHIPID, 105 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID), 106 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
87 .length = SZ_4K, 107 .length = SZ_4K,
88 .type = MT_DEVICE, 108 .type = MT_DEVICE,
89 }, { 109 },
110};
111
112static struct map_desc exynos4_iodesc[] __initdata = {
113 {
90 .virtual = (unsigned long)S3C_VA_SYS, 114 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), 115 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
92 .length = SZ_64K, 116 .length = SZ_64K,
@@ -136,11 +160,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
136 .pfn = __phys_to_pfn(EXYNOS4_PA_UART), 160 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
137 .length = SZ_512K, 161 .length = SZ_512K,
138 .type = MT_DEVICE, 162 .type = MT_DEVICE,
139 }, 163 }, {
140};
141
142static struct map_desc exynos4_iodesc[] __initdata = {
143 {
144 .virtual = (unsigned long)S5P_VA_CMU, 164 .virtual = (unsigned long)S5P_VA_CMU,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 165 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
146 .length = SZ_128K, 166 .length = SZ_128K,
@@ -156,24 +176,14 @@ static struct map_desc exynos4_iodesc[] __initdata = {
156 .length = SZ_4K, 176 .length = SZ_4K,
157 .type = MT_DEVICE, 177 .type = MT_DEVICE,
158 }, { 178 }, {
159 .virtual = (unsigned long)S5P_VA_GPIO1,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
161 .length = SZ_4K,
162 .type = MT_DEVICE,
163 }, {
164 .virtual = (unsigned long)S5P_VA_GPIO2,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
166 .length = SZ_4K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = (unsigned long)S5P_VA_GPIO3,
170 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
171 .length = SZ_256,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = (unsigned long)S5P_VA_DMC0, 179 .virtual = (unsigned long)S5P_VA_DMC0,
175 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), 180 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
176 .length = SZ_4K, 181 .length = SZ_64K,
182 .type = MT_DEVICE,
183 }, {
184 .virtual = (unsigned long)S5P_VA_DMC1,
185 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
186 .length = SZ_64K,
177 .type = MT_DEVICE, 187 .type = MT_DEVICE,
178 }, { 188 }, {
179 .virtual = (unsigned long)S3C_VA_USB_HSPHY, 189 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
@@ -201,19 +211,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
201 }, 211 },
202}; 212};
203 213
204static void exynos_idle(void) 214static struct map_desc exynos5_iodesc[] __initdata = {
205{ 215 {
206 if (!need_resched()) 216 .virtual = (unsigned long)S3C_VA_SYS,
207 cpu_do_idle(); 217 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
208 218 .length = SZ_64K,
209 local_irq_enable(); 219 .type = MT_DEVICE,
210} 220 }, {
221 .virtual = (unsigned long)S3C_VA_TIMER,
222 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
223 .length = SZ_16K,
224 .type = MT_DEVICE,
225 }, {
226 .virtual = (unsigned long)S3C_VA_WATCHDOG,
227 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
228 .length = SZ_4K,
229 .type = MT_DEVICE,
230 }, {
231 .virtual = (unsigned long)S5P_VA_SROMC,
232 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
233 .length = SZ_4K,
234 .type = MT_DEVICE,
235 }, {
236 .virtual = (unsigned long)S5P_VA_SYSTIMER,
237 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
238 .length = SZ_4K,
239 .type = MT_DEVICE,
240 }, {
241 .virtual = (unsigned long)S5P_VA_SYSRAM,
242 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
243 .length = SZ_4K,
244 .type = MT_DEVICE,
245 }, {
246 .virtual = (unsigned long)S5P_VA_CMU,
247 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
248 .length = 144 * SZ_1K,
249 .type = MT_DEVICE,
250 }, {
251 .virtual = (unsigned long)S5P_VA_PMU,
252 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
253 .length = SZ_64K,
254 .type = MT_DEVICE,
255 }, {
256 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
257 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
258 .length = SZ_4K,
259 .type = MT_DEVICE,
260 }, {
261 .virtual = (unsigned long)S3C_VA_UART,
262 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
263 .length = SZ_512K,
264 .type = MT_DEVICE,
265 }, {
266 .virtual = (unsigned long)S5P_VA_GIC_CPU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
268 .length = SZ_64K,
269 .type = MT_DEVICE,
270 }, {
271 .virtual = (unsigned long)S5P_VA_GIC_DIST,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
273 .length = SZ_64K,
274 .type = MT_DEVICE,
275 },
276};
211 277
212void exynos4_restart(char mode, const char *cmd) 278void exynos4_restart(char mode, const char *cmd)
213{ 279{
214 __raw_writel(0x1, S5P_SWRESET); 280 __raw_writel(0x1, S5P_SWRESET);
215} 281}
216 282
283void exynos5_restart(char mode, const char *cmd)
284{
285 __raw_writel(0x1, EXYNOS_SWRESET);
286}
287
217/* 288/*
218 * exynos_map_io 289 * exynos_map_io
219 * 290 *
@@ -233,7 +304,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
233 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 304 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
234} 305}
235 306
236void __init exynos4_map_io(void) 307static void __init exynos4_map_io(void)
237{ 308{
238 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 309 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
239 310
@@ -264,7 +335,22 @@ void __init exynos4_map_io(void)
264 s5p_hdmi_setname("exynos4-hdmi"); 335 s5p_hdmi_setname("exynos4-hdmi");
265} 336}
266 337
267void __init exynos4_init_clocks(int xtal) 338static void __init exynos5_map_io(void)
339{
340 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
341
342 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
343 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
344 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
345 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
346
347 /* The I2C bus controllers are directly compatible with s3c2440 */
348 s3c_i2c0_setname("s3c2440-i2c");
349 s3c_i2c1_setname("s3c2440-i2c");
350 s3c_i2c2_setname("s3c2440-i2c");
351}
352
353static void __init exynos4_init_clocks(int xtal)
268{ 354{
269 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 355 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
270 356
@@ -280,6 +366,17 @@ void __init exynos4_init_clocks(int xtal)
280 exynos4_setup_clocks(); 366 exynos4_setup_clocks();
281} 367}
282 368
369static void __init exynos5_init_clocks(int xtal)
370{
371 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
372
373 s3c24xx_register_baseclocks(xtal);
374 s5p_register_clocks(xtal);
375
376 exynos5_register_clocks();
377 exynos5_setup_clocks();
378}
379
283#define COMBINER_ENABLE_SET 0x0 380#define COMBINER_ENABLE_SET 0x0
284#define COMBINER_ENABLE_CLEAR 0x4 381#define COMBINER_ENABLE_CLEAR 0x4
285#define COMBINER_INT_STATUS 0xC 382#define COMBINER_INT_STATUS 0xC
@@ -353,7 +450,14 @@ static struct irq_chip combiner_chip = {
353 450
354static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 451static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
355{ 452{
356 if (combiner_nr >= MAX_COMBINER_NR) 453 unsigned int max_nr;
454
455 if (soc_is_exynos5250())
456 max_nr = EXYNOS5_MAX_COMBINER_NR;
457 else
458 max_nr = EXYNOS4_MAX_COMBINER_NR;
459
460 if (combiner_nr >= max_nr)
357 BUG(); 461 BUG();
358 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) 462 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
359 BUG(); 463 BUG();
@@ -364,8 +468,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
364 unsigned int irq_start) 468 unsigned int irq_start)
365{ 469{
366 unsigned int i; 470 unsigned int i;
471 unsigned int max_nr;
367 472
368 if (combiner_nr >= MAX_COMBINER_NR) 473 if (soc_is_exynos5250())
474 max_nr = EXYNOS5_MAX_COMBINER_NR;
475 else
476 max_nr = EXYNOS4_MAX_COMBINER_NR;
477
478 if (combiner_nr >= max_nr)
369 BUG(); 479 BUG();
370 480
371 combiner_data[combiner_nr].base = base; 481 combiner_data[combiner_nr].base = base;
@@ -402,13 +512,13 @@ void __init exynos4_init_irq(void)
402 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 512 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
403 513
404 if (!of_have_populated_dt()) 514 if (!of_have_populated_dt())
405 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); 515 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
406#ifdef CONFIG_OF 516#ifdef CONFIG_OF
407 else 517 else
408 of_irq_init(exynos4_dt_irq_match); 518 of_irq_init(exynos4_dt_irq_match);
409#endif 519#endif
410 520
411 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 521 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
412 522
413 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 523 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
414 COMBINER_IRQ(irq, 0)); 524 COMBINER_IRQ(irq, 0));
@@ -423,60 +533,144 @@ void __init exynos4_init_irq(void)
423 s5p_init_irq(NULL, 0); 533 s5p_init_irq(NULL, 0);
424} 534}
425 535
536void __init exynos5_init_irq(void)
537{
538 int irq;
539
540 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
541
542 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
543 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
544 COMBINER_IRQ(irq, 0));
545 combiner_cascade_irq(irq, IRQ_SPI(irq));
546 }
547
548 /*
549 * The parameters of s5p_init_irq() are for VIC init.
550 * Theses parameters should be NULL and 0 because EXYNOS4
551 * uses GIC instead of VIC.
552 */
553 s5p_init_irq(NULL, 0);
554}
555
426struct bus_type exynos4_subsys = { 556struct bus_type exynos4_subsys = {
427 .name = "exynos4-core", 557 .name = "exynos4-core",
428 .dev_name = "exynos4-core", 558 .dev_name = "exynos4-core",
429}; 559};
430 560
561struct bus_type exynos5_subsys = {
562 .name = "exynos5-core",
563 .dev_name = "exynos5-core",
564};
565
431static struct device exynos4_dev = { 566static struct device exynos4_dev = {
432 .bus = &exynos4_subsys, 567 .bus = &exynos4_subsys,
433}; 568};
434 569
435static int __init exynos4_core_init(void) 570static struct device exynos5_dev = {
571 .bus = &exynos5_subsys,
572};
573
574static int __init exynos_core_init(void)
436{ 575{
437 return subsys_system_register(&exynos4_subsys, NULL); 576 if (soc_is_exynos5250())
577 return subsys_system_register(&exynos5_subsys, NULL);
578 else
579 return subsys_system_register(&exynos4_subsys, NULL);
438} 580}
439core_initcall(exynos4_core_init); 581core_initcall(exynos_core_init);
440 582
441#ifdef CONFIG_CACHE_L2X0 583#ifdef CONFIG_CACHE_L2X0
442static int __init exynos4_l2x0_cache_init(void) 584static int __init exynos4_l2x0_cache_init(void)
443{ 585{
444 /* TAG, Data Latency Control: 2cycle */ 586 if (soc_is_exynos5250())
445 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 587 return 0;
588
589 int ret;
590 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
591 if (!ret) {
592 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
593 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
594 return 0;
595 }
446 596
447 if (soc_is_exynos4210()) 597 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
448 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 598 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
449 else if (soc_is_exynos4212() || soc_is_exynos4412()) 599 /* TAG, Data Latency Control: 2 cycles */
450 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 600 l2x0_saved_regs.tag_latency = 0x110;
601
602 if (soc_is_exynos4212() || soc_is_exynos4412())
603 l2x0_saved_regs.data_latency = 0x120;
604 else
605 l2x0_saved_regs.data_latency = 0x110;
451 606
452 /* L2X0 Prefetch Control */ 607 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
453 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); 608 l2x0_saved_regs.pwr_ctrl =
609 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
454 610
455 /* L2X0 Power Control */ 611 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
456 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
457 S5P_VA_L2CC + L2X0_POWER_CTRL);
458 612
459 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); 613 __raw_writel(l2x0_saved_regs.tag_latency,
614 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
615 __raw_writel(l2x0_saved_regs.data_latency,
616 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
460 617
618 /* L2X0 Prefetch Control */
619 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
620 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
621
622 /* L2X0 Power Control */
623 __raw_writel(l2x0_saved_regs.pwr_ctrl,
624 S5P_VA_L2CC + L2X0_POWER_CTRL);
625
626 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
627 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
628 }
629
630 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
461 return 0; 631 return 0;
462} 632}
463
464early_initcall(exynos4_l2x0_cache_init); 633early_initcall(exynos4_l2x0_cache_init);
465#endif 634#endif
466 635
467int __init exynos_init(void) 636static int __init exynos5_l2_cache_init(void)
468{ 637{
469 printk(KERN_INFO "EXYNOS: Initializing architecture\n"); 638 unsigned int val;
639
640 if (!soc_is_exynos5250())
641 return 0;
642
643 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
644 "bic %0, %0, #(1 << 2)\n" /* cache disable */
645 "mcr p15, 0, %0, c1, c0, 0\n"
646 "mrc p15, 1, %0, c9, c0, 2\n"
647 : "=r"(val));
648
649 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
650
651 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
652 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
653 "orr %0, %0, #(1 << 2)\n" /* cache enable */
654 "mcr p15, 0, %0, c1, c0, 0\n"
655 : : "r"(val));
656
657 return 0;
658}
659early_initcall(exynos5_l2_cache_init);
470 660
471 /* set idle function */ 661static int __init exynos_init(void)
472 pm_idle = exynos_idle; 662{
663 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
473 664
474 return device_register(&exynos4_dev); 665 if (soc_is_exynos5250())
666 return device_register(&exynos5_dev);
667 else
668 return device_register(&exynos4_dev);
475} 669}
476 670
477/* uart registration process */ 671/* uart registration process */
478 672
479void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) 673static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
480{ 674{
481 struct s3c2410_uartcfg *tcfg = cfg; 675 struct s3c2410_uartcfg *tcfg = cfg;
482 u32 ucnt; 676 u32 ucnt;
@@ -484,69 +678,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
484 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) 678 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
485 tcfg->has_fracval = 1; 679 tcfg->has_fracval = 1;
486 680
487 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no); 681 if (soc_is_exynos5250())
682 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
683 else
684 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
488} 685}
489 686
687static void __iomem *exynos_eint_base;
688
490static DEFINE_SPINLOCK(eint_lock); 689static DEFINE_SPINLOCK(eint_lock);
491 690
492static unsigned int eint0_15_data[16]; 691static unsigned int eint0_15_data[16];
493 692
494static unsigned int exynos4_get_irq_nr(unsigned int number) 693static inline int exynos4_irq_to_gpio(unsigned int irq)
495{ 694{
496 u32 ret = 0; 695 if (irq < IRQ_EINT(0))
696 return -EINVAL;
497 697
498 switch (number) { 698 irq -= IRQ_EINT(0);
499 case 0 ... 3: 699 if (irq < 8)
500 ret = (number + IRQ_EINT0); 700 return EXYNOS4_GPX0(irq);
501 break; 701
502 case 4 ... 7: 702 irq -= 8;
503 ret = (number + (IRQ_EINT4 - 4)); 703 if (irq < 8)
504 break; 704 return EXYNOS4_GPX1(irq);
505 case 8 ... 15: 705
506 ret = (number + (IRQ_EINT8 - 8)); 706 irq -= 8;
507 break; 707 if (irq < 8)
508 default: 708 return EXYNOS4_GPX2(irq);
509 printk(KERN_ERR "number available : %d\n", number);
510 }
511 709
512 return ret; 710 irq -= 8;
711 if (irq < 8)
712 return EXYNOS4_GPX3(irq);
713
714 return -EINVAL;
513} 715}
514 716
515static inline void exynos4_irq_eint_mask(struct irq_data *data) 717static inline int exynos5_irq_to_gpio(unsigned int irq)
718{
719 if (irq < IRQ_EINT(0))
720 return -EINVAL;
721
722 irq -= IRQ_EINT(0);
723 if (irq < 8)
724 return EXYNOS5_GPX0(irq);
725
726 irq -= 8;
727 if (irq < 8)
728 return EXYNOS5_GPX1(irq);
729
730 irq -= 8;
731 if (irq < 8)
732 return EXYNOS5_GPX2(irq);
733
734 irq -= 8;
735 if (irq < 8)
736 return EXYNOS5_GPX3(irq);
737
738 return -EINVAL;
739}
740
741static unsigned int exynos4_eint0_15_src_int[16] = {
742 EXYNOS4_IRQ_EINT0,
743 EXYNOS4_IRQ_EINT1,
744 EXYNOS4_IRQ_EINT2,
745 EXYNOS4_IRQ_EINT3,
746 EXYNOS4_IRQ_EINT4,
747 EXYNOS4_IRQ_EINT5,
748 EXYNOS4_IRQ_EINT6,
749 EXYNOS4_IRQ_EINT7,
750 EXYNOS4_IRQ_EINT8,
751 EXYNOS4_IRQ_EINT9,
752 EXYNOS4_IRQ_EINT10,
753 EXYNOS4_IRQ_EINT11,
754 EXYNOS4_IRQ_EINT12,
755 EXYNOS4_IRQ_EINT13,
756 EXYNOS4_IRQ_EINT14,
757 EXYNOS4_IRQ_EINT15,
758};
759
760static unsigned int exynos5_eint0_15_src_int[16] = {
761 EXYNOS5_IRQ_EINT0,
762 EXYNOS5_IRQ_EINT1,
763 EXYNOS5_IRQ_EINT2,
764 EXYNOS5_IRQ_EINT3,
765 EXYNOS5_IRQ_EINT4,
766 EXYNOS5_IRQ_EINT5,
767 EXYNOS5_IRQ_EINT6,
768 EXYNOS5_IRQ_EINT7,
769 EXYNOS5_IRQ_EINT8,
770 EXYNOS5_IRQ_EINT9,
771 EXYNOS5_IRQ_EINT10,
772 EXYNOS5_IRQ_EINT11,
773 EXYNOS5_IRQ_EINT12,
774 EXYNOS5_IRQ_EINT13,
775 EXYNOS5_IRQ_EINT14,
776 EXYNOS5_IRQ_EINT15,
777};
778static inline void exynos_irq_eint_mask(struct irq_data *data)
516{ 779{
517 u32 mask; 780 u32 mask;
518 781
519 spin_lock(&eint_lock); 782 spin_lock(&eint_lock);
520 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); 783 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
521 mask |= eint_irq_to_bit(data->irq); 784 mask |= EINT_OFFSET_BIT(data->irq);
522 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); 785 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
523 spin_unlock(&eint_lock); 786 spin_unlock(&eint_lock);
524} 787}
525 788
526static void exynos4_irq_eint_unmask(struct irq_data *data) 789static void exynos_irq_eint_unmask(struct irq_data *data)
527{ 790{
528 u32 mask; 791 u32 mask;
529 792
530 spin_lock(&eint_lock); 793 spin_lock(&eint_lock);
531 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); 794 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
532 mask &= ~(eint_irq_to_bit(data->irq)); 795 mask &= ~(EINT_OFFSET_BIT(data->irq));
533 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); 796 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
534 spin_unlock(&eint_lock); 797 spin_unlock(&eint_lock);
535} 798}
536 799
537static inline void exynos4_irq_eint_ack(struct irq_data *data) 800static inline void exynos_irq_eint_ack(struct irq_data *data)
538{ 801{
539 __raw_writel(eint_irq_to_bit(data->irq), 802 __raw_writel(EINT_OFFSET_BIT(data->irq),
540 S5P_EINT_PEND(EINT_REG_NR(data->irq))); 803 EINT_PEND(exynos_eint_base, data->irq));
541} 804}
542 805
543static void exynos4_irq_eint_maskack(struct irq_data *data) 806static void exynos_irq_eint_maskack(struct irq_data *data)
544{ 807{
545 exynos4_irq_eint_mask(data); 808 exynos_irq_eint_mask(data);
546 exynos4_irq_eint_ack(data); 809 exynos_irq_eint_ack(data);
547} 810}
548 811
549static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type) 812static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
550{ 813{
551 int offs = EINT_OFFSET(data->irq); 814 int offs = EINT_OFFSET(data->irq);
552 int shift; 815 int shift;
@@ -583,39 +846,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
583 mask = 0x7 << shift; 846 mask = 0x7 << shift;
584 847
585 spin_lock(&eint_lock); 848 spin_lock(&eint_lock);
586 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); 849 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
587 ctrl &= ~mask; 850 ctrl &= ~mask;
588 ctrl |= newvalue << shift; 851 ctrl |= newvalue << shift;
589 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); 852 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
590 spin_unlock(&eint_lock); 853 spin_unlock(&eint_lock);
591 854
592 switch (offs) { 855 if (soc_is_exynos5250())
593 case 0 ... 7: 856 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
594 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); 857 else
595 break; 858 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
596 case 8 ... 15:
597 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
598 break;
599 case 16 ... 23:
600 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
601 break;
602 case 24 ... 31:
603 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
604 break;
605 default:
606 printk(KERN_ERR "No such irq number %d", offs);
607 }
608 859
609 return 0; 860 return 0;
610} 861}
611 862
612static struct irq_chip exynos4_irq_eint = { 863static struct irq_chip exynos_irq_eint = {
613 .name = "exynos4-eint", 864 .name = "exynos-eint",
614 .irq_mask = exynos4_irq_eint_mask, 865 .irq_mask = exynos_irq_eint_mask,
615 .irq_unmask = exynos4_irq_eint_unmask, 866 .irq_unmask = exynos_irq_eint_unmask,
616 .irq_mask_ack = exynos4_irq_eint_maskack, 867 .irq_mask_ack = exynos_irq_eint_maskack,
617 .irq_ack = exynos4_irq_eint_ack, 868 .irq_ack = exynos_irq_eint_ack,
618 .irq_set_type = exynos4_irq_eint_set_type, 869 .irq_set_type = exynos_irq_eint_set_type,
619#ifdef CONFIG_PM 870#ifdef CONFIG_PM
620 .irq_set_wake = s3c_irqext_wake, 871 .irq_set_wake = s3c_irqext_wake,
621#endif 872#endif
@@ -630,12 +881,12 @@ static struct irq_chip exynos4_irq_eint = {
630 * 881 *
631 * Each EINT pend/mask registers handle eight of them. 882 * Each EINT pend/mask registers handle eight of them.
632 */ 883 */
633static inline void exynos4_irq_demux_eint(unsigned int start) 884static inline void exynos_irq_demux_eint(unsigned int start)
634{ 885{
635 unsigned int irq; 886 unsigned int irq;
636 887
637 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); 888 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
638 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); 889 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
639 890
640 status &= ~mask; 891 status &= ~mask;
641 status &= 0xff; 892 status &= 0xff;
@@ -647,16 +898,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
647 } 898 }
648} 899}
649 900
650static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 901static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
651{ 902{
652 struct irq_chip *chip = irq_get_chip(irq); 903 struct irq_chip *chip = irq_get_chip(irq);
653 chained_irq_enter(chip, desc); 904 chained_irq_enter(chip, desc);
654 exynos4_irq_demux_eint(IRQ_EINT(16)); 905 exynos_irq_demux_eint(IRQ_EINT(16));
655 exynos4_irq_demux_eint(IRQ_EINT(24)); 906 exynos_irq_demux_eint(IRQ_EINT(24));
656 chained_irq_exit(chip, desc); 907 chained_irq_exit(chip, desc);
657} 908}
658 909
659static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 910static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
660{ 911{
661 u32 *irq_data = irq_get_handler_data(irq); 912 u32 *irq_data = irq_get_handler_data(irq);
662 struct irq_chip *chip = irq_get_chip(irq); 913 struct irq_chip *chip = irq_get_chip(irq);
@@ -673,27 +924,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
673 chained_irq_exit(chip, desc); 924 chained_irq_exit(chip, desc);
674} 925}
675 926
676int __init exynos4_init_irq_eint(void) 927static int __init exynos_init_irq_eint(void)
677{ 928{
678 int irq; 929 int irq;
679 930
931 if (soc_is_exynos5250())
932 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
933 else
934 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
935
936 if (exynos_eint_base == NULL) {
937 pr_err("unable to ioremap for EINT base address\n");
938 return -ENOMEM;
939 }
940
680 for (irq = 0 ; irq <= 31 ; irq++) { 941 for (irq = 0 ; irq <= 31 ; irq++) {
681 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, 942 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
682 handle_level_irq); 943 handle_level_irq);
683 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 944 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
684 } 945 }
685 946
686 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); 947 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
687 948
688 for (irq = 0 ; irq <= 15 ; irq++) { 949 for (irq = 0 ; irq <= 15 ; irq++) {
689 eint0_15_data[irq] = IRQ_EINT(irq); 950 eint0_15_data[irq] = IRQ_EINT(irq);
690 951
691 irq_set_handler_data(exynos4_get_irq_nr(irq), 952 if (soc_is_exynos5250()) {
692 &eint0_15_data[irq]); 953 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
693 irq_set_chained_handler(exynos4_get_irq_nr(irq), 954 &eint0_15_data[irq]);
694 exynos4_irq_eint0_15); 955 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
956 exynos_irq_eint0_15);
957 } else {
958 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
959 &eint0_15_data[irq]);
960 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
961 exynos_irq_eint0_15);
962 }
695 } 963 }
696 964
697 return 0; 965 return 0;
698} 966}
699arch_initcall(exynos4_init_irq_eint); 967arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de0f398..677b5467df18 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,30 +12,44 @@
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H 12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H 13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14 14
15extern struct sys_timer exynos4_timer;
16
15void exynos_init_io(struct map_desc *mach_desc, int size); 17void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void); 18void exynos4_init_irq(void);
19void exynos5_init_irq(void);
20void exynos4_restart(char mode, const char *cmd);
21void exynos5_restart(char mode, const char *cmd);
17 22
23#ifdef CONFIG_ARCH_EXYNOS4
18void exynos4_register_clocks(void); 24void exynos4_register_clocks(void);
19void exynos4_setup_clocks(void); 25void exynos4_setup_clocks(void);
20 26
21void exynos4210_register_clocks(void); 27#else
22void exynos4212_register_clocks(void); 28#define exynos4_register_clocks()
29#define exynos4_setup_clocks()
30#endif
23 31
24void exynos4_restart(char mode, const char *cmd); 32#ifdef CONFIG_ARCH_EXYNOS5
33void exynos5_register_clocks(void);
34void exynos5_setup_clocks(void);
25 35
26extern struct sys_timer exynos4_timer; 36#else
37#define exynos5_register_clocks()
38#define exynos5_setup_clocks()
39#endif
40
41#ifdef CONFIG_CPU_EXYNOS4210
42void exynos4210_register_clocks(void);
27 43
28#ifdef CONFIG_ARCH_EXYNOS 44#else
29extern int exynos_init(void); 45#define exynos4210_register_clocks()
30extern void exynos4_map_io(void); 46#endif
31extern void exynos4_init_clocks(int xtal); 47
32extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); 48#ifdef CONFIG_SOC_EXYNOS4212
49void exynos4212_register_clocks(void);
33 50
34#else 51#else
35#define exynos4_init_clocks NULL 52#define exynos4212_register_clocks()
36#define exynos4_init_uarts NULL
37#define exynos4_map_io NULL
38#define exynos_init NULL
39#endif 53#endif
40 54
41#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ 55#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4ebb382c5979..33ab4e7558af 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -11,25 +11,53 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/cpuidle.h> 13#include <linux/cpuidle.h>
14#include <linux/cpu_pm.h>
14#include <linux/io.h> 15#include <linux/io.h>
15#include <linux/export.h> 16#include <linux/export.h>
16#include <linux/time.h> 17#include <linux/time.h>
17 18
18#include <asm/proc-fns.h> 19#include <asm/proc-fns.h>
20#include <asm/smp_scu.h>
21#include <asm/suspend.h>
22#include <asm/unified.h>
23#include <mach/regs-pmu.h>
24#include <mach/pmu.h>
25
26#include <plat/cpu.h>
27
28#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
29 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
30 (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
31#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
32 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
33 (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
34
35#define S5P_CHECK_AFTR 0xFCBA0D10
19 36
20static int exynos4_enter_idle(struct cpuidle_device *dev, 37static int exynos4_enter_idle(struct cpuidle_device *dev,
21 struct cpuidle_driver *drv, 38 struct cpuidle_driver *drv,
22 int index); 39 int index);
40static int exynos4_enter_lowpower(struct cpuidle_device *dev,
41 struct cpuidle_driver *drv,
42 int index);
23 43
24static struct cpuidle_state exynos4_cpuidle_set[] = { 44static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
25 [0] = { 45 [0] = {
26 .enter = exynos4_enter_idle, 46 .enter = exynos4_enter_idle,
27 .exit_latency = 1, 47 .exit_latency = 1,
28 .target_residency = 100000, 48 .target_residency = 100000,
29 .flags = CPUIDLE_FLAG_TIME_VALID, 49 .flags = CPUIDLE_FLAG_TIME_VALID,
30 .name = "IDLE", 50 .name = "C0",
31 .desc = "ARM clock gating(WFI)", 51 .desc = "ARM clock gating(WFI)",
32 }, 52 },
53 [1] = {
54 .enter = exynos4_enter_lowpower,
55 .exit_latency = 300,
56 .target_residency = 100000,
57 .flags = CPUIDLE_FLAG_TIME_VALID,
58 .name = "C1",
59 .desc = "ARM power down",
60 },
33}; 61};
34 62
35static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); 63static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
@@ -39,9 +67,102 @@ static struct cpuidle_driver exynos4_idle_driver = {
39 .owner = THIS_MODULE, 67 .owner = THIS_MODULE,
40}; 68};
41 69
70/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
71static void exynos4_set_wakeupmask(void)
72{
73 __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
74}
75
76static unsigned int g_pwr_ctrl, g_diag_reg;
77
78static void save_cpu_arch_register(void)
79{
80 /*read power control register*/
81 asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
82 /*read diagnostic register*/
83 asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
84 return;
85}
86
87static void restore_cpu_arch_register(void)
88{
89 /*write power control register*/
90 asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
91 /*write diagnostic register*/
92 asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
93 return;
94}
95
96static int idle_finisher(unsigned long flags)
97{
98 cpu_do_idle();
99 return 1;
100}
101
102static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
103 struct cpuidle_driver *drv,
104 int index)
105{
106 struct timeval before, after;
107 int idle_time;
108 unsigned long tmp;
109
110 local_irq_disable();
111 do_gettimeofday(&before);
112
113 exynos4_set_wakeupmask();
114
115 /* Set value of power down register for aftr mode */
116 exynos4_sys_powerdown_conf(SYS_AFTR);
117
118 __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
119 __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
120
121 save_cpu_arch_register();
122
123 /* Setting Central Sequence Register for power down mode */
124 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
125 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
126 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
127
128 cpu_pm_enter();
129 cpu_suspend(0, idle_finisher);
130
131#ifdef CONFIG_SMP
132 scu_enable(S5P_VA_SCU);
133#endif
134 cpu_pm_exit();
135
136 restore_cpu_arch_register();
137
138 /*
139 * If PMU failed while entering sleep mode, WFI will be
140 * ignored by PMU and then exiting cpu_do_idle().
141 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
142 * in this situation.
143 */
144 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
145 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
146 tmp |= S5P_CENTRAL_LOWPWR_CFG;
147 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
148 }
149
150 /* Clear wakeup state register */
151 __raw_writel(0x0, S5P_WAKEUP_STAT);
152
153 do_gettimeofday(&after);
154
155 local_irq_enable();
156 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
157 (after.tv_usec - before.tv_usec);
158
159 dev->last_residency = idle_time;
160 return index;
161}
162
42static int exynos4_enter_idle(struct cpuidle_device *dev, 163static int exynos4_enter_idle(struct cpuidle_device *dev,
43 struct cpuidle_driver *drv, 164 struct cpuidle_driver *drv,
44 int index) 165 int index)
45{ 166{
46 struct timeval before, after; 167 struct timeval before, after;
47 int idle_time; 168 int idle_time;
@@ -60,6 +181,22 @@ static int exynos4_enter_idle(struct cpuidle_device *dev,
60 return index; 181 return index;
61} 182}
62 183
184static int exynos4_enter_lowpower(struct cpuidle_device *dev,
185 struct cpuidle_driver *drv,
186 int index)
187{
188 int new_index = index;
189
190 /* This mode only can be entered when other core's are offline */
191 if (num_online_cpus() > 1)
192 new_index = drv->safe_state_index;
193
194 if (new_index == 0)
195 return exynos4_enter_idle(dev, drv, new_index);
196 else
197 return exynos4_enter_core0_aftr(dev, drv, new_index);
198}
199
63static int __init exynos4_init_cpuidle(void) 200static int __init exynos4_init_cpuidle(void)
64{ 201{
65 int i, max_cpuidle_state, cpu_id; 202 int i, max_cpuidle_state, cpu_id;
@@ -74,19 +211,25 @@ static int __init exynos4_init_cpuidle(void)
74 memcpy(&drv->states[i], &exynos4_cpuidle_set[i], 211 memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
75 sizeof(struct cpuidle_state)); 212 sizeof(struct cpuidle_state));
76 } 213 }
214 drv->safe_state_index = 0;
77 cpuidle_register_driver(&exynos4_idle_driver); 215 cpuidle_register_driver(&exynos4_idle_driver);
78 216
79 for_each_cpu(cpu_id, cpu_online_mask) { 217 for_each_cpu(cpu_id, cpu_online_mask) {
80 device = &per_cpu(exynos4_cpuidle_device, cpu_id); 218 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
81 device->cpu = cpu_id; 219 device->cpu = cpu_id;
82 220
83 device->state_count = drv->state_count; 221 if (cpu_id == 0)
222 device->state_count = (sizeof(exynos4_cpuidle_set) /
223 sizeof(struct cpuidle_state));
224 else
225 device->state_count = 1; /* Support IDLE only */
84 226
85 if (cpuidle_register_device(device)) { 227 if (cpuidle_register_device(device)) {
86 printk(KERN_ERR "CPUidle register device failed\n,"); 228 printk(KERN_ERR "CPUidle register device failed\n,");
87 return -EIO; 229 return -EIO;
88 } 230 }
89 } 231 }
232
90 return 0; 233 return 0;
91} 234}
92device_initcall(exynos4_init_cpuidle); 235device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de8e1d2..50ce5b0adcf1 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
242 .flags = IORESOURCE_MEM, 242 .flags = IORESOURCE_MEM,
243 }, 243 },
244 [1] = { 244 [1] = {
245 .start = IRQ_SATA, 245 .start = EXYNOS4_IRQ_SATA,
246 .end = IRQ_SATA, 246 .end = EXYNOS4_IRQ_SATA,
247 .flags = IORESOURCE_IRQ, 247 .flags = IORESOURCE_IRQ,
248 }, 248 },
249}; 249};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e53bf..7199e1ae79b4 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
304 .flags = IORESOURCE_DMA, 304 .flags = IORESOURCE_DMA,
305 }, 305 },
306 [4] = { 306 [4] = {
307 .start = IRQ_AC97, 307 .start = EXYNOS4_IRQ_AC97,
308 .end = IRQ_AC97, 308 .end = EXYNOS4_IRQ_AC97,
309 .flags = IORESOURCE_IRQ, 309 .flags = IORESOURCE_IRQ,
310 }, 310 },
311}; 311};
diff --git a/arch/arm/mach-exynos/dev-pd.c b/arch/arm/mach-exynos/dev-pd.c
deleted file mode 100644
index 3273f25d6a75..000000000000
--- a/arch/arm/mach-exynos/dev-pd.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dev-pd.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Power Domain support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17
18#include <mach/regs-pmu.h>
19
20#include <plat/pd.h>
21
22static int exynos4_pd_enable(struct device *dev)
23{
24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout;
26
27 __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
28
29 /* Wait max 1ms */
30 timeout = 10;
31 while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
32 != S5P_INT_LOCAL_PWR_EN) {
33 if (timeout == 0) {
34 printk(KERN_ERR "Power domain %s enable failed.\n",
35 dev_name(dev));
36 return -ETIMEDOUT;
37 }
38 timeout--;
39 udelay(100);
40 }
41
42 return 0;
43}
44
45static int exynos4_pd_disable(struct device *dev)
46{
47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout;
49
50 __raw_writel(0, pdata->base);
51
52 /* Wait max 1ms */
53 timeout = 10;
54 while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
55 if (timeout == 0) {
56 printk(KERN_ERR "Power domain %s disable failed.\n",
57 dev_name(dev));
58 return -ETIMEDOUT;
59 }
60 timeout--;
61 udelay(100);
62 }
63
64 return 0;
65}
66
67struct platform_device exynos4_device_pd[] = {
68 {
69 .name = "samsung-pd",
70 .id = 0,
71 .dev = {
72 .platform_data = &(struct samsung_pd_info) {
73 .enable = exynos4_pd_enable,
74 .disable = exynos4_pd_disable,
75 .base = S5P_PMU_MFC_CONF,
76 },
77 },
78 }, {
79 .name = "samsung-pd",
80 .id = 1,
81 .dev = {
82 .platform_data = &(struct samsung_pd_info) {
83 .enable = exynos4_pd_enable,
84 .disable = exynos4_pd_disable,
85 .base = S5P_PMU_G3D_CONF,
86 },
87 },
88 }, {
89 .name = "samsung-pd",
90 .id = 2,
91 .dev = {
92 .platform_data = &(struct samsung_pd_info) {
93 .enable = exynos4_pd_enable,
94 .disable = exynos4_pd_disable,
95 .base = S5P_PMU_LCD0_CONF,
96 },
97 },
98 }, {
99 .name = "samsung-pd",
100 .id = 3,
101 .dev = {
102 .platform_data = &(struct samsung_pd_info) {
103 .enable = exynos4_pd_enable,
104 .disable = exynos4_pd_disable,
105 .base = S5P_PMU_LCD1_CONF,
106 },
107 },
108 }, {
109 .name = "samsung-pd",
110 .id = 4,
111 .dev = {
112 .platform_data = &(struct samsung_pd_info) {
113 .enable = exynos4_pd_enable,
114 .disable = exynos4_pd_disable,
115 .base = S5P_PMU_TV_CONF,
116 },
117 },
118 }, {
119 .name = "samsung-pd",
120 .id = 5,
121 .dev = {
122 .platform_data = &(struct samsung_pd_info) {
123 .enable = exynos4_pd_enable,
124 .disable = exynos4_pd_disable,
125 .base = S5P_PMU_CAM_CONF,
126 },
127 },
128 }, {
129 .name = "samsung-pd",
130 .id = 6,
131 .dev = {
132 .platform_data = &(struct samsung_pd_info) {
133 .enable = exynos4_pd_enable,
134 .disable = exynos4_pd_disable,
135 .base = S5P_PMU_GPS_CONF,
136 },
137 },
138 },
139};
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 000000000000..2e85c022fd16
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Base EXYNOS UART resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/irq.h>
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/devs.h>
25
26#define EXYNOS_UART_RESOURCE(_series, _nr) \
27static struct resource exynos##_series##_uart##_nr##_resource[] = { \
28 [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
29 [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
30};
31
32EXYNOS_UART_RESOURCE(4, 0)
33EXYNOS_UART_RESOURCE(4, 1)
34EXYNOS_UART_RESOURCE(4, 2)
35EXYNOS_UART_RESOURCE(4, 3)
36
37struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
38 [0] = {
39 .resources = exynos4_uart0_resource,
40 .nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
41 },
42 [1] = {
43 .resources = exynos4_uart1_resource,
44 .nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
45 },
46 [2] = {
47 .resources = exynos4_uart2_resource,
48 .nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
49 },
50 [3] = {
51 .resources = exynos4_uart3_resource,
52 .nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
53 },
54};
55
56EXYNOS_UART_RESOURCE(5, 0)
57EXYNOS_UART_RESOURCE(5, 1)
58EXYNOS_UART_RESOURCE(5, 2)
59EXYNOS_UART_RESOURCE(5, 3)
60
61struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
62 [0] = {
63 .resources = exynos5_uart0_resource,
64 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
65 },
66 [1] = {
67 .resources = exynos5_uart1_resource,
68 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
69 },
70 [2] = {
71 .resources = exynos5_uart2_resource,
72 .nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
73 },
74 [3] = {
75 .resources = exynos5_uart3_resource,
76 .nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
77 },
78};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index b10fcd270f07..3983abee4264 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -29,6 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <plat/devs.h> 30#include <plat/devs.h>
31#include <plat/irqs.h> 31#include <plat/irqs.h>
32#include <plat/cpu.h>
32 33
33#include <mach/map.h> 34#include <mach/map.h>
34#include <mach/irqs.h> 35#include <mach/irqs.h>
@@ -36,7 +37,7 @@
36 37
37static u64 dma_dmamask = DMA_BIT_MASK(32); 38static u64 dma_dmamask = DMA_BIT_MASK(32);
38 39
39u8 pdma0_peri[] = { 40static u8 exynos4210_pdma0_peri[] = {
40 DMACH_PCM0_RX, 41 DMACH_PCM0_RX,
41 DMACH_PCM0_TX, 42 DMACH_PCM0_TX,
42 DMACH_PCM2_RX, 43 DMACH_PCM2_RX,
@@ -69,28 +70,47 @@ u8 pdma0_peri[] = {
69 DMACH_AC97_PCMOUT, 70 DMACH_AC97_PCMOUT,
70}; 71};
71 72
72struct dma_pl330_platdata exynos4_pdma0_pdata = { 73static u8 exynos4212_pdma0_peri[] = {
73 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 74 DMACH_PCM0_RX,
74 .peri_id = pdma0_peri, 75 DMACH_PCM0_TX,
76 DMACH_PCM2_RX,
77 DMACH_PCM2_TX,
78 DMACH_MIPI_HSI0,
79 DMACH_MIPI_HSI1,
80 DMACH_SPI0_RX,
81 DMACH_SPI0_TX,
82 DMACH_SPI2_RX,
83 DMACH_SPI2_TX,
84 DMACH_I2S0S_TX,
85 DMACH_I2S0_RX,
86 DMACH_I2S0_TX,
87 DMACH_I2S2_RX,
88 DMACH_I2S2_TX,
89 DMACH_UART0_RX,
90 DMACH_UART0_TX,
91 DMACH_UART2_RX,
92 DMACH_UART2_TX,
93 DMACH_UART4_RX,
94 DMACH_UART4_TX,
95 DMACH_SLIMBUS0_RX,
96 DMACH_SLIMBUS0_TX,
97 DMACH_SLIMBUS2_RX,
98 DMACH_SLIMBUS2_TX,
99 DMACH_SLIMBUS4_RX,
100 DMACH_SLIMBUS4_TX,
101 DMACH_AC97_MICIN,
102 DMACH_AC97_PCMIN,
103 DMACH_AC97_PCMOUT,
104 DMACH_MIPI_HSI4,
105 DMACH_MIPI_HSI5,
75}; 106};
76 107
77struct amba_device exynos4_device_pdma0 = { 108struct dma_pl330_platdata exynos4_pdma0_pdata;
78 .dev = { 109
79 .init_name = "dma-pl330.0", 110static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
80 .dma_mask = &dma_dmamask, 111 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
81 .coherent_dma_mask = DMA_BIT_MASK(32),
82 .platform_data = &exynos4_pdma0_pdata,
83 },
84 .res = {
85 .start = EXYNOS4_PA_PDMA0,
86 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
87 .flags = IORESOURCE_MEM,
88 },
89 .irq = {IRQ_PDMA0, NO_IRQ},
90 .periphid = 0x00041330,
91};
92 112
93u8 pdma1_peri[] = { 113static u8 exynos4210_pdma1_peri[] = {
94 DMACH_PCM0_RX, 114 DMACH_PCM0_RX,
95 DMACH_PCM0_TX, 115 DMACH_PCM0_TX,
96 DMACH_PCM1_RX, 116 DMACH_PCM1_RX,
@@ -118,39 +138,94 @@ u8 pdma1_peri[] = {
118 DMACH_SLIMBUS5_TX, 138 DMACH_SLIMBUS5_TX,
119}; 139};
120 140
121struct dma_pl330_platdata exynos4_pdma1_pdata = { 141static u8 exynos4212_pdma1_peri[] = {
122 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 142 DMACH_PCM0_RX,
123 .peri_id = pdma1_peri, 143 DMACH_PCM0_TX,
144 DMACH_PCM1_RX,
145 DMACH_PCM1_TX,
146 DMACH_MIPI_HSI2,
147 DMACH_MIPI_HSI3,
148 DMACH_SPI1_RX,
149 DMACH_SPI1_TX,
150 DMACH_I2S0S_TX,
151 DMACH_I2S0_RX,
152 DMACH_I2S0_TX,
153 DMACH_I2S1_RX,
154 DMACH_I2S1_TX,
155 DMACH_UART0_RX,
156 DMACH_UART0_TX,
157 DMACH_UART1_RX,
158 DMACH_UART1_TX,
159 DMACH_UART3_RX,
160 DMACH_UART3_TX,
161 DMACH_SLIMBUS1_RX,
162 DMACH_SLIMBUS1_TX,
163 DMACH_SLIMBUS3_RX,
164 DMACH_SLIMBUS3_TX,
165 DMACH_SLIMBUS5_RX,
166 DMACH_SLIMBUS5_TX,
167 DMACH_SLIMBUS0AUX_RX,
168 DMACH_SLIMBUS0AUX_TX,
169 DMACH_SPDIF,
170 DMACH_MIPI_HSI6,
171 DMACH_MIPI_HSI7,
124}; 172};
125 173
126struct amba_device exynos4_device_pdma1 = { 174static struct dma_pl330_platdata exynos4_pdma1_pdata;
127 .dev = { 175
128 .init_name = "dma-pl330.1", 176static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
129 .dma_mask = &dma_dmamask, 177 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
130 .coherent_dma_mask = DMA_BIT_MASK(32), 178
131 .platform_data = &exynos4_pdma1_pdata, 179static u8 mdma_peri[] = {
132 }, 180 DMACH_MTOM_0,
133 .res = { 181 DMACH_MTOM_1,
134 .start = EXYNOS4_PA_PDMA1, 182 DMACH_MTOM_2,
135 .end = EXYNOS4_PA_PDMA1 + SZ_4K, 183 DMACH_MTOM_3,
136 .flags = IORESOURCE_MEM, 184 DMACH_MTOM_4,
137 }, 185 DMACH_MTOM_5,
138 .irq = {IRQ_PDMA1, NO_IRQ}, 186 DMACH_MTOM_6,
139 .periphid = 0x00041330, 187 DMACH_MTOM_7,
188};
189
190static struct dma_pl330_platdata exynos4_mdma1_pdata = {
191 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
192 .peri_id = mdma_peri,
140}; 193};
141 194
195static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
196 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
197
142static int __init exynos4_dma_init(void) 198static int __init exynos4_dma_init(void)
143{ 199{
144 if (of_have_populated_dt()) 200 if (of_have_populated_dt())
145 return 0; 201 return 0;
146 202
203 if (soc_is_exynos4210()) {
204 exynos4_pdma0_pdata.nr_valid_peri =
205 ARRAY_SIZE(exynos4210_pdma0_peri);
206 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
207 exynos4_pdma1_pdata.nr_valid_peri =
208 ARRAY_SIZE(exynos4210_pdma1_peri);
209 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
210 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
211 exynos4_pdma0_pdata.nr_valid_peri =
212 ARRAY_SIZE(exynos4212_pdma0_peri);
213 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
214 exynos4_pdma1_pdata.nr_valid_peri =
215 ARRAY_SIZE(exynos4212_pdma1_peri);
216 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
217 }
218
147 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); 219 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
148 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); 220 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
149 amba_device_register(&exynos4_device_pdma0, &iomem_resource); 221 amba_device_register(&exynos4_pdma0_device, &iomem_resource);
150 222
151 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); 223 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
152 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); 224 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
153 amba_device_register(&exynos4_device_pdma1, &iomem_resource); 225 amba_device_register(&exynos4_pdma1_device, &iomem_resource);
226
227 dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
228 amba_device_register(&exynos4_mdma1_device, &iomem_resource);
154 229
155 return 0; 230 return 0;
156} 231}
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index da70e7e39937..dd1ad55524c9 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/smp_plat.h>
19 20
20#include <mach/regs-pmu.h> 21#include <mach/regs-pmu.h>
21 22
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 3df27f2d5034..7517c3f417af 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -32,3 +32,5 @@ struct exynos_dvfs_info {
32}; 32};
33 33
34extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *); 34extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
35extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
36extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a6..6c857ff0b5d8 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
21 */ 21 */
22 22
23 .macro addruart, rp, rv, tmp 23 .macro addruart, rp, rv, tmp
24 ldr \rp, = S3C_PA_UART 24 mov \rp, #0x10000000
25 ldr \rv, = S3C_VA_UART 25 ldr \rp, [\rp, #0x0]
26 and \rp, \rp, #0xf00000
27 teq \rp, #0x500000 @@ EXYNOS5
28 ldreq \rp, =EXYNOS5_PA_UART
29 movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
30 ldr \rv, =S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0 31#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) 32 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) 33 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
deleted file mode 100644
index 3ba4f547534b..000000000000
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
1/* arch/arm/mach-exynos4/include/mach/entry-macro.S
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 *
5 * Low-level IRQ helper macros for EXYNOS4 platforms
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10*/
11
12 .macro disable_fiq
13 .endm
14
15 .macro arch_ret_to_user, tmp1, tmp2
16 .endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644
index a07fcbf55251..000000000000
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Header file for exynos4 clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_CLOCK_H
15#define __ASM_ARCH_CLOCK_H __FILE__
16
17#include <linux/clk.h>
18
19extern struct clk clk_sclk_hdmi27m;
20extern struct clk clk_sclk_usbphy0;
21extern struct clk clk_sclk_usbphy1;
22extern struct clk clk_sclk_hdmiphy;
23
24extern struct clksrc_clk clk_sclk_apll;
25extern struct clksrc_clk clk_mout_mpll;
26extern struct clksrc_clk clk_aclk_133;
27extern struct clksrc_clk clk_mout_epll;
28extern struct clksrc_clk clk_sclk_vpll;
29
30extern struct clk *clkset_corebus_list[];
31extern struct clksrc_sources clkset_mout_corebus;
32
33extern struct clk *clkset_aclk_top_list[];
34extern struct clksrc_sources clkset_aclk;
35
36extern struct clk *clkset_group_list[];
37extern struct clksrc_sources clkset_group;
38
39extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
40extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
41extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
42
43#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 80523ca9bb49..d7498afe036a 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/gpio.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - GPIO lib support 5 * EXYNOS - GPIO lib support
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,9 +12,13 @@
13#ifndef __ASM_ARCH_GPIO_H 12#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__ 13#define __ASM_ARCH_GPIO_H __FILE__
15 14
16/* Practically, GPIO banks up to GPZ are the configurable gpio banks */ 15/* Macro for EXYNOS GPIO numbering */
16
17#define EXYNOS_GPIO_NEXT(__gpio) \
18 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
19
20/* EXYNOS4 GPIO bank sizes */
17 21
18/* GPIO bank sizes */
19#define EXYNOS4_GPIO_A0_NR (8) 22#define EXYNOS4_GPIO_A0_NR (8)
20#define EXYNOS4_GPIO_A1_NR (6) 23#define EXYNOS4_GPIO_A1_NR (6)
21#define EXYNOS4_GPIO_B_NR (8) 24#define EXYNOS4_GPIO_B_NR (8)
@@ -54,52 +57,50 @@
54#define EXYNOS4_GPIO_Y6_NR (8) 57#define EXYNOS4_GPIO_Y6_NR (8)
55#define EXYNOS4_GPIO_Z_NR (7) 58#define EXYNOS4_GPIO_Z_NR (7)
56 59
57/* GPIO bank numbers */ 60/* EXYNOS4 GPIO bank numbers */
58
59#define EXYNOS4_GPIO_NEXT(__gpio) \
60 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
61 61
62enum s5p_gpio_number { 62enum exynos4_gpio_number {
63 EXYNOS4_GPIO_A0_START = 0, 63 EXYNOS4_GPIO_A0_START = 0,
64 EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0), 64 EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
65 EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1), 65 EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
66 EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B), 66 EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
67 EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0), 67 EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
68 EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1), 68 EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
69 EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0), 69 EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
70 EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1), 70 EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
71 EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0), 71 EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
72 EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1), 72 EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
73 EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2), 73 EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
74 EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3), 74 EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
75 EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4), 75 EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
76 EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0), 76 EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
77 EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1), 77 EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
78 EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2), 78 EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
79 EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3), 79 EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
80 EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0), 80 EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
81 EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1), 81 EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
82 EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0), 82 EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
83 EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1), 83 EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
84 EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2), 84 EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
85 EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3), 85 EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
86 EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0), 86 EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
87 EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1), 87 EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
88 EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2), 88 EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
89 EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0), 89 EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
90 EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1), 90 EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
91 EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2), 91 EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
92 EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3), 92 EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
93 EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0), 93 EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
94 EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1), 94 EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
95 EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2), 95 EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
96 EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3), 96 EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
97 EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4), 97 EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
98 EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5), 98 EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
99 EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6), 99 EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
100}; 100};
101 101
102/* EXYNOS4 GPIO number definitions */ 102/* EXYNOS4 GPIO number definitions */
103
103#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr)) 104#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
104#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr)) 105#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
105#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr)) 106#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
@@ -139,11 +140,147 @@ enum s5p_gpio_number {
139#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr)) 140#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
140 141
141/* the end of the EXYNOS4 specific gpios */ 142/* the end of the EXYNOS4 specific gpios */
143
142#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1) 144#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
143#define S3C_GPIO_END EXYNOS4_GPIO_END
144 145
145/* define the number of gpios we need to the one after the GPZ() range */ 146/* EXYNOS5 GPIO bank sizes */
146#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \ 147
147 CONFIG_SAMSUNG_GPIO_EXTRA + 1) 148#define EXYNOS5_GPIO_A0_NR (8)
149#define EXYNOS5_GPIO_A1_NR (6)
150#define EXYNOS5_GPIO_A2_NR (8)
151#define EXYNOS5_GPIO_B0_NR (5)
152#define EXYNOS5_GPIO_B1_NR (5)
153#define EXYNOS5_GPIO_B2_NR (4)
154#define EXYNOS5_GPIO_B3_NR (4)
155#define EXYNOS5_GPIO_C0_NR (7)
156#define EXYNOS5_GPIO_C1_NR (7)
157#define EXYNOS5_GPIO_C2_NR (7)
158#define EXYNOS5_GPIO_C3_NR (7)
159#define EXYNOS5_GPIO_D0_NR (8)
160#define EXYNOS5_GPIO_D1_NR (8)
161#define EXYNOS5_GPIO_Y0_NR (6)
162#define EXYNOS5_GPIO_Y1_NR (4)
163#define EXYNOS5_GPIO_Y2_NR (6)
164#define EXYNOS5_GPIO_Y3_NR (8)
165#define EXYNOS5_GPIO_Y4_NR (8)
166#define EXYNOS5_GPIO_Y5_NR (8)
167#define EXYNOS5_GPIO_Y6_NR (8)
168#define EXYNOS5_GPIO_X0_NR (8)
169#define EXYNOS5_GPIO_X1_NR (8)
170#define EXYNOS5_GPIO_X2_NR (8)
171#define EXYNOS5_GPIO_X3_NR (8)
172#define EXYNOS5_GPIO_E0_NR (8)
173#define EXYNOS5_GPIO_E1_NR (2)
174#define EXYNOS5_GPIO_F0_NR (4)
175#define EXYNOS5_GPIO_F1_NR (4)
176#define EXYNOS5_GPIO_G0_NR (8)
177#define EXYNOS5_GPIO_G1_NR (8)
178#define EXYNOS5_GPIO_G2_NR (2)
179#define EXYNOS5_GPIO_H0_NR (4)
180#define EXYNOS5_GPIO_H1_NR (8)
181#define EXYNOS5_GPIO_V0_NR (8)
182#define EXYNOS5_GPIO_V1_NR (8)
183#define EXYNOS5_GPIO_V2_NR (8)
184#define EXYNOS5_GPIO_V3_NR (8)
185#define EXYNOS5_GPIO_V4_NR (2)
186#define EXYNOS5_GPIO_Z_NR (7)
187
188/* EXYNOS5 GPIO bank numbers */
189
190enum exynos5_gpio_number {
191 EXYNOS5_GPIO_A0_START = 0,
192 EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
193 EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
194 EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
195 EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
196 EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
197 EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
198 EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
199 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
200 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
201 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
202 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
203 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
204 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
205 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
206 EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
207 EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
208 EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
209 EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
210 EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
211 EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
212 EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
213 EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
214 EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
215 EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
216 EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
217 EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
218 EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
219 EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
220 EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
221 EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
222 EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
223 EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
224 EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
225 EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
226 EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
227 EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
228 EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
229 EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
230};
231
232/* EXYNOS5 GPIO number definitions */
233
234#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
235#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
236#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
237#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
238#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
239#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
240#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
241#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
242#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
243#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
244#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
245#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
246#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
247#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
248#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
249#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
250#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
251#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
252#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
253#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
254#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
255#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
256#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
257#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
258#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
259#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
260#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
261#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
262#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
263#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
264#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
265#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
266#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
267#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
268#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
269#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
270#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
271#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
272#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
273
274/* the end of the EXYNOS5 specific gpios */
275
276#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
277
278/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
279
280#define S3C_GPIO_END (EXYNOS5_GPIO_END)
281
282/* define the number of gpios */
283
284#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
148 285
149#endif /* __ASM_ARCH_GPIO_H */ 286#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce04789a..9bee8535d9e0 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/irqs.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - IRQ definitions 5 * EXYNOS - IRQ definitions
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -17,158 +16,450 @@
17 16
18/* PPI: Private Peripheral Interrupt */ 17/* PPI: Private Peripheral Interrupt */
19 18
20#define IRQ_PPI(x) (x+16) 19#define IRQ_PPI(x) (x + 16)
21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23 20
24/* SPI: Shared Peripheral Interrupt */ 21/* SPI: Shared Peripheral Interrupt */
25 22
26#define IRQ_SPI(x) (x+32) 23#define IRQ_SPI(x) (x + 32)
27 24
28#define IRQ_EINT0 IRQ_SPI(16) 25/* COMBINER */
29#define IRQ_EINT1 IRQ_SPI(17) 26
30#define IRQ_EINT2 IRQ_SPI(18) 27#define MAX_IRQ_IN_COMBINER 8
31#define IRQ_EINT3 IRQ_SPI(19) 28#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
32#define IRQ_EINT4 IRQ_SPI(20) 29#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
33#define IRQ_EINT5 IRQ_SPI(21) 30
34#define IRQ_EINT6 IRQ_SPI(22) 31/* For EXYNOS4 and EXYNOS5 */
35#define IRQ_EINT7 IRQ_SPI(23) 32
36#define IRQ_EINT8 IRQ_SPI(24) 33#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
37#define IRQ_EINT9 IRQ_SPI(25) 34
38#define IRQ_EINT10 IRQ_SPI(26) 35#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
39#define IRQ_EINT11 IRQ_SPI(27) 36
40#define IRQ_EINT12 IRQ_SPI(28) 37/* For EXYNOS4 SoCs */
41#define IRQ_EINT13 IRQ_SPI(29) 38
42#define IRQ_EINT14 IRQ_SPI(30) 39#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
43#define IRQ_EINT15 IRQ_SPI(31) 40#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
44#define IRQ_EINT16_31 IRQ_SPI(32) 41#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
45 42#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
46#define IRQ_PDMA0 IRQ_SPI(35) 43#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
47#define IRQ_PDMA1 IRQ_SPI(36) 44#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
48#define IRQ_TIMER0_VIC IRQ_SPI(37) 45#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
49#define IRQ_TIMER1_VIC IRQ_SPI(38) 46#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
50#define IRQ_TIMER2_VIC IRQ_SPI(39) 47#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
51#define IRQ_TIMER3_VIC IRQ_SPI(40) 48#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
52#define IRQ_TIMER4_VIC IRQ_SPI(41) 49#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
53#define IRQ_MCT_L0 IRQ_SPI(42) 50#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
54#define IRQ_WDT IRQ_SPI(43) 51#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
55#define IRQ_RTC_ALARM IRQ_SPI(44) 52#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
56#define IRQ_RTC_TIC IRQ_SPI(45) 53#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
57#define IRQ_GPIO_XB IRQ_SPI(46) 54#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
58#define IRQ_GPIO_XA IRQ_SPI(47) 55
59#define IRQ_MCT_L1 IRQ_SPI(48) 56#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
60 57#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
61#define IRQ_UART0 IRQ_SPI(52) 58#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
62#define IRQ_UART1 IRQ_SPI(53) 59#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
63#define IRQ_UART2 IRQ_SPI(54) 60#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
64#define IRQ_UART3 IRQ_SPI(55) 61#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
65#define IRQ_UART4 IRQ_SPI(56) 62#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
66#define IRQ_MCT_G0 IRQ_SPI(57) 63#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
67#define IRQ_IIC IRQ_SPI(58) 64#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
68#define IRQ_IIC1 IRQ_SPI(59) 65#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
69#define IRQ_IIC2 IRQ_SPI(60) 66#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
70#define IRQ_IIC3 IRQ_SPI(61) 67#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
71#define IRQ_IIC4 IRQ_SPI(62) 68#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
72#define IRQ_IIC5 IRQ_SPI(63) 69#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
73#define IRQ_IIC6 IRQ_SPI(64) 70#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
74#define IRQ_IIC7 IRQ_SPI(65) 71#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
75#define IRQ_SPI0 IRQ_SPI(66) 72
76#define IRQ_SPI1 IRQ_SPI(67) 73#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
77#define IRQ_SPI2 IRQ_SPI(68) 74#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
78 75#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
79#define IRQ_USB_HOST IRQ_SPI(70) 76#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
80#define IRQ_USB_HSOTG IRQ_SPI(71) 77#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
81#define IRQ_MODEM_IF IRQ_SPI(72) 78#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
82#define IRQ_HSMMC0 IRQ_SPI(73) 79#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
83#define IRQ_HSMMC1 IRQ_SPI(74) 80#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
84#define IRQ_HSMMC2 IRQ_SPI(75) 81#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
85#define IRQ_HSMMC3 IRQ_SPI(76) 82#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
86#define IRQ_DWMCI IRQ_SPI(77) 83#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
87 84#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
88#define IRQ_MIPI_CSIS0 IRQ_SPI(78) 85#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
89#define IRQ_MIPI_CSIS1 IRQ_SPI(80) 86#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
90 87#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
91#define IRQ_ONENAND_AUDI IRQ_SPI(82) 88#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
92#define IRQ_ROTATOR IRQ_SPI(83) 89#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
93#define IRQ_FIMC0 IRQ_SPI(84) 90
94#define IRQ_FIMC1 IRQ_SPI(85) 91#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
95#define IRQ_FIMC2 IRQ_SPI(86) 92#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
96#define IRQ_FIMC3 IRQ_SPI(87) 93#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
97#define IRQ_JPEG IRQ_SPI(88) 94#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
98#define IRQ_2D IRQ_SPI(89) 95#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
99#define IRQ_PCIE IRQ_SPI(90) 96#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
100 97#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
101#define IRQ_MIXER IRQ_SPI(91) 98#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
102#define IRQ_HDMI IRQ_SPI(92) 99
103#define IRQ_IIC_HDMIPHY IRQ_SPI(93) 100#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
104#define IRQ_MFC IRQ_SPI(94) 101#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
105#define IRQ_SDO IRQ_SPI(95) 102
106 103#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
107#define IRQ_AUDIO_SS IRQ_SPI(96) 104#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
108#define IRQ_I2S0 IRQ_SPI(97) 105#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
109#define IRQ_I2S1 IRQ_SPI(98) 106#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
110#define IRQ_I2S2 IRQ_SPI(99) 107#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
111#define IRQ_AC97 IRQ_SPI(100) 108#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
112 109#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
113#define IRQ_SPDIF IRQ_SPI(104) 110#define EXYNOS4_IRQ_2D IRQ_SPI(89)
114#define IRQ_ADC0 IRQ_SPI(105) 111#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
115#define IRQ_PEN0 IRQ_SPI(106) 112
116#define IRQ_ADC1 IRQ_SPI(107) 113#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
117#define IRQ_PEN1 IRQ_SPI(108) 114#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
118#define IRQ_KEYPAD IRQ_SPI(109) 115#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
119#define IRQ_PMU IRQ_SPI(110) 116#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
120#define IRQ_GPS IRQ_SPI(111) 117#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
121#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) 118
122#define IRQ_SLIMBUS IRQ_SPI(113) 119#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
123 120#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
124#define IRQ_TSI IRQ_SPI(115) 121#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
125#define IRQ_SATA IRQ_SPI(116) 122#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
126 123#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
127#define MAX_IRQ_IN_COMBINER 8 124
128#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) 125#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
129#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 126#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
130 127#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
131#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 128#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
132#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) 129#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
133#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) 130#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
134#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) 131#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
135#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) 132#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
136#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) 133#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
137#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) 134#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
138#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) 135
139 136#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
140#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) 137#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
141#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) 138
142#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) 139#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
143#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) 140#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
144#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) 141#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
145#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) 142#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
146#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 143#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
147#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 144#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
148 145#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
149#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) 146#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
150#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) 147
151#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) 148#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
152 149#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
153#define MAX_COMBINER_NR 16 150#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
154 151#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
155#define IRQ_ADC IRQ_ADC0 152#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
156#define IRQ_TC IRQ_PEN0 153#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
157 154#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
158#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 155#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
159 156
160#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) 157#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
161#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) 158#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
162 159#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
163/* optional GPIO interrupts */ 160
164#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32) 161#define EXYNOS4_MAX_COMBINER_NR 16
165#define IRQ_GPIO1_NR_GROUPS 16 162
166#define IRQ_GPIO2_NR_GROUPS 9 163#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
167#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 164#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
168 165
169#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) 166/*
167 * For Compatibility:
168 * the default is for EXYNOS4, and
169 * for exynos5, should be re-mapped at function
170 */
171
172#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
173#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
174#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
175#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
176#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
177
178#define IRQ_WDT EXYNOS4_IRQ_WDT
179#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
180#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
181#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
182#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
183
184#define IRQ_IIC EXYNOS4_IRQ_IIC
185#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
186#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
187#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
188#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
189#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
190
191#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
192
193#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
194#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
195#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
196#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
197
198#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
199
200#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
201
202#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
203#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
204#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
205#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
206#define IRQ_JPEG EXYNOS4_IRQ_JPEG
207#define IRQ_2D EXYNOS4_IRQ_2D
208
209#define IRQ_MIXER EXYNOS4_IRQ_MIXER
210#define IRQ_HDMI EXYNOS4_IRQ_HDMI
211#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
212#define IRQ_MFC EXYNOS4_IRQ_MFC
213#define IRQ_SDO EXYNOS4_IRQ_SDO
214
215#define IRQ_ADC EXYNOS4_IRQ_ADC0
216#define IRQ_TC EXYNOS4_IRQ_PEN0
217
218#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
219#define IRQ_PMU EXYNOS4_IRQ_PMU
220
221#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
222#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
223#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
224#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
225#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
226#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
227#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
228#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
229
230#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
231#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
232#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
233#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
234#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
235#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
236#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
237#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
238
239#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
240#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
241#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
242
243#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
244#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
245
246/* For EXYNOS5 SoCs */
247
248#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
249#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
250#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
251#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
252#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
253#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
254#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
255#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
256#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
257#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
258#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
259#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
260#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
261#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
262#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
263#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
264#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
265#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
266#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
267#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
268#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
269#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
270#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
271#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
272#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
273#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
274#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
275#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
276#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
277#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
278#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
279#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
280#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
281#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
282#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
283#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
284#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
285#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
286#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
287#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
288#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
289#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
290#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
291#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
292#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
293#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
294#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
295#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
296#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
297#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
298#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
299#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
300#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
301#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
302#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
303#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
304#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
305#define EXYNOS5_IRQ_2D IRQ_SPI(91)
306#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
307#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
308#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
309#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
310#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
311#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
312#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
313#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
314#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
315#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
316#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
317#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
318#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
319#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
320#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
321
322#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
323#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
324#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
325#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
326#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
327#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
328#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
329#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
330#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
331
332#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
333#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
334#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
335#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
336#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
337
338#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
339#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
340
341#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
342#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
343#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
344#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
345#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
346#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
347#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
348#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
349
350#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
351#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
352#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
353#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
354#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
355#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
356
357#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
358#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
359#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
360#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
361
362#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
363#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
364#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
365#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
366#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
367#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
368#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
369#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
370
371#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
372#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
373#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
374#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
375#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
376#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
377#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
378#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
379
380#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
381#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
382#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
383#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
384#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
385#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
386#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
387#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
388
389#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
390#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
391
392#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
393#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
394
395#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
396#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
397#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
398#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
399#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
400
401#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
402#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
403#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
404#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
405
406#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
407#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
408#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
409
410#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
411#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
412#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
413#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
414#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
415#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
416#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
417
418#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
419#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
420#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
421#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
422#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
423
424#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
425#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
426
427#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
428#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
429
430#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
431#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
432
433#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
434#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
435
436#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
437#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
438
439#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
440#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
441
442#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
443#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
444
445#define EXYNOS5_MAX_COMBINER_NR 32
446
447#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
448#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
449#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
450#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
451
452#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
453 EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
454
455#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
456#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
457#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
458#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
459#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
170 460
171/* Set the default NR_IRQS */ 461/* Set the default NR_IRQS */
172#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) 462
463#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
173 464
174#endif /* __ASM_ARCH_IRQS_H */ 465#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22a2bb3..024d38ff1718 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,12 +25,17 @@
25 25
26#define EXYNOS4_PA_SYSRAM0 0x02025000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000 27#define EXYNOS4_PA_SYSRAM1 0x02020000
28#define EXYNOS5_PA_SYSRAM 0x02020000
28 29
29#define EXYNOS4_PA_FIMC0 0x11800000 30#define EXYNOS4_PA_FIMC0 0x11800000
30#define EXYNOS4_PA_FIMC1 0x11810000 31#define EXYNOS4_PA_FIMC1 0x11810000
31#define EXYNOS4_PA_FIMC2 0x11820000 32#define EXYNOS4_PA_FIMC2 0x11820000
32#define EXYNOS4_PA_FIMC3 0x11830000 33#define EXYNOS4_PA_FIMC3 0x11830000
33 34
35#define EXYNOS4_PA_JPEG 0x11840000
36
37#define EXYNOS4_PA_G2D 0x12800000
38
34#define EXYNOS4_PA_I2S0 0x03830000 39#define EXYNOS4_PA_I2S0 0x03830000
35#define EXYNOS4_PA_I2S1 0xE3100000 40#define EXYNOS4_PA_I2S1 0xE3100000
36#define EXYNOS4_PA_I2S2 0xE2A00000 41#define EXYNOS4_PA_I2S2 0xE2A00000
@@ -44,30 +49,44 @@
44#define EXYNOS4_PA_ONENAND 0x0C000000 49#define EXYNOS4_PA_ONENAND 0x0C000000
45#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 50#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
46 51
47#define EXYNOS4_PA_CHIPID 0x10000000 52#define EXYNOS_PA_CHIPID 0x10000000
48 53
49#define EXYNOS4_PA_SYSCON 0x10010000 54#define EXYNOS4_PA_SYSCON 0x10010000
55#define EXYNOS5_PA_SYSCON 0x10050100
56
50#define EXYNOS4_PA_PMU 0x10020000 57#define EXYNOS4_PA_PMU 0x10020000
58#define EXYNOS5_PA_PMU 0x10040000
59
51#define EXYNOS4_PA_CMU 0x10030000 60#define EXYNOS4_PA_CMU 0x10030000
61#define EXYNOS5_PA_CMU 0x10010000
52 62
53#define EXYNOS4_PA_SYSTIMER 0x10050000 63#define EXYNOS4_PA_SYSTIMER 0x10050000
64#define EXYNOS5_PA_SYSTIMER 0x101C0000
65
54#define EXYNOS4_PA_WATCHDOG 0x10060000 66#define EXYNOS4_PA_WATCHDOG 0x10060000
67#define EXYNOS5_PA_WATCHDOG 0x101D0000
68
55#define EXYNOS4_PA_RTC 0x10070000 69#define EXYNOS4_PA_RTC 0x10070000
56 70
57#define EXYNOS4_PA_KEYPAD 0x100A0000 71#define EXYNOS4_PA_KEYPAD 0x100A0000
58 72
59#define EXYNOS4_PA_DMC0 0x10400000 73#define EXYNOS4_PA_DMC0 0x10400000
74#define EXYNOS4_PA_DMC1 0x10410000
60 75
61#define EXYNOS4_PA_COMBINER 0x10440000 76#define EXYNOS4_PA_COMBINER 0x10440000
77#define EXYNOS5_PA_COMBINER 0x10440000
62 78
63#define EXYNOS4_PA_GIC_CPU 0x10480000 79#define EXYNOS4_PA_GIC_CPU 0x10480000
64#define EXYNOS4_PA_GIC_DIST 0x10490000 80#define EXYNOS4_PA_GIC_DIST 0x10490000
81#define EXYNOS5_PA_GIC_CPU 0x10480000
82#define EXYNOS5_PA_GIC_DIST 0x10490000
65 83
66#define EXYNOS4_PA_COREPERI 0x10500000 84#define EXYNOS4_PA_COREPERI 0x10500000
67#define EXYNOS4_PA_TWD 0x10500600 85#define EXYNOS4_PA_TWD 0x10500600
68#define EXYNOS4_PA_L2CC 0x10502000 86#define EXYNOS4_PA_L2CC 0x10502000
69 87
70#define EXYNOS4_PA_MDMA 0x10810000 88#define EXYNOS4_PA_MDMA0 0x10810000
89#define EXYNOS4_PA_MDMA1 0x12840000
71#define EXYNOS4_PA_PDMA0 0x12680000 90#define EXYNOS4_PA_PDMA0 0x12680000
72#define EXYNOS4_PA_PDMA1 0x12690000 91#define EXYNOS4_PA_PDMA1 0x12690000
73 92
@@ -91,10 +110,13 @@
91#define EXYNOS4_PA_SPI1 0x13930000 110#define EXYNOS4_PA_SPI1 0x13930000
92#define EXYNOS4_PA_SPI2 0x13940000 111#define EXYNOS4_PA_SPI2 0x13940000
93 112
94
95#define EXYNOS4_PA_GPIO1 0x11400000 113#define EXYNOS4_PA_GPIO1 0x11400000
96#define EXYNOS4_PA_GPIO2 0x11000000 114#define EXYNOS4_PA_GPIO2 0x11000000
97#define EXYNOS4_PA_GPIO3 0x03860000 115#define EXYNOS4_PA_GPIO3 0x03860000
116#define EXYNOS5_PA_GPIO1 0x11400000
117#define EXYNOS5_PA_GPIO2 0x13400000
118#define EXYNOS5_PA_GPIO3 0x10D10000
119#define EXYNOS5_PA_GPIO4 0x03860000
98 120
99#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 121#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
100#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 122#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
@@ -109,6 +131,7 @@
109#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 131#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
110 132
111#define EXYNOS4_PA_SROMC 0x12570000 133#define EXYNOS4_PA_SROMC 0x12570000
134#define EXYNOS5_PA_SROMC 0x12250000
112 135
113#define EXYNOS4_PA_EHCI 0x12580000 136#define EXYNOS4_PA_EHCI 0x12580000
114#define EXYNOS4_PA_OHCI 0x12590000 137#define EXYNOS4_PA_OHCI 0x12590000
@@ -116,6 +139,7 @@
116#define EXYNOS4_PA_MFC 0x13400000 139#define EXYNOS4_PA_MFC 0x13400000
117 140
118#define EXYNOS4_PA_UART 0x13800000 141#define EXYNOS4_PA_UART 0x13800000
142#define EXYNOS5_PA_UART 0x12C00000
119 143
120#define EXYNOS4_PA_VP 0x12C00000 144#define EXYNOS4_PA_VP 0x12C00000
121#define EXYNOS4_PA_MIXER 0x12C10000 145#define EXYNOS4_PA_MIXER 0x12C10000
@@ -124,6 +148,7 @@
124#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 148#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
125 149
126#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 150#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
151#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
127 152
128#define EXYNOS4_PA_ADC 0x13910000 153#define EXYNOS4_PA_ADC 0x13910000
129#define EXYNOS4_PA_ADC1 0x13911000 154#define EXYNOS4_PA_ADC1 0x13911000
@@ -133,8 +158,10 @@
133#define EXYNOS4_PA_SPDIF 0x139B0000 158#define EXYNOS4_PA_SPDIF 0x139B0000
134 159
135#define EXYNOS4_PA_TIMER 0x139D0000 160#define EXYNOS4_PA_TIMER 0x139D0000
161#define EXYNOS5_PA_TIMER 0x12DD0000
136 162
137#define EXYNOS4_PA_SDRAM 0x40000000 163#define EXYNOS4_PA_SDRAM 0x40000000
164#define EXYNOS5_PA_SDRAM 0x40000000
138 165
139/* Compatibiltiy Defines */ 166/* Compatibiltiy Defines */
140 167
@@ -152,7 +179,6 @@
152#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 179#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
153#define S3C_PA_RTC EXYNOS4_PA_RTC 180#define S3C_PA_RTC EXYNOS4_PA_RTC
154#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 181#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
155#define S3C_PA_UART EXYNOS4_PA_UART
156#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 182#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
157#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 183#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
158#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 184#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
@@ -162,6 +188,8 @@
162#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 188#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
163#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 189#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
164#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 190#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
191#define S5P_PA_JPEG EXYNOS4_PA_JPEG
192#define S5P_PA_G2D EXYNOS4_PA_G2D
165#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 193#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
166#define S5P_PA_HDMI EXYNOS4_PA_HDMI 194#define S5P_PA_HDMI EXYNOS4_PA_HDMI
167#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY 195#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
@@ -181,15 +209,18 @@
181 209
182/* Compatibility UART */ 210/* Compatibility UART */
183 211
184#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 212#define EXYNOS4_PA_UART0 0x13800000
213#define EXYNOS4_PA_UART1 0x13810000
214#define EXYNOS4_PA_UART2 0x13820000
215#define EXYNOS4_PA_UART3 0x13830000
216#define EXYNOS4_SZ_UART SZ_256
185 217
186#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET)) 218#define EXYNOS5_PA_UART0 0x12C00000
187#define S5P_PA_UART0 S5P_PA_UART(0) 219#define EXYNOS5_PA_UART1 0x12C10000
188#define S5P_PA_UART1 S5P_PA_UART(1) 220#define EXYNOS5_PA_UART2 0x12C20000
189#define S5P_PA_UART2 S5P_PA_UART(2) 221#define EXYNOS5_PA_UART3 0x12C30000
190#define S5P_PA_UART3 S5P_PA_UART(3) 222#define EXYNOS5_SZ_UART SZ_256
191#define S5P_PA_UART4 S5P_PA_UART(4)
192 223
193#define S5P_SZ_UART SZ_256 224#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
194 225
195#endif /* __ASM_ARCH_MAP_H */ 226#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
index 632dd5630138..e76b7faba66b 100644
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -22,11 +22,13 @@ enum sys_powerdown {
22 NUM_SYS_POWERDOWN, 22 NUM_SYS_POWERDOWN,
23}; 23};
24 24
25extern unsigned long l2x0_regs_phys;
25struct exynos4_pmu_conf { 26struct exynos4_pmu_conf {
26 void __iomem *reg; 27 void __iomem *reg;
27 unsigned int val[NUM_SYS_POWERDOWN]; 28 unsigned int val[NUM_SYS_POWERDOWN];
28}; 29};
29 30
30extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); 31extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
32extern void s3c_cpu_resume(void);
31 33
32#endif /* __ASM_ARCH_PMU_H */ 34#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe94829..e141c1fd68d8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,309 @@
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <mach/map.h> 17#include <mach/map.h>
18 18
19#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) 19#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
20 20
21#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) 21#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
22#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) 22#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
23#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) 23#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
24 24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) 25#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 26#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
27#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) 27#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
28 28
29#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) 29#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
30#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) 30#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
31 31
32#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 32#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
33#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 33#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
34#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 34#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
35#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) 35#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
36 36
37#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 37#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
38#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 38#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
39#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 39#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
40#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) 40#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
41#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) 41#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
42#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) 42#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
43#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 43#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
44#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 44#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) 45#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) 46#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 47#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) 48#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
49 49
50#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 50#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
51#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 51#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
52#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) 52#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
53#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) 53#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
54#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) 54#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
55#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) 55#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
56#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 56#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
57#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) 57#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
58 58
59#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 59#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
60#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) 60#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
61#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) 61#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
62#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528) 62#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
63#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) 63#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
64#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) 64#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
65#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) 65#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
66#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) 66#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
67#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) 67#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
68#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) 68#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
69#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) 69#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
70#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) 70#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
71#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) 71#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
72#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) 72#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
73#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) 73#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
74#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) 74#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
75#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 75#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
76#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 76#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
77#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) 77#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
78 78
79#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) 79#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
80 80#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
81#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) 81
82#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) 82#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
83#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) 83#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
84#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) 84#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
85#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) 85#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
86#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ 86#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
87 S5P_CLKREG(0x0C930) : \ 87#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
88 S5P_CLKREG(0x04930)) 88 EXYNOS_CLKREG(0x0C930) : \
89#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) 89 EXYNOS_CLKREG(0x04930))
90#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) 90#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
91#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 91#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
92#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) 92#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
93#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) 93#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
94#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 94#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
95#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ 95#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
96 S5P_CLKREG(0x0C960) : \ 96#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
97 S5P_CLKREG(0x08960)) 97 EXYNOS_CLKREG(0x0C960) : \
98#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) 98 EXYNOS_CLKREG(0x08960))
99#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) 99#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
100#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) 100#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
101 101#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
102#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) 102
103#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) 103#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
104#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) 104#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
105#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504) 105#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
106#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) 106#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
107#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) 107#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
108 108#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
109#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 109#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
110#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ 110
111 S5P_CLKREG(0x14004) : \ 111#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
112 S5P_CLKREG(0x10008)) 112#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
113#define S5P_APLL_CON0 S5P_CLKREG(0x14100) 113
114#define S5P_APLL_CON1 S5P_CLKREG(0x14104) 114#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
115#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ 115#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
116 S5P_CLKREG(0x14108) : \ 116 EXYNOS_CLKREG(0x14004) : \
117 S5P_CLKREG(0x10108)) 117 EXYNOS_CLKREG(0x10008))
118#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ 118#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
119 S5P_CLKREG(0x1410C) : \ 119#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
120 S5P_CLKREG(0x1010C)) 120#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
121 121 EXYNOS_CLKREG(0x14108) : \
122#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) 122 EXYNOS_CLKREG(0x10108))
123#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) 123#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
124 124 EXYNOS_CLKREG(0x1410C) : \
125#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) 125 EXYNOS_CLKREG(0x1010C))
126#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) 126
127#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) 127#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
128#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) 128#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
129 129
130#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 130#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
131#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) 131#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
132 132#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
133#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ 133#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
134 134
135#define S5P_APLLCON0_ENABLE_SHIFT (31) 135#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
136#define S5P_APLLCON0_LOCKED_SHIFT (29) 136#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
137#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) 137
138#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) 138#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
139 139
140#define S5P_EPLLCON0_ENABLE_SHIFT (31) 140#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
141#define S5P_EPLLCON0_LOCKED_SHIFT (29) 141#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
142 142#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
143#define S5P_VPLLCON0_ENABLE_SHIFT (31) 143#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
144#define S5P_VPLLCON0_LOCKED_SHIFT (29) 144
145 145#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
146#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) 146#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
147#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) 147
148 148#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
149#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) 149#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
150#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) 150
151#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) 151#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
152#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) 152#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
153#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) 153
154#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) 154#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
155#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) 155#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
156#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) 156#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
157#define S5P_CLKDIV_CPU0_ATB_SHIFT (16) 157#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
158#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) 158#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
159#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) 159#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
160#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) 160#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
161#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) 161#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
162#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) 162#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
163 163#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
164#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) 164#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
165#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) 165#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
166#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) 166#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
167#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) 167#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
168#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) 168#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
169#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) 169#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
170#define S5P_CLKDIV_DMC0_DMC_SHIFT (12) 170
171#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) 171#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
172#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) 172#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
173#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) 173#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
174#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) 174#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
175#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) 175#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
176#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) 176#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
177#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) 177
178#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) 178#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
179#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) 179#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
180 180#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
181#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) 181#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
182#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) 182#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
183#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) 183#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
184#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) 184#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
185#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) 185#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
186#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) 186#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
187#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) 187#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
188#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) 188#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
189#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) 189#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
190#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) 190#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
191 191#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
192#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) 192#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
193#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) 193#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
194#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) 194
195#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) 195#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
196#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
197#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
198#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
199#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
200#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
201#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
202#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
203#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
204#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
205#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
206#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
207
208#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
209#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
210
211#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
212#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
213#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
214#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
215#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
216#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
217#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
218#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
219#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
220#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
221#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
222#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
223#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
224#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
225
226#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
227#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
228#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
229#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
230
231#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
232#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
233#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
234#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
235#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
236#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
237#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
238#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
196 239
197/* Only for EXYNOS4210 */ 240/* Only for EXYNOS4210 */
198 241
199#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 242#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
200#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) 243#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
201#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) 244#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
202#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) 245#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
246
247/* Only for EXYNOS4212 */
248
249#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
250
251#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
252
253#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
254#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
255
256/* For EXYNOS5250 */
257
258#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
259#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
260#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
261#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
262#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
263
264#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
265
266#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
267
268#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
269#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
270#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
271#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
272#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
273#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
274
275#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
276#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
277#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
278#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
279#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
280#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
281
282#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
283#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
284#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
285#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
286#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
287
288#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
289#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
290#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
291#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
292#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
293#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
294#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
295#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
296#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
297#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
298
299#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
300#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
301#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
302#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
303#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
304#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
305#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
306#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
307#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
308#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
309
310#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
311#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
312#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
313
314#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
315
316#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
203 317
204/* Compatibility defines and inclusion */ 318/* Compatibility defines and inclusion */
205 319
206#include <mach/regs-pmu.h> 320#include <mach/regs-pmu.h>
207 321
208#define S5P_EPLL_CON S5P_EPLL_CON0 322#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
209 323
210#endif /* __ASM_ARCH_REGS_CLOCK_H */ 324#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21663a5..e4b5b60dcb85 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
16#include <mach/map.h> 16#include <mach/map.h>
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18 18
19#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
20#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
21#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
22#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
23#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
24
25#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
26
27/* compatibility for plat-s5p/irq-pm.c */
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) 28#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) 29#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21 30
@@ -28,15 +37,4 @@
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) 37#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) 38#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30 39
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */ 40#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e938fec..4c53f38b5a9e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) 31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
32 32
33#define S5P_SWRESET S5P_PMUREG(0x0400) 33#define S5P_SWRESET S5P_PMUREG(0x0400)
34#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
34 35
35#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 36#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
36#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 37#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
deleted file mode 100644
index 0063a6de3dc8..000000000000
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/system.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9acb..493f4f365ddf 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - uncompress code 5 * EXYNOS - uncompress code
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
13#ifndef __ASM_ARCH_UNCOMPRESS_H 12#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__ 13#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15 14
15#include <asm/mach-types.h>
16
16#include <mach/map.h> 17#include <mach/map.h>
18
19volatile u8 *uart_base;
20
17#include <plat/uncompress.h> 21#include <plat/uncompress.h>
18 22
19static void arch_detect_cpu(void) 23static void arch_detect_cpu(void)
20{ 24{
21 /* we do not need to do any cpu detection here at the moment. */ 25 if (machine_is_smdk5250())
26 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
27 else
28 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
22 29
23 /* 30 /*
24 * For preventing FIFO overrun or infinite loop of UART console, 31 * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 85fa02767d67..8245f1c761d9 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -15,11 +15,13 @@
15#include <linux/serial_core.h> 15#include <linux/serial_core.h>
16 16
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/hardware/gic.h>
18#include <mach/map.h> 19#include <mach/map.h>
19 20
20#include <plat/cpu.h> 21#include <plat/cpu.h>
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
22#include <plat/exynos4.h> 23
24#include "common.h"
23 25
24/* 26/*
25 * The following lookup table is used to override device names when devices 27 * The following lookup table is used to override device names when devices
@@ -35,13 +37,13 @@
35 * data from the device tree. 37 * data from the device tree.
36 */ 38 */
37static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { 39static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
38 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0, 40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
39 "exynos4210-uart.0", NULL), 41 "exynos4210-uart.0", NULL),
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1, 42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
41 "exynos4210-uart.1", NULL), 43 "exynos4210-uart.1", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2, 44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
43 "exynos4210-uart.2", NULL), 45 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3, 46 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
45 "exynos4210-uart.3", NULL), 47 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), 48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
47 "exynos4-sdhci.0", NULL), 49 "exynos4-sdhci.0", NULL),
@@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
60 62
61static void __init exynos4210_dt_map_io(void) 63static void __init exynos4210_dt_map_io(void)
62{ 64{
63 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 65 exynos_init_io(NULL, 0);
64 s3c24xx_init_clocks(24000000); 66 s3c24xx_init_clocks(24000000);
65} 67}
66 68
@@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 81 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
80 .init_irq = exynos4_init_irq, 82 .init_irq = exynos4_init_irq,
81 .map_io = exynos4210_dt_map_io, 83 .map_io = exynos4210_dt_map_io,
84 .handle_irq = gic_handle_irq,
82 .init_machine = exynos4210_dt_machine_init, 85 .init_machine = exynos4210_dt_machine_init,
83 .timer = &exynos4_timer, 86 .timer = &exynos4_timer,
84 .dt_compat = exynos4210_dt_compat, 87 .dt_compat = exynos4210_dt_compat,
88 .restart = exynos4_restart,
85MACHINE_END 89MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 000000000000..0d26f50081ad
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
1/*
2 * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/of_platform.h>
13#include <linux/serial_core.h>
14
15#include <asm/mach/arch.h>
16#include <asm/hardware/gic.h>
17#include <mach/map.h>
18
19#include <plat/cpu.h>
20#include <plat/regs-serial.h>
21
22#include "common.h"
23
24/*
25 * The following lookup table is used to override device names when devices
26 * are registered from device tree. This is temporarily added to enable
27 * device tree support addition for the EXYNOS5 architecture.
28 *
29 * For drivers that require platform data to be provided from the machine
30 * file, a platform data pointer can also be supplied along with the
31 * devices names. Usually, the platform data elements that cannot be parsed
32 * from the device tree by the drivers (example: function pointers) are
33 * supplied. But it should be noted that this is a temporary mechanism and
34 * at some point, the drivers should be capable of parsing all the platform
35 * data from the device tree.
36 */
37static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
38 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
39 "exynos4210-uart.0", NULL),
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
41 "exynos4210-uart.1", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
47 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
48 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
49 {},
50};
51
52static void __init exynos5250_dt_map_io(void)
53{
54 exynos_init_io(NULL, 0);
55 s3c24xx_init_clocks(24000000);
56}
57
58static void __init exynos5250_dt_machine_init(void)
59{
60 of_platform_populate(NULL, of_default_bus_match_table,
61 exynos5250_auxdata_lookup, NULL);
62}
63
64static char const *exynos5250_dt_compat[] __initdata = {
65 "samsung,exynos5250",
66 NULL
67};
68
69DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
70 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
71 .init_irq = exynos5_init_irq,
72 .map_io = exynos5250_dt_map_io,
73 .handle_irq = gic_handle_irq,
74 .init_machine = exynos5250_dt_machine_init,
75 .timer = &exynos4_timer,
76 .dt_compat = exynos5250_dt_compat,
77 .restart = exynos5_restart,
78MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b895ec031105..82ea6fccfb34 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -28,6 +28,7 @@
28 28
29#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
30#include <media/m5mols.h> 30#include <media/m5mols.h>
31#include <media/s5k6aa.h>
31#include <media/s5p_fimc.h> 32#include <media/s5p_fimc.h>
32#include <media/v4l2-mediabus.h> 33#include <media/v4l2-mediabus.h>
33 34
@@ -75,6 +76,7 @@ enum fixed_regulator_id {
75 FIXED_REG_ID_MAX8903, 76 FIXED_REG_ID_MAX8903,
76 FIXED_REG_ID_CAM_A28V, 77 FIXED_REG_ID_CAM_A28V,
77 FIXED_REG_ID_CAM_12V, 78 FIXED_REG_ID_CAM_12V,
79 FIXED_REG_ID_CAM_VT_15V,
78}; 80};
79 81
80static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { 82static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -115,7 +117,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
115}; 117};
116 118
117static struct regulator_consumer_supply emmc_supplies[] = { 119static struct regulator_consumer_supply emmc_supplies[] = {
118 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), 120 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
119 REGULATOR_SUPPLY("vmmc", "dw_mmc"), 121 REGULATOR_SUPPLY("vmmc", "dw_mmc"),
120}; 122};
121 123
@@ -220,14 +222,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = {
220 .lower_margin = 1, 222 .lower_margin = 1,
221 .hsync_len = 48, 223 .hsync_len = 48,
222 .vsync_len = 3, 224 .vsync_len = 3,
223 .xres = 1280, 225 .xres = 1024,
224 .yres = 800, 226 .yres = 600,
225 .refresh = 60, 227 .refresh = 60,
226 }, 228 },
227 .max_bpp = 24, 229 .max_bpp = 24,
228 .default_bpp = 16, 230 .default_bpp = 16,
229 .virtual_x = 1280, 231 .virtual_x = 1024,
230 .virtual_y = 800, 232 .virtual_y = 2 * 600,
231}; 233};
232 234
233static struct s3c_fb_platdata nuri_fb_pdata __initdata = { 235static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
@@ -399,6 +401,9 @@ static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
399static struct regulator_consumer_supply __initdata max8997_ldo5_[] = { 401static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
400 REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */ 402 REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
401}; 403};
404static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
405 REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
406};
402static struct regulator_consumer_supply __initdata max8997_ldo7_[] = { 407static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
403 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */ 408 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
404}; 409};
@@ -413,7 +418,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
413 REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */ 418 REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
414}; 419};
415static struct regulator_consumer_supply __initdata max8997_ldo13_[] = { 420static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
416 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */ 421 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
417}; 422};
418static struct regulator_consumer_supply __initdata max8997_ldo14_[] = { 423static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
419 REGULATOR_SUPPLY("inmotor", "max8997-haptic"), 424 REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
@@ -431,7 +436,7 @@ static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
431 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ 436 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
432}; 437};
433static struct regulator_consumer_supply __initdata max8997_buck2_[] = { 438static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
434 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ 439 REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
435}; 440};
436static struct regulator_consumer_supply __initdata max8997_buck3_[] = { 441static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
437 REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */ 442 REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
@@ -546,6 +551,8 @@ static struct regulator_init_data __initdata max8997_ldo6_data = {
546 .enabled = 1, 551 .enabled = 1,
547 }, 552 },
548 }, 553 },
554 .num_consumer_supplies = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
555 .consumer_supplies = nuri_max8997_ldo6_consumer,
549}; 556};
550 557
551static struct regulator_init_data __initdata max8997_ldo7_data = { 558static struct regulator_init_data __initdata max8997_ldo7_data = {
@@ -742,7 +749,7 @@ static struct regulator_init_data __initdata max8997_buck2_data = {
742 .constraints = { 749 .constraints = {
743 .name = "VINT_1.1V_C210", 750 .name = "VINT_1.1V_C210",
744 .min_uV = 900000, 751 .min_uV = 900000,
745 .max_uV = 1100000, 752 .max_uV = 1200000,
746 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 753 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
747 .always_on = 1, 754 .always_on = 1,
748 .state_mem = { 755 .state_mem = {
@@ -957,7 +964,6 @@ static struct max8997_platform_data __initdata nuri_max8997_pdata = {
957 .regulators = nuri_max8997_regulators, 964 .regulators = nuri_max8997_regulators,
958 965
959 .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) }, 966 .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
960 .buck2_gpiodvs = true,
961 967
962 .buck1_voltage[0] = 1350000, /* 1.35V */ 968 .buck1_voltage[0] = 1350000, /* 1.35V */
963 .buck1_voltage[1] = 1300000, /* 1.3V */ 969 .buck1_voltage[1] = 1300000, /* 1.3V */
@@ -1116,7 +1122,30 @@ static void __init nuri_ehci_init(void)
1116} 1122}
1117 1123
1118/* CAMERA */ 1124/* CAMERA */
1125static struct regulator_consumer_supply cam_vt_cam15_supply =
1126 REGULATOR_SUPPLY("vdd_core", "6-003c");
1127
1128static struct regulator_init_data cam_vt_cam15_reg_init_data = {
1129 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
1130 .num_consumer_supplies = 1,
1131 .consumer_supplies = &cam_vt_cam15_supply,
1132};
1133
1134static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
1135 .supply_name = "VT_CAM_1.5V",
1136 .microvolts = 1500000,
1137 .gpio = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
1138 .enable_high = 1,
1139 .init_data = &cam_vt_cam15_reg_init_data,
1140};
1141
1142static struct platform_device cam_vt_cam15_fixed_rdev = {
1143 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
1144 .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
1145};
1146
1119static struct regulator_consumer_supply cam_vdda_supply[] = { 1147static struct regulator_consumer_supply cam_vdda_supply[] = {
1148 REGULATOR_SUPPLY("vdda", "6-003c"),
1120 REGULATOR_SUPPLY("a_sensor", "0-001f"), 1149 REGULATOR_SUPPLY("a_sensor", "0-001f"),
1121}; 1150};
1122 1151
@@ -1173,6 +1202,21 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
1173 1202
1174#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */ 1203#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
1175#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5) 1204#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5)
1205#define GPIO_CAM_VT_NSTBY EXYNOS4_GPL2(0)
1206#define GPIO_CAM_VT_NRST EXYNOS4_GPL2(1)
1207
1208static struct s5k6aa_platform_data s5k6aa_pldata = {
1209 .mclk_frequency = 24000000UL,
1210 .gpio_reset = { GPIO_CAM_VT_NRST, 0 },
1211 .gpio_stby = { GPIO_CAM_VT_NSTBY, 0 },
1212 .bus_type = V4L2_MBUS_PARALLEL,
1213 .horiz_flip = 1,
1214};
1215
1216static struct i2c_board_info s5k6aa_board_info = {
1217 I2C_BOARD_INFO("S5K6AA", 0x3c),
1218 .platform_data = &s5k6aa_pldata,
1219};
1176 1220
1177static struct m5mols_platform_data m5mols_platdata = { 1221static struct m5mols_platform_data m5mols_platdata = {
1178 .gpio_reset = GPIO_CAM_MEGA_RST, 1222 .gpio_reset = GPIO_CAM_MEGA_RST,
@@ -1185,6 +1229,13 @@ static struct i2c_board_info m5mols_board_info = {
1185 1229
1186static struct s5p_fimc_isp_info nuri_camera_sensors[] = { 1230static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
1187 { 1231 {
1232 .flags = V4L2_MBUS_PCLK_SAMPLE_RISING |
1233 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1234 .bus_type = FIMC_ITU_601,
1235 .board_info = &s5k6aa_board_info,
1236 .clk_frequency = 24000000UL,
1237 .i2c_bus_num = 6,
1238 }, {
1188 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | 1239 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
1189 V4L2_MBUS_VSYNC_ACTIVE_LOW, 1240 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1190 .bus_type = FIMC_MIPI_CSI2, 1241 .bus_type = FIMC_MIPI_CSI2,
@@ -1200,11 +1251,13 @@ static struct s5p_platform_fimc fimc_md_platdata = {
1200}; 1251};
1201 1252
1202static struct gpio nuri_camera_gpios[] = { 1253static struct gpio nuri_camera_gpios[] = {
1254 { GPIO_CAM_VT_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
1255 { GPIO_CAM_VT_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
1203 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, 1256 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
1204 { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, 1257 { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
1205}; 1258};
1206 1259
1207static void nuri_camera_init(void) 1260static void __init nuri_camera_init(void)
1208{ 1261{
1209 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), 1262 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
1210 &s5p_device_mipi_csis0); 1263 &s5p_device_mipi_csis0);
@@ -1224,6 +1277,8 @@ static void nuri_camera_init(void)
1224 pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__); 1277 pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
1225 1278
1226 /* Free GPIOs controlled directly by the sensor drivers. */ 1279 /* Free GPIOs controlled directly by the sensor drivers. */
1280 gpio_free(GPIO_CAM_VT_NRST);
1281 gpio_free(GPIO_CAM_VT_NSTBY);
1227 gpio_free(GPIO_CAM_MEGA_RST); 1282 gpio_free(GPIO_CAM_MEGA_RST);
1228 1283
1229 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) { 1284 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
@@ -1234,15 +1289,27 @@ static void nuri_camera_init(void)
1234 s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4); 1289 s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
1235} 1290}
1236 1291
1292static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
1293 .frequency = 400000U,
1294 .sda_delay = 200,
1295 .bus_num = 6,
1296};
1297
1237static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = { 1298static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
1238 .frequency = 400000U, 1299 .frequency = 400000U,
1239 .sda_delay = 200, 1300 .sda_delay = 200,
1240}; 1301};
1241 1302
1303/* DEVFREQ controlling memory/bus */
1304static struct platform_device exynos4_bus_devfreq = {
1305 .name = "exynos4210-busfreq",
1306};
1307
1242static struct platform_device *nuri_devices[] __initdata = { 1308static struct platform_device *nuri_devices[] __initdata = {
1243 /* Samsung Platform Devices */ 1309 /* Samsung Platform Devices */
1244 &s3c_device_i2c5, /* PMIC should initialize first */ 1310 &s3c_device_i2c5, /* PMIC should initialize first */
1245 &s3c_device_i2c0, 1311 &s3c_device_i2c0,
1312 &s3c_device_i2c6,
1246 &emmc_fixed_voltage, 1313 &emmc_fixed_voltage,
1247 &s5p_device_mipi_csis0, 1314 &s5p_device_mipi_csis0,
1248 &s5p_device_fimc0, 1315 &s5p_device_fimc0,
@@ -1259,13 +1326,12 @@ static struct platform_device *nuri_devices[] __initdata = {
1259 &s3c_device_i2c3, 1326 &s3c_device_i2c3,
1260 &i2c9_gpio, 1327 &i2c9_gpio,
1261 &s3c_device_adc, 1328 &s3c_device_adc,
1329 &s5p_device_g2d,
1330 &s5p_device_jpeg,
1262 &s3c_device_rtc, 1331 &s3c_device_rtc,
1263 &s5p_device_mfc, 1332 &s5p_device_mfc,
1264 &s5p_device_mfc_l, 1333 &s5p_device_mfc_l,
1265 &s5p_device_mfc_r, 1334 &s5p_device_mfc_r,
1266 &exynos4_device_pd[PD_MFC],
1267 &exynos4_device_pd[PD_LCD0],
1268 &exynos4_device_pd[PD_CAM],
1269 &s5p_device_fimc_md, 1335 &s5p_device_fimc_md,
1270 1336
1271 /* NURI Devices */ 1337 /* NURI Devices */
@@ -1274,8 +1340,10 @@ static struct platform_device *nuri_devices[] __initdata = {
1274 &nuri_backlight_device, 1340 &nuri_backlight_device,
1275 &max8903_fixed_reg_dev, 1341 &max8903_fixed_reg_dev,
1276 &nuri_max8903_device, 1342 &nuri_max8903_device,
1343 &cam_vt_cam15_fixed_rdev,
1277 &cam_vdda_fixed_rdev, 1344 &cam_vdda_fixed_rdev,
1278 &cam_8m_12v_fixed_rdev, 1345 &cam_8m_12v_fixed_rdev,
1346 &exynos4_bus_devfreq,
1279}; 1347};
1280 1348
1281static void __init nuri_map_io(void) 1349static void __init nuri_map_io(void)
@@ -1305,6 +1373,7 @@ static void __init nuri_machine_init(void)
1305 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); 1373 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1306 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3)); 1374 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
1307 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs)); 1375 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
1376 s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
1308 1377
1309 s5p_fimd0_set_platdata(&nuri_fb_pdata); 1378 s5p_fimd0_set_platdata(&nuri_fb_pdata);
1310 1379
@@ -1315,14 +1384,6 @@ static void __init nuri_machine_init(void)
1315 1384
1316 /* Last */ 1385 /* Last */
1317 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); 1386 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
1318 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
1319 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
1320
1321 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1322 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1323 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1324 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1325 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1326} 1387}
1327 1388
1328MACHINE_START(NURI, "NURI") 1389MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 0679b8ad2d1e..878d4c99142d 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -20,6 +20,7 @@
20#include <linux/regulator/machine.h> 20#include <linux/regulator/machine.h>
21#include <linux/mfd/max8997.h> 21#include <linux/mfd/max8997.h>
22#include <linux/lcd.h> 22#include <linux/lcd.h>
23#include <linux/rfkill-gpio.h>
23 24
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
25#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
@@ -235,6 +236,7 @@ static struct regulator_init_data __initdata max8997_ldo9_data = {
235 .min_uV = 2800000, 236 .min_uV = 2800000,
236 .max_uV = 2800000, 237 .max_uV = 2800000,
237 .apply_uV = 1, 238 .apply_uV = 1,
239 .always_on = 1,
238 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 240 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
239 .state_mem = { 241 .state_mem = {
240 .disabled = 1, 242 .disabled = 1,
@@ -278,6 +280,7 @@ static struct regulator_init_data __initdata max8997_ldo14_data = {
278 .min_uV = 1800000, 280 .min_uV = 1800000,
279 .max_uV = 1800000, 281 .max_uV = 1800000,
280 .apply_uV = 1, 282 .apply_uV = 1,
283 .always_on = 1,
281 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 284 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
282 .state_mem = { 285 .state_mem = {
283 .disabled = 1, 286 .disabled = 1,
@@ -293,6 +296,7 @@ static struct regulator_init_data __initdata max8997_ldo17_data = {
293 .min_uV = 3300000, 296 .min_uV = 3300000,
294 .max_uV = 3300000, 297 .max_uV = 3300000,
295 .apply_uV = 1, 298 .apply_uV = 1,
299 .always_on = 1,
296 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 300 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
297 .state_mem = { 301 .state_mem = {
298 .disabled = 1, 302 .disabled = 1,
@@ -412,7 +416,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
412 { MAX8997_BUCK7, &max8997_buck7_data }, 416 { MAX8997_BUCK7, &max8997_buck7_data },
413}; 417};
414 418
415struct max8997_platform_data __initdata origen_max8997_pdata = { 419static struct max8997_platform_data __initdata origen_max8997_pdata = {
416 .num_regulators = ARRAY_SIZE(origen_max8997_regulators), 420 .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
417 .regulators = origen_max8997_regulators, 421 .regulators = origen_max8997_regulators,
418 422
@@ -602,6 +606,23 @@ static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
602 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, 606 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
603}; 607};
604 608
609/* Bluetooth rfkill gpio platform data */
610struct rfkill_gpio_platform_data origen_bt_pdata = {
611 .reset_gpio = EXYNOS4_GPX2(2),
612 .shutdown_gpio = -1,
613 .type = RFKILL_TYPE_BLUETOOTH,
614 .name = "origen-bt",
615};
616
617/* Bluetooth Platform device */
618static struct platform_device origen_device_bluetooth = {
619 .name = "rfkill_gpio",
620 .id = -1,
621 .dev = {
622 .platform_data = &origen_bt_pdata,
623 },
624};
625
605static struct platform_device *origen_devices[] __initdata = { 626static struct platform_device *origen_devices[] __initdata = {
606 &s3c_device_hsmmc2, 627 &s3c_device_hsmmc2,
607 &s3c_device_hsmmc0, 628 &s3c_device_hsmmc0,
@@ -613,23 +634,20 @@ static struct platform_device *origen_devices[] __initdata = {
613 &s5p_device_fimc1, 634 &s5p_device_fimc1,
614 &s5p_device_fimc2, 635 &s5p_device_fimc2,
615 &s5p_device_fimc3, 636 &s5p_device_fimc3,
637 &s5p_device_fimc_md,
616 &s5p_device_fimd0, 638 &s5p_device_fimd0,
639 &s5p_device_g2d,
617 &s5p_device_hdmi, 640 &s5p_device_hdmi,
618 &s5p_device_i2c_hdmiphy, 641 &s5p_device_i2c_hdmiphy,
642 &s5p_device_jpeg,
619 &s5p_device_mfc, 643 &s5p_device_mfc,
620 &s5p_device_mfc_l, 644 &s5p_device_mfc_l,
621 &s5p_device_mfc_r, 645 &s5p_device_mfc_r,
622 &s5p_device_mixer, 646 &s5p_device_mixer,
623 &exynos4_device_ohci, 647 &exynos4_device_ohci,
624 &exynos4_device_pd[PD_LCD0],
625 &exynos4_device_pd[PD_TV],
626 &exynos4_device_pd[PD_G3D],
627 &exynos4_device_pd[PD_LCD1],
628 &exynos4_device_pd[PD_CAM],
629 &exynos4_device_pd[PD_GPS],
630 &exynos4_device_pd[PD_MFC],
631 &origen_device_gpiokeys, 648 &origen_device_gpiokeys,
632 &origen_lcd_hv070wsa, 649 &origen_lcd_hv070wsa,
650 &origen_device_bluetooth,
633}; 651};
634 652
635/* LCD Backlight data */ 653/* LCD Backlight data */
@@ -643,6 +661,16 @@ static struct platform_pwm_backlight_data origen_bl_data = {
643 .pwm_period_ns = 1000, 661 .pwm_period_ns = 1000,
644}; 662};
645 663
664static void __init origen_bt_setup(void)
665{
666 gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
667 /* 4 UART Pins configuration */
668 s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
669 /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
670 s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
671 s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
672}
673
646static void s5p_tv_setup(void) 674static void s5p_tv_setup(void)
647{ 675{
648 /* Direct HPD to HDMI chip */ 676 /* Direct HPD to HDMI chip */
@@ -695,14 +723,9 @@ static void __init origen_machine_init(void)
695 723
696 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); 724 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
697 725
698 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
699
700 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
701 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
702
703 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
704
705 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); 726 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
727
728 origen_bt_setup();
706} 729}
707 730
708MACHINE_START(ORIGEN, "ORIGEN") 731MACHINE_START(ORIGEN, "ORIGEN")
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index b2c5557f50e4..83b91fa777c1 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -270,6 +270,9 @@ static struct platform_device *smdkv310_devices[] __initdata = {
270 &s5p_device_fimc1, 270 &s5p_device_fimc1,
271 &s5p_device_fimc2, 271 &s5p_device_fimc2,
272 &s5p_device_fimc3, 272 &s5p_device_fimc3,
273 &s5p_device_fimc_md,
274 &s5p_device_g2d,
275 &s5p_device_jpeg,
273 &exynos4_device_ac97, 276 &exynos4_device_ac97,
274 &exynos4_device_i2s0, 277 &exynos4_device_i2s0,
275 &exynos4_device_ohci, 278 &exynos4_device_ohci,
@@ -277,13 +280,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
277 &s5p_device_mfc, 280 &s5p_device_mfc,
278 &s5p_device_mfc_l, 281 &s5p_device_mfc_l,
279 &s5p_device_mfc_r, 282 &s5p_device_mfc_r,
280 &exynos4_device_pd[PD_MFC],
281 &exynos4_device_pd[PD_G3D],
282 &exynos4_device_pd[PD_LCD0],
283 &exynos4_device_pd[PD_LCD1],
284 &exynos4_device_pd[PD_CAM],
285 &exynos4_device_pd[PD_TV],
286 &exynos4_device_pd[PD_GPS],
287 &exynos4_device_spdif, 283 &exynos4_device_spdif,
288 &exynos4_device_sysmmu, 284 &exynos4_device_sysmmu,
289 &samsung_asoc_dma, 285 &samsung_asoc_dma,
@@ -336,10 +332,6 @@ static void s5p_tv_setup(void)
336 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); 332 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
337 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 333 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
338 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 334 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
339
340 /* setup dependencies between TV devices */
341 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
342 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
343} 335}
344 336
345static void __init smdkv310_map_io(void) 337static void __init smdkv310_map_io(void)
@@ -379,7 +371,6 @@ static void __init smdkv310_machine_init(void)
379 clk_xusbxti.rate = 24000000; 371 clk_xusbxti.rate = 24000000;
380 372
381 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 373 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
382 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
383} 374}
384 375
385MACHINE_START(SMDKV310, "SMDKV310") 376MACHINE_START(SMDKV310, "SMDKV310")
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 37ac93e8d6d9..28658da9f423 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -13,6 +13,7 @@
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/gpio_keys.h> 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/interrupt.h>
16#include <linux/fb.h> 17#include <linux/fb.h>
17#include <linux/mfd/max8998.h> 18#include <linux/mfd/max8998.h>
18#include <linux/regulator/machine.h> 19#include <linux/regulator/machine.h>
@@ -46,6 +47,7 @@
46#include <media/v4l2-mediabus.h> 47#include <media/v4l2-mediabus.h>
47#include <media/s5p_fimc.h> 48#include <media/s5p_fimc.h>
48#include <media/m5mols.h> 49#include <media/m5mols.h>
50#include <media/s5k6aa.h>
49 51
50#include "common.h" 52#include "common.h"
51 53
@@ -122,8 +124,10 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
122static struct regulator_consumer_supply lp3974_buck2_consumer = 124static struct regulator_consumer_supply lp3974_buck2_consumer =
123 REGULATOR_SUPPLY("vddg3d", NULL); 125 REGULATOR_SUPPLY("vddg3d", NULL);
124 126
125static struct regulator_consumer_supply lp3974_buck3_consumer = 127static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
126 REGULATOR_SUPPLY("vdet", "s5p-sdo"); 128 REGULATOR_SUPPLY("vdet", "s5p-sdo"),
129 REGULATOR_SUPPLY("vdd_reg", "0-003c"),
130};
127 131
128static struct regulator_init_data lp3974_buck1_data = { 132static struct regulator_init_data lp3974_buck1_data = {
129 .constraints = { 133 .constraints = {
@@ -168,8 +172,8 @@ static struct regulator_init_data lp3974_buck3_data = {
168 .enabled = 1, 172 .enabled = 1,
169 }, 173 },
170 }, 174 },
171 .num_consumer_supplies = 1, 175 .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
172 .consumer_supplies = &lp3974_buck3_consumer, 176 .consumer_supplies = lp3974_buck3_consumer,
173}; 177};
174 178
175static struct regulator_init_data lp3974_buck4_data = { 179static struct regulator_init_data lp3974_buck4_data = {
@@ -302,6 +306,9 @@ static struct regulator_init_data lp3974_ldo8_data = {
302 .consumer_supplies = lp3974_ldo8_consumer, 306 .consumer_supplies = lp3974_ldo8_consumer,
303}; 307};
304 308
309static struct regulator_consumer_supply lp3974_ldo9_consumer =
310 REGULATOR_SUPPLY("vddio", "0-003c");
311
305static struct regulator_init_data lp3974_ldo9_data = { 312static struct regulator_init_data lp3974_ldo9_data = {
306 .constraints = { 313 .constraints = {
307 .name = "VCC_2.8V", 314 .name = "VCC_2.8V",
@@ -313,6 +320,8 @@ static struct regulator_init_data lp3974_ldo9_data = {
313 .enabled = 1, 320 .enabled = 1,
314 }, 321 },
315 }, 322 },
323 .num_consumer_supplies = 1,
324 .consumer_supplies = &lp3974_ldo9_consumer,
316}; 325};
317 326
318static struct regulator_init_data lp3974_ldo10_data = { 327static struct regulator_init_data lp3974_ldo10_data = {
@@ -411,6 +420,7 @@ static struct regulator_init_data lp3974_ldo15_data = {
411}; 420};
412 421
413static struct regulator_consumer_supply lp3974_ldo16_consumer[] = { 422static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
423 REGULATOR_SUPPLY("vdda", "0-003c"),
414 REGULATOR_SUPPLY("a_sensor", "0-001f"), 424 REGULATOR_SUPPLY("a_sensor", "0-001f"),
415}; 425};
416 426
@@ -595,6 +605,7 @@ static struct mxt_platform_data qt602240_platform_data = {
595 .threshold = 0x28, 605 .threshold = 0x28,
596 .voltage = 2800000, /* 2.8V */ 606 .voltage = 2800000, /* 2.8V */
597 .orient = MXT_DIAGONAL, 607 .orient = MXT_DIAGONAL,
608 .irqflags = IRQF_TRIGGER_FALLING,
598}; 609};
599 610
600static struct i2c_board_info i2c3_devs[] __initdata = { 611static struct i2c_board_info i2c3_devs[] __initdata = {
@@ -741,7 +752,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
741}; 752};
742 753
743static struct regulator_consumer_supply mmc0_supplies[] = { 754static struct regulator_consumer_supply mmc0_supplies[] = {
744 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), 755 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
745}; 756};
746 757
747static struct regulator_init_data mmc0_fixed_voltage_init_data = { 758static struct regulator_init_data mmc0_fixed_voltage_init_data = {
@@ -817,6 +828,8 @@ static struct s3c_fb_pd_win universal_fb_win0 = {
817 }, 828 },
818 .max_bpp = 32, 829 .max_bpp = 32,
819 .default_bpp = 16, 830 .default_bpp = 16,
831 .virtual_x = 480,
832 .virtual_y = 2 * 800,
820}; 833};
821 834
822static struct s3c_fb_platdata universal_lcd_pdata __initdata = { 835static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
@@ -828,6 +841,28 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
828 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, 841 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
829}; 842};
830 843
844static struct regulator_consumer_supply cam_vt_dio_supply =
845 REGULATOR_SUPPLY("vdd_core", "0-003c");
846
847static struct regulator_init_data cam_vt_dio_reg_init_data = {
848 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
849 .num_consumer_supplies = 1,
850 .consumer_supplies = &cam_vt_dio_supply,
851};
852
853static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
854 .supply_name = "CAM_VT_D_IO",
855 .microvolts = 2800000,
856 .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
857 .enable_high = 1,
858 .init_data = &cam_vt_dio_reg_init_data,
859};
860
861static struct platform_device cam_vt_dio_fixed_reg_dev = {
862 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
863 .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
864};
865
831static struct regulator_consumer_supply cam_i_core_supply = 866static struct regulator_consumer_supply cam_i_core_supply =
832 REGULATOR_SUPPLY("core", "0-001f"); 867 REGULATOR_SUPPLY("core", "0-001f");
833 868
@@ -883,6 +918,28 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
883#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3) 918#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
884#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */ 919#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
885#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5) 920#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
921#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7)
922#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6)
923
924static int s5k6aa_set_power(int on)
925{
926 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
927 return 0;
928}
929
930static struct s5k6aa_platform_data s5k6aa_platdata = {
931 .mclk_frequency = 21600000UL,
932 .gpio_reset = { GPIO_CAM_VGA_NRST, 0 },
933 .gpio_stby = { GPIO_CAM_VGA_NSTBY, 0 },
934 .bus_type = V4L2_MBUS_PARALLEL,
935 .horiz_flip = 1,
936 .set_power = s5k6aa_set_power,
937};
938
939static struct i2c_board_info s5k6aa_board_info = {
940 I2C_BOARD_INFO("S5K6AA", 0x3C),
941 .platform_data = &s5k6aa_platdata,
942};
886 943
887static int m5mols_set_power(struct device *dev, int on) 944static int m5mols_set_power(struct device *dev, int on)
888{ 945{
@@ -907,10 +964,18 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
907 .mux_id = 0, 964 .mux_id = 0,
908 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | 965 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
909 V4L2_MBUS_VSYNC_ACTIVE_LOW, 966 V4L2_MBUS_VSYNC_ACTIVE_LOW,
967 .bus_type = FIMC_ITU_601,
968 .board_info = &s5k6aa_board_info,
969 .i2c_bus_num = 0,
970 .clk_frequency = 24000000UL,
971 }, {
972 .mux_id = 0,
973 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
974 V4L2_MBUS_VSYNC_ACTIVE_LOW,
910 .bus_type = FIMC_MIPI_CSI2, 975 .bus_type = FIMC_MIPI_CSI2,
911 .board_info = &m5mols_board_info, 976 .board_info = &m5mols_board_info,
912 .i2c_bus_num = 0, 977 .i2c_bus_num = 0,
913 .clk_frequency = 21600000UL, 978 .clk_frequency = 24000000UL,
914 .csi_data_align = 32, 979 .csi_data_align = 32,
915 }, 980 },
916}; 981};
@@ -925,9 +990,11 @@ static struct gpio universal_camera_gpios[] = {
925 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" }, 990 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
926 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, 991 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
927 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, 992 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
993 { GPIO_CAM_VGA_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
994 { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
928}; 995};
929 996
930static void universal_camera_init(void) 997static void __init universal_camera_init(void)
931{ 998{
932 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), 999 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
933 &s5p_device_mipi_csis0); 1000 &s5p_device_mipi_csis0);
@@ -948,6 +1015,8 @@ static void universal_camera_init(void)
948 /* Free GPIOs controlled directly by the sensor drivers. */ 1015 /* Free GPIOs controlled directly by the sensor drivers. */
949 gpio_free(GPIO_CAM_MEGA_nRST); 1016 gpio_free(GPIO_CAM_MEGA_nRST);
950 gpio_free(GPIO_CAM_8M_ISP_INT); 1017 gpio_free(GPIO_CAM_8M_ISP_INT);
1018 gpio_free(GPIO_CAM_VGA_NRST);
1019 gpio_free(GPIO_CAM_VGA_NSTBY);
951 1020
952 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) 1021 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
953 pr_err("Camera port A setup failed\n"); 1022 pr_err("Camera port A setup failed\n");
@@ -960,6 +1029,7 @@ static struct platform_device *universal_devices[] __initdata = {
960 &s5p_device_fimc1, 1029 &s5p_device_fimc1,
961 &s5p_device_fimc2, 1030 &s5p_device_fimc2,
962 &s5p_device_fimc3, 1031 &s5p_device_fimc3,
1032 &s5p_device_g2d,
963 &mmc0_fixed_voltage, 1033 &mmc0_fixed_voltage,
964 &s3c_device_hsmmc0, 1034 &s3c_device_hsmmc0,
965 &s3c_device_hsmmc2, 1035 &s3c_device_hsmmc2,
@@ -969,7 +1039,6 @@ static struct platform_device *universal_devices[] __initdata = {
969 &s3c_device_i2c5, 1039 &s3c_device_i2c5,
970 &s5p_device_i2c_hdmiphy, 1040 &s5p_device_i2c_hdmiphy,
971 &hdmi_fixed_voltage, 1041 &hdmi_fixed_voltage,
972 &exynos4_device_pd[PD_TV],
973 &s5p_device_hdmi, 1042 &s5p_device_hdmi,
974 &s5p_device_sdo, 1043 &s5p_device_sdo,
975 &s5p_device_mixer, 1044 &s5p_device_mixer,
@@ -979,12 +1048,11 @@ static struct platform_device *universal_devices[] __initdata = {
979 &universal_gpio_keys, 1048 &universal_gpio_keys,
980 &s5p_device_onenand, 1049 &s5p_device_onenand,
981 &s5p_device_fimd0, 1050 &s5p_device_fimd0,
1051 &s5p_device_jpeg,
982 &s5p_device_mfc, 1052 &s5p_device_mfc,
983 &s5p_device_mfc_l, 1053 &s5p_device_mfc_l,
984 &s5p_device_mfc_r, 1054 &s5p_device_mfc_r,
985 &exynos4_device_pd[PD_MFC], 1055 &cam_vt_dio_fixed_reg_dev,
986 &exynos4_device_pd[PD_LCD0],
987 &exynos4_device_pd[PD_CAM],
988 &cam_i_core_fixed_reg_dev, 1056 &cam_i_core_fixed_reg_dev,
989 &cam_s_if_fixed_reg_dev, 1057 &cam_s_if_fixed_reg_dev,
990 &s5p_device_fimc_md, 1058 &s5p_device_fimc_md,
@@ -997,16 +1065,12 @@ static void __init universal_map_io(void)
997 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 1065 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
998} 1066}
999 1067
1000void s5p_tv_setup(void) 1068static void s5p_tv_setup(void)
1001{ 1069{
1002 /* direct HPD to HDMI chip */ 1070 /* direct HPD to HDMI chip */
1003 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); 1071 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
1004 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 1072 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1005 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 1073 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1006
1007 /* setup dependencies between TV devices */
1008 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
1009 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
1010} 1074}
1011 1075
1012static void __init universal_reserve(void) 1076static void __init universal_reserve(void)
@@ -1040,15 +1104,6 @@ static void __init universal_machine_init(void)
1040 1104
1041 /* Last */ 1105 /* Last */
1042 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); 1106 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
1043
1044 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
1045 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
1046
1047 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1048 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1049 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1050 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1051 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1052} 1107}
1053 1108
1054MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 1109MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527d0918..897d9a9cf226 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -21,6 +21,7 @@
21#include <linux/percpu.h> 21#include <linux/percpu.h>
22 22
23#include <asm/hardware/gic.h> 23#include <asm/hardware/gic.h>
24#include <asm/localtimer.h>
24 25
25#include <plat/cpu.h> 26#include <plat/cpu.h>
26 27
@@ -29,12 +30,13 @@
29#include <mach/regs-mct.h> 30#include <mach/regs-mct.h>
30#include <asm/mach/time.h> 31#include <asm/mach/time.h>
31 32
33#define TICK_BASE_CNT 1
34
32enum { 35enum {
33 MCT_INT_SPI, 36 MCT_INT_SPI,
34 MCT_INT_PPI 37 MCT_INT_PPI
35}; 38};
36 39
37static unsigned long clk_cnt_per_tick;
38static unsigned long clk_rate; 40static unsigned long clk_rate;
39static unsigned int mct_int_type; 41static unsigned int mct_int_type;
40 42
@@ -205,11 +207,14 @@ static int exynos4_comp_set_next_event(unsigned long cycles,
205static void exynos4_comp_set_mode(enum clock_event_mode mode, 207static void exynos4_comp_set_mode(enum clock_event_mode mode,
206 struct clock_event_device *evt) 208 struct clock_event_device *evt)
207{ 209{
210 unsigned long cycles_per_jiffy;
208 exynos4_mct_comp0_stop(); 211 exynos4_mct_comp0_stop();
209 212
210 switch (mode) { 213 switch (mode) {
211 case CLOCK_EVT_MODE_PERIODIC: 214 case CLOCK_EVT_MODE_PERIODIC:
212 exynos4_mct_comp0_start(mode, clk_cnt_per_tick); 215 cycles_per_jiffy =
216 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
217 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
213 break; 218 break;
214 219
215 case CLOCK_EVT_MODE_ONESHOT: 220 case CLOCK_EVT_MODE_ONESHOT:
@@ -248,9 +253,7 @@ static struct irqaction mct_comp_event_irq = {
248 253
249static void exynos4_clockevent_init(void) 254static void exynos4_clockevent_init(void)
250{ 255{
251 clk_cnt_per_tick = clk_rate / 2 / HZ; 256 clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
252
253 clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
254 mct_comp_device.max_delta_ns = 257 mct_comp_device.max_delta_ns =
255 clockevent_delta2ns(0xffffffff, &mct_comp_device); 258 clockevent_delta2ns(0xffffffff, &mct_comp_device);
256 mct_comp_device.min_delta_ns = 259 mct_comp_device.min_delta_ns =
@@ -258,7 +261,10 @@ static void exynos4_clockevent_init(void)
258 mct_comp_device.cpumask = cpumask_of(0); 261 mct_comp_device.cpumask = cpumask_of(0);
259 clockevents_register_device(&mct_comp_device); 262 clockevents_register_device(&mct_comp_device);
260 263
261 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq); 264 if (soc_is_exynos5250())
265 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
266 else
267 setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
262} 268}
263 269
264#ifdef CONFIG_LOCAL_TIMERS 270#ifdef CONFIG_LOCAL_TIMERS
@@ -314,12 +320,15 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
314 struct clock_event_device *evt) 320 struct clock_event_device *evt)
315{ 321{
316 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); 322 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
323 unsigned long cycles_per_jiffy;
317 324
318 exynos4_mct_tick_stop(mevt); 325 exynos4_mct_tick_stop(mevt);
319 326
320 switch (mode) { 327 switch (mode) {
321 case CLOCK_EVT_MODE_PERIODIC: 328 case CLOCK_EVT_MODE_PERIODIC:
322 exynos4_mct_tick_start(clk_cnt_per_tick, mevt); 329 cycles_per_jiffy =
330 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
331 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
323 break; 332 break;
324 333
325 case CLOCK_EVT_MODE_ONESHOT: 334 case CLOCK_EVT_MODE_ONESHOT:
@@ -375,7 +384,7 @@ static struct irqaction mct_tick1_event_irq = {
375 .handler = exynos4_mct_tick_isr, 384 .handler = exynos4_mct_tick_isr,
376}; 385};
377 386
378static void exynos4_mct_tick_init(struct clock_event_device *evt) 387static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
379{ 388{
380 struct mct_clock_event_device *mevt; 389 struct mct_clock_event_device *mevt;
381 unsigned int cpu = smp_processor_id(); 390 unsigned int cpu = smp_processor_id();
@@ -393,7 +402,7 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
393 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 402 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
394 evt->rating = 450; 403 evt->rating = 450;
395 404
396 clockevents_calc_mult_shift(evt, clk_rate / 2, 5); 405 clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
397 evt->max_delta_ns = 406 evt->max_delta_ns =
398 clockevent_delta2ns(0x7fffffff, evt); 407 clockevent_delta2ns(0x7fffffff, evt);
399 evt->min_delta_ns = 408 evt->min_delta_ns =
@@ -401,33 +410,27 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
401 410
402 clockevents_register_device(evt); 411 clockevents_register_device(evt);
403 412
404 exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET); 413 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
405 414
406 if (mct_int_type == MCT_INT_SPI) { 415 if (mct_int_type == MCT_INT_SPI) {
407 if (cpu == 0) { 416 if (cpu == 0) {
408 mct_tick0_event_irq.dev_id = mevt; 417 mct_tick0_event_irq.dev_id = mevt;
409 evt->irq = IRQ_MCT_L0; 418 evt->irq = EXYNOS4_IRQ_MCT_L0;
410 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 419 setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
411 } else { 420 } else {
412 mct_tick1_event_irq.dev_id = mevt; 421 mct_tick1_event_irq.dev_id = mevt;
413 evt->irq = IRQ_MCT_L1; 422 evt->irq = EXYNOS4_IRQ_MCT_L1;
414 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); 423 setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
415 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); 424 irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
416 } 425 }
417 } else { 426 } else {
418 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0); 427 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
419 } 428 }
420}
421
422/* Setup the local clock events for a CPU */
423int __cpuinit local_timer_setup(struct clock_event_device *evt)
424{
425 exynos4_mct_tick_init(evt);
426 429
427 return 0; 430 return 0;
428} 431}
429 432
430void local_timer_stop(struct clock_event_device *evt) 433static void exynos4_local_timer_stop(struct clock_event_device *evt)
431{ 434{
432 unsigned int cpu = smp_processor_id(); 435 unsigned int cpu = smp_processor_id();
433 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 436 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
@@ -437,8 +440,13 @@ void local_timer_stop(struct clock_event_device *evt)
437 else 440 else
438 remove_irq(evt->irq, &mct_tick1_event_irq); 441 remove_irq(evt->irq, &mct_tick1_event_irq);
439 else 442 else
440 disable_percpu_irq(IRQ_MCT_LOCALTIMER); 443 disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
441} 444}
445
446static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
447 .setup = exynos4_local_timer_setup,
448 .stop = exynos4_local_timer_stop,
449};
442#endif /* CONFIG_LOCAL_TIMERS */ 450#endif /* CONFIG_LOCAL_TIMERS */
443 451
444static void __init exynos4_timer_resources(void) 452static void __init exynos4_timer_resources(void)
@@ -452,12 +460,14 @@ static void __init exynos4_timer_resources(void)
452 if (mct_int_type == MCT_INT_PPI) { 460 if (mct_int_type == MCT_INT_PPI) {
453 int err; 461 int err;
454 462
455 err = request_percpu_irq(IRQ_MCT_LOCALTIMER, 463 err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
456 exynos4_mct_tick_isr, "MCT", 464 exynos4_mct_tick_isr, "MCT",
457 &percpu_mct_tick); 465 &percpu_mct_tick);
458 WARN(err, "MCT: can't request IRQ %d (%d)\n", 466 WARN(err, "MCT: can't request IRQ %d (%d)\n",
459 IRQ_MCT_LOCALTIMER, err); 467 EXYNOS_IRQ_MCT_LOCALTIMER, err);
460 } 468 }
469
470 local_timer_register(&exynos4_mct_tick_ops);
461#endif /* CONFIG_LOCAL_TIMERS */ 471#endif /* CONFIG_LOCAL_TIMERS */
462} 472}
463 473
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 683aec786b78..36c3984aaa47 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
26#include <asm/smp_plat.h>
26#include <asm/smp_scu.h> 27#include <asm/smp_scu.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
@@ -165,7 +166,10 @@ void __init smp_init_cpus(void)
165 void __iomem *scu_base = scu_base_addr(); 166 void __iomem *scu_base = scu_base_addr();
166 unsigned int i, ncores; 167 unsigned int i, ncores;
167 168
168 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 169 if (soc_is_exynos5250())
170 ncores = 2;
171 else
172 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
169 173
170 /* sanity check */ 174 /* sanity check */
171 if (ncores > nr_cpu_ids) { 175 if (ncores > nr_cpu_ids) {
@@ -182,8 +186,8 @@ void __init smp_init_cpus(void)
182 186
183void __init platform_smp_prepare_cpus(unsigned int max_cpus) 187void __init platform_smp_prepare_cpus(unsigned int max_cpus)
184{ 188{
185 189 if (!soc_is_exynos5250())
186 scu_enable(scu_base_addr()); 190 scu_enable(scu_base_addr());
187 191
188 /* 192 /*
189 * Write the address of secondary startup into the 193 * Write the address of secondary startup into the
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a4f61a43c7ba..428cfeb57724 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
38#include <mach/pmu.h> 38#include <mach/pmu.h>
39 39
40static struct sleep_save exynos4_set_clksrc[] = { 40static struct sleep_save exynos4_set_clksrc[] = {
41 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, 41 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
42 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, 42 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
43 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, 43 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
44 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, 44 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
45 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, 45 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
46 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, 46 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
47 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, 47 { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
48 { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, 48 { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
49 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, 49 { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
50}; 50};
51 51
52static struct sleep_save exynos4210_set_clksrc[] = { 52static struct sleep_save exynos4210_set_clksrc[] = {
53 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, 53 { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
54}; 54};
55 55
56static struct sleep_save exynos4_epll_save[] = { 56static struct sleep_save exynos4_epll_save[] = {
57 SAVE_ITEM(S5P_EPLL_CON0), 57 SAVE_ITEM(EXYNOS4_EPLL_CON0),
58 SAVE_ITEM(S5P_EPLL_CON1), 58 SAVE_ITEM(EXYNOS4_EPLL_CON1),
59}; 59};
60 60
61static struct sleep_save exynos4_vpll_save[] = { 61static struct sleep_save exynos4_vpll_save[] = {
62 SAVE_ITEM(S5P_VPLL_CON0), 62 SAVE_ITEM(EXYNOS4_VPLL_CON0),
63 SAVE_ITEM(S5P_VPLL_CON1), 63 SAVE_ITEM(EXYNOS4_VPLL_CON1),
64}; 64};
65 65
66static struct sleep_save exynos4_core_save[] = { 66static struct sleep_save exynos4_core_save[] = {
@@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = {
155 SAVE_ITEM(S5P_SROM_BC3), 155 SAVE_ITEM(S5P_SROM_BC3),
156}; 156};
157 157
158static struct sleep_save exynos4_l2cc_save[] = {
159 SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
160 SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
161 SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
162 SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
163 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
164};
165 158
166/* For Cortex-A9 Diagnostic and Power control register */ 159/* For Cortex-A9 Diagnostic and Power control register */
167static unsigned int save_arm_register[2]; 160static unsigned int save_arm_register[2];
@@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void)
182 u32 tmp; 175 u32 tmp;
183 176
184 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 177 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
185 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
186 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); 178 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
187 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); 179 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
188 180
@@ -206,7 +198,7 @@ static void exynos4_pm_prepare(void)
206 198
207} 199}
208 200
209static int exynos4_pm_add(struct device *dev) 201static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
210{ 202{
211 pm_cpu_prep = exynos4_pm_prepare; 203 pm_cpu_prep = exynos4_pm_prepare;
212 pm_cpu_sleep = exynos4_cpu_suspend; 204 pm_cpu_sleep = exynos4_cpu_suspend;
@@ -239,7 +231,7 @@ static void exynos4_restore_pll(void)
239 locktime = (3000 / pll_in_rate) * p_div; 231 locktime = (3000 / pll_in_rate) * p_div;
240 lockcnt = locktime * 10000 / (10000 / pll_in_rate); 232 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
241 233
242 __raw_writel(lockcnt, S5P_EPLL_LOCK); 234 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
243 235
244 s3c_pm_do_restore_core(exynos4_epll_save, 236 s3c_pm_do_restore_core(exynos4_epll_save,
245 ARRAY_SIZE(exynos4_epll_save)); 237 ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +249,7 @@ static void exynos4_restore_pll(void)
257 locktime = 750; 249 locktime = 750;
258 lockcnt = locktime * 10000 / (10000 / pll_in_rate); 250 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
259 251
260 __raw_writel(lockcnt, S5P_VPLL_LOCK); 252 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
261 253
262 s3c_pm_do_restore_core(exynos4_vpll_save, 254 s3c_pm_do_restore_core(exynos4_vpll_save,
263 ARRAY_SIZE(exynos4_vpll_save)); 255 ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +260,14 @@ static void exynos4_restore_pll(void)
268 260
269 do { 261 do {
270 if (epll_wait) { 262 if (epll_wait) {
271 pll_con = __raw_readl(S5P_EPLL_CON0); 263 pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
272 if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) 264 if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
273 epll_wait = 0; 265 epll_wait = 0;
274 } 266 }
275 267
276 if (vpll_wait) { 268 if (vpll_wait) {
277 pll_con = __raw_readl(S5P_VPLL_CON0); 269 pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
278 if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) 270 if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
279 vpll_wait = 0; 271 vpll_wait = 0;
280 } 272 }
281 } while (epll_wait || vpll_wait); 273 } while (epll_wait || vpll_wait);
@@ -384,13 +376,8 @@ static void exynos4_pm_resume(void)
384 376
385 exynos4_restore_pll(); 377 exynos4_restore_pll();
386 378
379#ifdef CONFIG_SMP
387 scu_enable(S5P_VA_SCU); 380 scu_enable(S5P_VA_SCU);
388
389#ifdef CONFIG_CACHE_L2X0
390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
391 outer_inv_all();
392 /* enable L2X0*/
393 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
394#endif 381#endif
395 382
396early_wakeup: 383early_wakeup:
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
new file mode 100644
index 000000000000..13b306808b42
--- /dev/null
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -0,0 +1,201 @@
1/*
2 * Exynos Generic power domain support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Implementation of Exynos specific power domain control which is used in
8 * conjunction with runtime-pm. Support for both device-tree and non-device-tree
9 * based power domain support is included.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/pm_domain.h>
20#include <linux/delay.h>
21#include <linux/of_address.h>
22
23#include <mach/regs-pmu.h>
24#include <plat/devs.h>
25
26/*
27 * Exynos specific wrapper around the generic power domain
28 */
29struct exynos_pm_domain {
30 void __iomem *base;
31 char const *name;
32 bool is_off;
33 struct generic_pm_domain pd;
34};
35
36static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
37{
38 struct exynos_pm_domain *pd;
39 void __iomem *base;
40 u32 timeout, pwr;
41 char *op;
42
43 pd = container_of(domain, struct exynos_pm_domain, pd);
44 base = pd->base;
45
46 pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
47 __raw_writel(pwr, base);
48
49 /* Wait max 1ms */
50 timeout = 10;
51
52 while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
53 if (!timeout) {
54 op = (power_on) ? "enable" : "disable";
55 pr_err("Power domain %s %s failed\n", domain->name, op);
56 return -ETIMEDOUT;
57 }
58 timeout--;
59 cpu_relax();
60 usleep_range(80, 100);
61 }
62 return 0;
63}
64
65static int exynos_pd_power_on(struct generic_pm_domain *domain)
66{
67 return exynos_pd_power(domain, true);
68}
69
70static int exynos_pd_power_off(struct generic_pm_domain *domain)
71{
72 return exynos_pd_power(domain, false);
73}
74
75#define EXYNOS_GPD(PD, BASE, NAME) \
76static struct exynos_pm_domain PD = { \
77 .base = (void __iomem *)BASE, \
78 .name = NAME, \
79 .pd = { \
80 .power_off = exynos_pd_power_off, \
81 .power_on = exynos_pd_power_on, \
82 }, \
83}
84
85#ifdef CONFIG_OF
86static __init int exynos_pm_dt_parse_domains(void)
87{
88 struct device_node *np;
89
90 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
91 struct exynos_pm_domain *pd;
92
93 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
94 if (!pd) {
95 pr_err("%s: failed to allocate memory for domain\n",
96 __func__);
97 return -ENOMEM;
98 }
99
100 if (of_get_property(np, "samsung,exynos4210-pd-off", NULL))
101 pd->is_off = true;
102 pd->name = np->name;
103 pd->base = of_iomap(np, 0);
104 pd->pd.power_off = exynos_pd_power_off;
105 pd->pd.power_on = exynos_pd_power_on;
106 pd->pd.of_node = np;
107 pm_genpd_init(&pd->pd, NULL, false);
108 }
109 return 0;
110}
111#else
112static __init int exynos_pm_dt_parse_domains(void)
113{
114 return 0;
115}
116#endif /* CONFIG_OF */
117
118static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
119 struct exynos_pm_domain *pd)
120{
121 if (pdev->dev.bus) {
122 if (pm_genpd_add_device(&pd->pd, &pdev->dev))
123 pr_info("%s: error in adding %s device to %s power"
124 "domain\n", __func__, dev_name(&pdev->dev),
125 pd->name);
126 }
127}
128
129EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
130EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
131EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
132EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
133EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
134EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
135EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
136
137static struct exynos_pm_domain *exynos4_pm_domains[] = {
138 &exynos4_pd_mfc,
139 &exynos4_pd_g3d,
140 &exynos4_pd_lcd0,
141 &exynos4_pd_lcd1,
142 &exynos4_pd_tv,
143 &exynos4_pd_cam,
144 &exynos4_pd_gps,
145};
146
147static __init int exynos4_pm_init_power_domain(void)
148{
149 int idx;
150
151 if (of_have_populated_dt())
152 return exynos_pm_dt_parse_domains();
153
154 for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++)
155 pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL,
156 exynos4_pm_domains[idx]->is_off);
157
158#ifdef CONFIG_S5P_DEV_FIMD0
159 exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
160#endif
161#ifdef CONFIG_S5P_DEV_TV
162 exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
163 exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
164#endif
165#ifdef CONFIG_S5P_DEV_MFC
166 exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
167#endif
168#ifdef CONFIG_S5P_DEV_FIMC0
169 exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
170#endif
171#ifdef CONFIG_S5P_DEV_FIMC1
172 exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
173#endif
174#ifdef CONFIG_S5P_DEV_FIMC2
175 exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
176#endif
177#ifdef CONFIG_S5P_DEV_FIMC3
178 exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
179#endif
180#ifdef CONFIG_S5P_DEV_CSIS0
181 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
182#endif
183#ifdef CONFIG_S5P_DEV_CSIS1
184 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
185#endif
186#ifdef CONFIG_S5P_DEV_G2D
187 exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
188#endif
189#ifdef CONFIG_S5P_DEV_JPEG
190 exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
191#endif
192 return 0;
193}
194arch_initcall(exynos4_pm_init_power_domain);
195
196static __init int exynos_pm_late_initcall(void)
197{
198 pm_genpd_poweroff_unused();
199 return 0;
200}
201late_initcall(exynos_pm_late_initcall);
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd17c38b..b90d94c17f7c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c0.c 2 * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/ 3 * http://www.samsung.com/
6 * 4 *
7 * I2C0 GPIO configuration. 5 * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
18#include <linux/gpio.h> 16#include <linux/gpio.h>
19#include <plat/iic.h> 17#include <plat/iic.h>
20#include <plat/gpio-cfg.h> 18#include <plat/gpio-cfg.h>
19#include <plat/cpu.h>
21 20
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 21void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 22{
23 if (soc_is_exynos5250())
24 /* will be implemented with gpio function */
25 return;
26
24 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, 27 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26} 29}