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-rw-r--r--arch/arm/mach-exynos/Kconfig2
-rw-r--r--arch/arm/mach-exynos/Makefile9
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c3
-rw-r--r--arch/arm/mach-exynos/clock.c3
-rw-r--r--arch/arm/mach-exynos/common.c713
-rw-r--r--arch/arm/mach-exynos/common.h41
-rw-r--r--arch/arm/mach-exynos/cpu.c298
-rw-r--r--arch/arm/mach-exynos/include/mach/entry-macro.S75
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/vmalloc.h22
-rw-r--r--arch/arm/mach-exynos/init.c42
-rw-r--r--arch/arm/mach-exynos/irq-combiner.c124
-rw-r--r--arch/arm/mach-exynos/irq-eint.c237
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c8
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c8
-rw-r--r--arch/arm/mach-exynos/mach-origen.c8
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c10
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c10
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c8
-rw-r--r--arch/arm/mach-exynos/mct.c13
-rw-r--r--arch/arm/mach-exynos/platsmp.c28
23 files changed, 820 insertions, 859 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 724ec0f3560d..e1efbca2a539 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -17,6 +17,8 @@ choice
17 17
18config ARCH_EXYNOS4 18config ARCH_EXYNOS4
19 bool "SAMSUNG EXYNOS4" 19 bool "SAMSUNG EXYNOS4"
20 select HAVE_SMP
21 select MIGHT_HAVE_CACHE_L2X0
20 help 22 help
21 Samsung EXYNOS4 SoCs based systems 23 Samsung EXYNOS4 SoCs based systems
22 24
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 59069a35e40b..bcb9efc576e9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -10,15 +10,17 @@ obj-m :=
10obj-n := 10obj-n :=
11obj- := 11obj- :=
12 12
13# Core support for EXYNOS4 system 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o 15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
16obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 21
22obj-$(CONFIG_ARCH_EXYNOS4) += dma.o pmu.o
23
22obj-$(CONFIG_SMP) += platsmp.o headsmp.o 24obj-$(CONFIG_SMP) += platsmp.o headsmp.o
23 25
24obj-$(CONFIG_EXYNOS4_MCT) += mct.o 26obj-$(CONFIG_EXYNOS4_MCT) += mct.o
@@ -45,6 +47,7 @@ obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
45obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 47obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
46obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 48obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
47 49
50obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
48obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 51obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
49obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 52obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 53obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index b9d5ef670eb4..a5823a7f249e 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4210_clock_save[] = { 35static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1), 37 SAVE_ITEM(S5P_CLKSRC_LCD1),
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 77d5decb34fd..26a668b0d101 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4212_clock_save[] = { 35static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKDIV_IMAGE), 37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5c..83616a039b15 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -21,7 +21,6 @@
21#include <plat/pll.h> 21#include <plat/pll.h>
22#include <plat/s5p-clock.h> 22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h> 23#include <plat/clock-clksrc.h>
24#include <plat/exynos4.h>
25#include <plat/pm.h> 24#include <plat/pm.h>
26 25
27#include <mach/map.h> 26#include <mach/map.h>
@@ -29,6 +28,8 @@
29#include <mach/sysmmu.h> 28#include <mach/sysmmu.h>
30#include <mach/exynos4-clock.h> 29#include <mach/exynos4-clock.h>
31 30
31#include "common.h"
32
32static struct sleep_save exynos4_clock_save[] = { 33static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
new file mode 100644
index 000000000000..d2acb0f948c6
--- /dev/null
+++ b/arch/arm/mach-exynos/common.c
@@ -0,0 +1,713 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/sysdev.h>
17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
20
21#include <asm/proc-fns.h>
22#include <asm/hardware/cache-l2x0.h>
23#include <asm/hardware/gic.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <mach/regs-irq.h>
28#include <mach/regs-pmu.h>
29#include <mach/regs-gpio.h>
30
31#include <plat/cpu.h>
32#include <plat/clock.h>
33#include <plat/devs.h>
34#include <plat/pm.h>
35#include <plat/sdhci.h>
36#include <plat/gpio-cfg.h>
37#include <plat/adc-core.h>
38#include <plat/fb-core.h>
39#include <plat/fimc-core.h>
40#include <plat/iic-core.h>
41#include <plat/tv-core.h>
42#include <plat/regs-serial.h>
43
44#include "common.h"
45
46unsigned int gic_bank_offset __read_mostly;
47
48static const char name_exynos4210[] = "EXYNOS4210";
49static const char name_exynos4212[] = "EXYNOS4212";
50static const char name_exynos4412[] = "EXYNOS4412";
51
52static struct cpu_table cpu_ids[] __initdata = {
53 {
54 .idcode = EXYNOS4210_CPU_ID,
55 .idmask = EXYNOS4_CPU_MASK,
56 .map_io = exynos4_map_io,
57 .init_clocks = exynos4_init_clocks,
58 .init_uarts = exynos4_init_uarts,
59 .init = exynos_init,
60 .name = name_exynos4210,
61 }, {
62 .idcode = EXYNOS4212_CPU_ID,
63 .idmask = EXYNOS4_CPU_MASK,
64 .map_io = exynos4_map_io,
65 .init_clocks = exynos4_init_clocks,
66 .init_uarts = exynos4_init_uarts,
67 .init = exynos_init,
68 .name = name_exynos4212,
69 }, {
70 .idcode = EXYNOS4412_CPU_ID,
71 .idmask = EXYNOS4_CPU_MASK,
72 .map_io = exynos4_map_io,
73 .init_clocks = exynos4_init_clocks,
74 .init_uarts = exynos4_init_uarts,
75 .init = exynos_init,
76 .name = name_exynos4412,
77 },
78};
79
80/* Initial IO mappings */
81
82static struct map_desc exynos_iodesc[] __initdata = {
83 {
84 .virtual = (unsigned long)S5P_VA_CHIPID,
85 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
86 .length = SZ_4K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S3C_VA_SYS,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
91 .length = SZ_64K,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (unsigned long)S3C_VA_TIMER,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
96 .length = SZ_16K,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = (unsigned long)S3C_VA_WATCHDOG,
100 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
101 .length = SZ_4K,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (unsigned long)S5P_VA_SROMC,
105 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
106 .length = SZ_4K,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = (unsigned long)S5P_VA_SYSTIMER,
110 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
111 .length = SZ_4K,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = (unsigned long)S5P_VA_PMU,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
116 .length = SZ_64K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = (unsigned long)S5P_VA_GIC_CPU,
125 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
126 .length = SZ_64K,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = (unsigned long)S5P_VA_GIC_DIST,
130 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
131 .length = SZ_64K,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = (unsigned long)S3C_VA_UART,
135 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
136 .length = SZ_512K,
137 .type = MT_DEVICE,
138 },
139};
140
141static struct map_desc exynos4_iodesc[] __initdata = {
142 {
143 .virtual = (unsigned long)S5P_VA_CMU,
144 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
145 .length = SZ_128K,
146 .type = MT_DEVICE,
147 }, {
148 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
150 .length = SZ_8K,
151 .type = MT_DEVICE,
152 }, {
153 .virtual = (unsigned long)S5P_VA_L2CC,
154 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
155 .length = SZ_4K,
156 .type = MT_DEVICE,
157 }, {
158 .virtual = (unsigned long)S5P_VA_GPIO1,
159 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
160 .length = SZ_4K,
161 .type = MT_DEVICE,
162 }, {
163 .virtual = (unsigned long)S5P_VA_GPIO2,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
165 .length = SZ_4K,
166 .type = MT_DEVICE,
167 }, {
168 .virtual = (unsigned long)S5P_VA_GPIO3,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
170 .length = SZ_256,
171 .type = MT_DEVICE,
172 }, {
173 .virtual = (unsigned long)S5P_VA_DMC0,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
175 .length = SZ_4K,
176 .type = MT_DEVICE,
177 }, {
178 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
180 .length = SZ_4K,
181 .type = MT_DEVICE,
182 },
183};
184
185static struct map_desc exynos4_iodesc0[] __initdata = {
186 {
187 .virtual = (unsigned long)S5P_VA_SYSRAM,
188 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
189 .length = SZ_4K,
190 .type = MT_DEVICE,
191 },
192};
193
194static struct map_desc exynos4_iodesc1[] __initdata = {
195 {
196 .virtual = (unsigned long)S5P_VA_SYSRAM,
197 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
198 .length = SZ_4K,
199 .type = MT_DEVICE,
200 },
201};
202
203static void exynos_idle(void)
204{
205 if (!need_resched())
206 cpu_do_idle();
207
208 local_irq_enable();
209}
210
211void exynos4_restart(char mode, const char *cmd)
212{
213 __raw_writel(0x1, S5P_SWRESET);
214}
215
216/*
217 * exynos_map_io
218 *
219 * register the standard cpu IO areas
220 */
221
222void __init exynos_init_io(struct map_desc *mach_desc, int size)
223{
224 /* initialize the io descriptors we need for initialization */
225 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
226 if (mach_desc)
227 iotable_init(mach_desc, size);
228
229 /* detect cpu id and rev. */
230 s5p_init_cpu(S5P_VA_CHIPID);
231
232 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
233}
234
235void __init exynos4_map_io(void)
236{
237 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
238
239 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
240 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
241 else
242 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
243
244 /* initialize device information early */
245 exynos4_default_sdhci0();
246 exynos4_default_sdhci1();
247 exynos4_default_sdhci2();
248 exynos4_default_sdhci3();
249
250 s3c_adc_setname("samsung-adc-v3");
251
252 s3c_fimc_setname(0, "exynos4-fimc");
253 s3c_fimc_setname(1, "exynos4-fimc");
254 s3c_fimc_setname(2, "exynos4-fimc");
255 s3c_fimc_setname(3, "exynos4-fimc");
256
257 /* The I2C bus controllers are directly compatible with s3c2440 */
258 s3c_i2c0_setname("s3c2440-i2c");
259 s3c_i2c1_setname("s3c2440-i2c");
260 s3c_i2c2_setname("s3c2440-i2c");
261
262 s5p_fb_setname(0, "exynos4-fb");
263 s5p_hdmi_setname("exynos4-hdmi");
264}
265
266void __init exynos4_init_clocks(int xtal)
267{
268 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
269
270 s3c24xx_register_baseclocks(xtal);
271 s5p_register_clocks(xtal);
272
273 if (soc_is_exynos4210())
274 exynos4210_register_clocks();
275 else if (soc_is_exynos4212() || soc_is_exynos4412())
276 exynos4212_register_clocks();
277
278 exynos4_register_clocks();
279 exynos4_setup_clocks();
280}
281
282#define COMBINER_ENABLE_SET 0x0
283#define COMBINER_ENABLE_CLEAR 0x4
284#define COMBINER_INT_STATUS 0xC
285
286static DEFINE_SPINLOCK(irq_controller_lock);
287
288struct combiner_chip_data {
289 unsigned int irq_offset;
290 unsigned int irq_mask;
291 void __iomem *base;
292};
293
294static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
295
296static inline void __iomem *combiner_base(struct irq_data *data)
297{
298 struct combiner_chip_data *combiner_data =
299 irq_data_get_irq_chip_data(data);
300
301 return combiner_data->base;
302}
303
304static void combiner_mask_irq(struct irq_data *data)
305{
306 u32 mask = 1 << (data->irq % 32);
307
308 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
309}
310
311static void combiner_unmask_irq(struct irq_data *data)
312{
313 u32 mask = 1 << (data->irq % 32);
314
315 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
316}
317
318static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
319{
320 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
321 struct irq_chip *chip = irq_get_chip(irq);
322 unsigned int cascade_irq, combiner_irq;
323 unsigned long status;
324
325 chained_irq_enter(chip, desc);
326
327 spin_lock(&irq_controller_lock);
328 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
329 spin_unlock(&irq_controller_lock);
330 status &= chip_data->irq_mask;
331
332 if (status == 0)
333 goto out;
334
335 combiner_irq = __ffs(status);
336
337 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
338 if (unlikely(cascade_irq >= NR_IRQS))
339 do_bad_IRQ(cascade_irq, desc);
340 else
341 generic_handle_irq(cascade_irq);
342
343 out:
344 chained_irq_exit(chip, desc);
345}
346
347static struct irq_chip combiner_chip = {
348 .name = "COMBINER",
349 .irq_mask = combiner_mask_irq,
350 .irq_unmask = combiner_unmask_irq,
351};
352
353static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
354{
355 if (combiner_nr >= MAX_COMBINER_NR)
356 BUG();
357 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
358 BUG();
359 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
360}
361
362static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
363 unsigned int irq_start)
364{
365 unsigned int i;
366
367 if (combiner_nr >= MAX_COMBINER_NR)
368 BUG();
369
370 combiner_data[combiner_nr].base = base;
371 combiner_data[combiner_nr].irq_offset = irq_start;
372 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
373
374 /* Disable all interrupts */
375
376 __raw_writel(combiner_data[combiner_nr].irq_mask,
377 base + COMBINER_ENABLE_CLEAR);
378
379 /* Setup the Linux IRQ subsystem */
380
381 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
382 + MAX_IRQ_IN_COMBINER; i++) {
383 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
384 irq_set_chip_data(i, &combiner_data[combiner_nr]);
385 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
386 }
387}
388
389static void exynos4_gic_irq_fix_base(struct irq_data *d)
390{
391 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
392
393 gic_data->cpu_base = S5P_VA_GIC_CPU +
394 (gic_bank_offset * smp_processor_id());
395
396 gic_data->dist_base = S5P_VA_GIC_DIST +
397 (gic_bank_offset * smp_processor_id());
398}
399
400void __init exynos4_init_irq(void)
401{
402 int irq;
403
404 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
405
406 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
407 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
408 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
409 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
410
411 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
412
413 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
414 COMBINER_IRQ(irq, 0));
415 combiner_cascade_irq(irq, IRQ_SPI(irq));
416 }
417
418 /*
419 * The parameters of s5p_init_irq() are for VIC init.
420 * Theses parameters should be NULL and 0 because EXYNOS4
421 * uses GIC instead of VIC.
422 */
423 s5p_init_irq(NULL, 0);
424}
425
426struct sysdev_class exynos4_sysclass = {
427 .name = "exynos4-core",
428};
429
430static struct sys_device exynos4_sysdev = {
431 .cls = &exynos4_sysclass,
432};
433
434static int __init exynos4_core_init(void)
435{
436 return sysdev_class_register(&exynos4_sysclass);
437}
438core_initcall(exynos4_core_init);
439
440#ifdef CONFIG_CACHE_L2X0
441static int __init exynos4_l2x0_cache_init(void)
442{
443 /* TAG, Data Latency Control: 2cycle */
444 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
445
446 if (soc_is_exynos4210())
447 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
448 else if (soc_is_exynos4212() || soc_is_exynos4412())
449 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
450
451 /* L2X0 Prefetch Control */
452 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
453
454 /* L2X0 Power Control */
455 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
456 S5P_VA_L2CC + L2X0_POWER_CTRL);
457
458 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
459
460 return 0;
461}
462
463early_initcall(exynos4_l2x0_cache_init);
464#endif
465
466int __init exynos_init(void)
467{
468 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
469
470 /* set idle function */
471 pm_idle = exynos_idle;
472
473 return sysdev_register(&exynos4_sysdev);
474}
475
476static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
477 [0] = {
478 .name = "uclk1",
479 .divisor = 1,
480 .min_baud = 0,
481 .max_baud = 0,
482 },
483};
484
485/* uart registration process */
486
487void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
488{
489 struct s3c2410_uartcfg *tcfg = cfg;
490 u32 ucnt;
491
492 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
493 if (!tcfg->clocks) {
494 tcfg->has_fracval = 1;
495 tcfg->clocks = exynos4_serial_clocks;
496 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
497 }
498 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
499 }
500
501 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
502}
503
504static DEFINE_SPINLOCK(eint_lock);
505
506static unsigned int eint0_15_data[16];
507
508static unsigned int exynos4_get_irq_nr(unsigned int number)
509{
510 u32 ret = 0;
511
512 switch (number) {
513 case 0 ... 3:
514 ret = (number + IRQ_EINT0);
515 break;
516 case 4 ... 7:
517 ret = (number + (IRQ_EINT4 - 4));
518 break;
519 case 8 ... 15:
520 ret = (number + (IRQ_EINT8 - 8));
521 break;
522 default:
523 printk(KERN_ERR "number available : %d\n", number);
524 }
525
526 return ret;
527}
528
529static inline void exynos4_irq_eint_mask(struct irq_data *data)
530{
531 u32 mask;
532
533 spin_lock(&eint_lock);
534 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
535 mask |= eint_irq_to_bit(data->irq);
536 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
537 spin_unlock(&eint_lock);
538}
539
540static void exynos4_irq_eint_unmask(struct irq_data *data)
541{
542 u32 mask;
543
544 spin_lock(&eint_lock);
545 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
546 mask &= ~(eint_irq_to_bit(data->irq));
547 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
548 spin_unlock(&eint_lock);
549}
550
551static inline void exynos4_irq_eint_ack(struct irq_data *data)
552{
553 __raw_writel(eint_irq_to_bit(data->irq),
554 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
555}
556
557static void exynos4_irq_eint_maskack(struct irq_data *data)
558{
559 exynos4_irq_eint_mask(data);
560 exynos4_irq_eint_ack(data);
561}
562
563static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
564{
565 int offs = EINT_OFFSET(data->irq);
566 int shift;
567 u32 ctrl, mask;
568 u32 newvalue = 0;
569
570 switch (type) {
571 case IRQ_TYPE_EDGE_RISING:
572 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
573 break;
574
575 case IRQ_TYPE_EDGE_FALLING:
576 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
577 break;
578
579 case IRQ_TYPE_EDGE_BOTH:
580 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
581 break;
582
583 case IRQ_TYPE_LEVEL_LOW:
584 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
585 break;
586
587 case IRQ_TYPE_LEVEL_HIGH:
588 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
589 break;
590
591 default:
592 printk(KERN_ERR "No such irq type %d", type);
593 return -EINVAL;
594 }
595
596 shift = (offs & 0x7) * 4;
597 mask = 0x7 << shift;
598
599 spin_lock(&eint_lock);
600 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
601 ctrl &= ~mask;
602 ctrl |= newvalue << shift;
603 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
604 spin_unlock(&eint_lock);
605
606 switch (offs) {
607 case 0 ... 7:
608 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
609 break;
610 case 8 ... 15:
611 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
612 break;
613 case 16 ... 23:
614 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
615 break;
616 case 24 ... 31:
617 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
618 break;
619 default:
620 printk(KERN_ERR "No such irq number %d", offs);
621 }
622
623 return 0;
624}
625
626static struct irq_chip exynos4_irq_eint = {
627 .name = "exynos4-eint",
628 .irq_mask = exynos4_irq_eint_mask,
629 .irq_unmask = exynos4_irq_eint_unmask,
630 .irq_mask_ack = exynos4_irq_eint_maskack,
631 .irq_ack = exynos4_irq_eint_ack,
632 .irq_set_type = exynos4_irq_eint_set_type,
633#ifdef CONFIG_PM
634 .irq_set_wake = s3c_irqext_wake,
635#endif
636};
637
638/*
639 * exynos4_irq_demux_eint
640 *
641 * This function demuxes the IRQ from from EINTs 16 to 31.
642 * It is designed to be inlined into the specific handler
643 * s5p_irq_demux_eintX_Y.
644 *
645 * Each EINT pend/mask registers handle eight of them.
646 */
647static inline void exynos4_irq_demux_eint(unsigned int start)
648{
649 unsigned int irq;
650
651 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
652 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
653
654 status &= ~mask;
655 status &= 0xff;
656
657 while (status) {
658 irq = fls(status) - 1;
659 generic_handle_irq(irq + start);
660 status &= ~(1 << irq);
661 }
662}
663
664static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
665{
666 struct irq_chip *chip = irq_get_chip(irq);
667 chained_irq_enter(chip, desc);
668 exynos4_irq_demux_eint(IRQ_EINT(16));
669 exynos4_irq_demux_eint(IRQ_EINT(24));
670 chained_irq_exit(chip, desc);
671}
672
673static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
674{
675 u32 *irq_data = irq_get_handler_data(irq);
676 struct irq_chip *chip = irq_get_chip(irq);
677
678 chained_irq_enter(chip, desc);
679 chip->irq_mask(&desc->irq_data);
680
681 if (chip->irq_ack)
682 chip->irq_ack(&desc->irq_data);
683
684 generic_handle_irq(*irq_data);
685
686 chip->irq_unmask(&desc->irq_data);
687 chained_irq_exit(chip, desc);
688}
689
690int __init exynos4_init_irq_eint(void)
691{
692 int irq;
693
694 for (irq = 0 ; irq <= 31 ; irq++) {
695 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
696 handle_level_irq);
697 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
698 }
699
700 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
701
702 for (irq = 0 ; irq <= 15 ; irq++) {
703 eint0_15_data[irq] = IRQ_EINT(irq);
704
705 irq_set_handler_data(exynos4_get_irq_nr(irq),
706 &eint0_15_data[irq]);
707 irq_set_chained_handler(exynos4_get_irq_nr(irq),
708 exynos4_irq_eint0_15);
709 }
710
711 return 0;
712}
713arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
new file mode 100644
index 000000000000..1ac49de0f398
--- /dev/null
+++ b/arch/arm/mach-exynos/common.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for EXYNOS machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14
15void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void);
17
18void exynos4_register_clocks(void);
19void exynos4_setup_clocks(void);
20
21void exynos4210_register_clocks(void);
22void exynos4212_register_clocks(void);
23
24void exynos4_restart(char mode, const char *cmd);
25
26extern struct sys_timer exynos4_timer;
27
28#ifdef CONFIG_ARCH_EXYNOS
29extern int exynos_init(void);
30extern void exynos4_map_io(void);
31extern void exynos4_init_clocks(int xtal);
32extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
33
34#else
35#define exynos4_init_clocks NULL
36#define exynos4_init_uarts NULL
37#define exynos4_map_io NULL
38#define exynos_init NULL
39#endif
40
41#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
deleted file mode 100644
index 90ec247f3b37..000000000000
--- a/arch/arm/mach-exynos/cpu.c
+++ /dev/null
@@ -1,298 +0,0 @@
1/* linux/arch/arm/mach-exynos/cpu.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h>
19#include <asm/hardware/gic.h>
20
21#include <plat/cpu.h>
22#include <plat/clock.h>
23#include <plat/devs.h>
24#include <plat/exynos4.h>
25#include <plat/adc-core.h>
26#include <plat/sdhci.h>
27#include <plat/fb-core.h>
28#include <plat/fimc-core.h>
29#include <plat/iic-core.h>
30#include <plat/reset.h>
31#include <plat/tv-core.h>
32
33#include <mach/regs-irq.h>
34#include <mach/regs-pmu.h>
35
36unsigned int gic_bank_offset __read_mostly;
37
38extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
39 unsigned int irq_start);
40extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
41
42/* Initial IO mappings */
43static struct map_desc exynos_iodesc[] __initdata = {
44 {
45 .virtual = (unsigned long)S5P_VA_SYSTIMER,
46 .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
47 .length = SZ_4K,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = (unsigned long)S5P_VA_PMU,
51 .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
52 .length = SZ_64K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
56 .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (unsigned long)S5P_VA_GIC_CPU,
61 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
62 .length = SZ_64K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (unsigned long)S5P_VA_GIC_DIST,
66 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
67 .length = SZ_64K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (unsigned long)S3C_VA_UART,
71 .pfn = __phys_to_pfn(S3C_PA_UART),
72 .length = SZ_512K,
73 .type = MT_DEVICE,
74 },
75};
76
77static struct map_desc exynos4_iodesc[] __initdata = {
78 {
79 .virtual = (unsigned long)S5P_VA_CMU,
80 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
81 .length = SZ_128K,
82 .type = MT_DEVICE,
83 }, {
84 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
85 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
86 .length = SZ_8K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S5P_VA_L2CC,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
91 .length = SZ_4K,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (unsigned long)S5P_VA_GPIO1,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
96 .length = SZ_4K,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = (unsigned long)S5P_VA_GPIO2,
100 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
101 .length = SZ_4K,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (unsigned long)S5P_VA_GPIO3,
105 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
106 .length = SZ_256,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = (unsigned long)S5P_VA_DMC0,
110 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
111 .length = SZ_4K,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = (unsigned long)S5P_VA_SROMC,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
116 .length = SZ_4K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
123 },
124};
125
126static struct map_desc exynos4_iodesc0[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_SYSRAM,
129 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
134
135static struct map_desc exynos4_iodesc1[] __initdata = {
136 {
137 .virtual = (unsigned long)S5P_VA_SYSRAM,
138 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
139 .length = SZ_4K,
140 .type = MT_DEVICE,
141 },
142};
143
144static void exynos_idle(void)
145{
146 if (!need_resched())
147 cpu_do_idle();
148
149 local_irq_enable();
150}
151
152static void exynos4_sw_reset(void)
153{
154 __raw_writel(0x1, S5P_SWRESET);
155}
156
157/*
158 * exynos_map_io
159 *
160 * register the standard cpu IO areas
161 */
162void __init exynos4_map_io(void)
163{
164 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
165 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
166
167 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
168 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
169 else
170 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
171
172 /* initialize device information early */
173 exynos4_default_sdhci0();
174 exynos4_default_sdhci1();
175 exynos4_default_sdhci2();
176 exynos4_default_sdhci3();
177
178 s3c_adc_setname("samsung-adc-v3");
179
180 s3c_fimc_setname(0, "exynos4-fimc");
181 s3c_fimc_setname(1, "exynos4-fimc");
182 s3c_fimc_setname(2, "exynos4-fimc");
183 s3c_fimc_setname(3, "exynos4-fimc");
184
185 /* The I2C bus controllers are directly compatible with s3c2440 */
186 s3c_i2c0_setname("s3c2440-i2c");
187 s3c_i2c1_setname("s3c2440-i2c");
188 s3c_i2c2_setname("s3c2440-i2c");
189
190 s5p_fb_setname(0, "exynos4-fb");
191 s5p_hdmi_setname("exynos4-hdmi");
192}
193
194void __init exynos4_init_clocks(int xtal)
195{
196 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
197
198 s3c24xx_register_baseclocks(xtal);
199 s5p_register_clocks(xtal);
200
201 if (soc_is_exynos4210())
202 exynos4210_register_clocks();
203 else if (soc_is_exynos4212() || soc_is_exynos4412())
204 exynos4212_register_clocks();
205
206 exynos4_register_clocks();
207 exynos4_setup_clocks();
208}
209
210static void exynos4_gic_irq_fix_base(struct irq_data *d)
211{
212 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
213
214 gic_data->cpu_base = S5P_VA_GIC_CPU +
215 (gic_bank_offset * smp_processor_id());
216
217 gic_data->dist_base = S5P_VA_GIC_DIST +
218 (gic_bank_offset * smp_processor_id());
219}
220
221void __init exynos4_init_irq(void)
222{
223 int irq;
224
225 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
226
227 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
228 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
229 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
230 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
231
232 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
233
234 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
235 COMBINER_IRQ(irq, 0));
236 combiner_cascade_irq(irq, IRQ_SPI(irq));
237 }
238
239 /* The parameters of s5p_init_irq() are for VIC init.
240 * Theses parameters should be NULL and 0 because EXYNOS4
241 * uses GIC instead of VIC.
242 */
243 s5p_init_irq(NULL, 0);
244}
245
246struct sysdev_class exynos4_sysclass = {
247 .name = "exynos4-core",
248};
249
250static struct sys_device exynos4_sysdev = {
251 .cls = &exynos4_sysclass,
252};
253
254static int __init exynos4_core_init(void)
255{
256 return sysdev_class_register(&exynos4_sysclass);
257}
258core_initcall(exynos4_core_init);
259
260#ifdef CONFIG_CACHE_L2X0
261static int __init exynos4_l2x0_cache_init(void)
262{
263 /* TAG, Data Latency Control: 2cycle */
264 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
265
266 if (soc_is_exynos4210())
267 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
268 else if (soc_is_exynos4212() || soc_is_exynos4412())
269 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
270
271 /* L2X0 Prefetch Control */
272 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
273
274 /* L2X0 Power Control */
275 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
276 S5P_VA_L2CC + L2X0_POWER_CTRL);
277
278 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
279
280 return 0;
281}
282
283early_initcall(exynos4_l2x0_cache_init);
284#endif
285
286int __init exynos_init(void)
287{
288 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
289
290 /* set idle function */
291 pm_idle = exynos_idle;
292
293 /* set sw_reset function */
294 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
295 s5p_reset_hook = exynos4_sw_reset;
296
297 return sysdev_register(&exynos4_sysdev);
298}
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
index f5e9fd8e37b4..3ba4f547534b 100644
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -9,83 +9,8 @@
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10*/ 10*/
11 11
12#include <mach/hardware.h>
13#include <mach/map.h>
14#include <asm/hardware/gic.h>
15
16 .macro disable_fiq 12 .macro disable_fiq
17 .endm 13 .endm
18 14
19 .macro get_irqnr_preamble, base, tmp
20 mov \tmp, #0
21
22 mrc p15, 0, \base, c0, c0, 5
23 and \base, \base, #3
24 cmp \base, #0
25 beq 1f
26
27 ldr \tmp, =gic_bank_offset
28 ldr \tmp, [\tmp]
29 cmp \base, #1
30 beq 1f
31
32 cmp \base, #2
33 addeq \tmp, \tmp, \tmp
34 addne \tmp, \tmp, \tmp, LSL #1
35
361: ldr \base, =gic_cpu_base_addr
37 ldr \base, [\base]
38 add \base, \base, \tmp
39 .endm
40
41 .macro arch_ret_to_user, tmp1, tmp2 15 .macro arch_ret_to_user, tmp1, tmp2
42 .endm 16 .endm
43
44 /*
45 * The interrupt numbering scheme is defined in the
46 * interrupt controller spec. To wit:
47 *
48 * Interrupts 0-15 are IPI
49 * 16-28 are reserved
50 * 29-31 are local. We allow 30 to be used for the watchdog.
51 * 32-1020 are global
52 * 1021-1022 are reserved
53 * 1023 is "spurious" (no interrupt)
54 *
55 * For now, we ignore all local interrupts so only return an interrupt if it's
56 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
57 *
58 * A simple read from the controller will tell us the number of the highest
59 * priority enabled interrupt. We then just need to check whether it is in the
60 * valid range for an IRQ (30-1020 inclusive).
61 */
62
63 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
64
65 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
66
67 ldr \tmp, =1021
68
69 bic \irqnr, \irqstat, #0x1c00
70
71 cmp \irqnr, #15
72 cmpcc \irqnr, \irqnr
73 cmpne \irqnr, \tmp
74 cmpcs \irqnr, \irqnr
75 addne \irqnr, \irqnr, #32
76
77 .endm
78
79 /* We assume that irqstat (the raw value of the IRQ acknowledge
80 * register) is preserved from the macro above.
81 * If there is an IPI, we immediately signal end of interrupt on the
82 * controller, since this requires the original irqstat value which
83 * we won't easily be able to recreate later.
84 */
85
86 .macro test_for_ipi, irqnr, irqstat, base, tmp
87 bic \irqnr, \irqstat, #0x1c00
88 cmp \irqnr, #16
89 strcc \irqstat, [\base, #GIC_CPU_EOI]
90 cmpcs \irqnr, \irqnr
91 .endm
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 058541d45af0..d1829860a0ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -149,7 +149,6 @@
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART 150#define S3C_PA_UART EXYNOS4_PA_UART
151 151
152#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
153#define S5P_PA_EHCI EXYNOS4_PA_EHCI 152#define S5P_PA_EHCI EXYNOS4_PA_EHCI
154#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 153#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
155#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 154#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
@@ -166,26 +165,17 @@
166#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 165#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
167#define S5P_PA_SDO EXYNOS4_PA_SDO 166#define S5P_PA_SDO EXYNOS4_PA_SDO
168#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 167#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
169#define S5P_PA_SROMC EXYNOS4_PA_SROMC
170#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
171#define S5P_PA_TIMER EXYNOS4_PA_TIMER
172#define S5P_PA_VP EXYNOS4_PA_VP 168#define S5P_PA_VP EXYNOS4_PA_VP
173 169
174#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC 170#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
175#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 171#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
176#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 172#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
177 173
178#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
179#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
180#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
181#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
182#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
183
184/* Compatibility UART */ 174/* Compatibility UART */
185 175
186#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 176#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
187 177
188#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 178#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
189#define S5P_PA_UART0 S5P_PA_UART(0) 179#define S5P_PA_UART0 S5P_PA_UART(0)
190#define S5P_PA_UART1 S5P_PA_UART(1) 180#define S5P_PA_UART1 S5P_PA_UART(1)
191#define S5P_PA_UART2 S5P_PA_UART(2) 181#define S5P_PA_UART2 S5P_PA_UART(2)
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 5e3220c18fc7..0063a6de3dc8 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -13,8 +13,6 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16#include <plat/system-reset.h>
17
18static void arch_idle(void) 16static void arch_idle(void)
19{ 17{
20 /* nothing here yet */ 18 /* nothing here yet */
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
deleted file mode 100644
index 284330e571d2..000000000000
--- a/arch/arm/mach-exynos/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * EXYNOS4 vmalloc definition
15*/
16
17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__
19
20#define VMALLOC_END 0xF6000000UL
21
22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
deleted file mode 100644
index a8a83e3881a4..000000000000
--- a/arch/arm/mach-exynos/init.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-exynos4/init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12
13#include <plat/cpu.h>
14#include <plat/devs.h>
15#include <plat/regs-serial.h>
16
17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = {
19 .name = "uclk1",
20 .divisor = 1,
21 .min_baud = 0,
22 .max_baud = 0,
23 },
24};
25
26/* uart registration process */
27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{
29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt;
31
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1;
35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 }
38 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
39 }
40
41 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
42}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
deleted file mode 100644
index 5a2758ab055e..000000000000
--- a/arch/arm/mach-exynos/irq-combiner.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-combiner.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/common/gic.c
7 *
8 * IRQ COMBINER support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/io.h>
16
17#include <asm/mach/irq.h>
18
19#define COMBINER_ENABLE_SET 0x0
20#define COMBINER_ENABLE_CLEAR 0x4
21#define COMBINER_INT_STATUS 0xC
22
23static DEFINE_SPINLOCK(irq_controller_lock);
24
25struct combiner_chip_data {
26 unsigned int irq_offset;
27 unsigned int irq_mask;
28 void __iomem *base;
29};
30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32
33static inline void __iomem *combiner_base(struct irq_data *data)
34{
35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
38 return combiner_data->base;
39}
40
41static void combiner_mask_irq(struct irq_data *data)
42{
43 u32 mask = 1 << (data->irq % 32);
44
45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
46}
47
48static void combiner_unmask_irq(struct irq_data *data)
49{
50 u32 mask = 1 << (data->irq % 32);
51
52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
53}
54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{
57 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58 struct irq_chip *chip = irq_get_chip(irq);
59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status;
61
62 chained_irq_enter(chip, desc);
63
64 spin_lock(&irq_controller_lock);
65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
66 spin_unlock(&irq_controller_lock);
67 status &= chip_data->irq_mask;
68
69 if (status == 0)
70 goto out;
71
72 combiner_irq = __ffs(status);
73
74 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
75 if (unlikely(cascade_irq >= NR_IRQS))
76 do_bad_IRQ(cascade_irq, desc);
77 else
78 generic_handle_irq(cascade_irq);
79
80 out:
81 chained_irq_exit(chip, desc);
82}
83
84static struct irq_chip combiner_chip = {
85 .name = "COMBINER",
86 .irq_mask = combiner_mask_irq,
87 .irq_unmask = combiner_unmask_irq,
88};
89
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
91{
92 if (combiner_nr >= MAX_COMBINER_NR)
93 BUG();
94 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
95 BUG();
96 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
97}
98
99void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
100 unsigned int irq_start)
101{
102 unsigned int i;
103
104 if (combiner_nr >= MAX_COMBINER_NR)
105 BUG();
106
107 combiner_data[combiner_nr].base = base;
108 combiner_data[combiner_nr].irq_offset = irq_start;
109 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
110
111 /* Disable all interrupts */
112
113 __raw_writel(combiner_data[combiner_nr].irq_mask,
114 base + COMBINER_ENABLE_CLEAR);
115
116 /* Setup the Linux IRQ subsystem */
117
118 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
119 + MAX_IRQ_IN_COMBINER; i++) {
120 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
121 irq_set_chip_data(i, &combiner_data[combiner_nr]);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 }
124}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
deleted file mode 100644
index badb8c66fc9b..000000000000
--- a/arch/arm/mach-exynos/irq-eint.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-eint.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <plat/pm.h>
21#include <plat/cpu.h>
22#include <plat/gpio-cfg.h>
23
24#include <mach/regs-gpio.h>
25
26#include <asm/mach/irq.h>
27
28static DEFINE_SPINLOCK(eint_lock);
29
30static unsigned int eint0_15_data[16];
31
32static unsigned int exynos4_get_irq_nr(unsigned int number)
33{
34 u32 ret = 0;
35
36 switch (number) {
37 case 0 ... 3:
38 ret = (number + IRQ_EINT0);
39 break;
40 case 4 ... 7:
41 ret = (number + (IRQ_EINT4 - 4));
42 break;
43 case 8 ... 15:
44 ret = (number + (IRQ_EINT8 - 8));
45 break;
46 default:
47 printk(KERN_ERR "number available : %d\n", number);
48 }
49
50 return ret;
51}
52
53static inline void exynos4_irq_eint_mask(struct irq_data *data)
54{
55 u32 mask;
56
57 spin_lock(&eint_lock);
58 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 mask |= eint_irq_to_bit(data->irq);
60 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
61 spin_unlock(&eint_lock);
62}
63
64static void exynos4_irq_eint_unmask(struct irq_data *data)
65{
66 u32 mask;
67
68 spin_lock(&eint_lock);
69 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 mask &= ~(eint_irq_to_bit(data->irq));
71 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
72 spin_unlock(&eint_lock);
73}
74
75static inline void exynos4_irq_eint_ack(struct irq_data *data)
76{
77 __raw_writel(eint_irq_to_bit(data->irq),
78 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
79}
80
81static void exynos4_irq_eint_maskack(struct irq_data *data)
82{
83 exynos4_irq_eint_mask(data);
84 exynos4_irq_eint_ack(data);
85}
86
87static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
88{
89 int offs = EINT_OFFSET(data->irq);
90 int shift;
91 u32 ctrl, mask;
92 u32 newvalue = 0;
93
94 switch (type) {
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
97 break;
98
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
101 break;
102
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
105 break;
106
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
109 break;
110
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
113 break;
114
115 default:
116 printk(KERN_ERR "No such irq type %d", type);
117 return -EINVAL;
118 }
119
120 shift = (offs & 0x7) * 4;
121 mask = 0x7 << shift;
122
123 spin_lock(&eint_lock);
124 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 ctrl &= ~mask;
126 ctrl |= newvalue << shift;
127 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
128 spin_unlock(&eint_lock);
129
130 switch (offs) {
131 case 0 ... 7:
132 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
133 break;
134 case 8 ... 15:
135 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
136 break;
137 case 16 ... 23:
138 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
139 break;
140 case 24 ... 31:
141 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
142 break;
143 default:
144 printk(KERN_ERR "No such irq number %d", offs);
145 }
146
147 return 0;
148}
149
150static struct irq_chip exynos4_irq_eint = {
151 .name = "exynos4-eint",
152 .irq_mask = exynos4_irq_eint_mask,
153 .irq_unmask = exynos4_irq_eint_unmask,
154 .irq_mask_ack = exynos4_irq_eint_maskack,
155 .irq_ack = exynos4_irq_eint_ack,
156 .irq_set_type = exynos4_irq_eint_set_type,
157#ifdef CONFIG_PM
158 .irq_set_wake = s3c_irqext_wake,
159#endif
160};
161
162/* exynos4_irq_demux_eint
163 *
164 * This function demuxes the IRQ from from EINTs 16 to 31.
165 * It is designed to be inlined into the specific handler
166 * s5p_irq_demux_eintX_Y.
167 *
168 * Each EINT pend/mask registers handle eight of them.
169 */
170static inline void exynos4_irq_demux_eint(unsigned int start)
171{
172 unsigned int irq;
173
174 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
175 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
176
177 status &= ~mask;
178 status &= 0xff;
179
180 while (status) {
181 irq = fls(status) - 1;
182 generic_handle_irq(irq + start);
183 status &= ~(1 << irq);
184 }
185}
186
187static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
188{
189 struct irq_chip *chip = irq_get_chip(irq);
190 chained_irq_enter(chip, desc);
191 exynos4_irq_demux_eint(IRQ_EINT(16));
192 exynos4_irq_demux_eint(IRQ_EINT(24));
193 chained_irq_exit(chip, desc);
194}
195
196static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
197{
198 u32 *irq_data = irq_get_handler_data(irq);
199 struct irq_chip *chip = irq_get_chip(irq);
200
201 chained_irq_enter(chip, desc);
202 chip->irq_mask(&desc->irq_data);
203
204 if (chip->irq_ack)
205 chip->irq_ack(&desc->irq_data);
206
207 generic_handle_irq(*irq_data);
208
209 chip->irq_unmask(&desc->irq_data);
210 chained_irq_exit(chip, desc);
211}
212
213int __init exynos4_init_irq_eint(void)
214{
215 int irq;
216
217 for (irq = 0 ; irq <= 31 ; irq++) {
218 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
219 handle_level_irq);
220 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
221 }
222
223 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
224
225 for (irq = 0 ; irq <= 15 ; irq++) {
226 eint0_15_data[irq] = IRQ_EINT(irq);
227
228 irq_set_handler_data(exynos4_get_irq_nr(irq),
229 &eint0_15_data[irq]);
230 irq_set_chained_handler(exynos4_get_irq_nr(irq),
231 exynos4_irq_eint0_15);
232 }
233
234 return 0;
235}
236
237arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index f0ca6c157d29..d726fcd3acf9 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -16,11 +16,11 @@
16#include <linux/smsc911x.h> 16#include <linux/smsc911x.h>
17 17
18#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
19#include <asm/hardware/gic.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20 21
21#include <plat/cpu.h> 22#include <plat/cpu.h>
22#include <plat/devs.h> 23#include <plat/devs.h>
23#include <plat/exynos4.h>
24#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
25#include <plat/regs-serial.h> 25#include <plat/regs-serial.h>
26#include <plat/regs-srom.h> 26#include <plat/regs-srom.h>
@@ -28,6 +28,8 @@
28 28
29#include <mach/map.h> 29#include <mach/map.h>
30 30
31#include "common.h"
32
31/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \ 35 S3C2410_UCON_RXILEVEL | \
@@ -187,7 +189,7 @@ static void __init armlex4210_smsc911x_init(void)
187 189
188static void __init armlex4210_map_io(void) 190static void __init armlex4210_map_io(void)
189{ 191{
190 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 192 exynos_init_io(NULL, 0);
191 s3c24xx_init_clocks(24000000); 193 s3c24xx_init_clocks(24000000);
192 s3c24xx_init_uarts(armlex4210_uartcfgs, 194 s3c24xx_init_uarts(armlex4210_uartcfgs,
193 ARRAY_SIZE(armlex4210_uartcfgs)); 195 ARRAY_SIZE(armlex4210_uartcfgs));
@@ -210,6 +212,8 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
210 .atag_offset = 0x100, 212 .atag_offset = 0x100,
211 .init_irq = exynos4_init_irq, 213 .init_irq = exynos4_init_irq,
212 .map_io = armlex4210_map_io, 214 .map_io = armlex4210_map_io,
215 .handle_irq = gic_handle_irq,
213 .init_machine = armlex4210_machine_init, 216 .init_machine = armlex4210_machine_init,
214 .timer = &exynos4_timer, 217 .timer = &exynos4_timer,
218 .restart = exynos4_restart,
215MACHINE_END 219MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 236bbe187163..635fb97e31ab 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -32,12 +32,12 @@
32#include <media/v4l2-mediabus.h> 32#include <media/v4l2-mediabus.h>
33 33
34#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
35#include <asm/hardware/gic.h>
35#include <asm/mach-types.h> 36#include <asm/mach-types.h>
36 37
37#include <plat/adc.h> 38#include <plat/adc.h>
38#include <plat/regs-fb-v4.h> 39#include <plat/regs-fb-v4.h>
39#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
40#include <plat/exynos4.h>
41#include <plat/cpu.h> 41#include <plat/cpu.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/fb.h> 43#include <plat/fb.h>
@@ -54,6 +54,8 @@
54 54
55#include <mach/map.h> 55#include <mach/map.h>
56 56
57#include "common.h"
58
57/* Following are default values for UCON, ULCON and UFCON UART registers */ 59/* Following are default values for UCON, ULCON and UFCON UART registers */
58#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 60#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
59 S3C2410_UCON_RXILEVEL | \ 61 S3C2410_UCON_RXILEVEL | \
@@ -1283,7 +1285,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1283 1285
1284static void __init nuri_map_io(void) 1286static void __init nuri_map_io(void)
1285{ 1287{
1286 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 1288 exynos_init_io(NULL, 0);
1287 s3c24xx_init_clocks(24000000); 1289 s3c24xx_init_clocks(24000000);
1288 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1290 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1289} 1291}
@@ -1333,7 +1335,9 @@ MACHINE_START(NURI, "NURI")
1333 .atag_offset = 0x100, 1335 .atag_offset = 0x100,
1334 .init_irq = exynos4_init_irq, 1336 .init_irq = exynos4_init_irq,
1335 .map_io = nuri_map_io, 1337 .map_io = nuri_map_io,
1338 .handle_irq = gic_handle_irq,
1336 .init_machine = nuri_machine_init, 1339 .init_machine = nuri_machine_init,
1337 .timer = &exynos4_timer, 1340 .timer = &exynos4_timer,
1338 .reserve = &nuri_reserve, 1341 .reserve = &nuri_reserve,
1342 .restart = exynos4_restart,
1339MACHINE_END 1343MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f80b563f2be7..586eb995aa96 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -22,13 +22,13 @@
22#include <linux/lcd.h> 22#include <linux/lcd.h>
23 23
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/hardware/gic.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26 27
27#include <video/platform_lcd.h> 28#include <video/platform_lcd.h>
28 29
29#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
30#include <plat/regs-fb-v4.h> 31#include <plat/regs-fb-v4.h>
31#include <plat/exynos4.h>
32#include <plat/cpu.h> 32#include <plat/cpu.h>
33#include <plat/devs.h> 33#include <plat/devs.h>
34#include <plat/sdhci.h> 34#include <plat/sdhci.h>
@@ -43,6 +43,8 @@
43 43
44#include <mach/map.h> 44#include <mach/map.h>
45 45
46#include "common.h"
47
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 48/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
@@ -638,7 +640,7 @@ static void s5p_tv_setup(void)
638 640
639static void __init origen_map_io(void) 641static void __init origen_map_io(void)
640{ 642{
641 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 643 exynos_init_io(NULL, 0);
642 s3c24xx_init_clocks(24000000); 644 s3c24xx_init_clocks(24000000);
643 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 645 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
644} 646}
@@ -694,7 +696,9 @@ MACHINE_START(ORIGEN, "ORIGEN")
694 .atag_offset = 0x100, 696 .atag_offset = 0x100,
695 .init_irq = exynos4_init_irq, 697 .init_irq = exynos4_init_irq,
696 .map_io = origen_map_io, 698 .map_io = origen_map_io,
699 .handle_irq = gic_handle_irq,
697 .init_machine = origen_machine_init, 700 .init_machine = origen_machine_init,
698 .timer = &exynos4_timer, 701 .timer = &exynos4_timer,
699 .reserve = &origen_reserve, 702 .reserve = &origen_reserve,
703 .restart = exynos4_restart,
700MACHINE_END 704MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fcf2e0e23d53..d00e4f016a68 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -21,13 +21,13 @@
21#include <linux/serial_core.h> 21#include <linux/serial_core.h>
22 22
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/hardware/gic.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25 26
26#include <plat/backlight.h> 27#include <plat/backlight.h>
27#include <plat/clock.h> 28#include <plat/clock.h>
28#include <plat/cpu.h> 29#include <plat/cpu.h>
29#include <plat/devs.h> 30#include <plat/devs.h>
30#include <plat/exynos4.h>
31#include <plat/gpio-cfg.h> 31#include <plat/gpio-cfg.h>
32#include <plat/iic.h> 32#include <plat/iic.h>
33#include <plat/keypad.h> 33#include <plat/keypad.h>
@@ -36,6 +36,8 @@
36 36
37#include <mach/map.h> 37#include <mach/map.h>
38 38
39#include "common.h"
40
39/* Following are default values for UCON, ULCON and UFCON UART registers */ 41/* Following are default values for UCON, ULCON and UFCON UART registers */
40#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 42#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
41 S3C2410_UCON_RXILEVEL | \ 43 S3C2410_UCON_RXILEVEL | \
@@ -249,7 +251,7 @@ static void __init smdk4x12_map_io(void)
249{ 251{
250 clk_xusbxti.rate = 24000000; 252 clk_xusbxti.rate = 24000000;
251 253
252 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 254 exynos_init_io(NULL, 0);
253 s3c24xx_init_clocks(clk_xusbxti.rate); 255 s3c24xx_init_clocks(clk_xusbxti.rate);
254 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 256 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
255} 257}
@@ -287,8 +289,10 @@ MACHINE_START(SMDK4212, "SMDK4212")
287 .atag_offset = 0x100, 289 .atag_offset = 0x100,
288 .init_irq = exynos4_init_irq, 290 .init_irq = exynos4_init_irq,
289 .map_io = smdk4x12_map_io, 291 .map_io = smdk4x12_map_io,
292 .handle_irq = gic_handle_irq,
290 .init_machine = smdk4x12_machine_init, 293 .init_machine = smdk4x12_machine_init,
291 .timer = &exynos4_timer, 294 .timer = &exynos4_timer,
295 .restart = exynos4_restart,
292MACHINE_END 296MACHINE_END
293 297
294MACHINE_START(SMDK4412, "SMDK4412") 298MACHINE_START(SMDK4412, "SMDK4412")
@@ -297,6 +301,8 @@ MACHINE_START(SMDK4412, "SMDK4412")
297 .atag_offset = 0x100, 301 .atag_offset = 0x100,
298 .init_irq = exynos4_init_irq, 302 .init_irq = exynos4_init_irq,
299 .map_io = smdk4x12_map_io, 303 .map_io = smdk4x12_map_io,
304 .handle_irq = gic_handle_irq,
300 .init_machine = smdk4x12_machine_init, 305 .init_machine = smdk4x12_machine_init,
301 .timer = &exynos4_timer, 306 .timer = &exynos4_timer,
307 .restart = exynos4_restart,
302MACHINE_END 308MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index cec2afabe7b4..5b365613b470 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -21,13 +21,13 @@
21#include <linux/pwm_backlight.h> 21#include <linux/pwm_backlight.h>
22 22
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/hardware/gic.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25 26
26#include <video/platform_lcd.h> 27#include <video/platform_lcd.h>
27#include <plat/regs-serial.h> 28#include <plat/regs-serial.h>
28#include <plat/regs-srom.h> 29#include <plat/regs-srom.h>
29#include <plat/regs-fb-v4.h> 30#include <plat/regs-fb-v4.h>
30#include <plat/exynos4.h>
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/fb.h> 33#include <plat/fb.h>
@@ -43,6 +43,8 @@
43 43
44#include <mach/map.h> 44#include <mach/map.h>
45 45
46#include "common.h"
47
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 48/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
@@ -332,7 +334,7 @@ static void s5p_tv_setup(void)
332 334
333static void __init smdkv310_map_io(void) 335static void __init smdkv310_map_io(void)
334{ 336{
335 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 337 exynos_init_io(NULL, 0);
336 s3c24xx_init_clocks(24000000); 338 s3c24xx_init_clocks(24000000);
337 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 339 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
338} 340}
@@ -375,9 +377,11 @@ MACHINE_START(SMDKV310, "SMDKV310")
375 .atag_offset = 0x100, 377 .atag_offset = 0x100,
376 .init_irq = exynos4_init_irq, 378 .init_irq = exynos4_init_irq,
377 .map_io = smdkv310_map_io, 379 .map_io = smdkv310_map_io,
380 .handle_irq = gic_handle_irq,
378 .init_machine = smdkv310_machine_init, 381 .init_machine = smdkv310_machine_init,
379 .timer = &exynos4_timer, 382 .timer = &exynos4_timer,
380 .reserve = &smdkv310_reserve, 383 .reserve = &smdkv310_reserve,
384 .restart = exynos4_restart,
381MACHINE_END 385MACHINE_END
382 386
383MACHINE_START(SMDKC210, "SMDKC210") 387MACHINE_START(SMDKC210, "SMDKC210")
@@ -385,6 +389,8 @@ MACHINE_START(SMDKC210, "SMDKC210")
385 .atag_offset = 0x100, 389 .atag_offset = 0x100,
386 .init_irq = exynos4_init_irq, 390 .init_irq = exynos4_init_irq,
387 .map_io = smdkv310_map_io, 391 .map_io = smdkv310_map_io,
392 .handle_irq = gic_handle_irq,
388 .init_machine = smdkv310_machine_init, 393 .init_machine = smdkv310_machine_init,
389 .timer = &exynos4_timer, 394 .timer = &exynos4_timer,
395 .restart = exynos4_restart,
390MACHINE_END 396MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index a2a177ff4b44..52aea972746a 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -24,10 +24,10 @@
24#include <linux/i2c/atmel_mxt_ts.h> 24#include <linux/i2c/atmel_mxt_ts.h>
25 25
26#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
27#include <asm/hardware/gic.h>
27#include <asm/mach-types.h> 28#include <asm/mach-types.h>
28 29
29#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
30#include <plat/exynos4.h>
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/iic.h> 33#include <plat/iic.h>
@@ -47,6 +47,8 @@
47#include <media/s5p_fimc.h> 47#include <media/s5p_fimc.h>
48#include <media/m5mols.h> 48#include <media/m5mols.h>
49 49
50#include "common.h"
51
50/* Following are default values for UCON, ULCON and UFCON UART registers */ 52/* Following are default values for UCON, ULCON and UFCON UART registers */
51#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 53#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
52 S3C2410_UCON_RXILEVEL | \ 54 S3C2410_UCON_RXILEVEL | \
@@ -992,7 +994,7 @@ static struct platform_device *universal_devices[] __initdata = {
992 994
993static void __init universal_map_io(void) 995static void __init universal_map_io(void)
994{ 996{
995 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 997 exynos_init_io(NULL, 0);
996 s3c24xx_init_clocks(24000000); 998 s3c24xx_init_clocks(24000000);
997 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 999 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
998} 1000}
@@ -1058,7 +1060,9 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1058 .atag_offset = 0x100, 1060 .atag_offset = 0x100,
1059 .init_irq = exynos4_init_irq, 1061 .init_irq = exynos4_init_irq,
1060 .map_io = universal_map_io, 1062 .map_io = universal_map_io,
1063 .handle_irq = gic_handle_irq,
1061 .init_machine = universal_machine_init, 1064 .init_machine = universal_machine_init,
1062 .timer = &exynos4_timer, 1065 .timer = &exynos4_timer,
1063 .reserve = &universal_reserve, 1066 .reserve = &universal_reserve,
1067 .restart = exynos4_restart,
1064MACHINE_END 1068MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 97343df8f132..85b5527d0918 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -44,8 +44,6 @@ struct mct_clock_event_device {
44 char name[10]; 44 char name[10];
45}; 45};
46 46
47static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
48
49static void exynos4_mct_write(unsigned int value, void *addr) 47static void exynos4_mct_write(unsigned int value, void *addr)
50{ 48{
51 void __iomem *stat_addr; 49 void __iomem *stat_addr;
@@ -264,6 +262,9 @@ static void exynos4_clockevent_init(void)
264} 262}
265 263
266#ifdef CONFIG_LOCAL_TIMERS 264#ifdef CONFIG_LOCAL_TIMERS
265
266static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
267
267/* Clock event handling */ 268/* Clock event handling */
268static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) 269static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
269{ 270{
@@ -428,9 +429,13 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
428 429
429void local_timer_stop(struct clock_event_device *evt) 430void local_timer_stop(struct clock_event_device *evt)
430{ 431{
432 unsigned int cpu = smp_processor_id();
431 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 433 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
432 if (mct_int_type == MCT_INT_SPI) 434 if (mct_int_type == MCT_INT_SPI)
433 disable_irq(evt->irq); 435 if (cpu == 0)
436 remove_irq(evt->irq, &mct_tick0_event_irq);
437 else
438 remove_irq(evt->irq, &mct_tick1_event_irq);
434 else 439 else
435 disable_percpu_irq(IRQ_MCT_LOCALTIMER); 440 disable_percpu_irq(IRQ_MCT_LOCALTIMER);
436} 441}
@@ -443,6 +448,7 @@ static void __init exynos4_timer_resources(void)
443 448
444 clk_rate = clk_get_rate(mct_clk); 449 clk_rate = clk_get_rate(mct_clk);
445 450
451#ifdef CONFIG_LOCAL_TIMERS
446 if (mct_int_type == MCT_INT_PPI) { 452 if (mct_int_type == MCT_INT_PPI) {
447 int err; 453 int err;
448 454
@@ -452,6 +458,7 @@ static void __init exynos4_timer_resources(void)
452 WARN(err, "MCT: can't request IRQ %d (%d)\n", 458 WARN(err, "MCT: can't request IRQ %d (%d)\n",
453 IRQ_MCT_LOCALTIMER, err); 459 IRQ_MCT_LOCALTIMER, err);
454 } 460 }
461#endif /* CONFIG_LOCAL_TIMERS */
455} 462}
456 463
457static void __init exynos4_timer_init(void) 464static void __init exynos4_timer_init(void)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 69ffb2fb3875..60bc45e3e709 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,7 +32,6 @@
32 32
33#include <plat/cpu.h> 33#include <plat/cpu.h>
34 34
35extern unsigned int gic_bank_offset;
36extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
37 36
38#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 37#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void)
65 64
66static DEFINE_SPINLOCK(boot_lock); 65static DEFINE_SPINLOCK(boot_lock);
67 66
68static void __cpuinit exynos4_gic_secondary_init(void)
69{
70 void __iomem *dist_base = S5P_VA_GIC_DIST +
71 (gic_bank_offset * smp_processor_id());
72 void __iomem *cpu_base = S5P_VA_GIC_CPU +
73 (gic_bank_offset * smp_processor_id());
74 int i;
75
76 /*
77 * Deal with the banked PPI and SGI interrupts - disable all
78 * PPI interrupts, ensure all SGI interrupts are enabled.
79 */
80 __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
81 __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
82
83 /*
84 * Set priority on PPI and SGI interrupts
85 */
86 for (i = 0; i < 32; i += 4)
87 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
88
89 __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
90 __raw_writel(1, cpu_base + GIC_CPU_CTRL);
91}
92
93void __cpuinit platform_secondary_init(unsigned int cpu) 67void __cpuinit platform_secondary_init(unsigned int cpu)
94{ 68{
95 /* 69 /*
@@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
97 * core (e.g. timer irq), then they will not have been enabled 71 * core (e.g. timer irq), then they will not have been enabled
98 * for us: do so 72 * for us: do so
99 */ 73 */
100 exynos4_gic_secondary_init(); 74 gic_secondary_init(0);
101 75
102 /* 76 /*
103 * let the primary processor know we're out of the 77 * let the primary processor know we're out of the
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 02:14:56 -0500