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-rw-r--r--arch/arm/include/asm/elf.h2
-rw-r--r--arch/arm/include/asm/hardware/entry-macro-gic.S75
-rw-r--r--arch/arm/include/asm/hardware/gic.h7
-rw-r--r--arch/arm/include/asm/hardware/it8152.h1
-rw-r--r--arch/arm/include/asm/hardware/timer-sp.h2
-rw-r--r--arch/arm/include/asm/highmem.h3
-rw-r--r--arch/arm/include/asm/kexec.h18
-rw-r--r--arch/arm/include/asm/module.h15
-rw-r--r--arch/arm/include/asm/sizes.h6
-rw-r--r--arch/arm/include/asm/system.h1
10 files changed, 108 insertions, 22 deletions
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 8bb66bca2e3e..c3cd8755e648 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -99,6 +99,8 @@ struct elf32_hdr;
99extern int elf_check_arch(const struct elf32_hdr *); 99extern int elf_check_arch(const struct elf32_hdr *);
100#define elf_check_arch elf_check_arch 100#define elf_check_arch elf_check_arch
101 101
102#define vmcore_elf64_check_arch(x) (0)
103
102extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); 104extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int);
103#define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk) 105#define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk)
104 106
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
new file mode 100644
index 000000000000..c115b82fe80a
--- /dev/null
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -0,0 +1,75 @@
1/*
2 * arch/arm/include/asm/hardware/entry-macro-gic.S
3 *
4 * Low-level IRQ helper macros for GIC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/hardware/gic.h>
12
13#ifndef HAVE_GET_IRQNR_PREAMBLE
14 .macro get_irqnr_preamble, base, tmp
15 ldr \base, =gic_cpu_base_addr
16 ldr \base, [\base]
17 .endm
18#endif
19
20/*
21 * The interrupt numbering scheme is defined in the
22 * interrupt controller spec. To wit:
23 *
24 * Interrupts 0-15 are IPI
25 * 16-28 are reserved
26 * 29-31 are local. We allow 30 to be used for the watchdog.
27 * 32-1020 are global
28 * 1021-1022 are reserved
29 * 1023 is "spurious" (no interrupt)
30 *
31 * For now, we ignore all local interrupts so only return an interrupt if it's
32 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
33 *
34 * A simple read from the controller will tell us the number of the highest
35 * priority enabled interrupt. We then just need to check whether it is in the
36 * valid range for an IRQ (30-1020 inclusive).
37 */
38
39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40
41 ldr \irqstat, [\base, #GIC_CPU_INTACK]
42 /* bits 12-10 = src CPU, 9-0 = int # */
43
44 ldr \tmp, =1021
45 bic \irqnr, \irqstat, #0x1c00
46 cmp \irqnr, #29
47 cmpcc \irqnr, \irqnr
48 cmpne \irqnr, \tmp
49 cmpcs \irqnr, \irqnr
50 .endm
51
52/* We assume that irqstat (the raw value of the IRQ acknowledge
53 * register) is preserved from the macro above.
54 * If there is an IPI, we immediately signal end of interrupt on the
55 * controller, since this requires the original irqstat value which
56 * we won't easily be able to recreate later.
57 */
58
59 .macro test_for_ipi, irqnr, irqstat, base, tmp
60 bic \irqnr, \irqstat, #0x1c00
61 cmp \irqnr, #16
62 strcc \irqstat, [\base, #GIC_CPU_EOI]
63 cmpcs \irqnr, \irqnr
64 .endm
65
66/* As above, this assumes that irqstat and base are preserved.. */
67
68 .macro test_for_ltirq, irqnr, irqstat, base, tmp
69 bic \irqnr, \irqstat, #0x1c00
70 mov \tmp, #0
71 cmp \irqnr, #29
72 moveq \tmp, #1
73 streq \irqstat, [\base, #GIC_CPU_EOI]
74 cmp \tmp, #0
75 .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 7f34333bb545..84557d321001 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,10 +33,13 @@
33#define GIC_DIST_SOFTINT 0xf00 33#define GIC_DIST_SOFTINT 0xf00
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); 36extern void __iomem *gic_cpu_base_addr;
37void gic_cpu_init(unsigned int gic_nr, void __iomem *base); 37
38void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
39void gic_secondary_init(unsigned int);
38void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 40void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
39void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); 41void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
42void gic_enable_ppi(unsigned int);
40#endif 43#endif
41 44
42#endif 45#endif
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 21fa272301f8..b2f95c72287c 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -76,6 +76,7 @@ extern unsigned long it8152_base_address;
76 IT8152_PD_IRQ(0) Audio controller (ACR) 76 IT8152_PD_IRQ(0) Audio controller (ACR)
77 */ 77 */
78#define IT8152_IRQ(x) (IRQ_BOARD_START + (x)) 78#define IT8152_IRQ(x) (IRQ_BOARD_START + (x))
79#define IT8152_LAST_IRQ (IRQ_BOARD_START + 40)
79 80
80/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ 81/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
81#define IT8152_LD_IRQ_COUNT 9 82#define IT8152_LD_IRQ_COUNT 9
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
new file mode 100644
index 000000000000..21e75e30d497
--- /dev/null
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -0,0 +1,2 @@
1void sp804_clocksource_init(void __iomem *);
2void sp804_clockevents_init(void __iomem *, unsigned int);
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 1fc684e70ab6..7080e2c8fa62 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -25,9 +25,6 @@ extern void *kmap_high(struct page *page);
25extern void *kmap_high_get(struct page *page); 25extern void *kmap_high_get(struct page *page);
26extern void kunmap_high(struct page *page); 26extern void kunmap_high(struct page *page);
27 27
28extern void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte);
29extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte);
30
31/* 28/*
32 * The following functions are already defined by <linux/highmem.h> 29 * The following functions are already defined by <linux/highmem.h>
33 * when CONFIG_HIGHMEM is not set. 30 * when CONFIG_HIGHMEM is not set.
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index 8ec9ef5c3c7b..c0094d8edae4 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -33,10 +33,20 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
33 if (oldregs) { 33 if (oldregs) {
34 memcpy(newregs, oldregs, sizeof(*newregs)); 34 memcpy(newregs, oldregs, sizeof(*newregs));
35 } else { 35 } else {
36 __asm__ __volatile__ ("stmia %0, {r0 - r15}" 36 __asm__ __volatile__ (
37 : : "r" (&newregs->ARM_r0)); 37 "stmia %[regs_base], {r0-r12}\n\t"
38 __asm__ __volatile__ ("mrs %0, cpsr" 38 "mov %[_ARM_sp], sp\n\t"
39 : "=r" (newregs->ARM_cpsr)); 39 "str lr, %[_ARM_lr]\n\t"
40 "adr %[_ARM_pc], 1f\n\t"
41 "mrs %[_ARM_cpsr], cpsr\n\t"
42 "1:"
43 : [_ARM_pc] "=r" (newregs->ARM_pc),
44 [_ARM_cpsr] "=r" (newregs->ARM_cpsr),
45 [_ARM_sp] "=r" (newregs->ARM_sp),
46 [_ARM_lr] "=o" (newregs->ARM_lr)
47 : [regs_base] "r" (&newregs->ARM_r0)
48 : "memory"
49 );
40 } 50 }
41} 51}
42 52
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index cbb0bc295d2b..12c8e680cbff 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -8,11 +8,6 @@
8struct unwind_table; 8struct unwind_table;
9 9
10#ifdef CONFIG_ARM_UNWIND 10#ifdef CONFIG_ARM_UNWIND
11struct arm_unwind_mapping {
12 Elf_Shdr *unw_sec;
13 Elf_Shdr *sec_text;
14 struct unwind_table *unwind;
15};
16enum { 11enum {
17 ARM_SEC_INIT, 12 ARM_SEC_INIT,
18 ARM_SEC_DEVINIT, 13 ARM_SEC_DEVINIT,
@@ -21,13 +16,13 @@ enum {
21 ARM_SEC_DEVEXIT, 16 ARM_SEC_DEVEXIT,
22 ARM_SEC_MAX, 17 ARM_SEC_MAX,
23}; 18};
19#endif
20
24struct mod_arch_specific { 21struct mod_arch_specific {
25 struct arm_unwind_mapping map[ARM_SEC_MAX]; 22#ifdef CONFIG_ARM_UNWIND
26}; 23 struct unwind_table *unwind[ARM_SEC_MAX];
27#else
28struct mod_arch_specific {
29};
30#endif 24#endif
25};
31 26
32/* 27/*
33 * Include the ARM architecture version. 28 * Include the ARM architecture version.
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 4fc1565e4f93..316bb2b2be3d 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -13,9 +13,6 @@
13 * along with this program; if not, write to the Free Software 13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */ 15 */
16/* DO NOT EDIT!! - this file automatically generated
17 * from .s file by awk -f s2h.awk
18 */
19/* Size definitions 16/* Size definitions
20 * Copyright (C) ARM Limited 1998. All rights reserved. 17 * Copyright (C) ARM Limited 1998. All rights reserved.
21 */ 18 */
@@ -25,6 +22,9 @@
25 22
26/* handy sizes */ 23/* handy sizes */
27#define SZ_16 0x00000010 24#define SZ_16 0x00000010
25#define SZ_32 0x00000020
26#define SZ_64 0x00000040
27#define SZ_128 0x00000080
28#define SZ_256 0x00000100 28#define SZ_256 0x00000100
29#define SZ_512 0x00000200 29#define SZ_512 0x00000200
30 30
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1120f18a6b17..80025948b8ad 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -150,6 +150,7 @@ extern unsigned int user_debug;
150#define rmb() dmb() 150#define rmb() dmb()
151#define wmb() mb() 151#define wmb() mb()
152#else 152#else
153#include <asm/memory.h>
153#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) 154#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
154#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) 155#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
155#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) 156#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)