diff options
Diffstat (limited to 'arch/arm/include/asm/hardware/sa1111.h')
-rw-r--r-- | arch/arm/include/asm/hardware/sa1111.h | 156 |
1 files changed, 23 insertions, 133 deletions
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h index 92ed254c175b..7c2bbc7f0be1 100644 --- a/arch/arm/include/asm/hardware/sa1111.h +++ b/arch/arm/include/asm/hardware/sa1111.h | |||
@@ -132,34 +132,10 @@ | |||
132 | #define SKPCR_DCLKEN (1<<7) | 132 | #define SKPCR_DCLKEN (1<<7) |
133 | #define SKPCR_PWMCLKEN (1<<8) | 133 | #define SKPCR_PWMCLKEN (1<<8) |
134 | 134 | ||
135 | /* | 135 | /* USB Host controller */ |
136 | * USB Host controller | ||
137 | */ | ||
138 | #define SA1111_USB 0x0400 | 136 | #define SA1111_USB 0x0400 |
139 | 137 | ||
140 | /* | 138 | /* |
141 | * Offsets from SA1111_USB_BASE | ||
142 | */ | ||
143 | #define SA1111_USB_STATUS 0x0118 | ||
144 | #define SA1111_USB_RESET 0x011c | ||
145 | #define SA1111_USB_IRQTEST 0x0120 | ||
146 | |||
147 | #define USB_RESET_FORCEIFRESET (1 << 0) | ||
148 | #define USB_RESET_FORCEHCRESET (1 << 1) | ||
149 | #define USB_RESET_CLKGENRESET (1 << 2) | ||
150 | #define USB_RESET_SIMSCALEDOWN (1 << 3) | ||
151 | #define USB_RESET_USBINTTEST (1 << 4) | ||
152 | #define USB_RESET_SLEEPSTBYEN (1 << 5) | ||
153 | #define USB_RESET_PWRSENSELOW (1 << 6) | ||
154 | #define USB_RESET_PWRCTRLLOW (1 << 7) | ||
155 | |||
156 | #define USB_STATUS_IRQHCIRMTWKUP (1 << 7) | ||
157 | #define USB_STATUS_IRQHCIBUFFACC (1 << 8) | ||
158 | #define USB_STATUS_NIRQHCIM (1 << 9) | ||
159 | #define USB_STATUS_NHCIMFCLR (1 << 10) | ||
160 | #define USB_STATUS_USBPWRSENSE (1 << 11) | ||
161 | |||
162 | /* | ||
163 | * Serial Audio Controller | 139 | * Serial Audio Controller |
164 | * | 140 | * |
165 | * Registers | 141 | * Registers |
@@ -327,22 +303,6 @@ | |||
327 | * PC_SSR GPIO Block C Sleep State | 303 | * PC_SSR GPIO Block C Sleep State |
328 | */ | 304 | */ |
329 | 305 | ||
330 | #define _PA_DDR _SA1111( 0x1000 ) | ||
331 | #define _PA_DRR _SA1111( 0x1004 ) | ||
332 | #define _PA_DWR _SA1111( 0x1004 ) | ||
333 | #define _PA_SDR _SA1111( 0x1008 ) | ||
334 | #define _PA_SSR _SA1111( 0x100c ) | ||
335 | #define _PB_DDR _SA1111( 0x1010 ) | ||
336 | #define _PB_DRR _SA1111( 0x1014 ) | ||
337 | #define _PB_DWR _SA1111( 0x1014 ) | ||
338 | #define _PB_SDR _SA1111( 0x1018 ) | ||
339 | #define _PB_SSR _SA1111( 0x101c ) | ||
340 | #define _PC_DDR _SA1111( 0x1020 ) | ||
341 | #define _PC_DRR _SA1111( 0x1024 ) | ||
342 | #define _PC_DWR _SA1111( 0x1024 ) | ||
343 | #define _PC_SDR _SA1111( 0x1028 ) | ||
344 | #define _PC_SSR _SA1111( 0x102c ) | ||
345 | |||
346 | #define SA1111_GPIO 0x1000 | 306 | #define SA1111_GPIO 0x1000 |
347 | 307 | ||
348 | #define SA1111_GPIO_PADDR (0x000) | 308 | #define SA1111_GPIO_PADDR (0x000) |
@@ -425,106 +385,30 @@ | |||
425 | #define SA1111_WAKEPOL0 0x0034 | 385 | #define SA1111_WAKEPOL0 0x0034 |
426 | #define SA1111_WAKEPOL1 0x0038 | 386 | #define SA1111_WAKEPOL1 0x0038 |
427 | 387 | ||
428 | /* | 388 | /* PS/2 Trackpad and Mouse Interfaces */ |
429 | * PS/2 Trackpad and Mouse Interfaces | ||
430 | * | ||
431 | * Registers | ||
432 | * PS2CR Control Register | ||
433 | * PS2STAT Status Register | ||
434 | * PS2DATA Transmit/Receive Data register | ||
435 | * PS2CLKDIV Clock Division Register | ||
436 | * PS2PRECNT Clock Precount Register | ||
437 | * PS2TEST1 Test register 1 | ||
438 | * PS2TEST2 Test register 2 | ||
439 | * PS2TEST3 Test register 3 | ||
440 | * PS2TEST4 Test register 4 | ||
441 | */ | ||
442 | |||
443 | #define SA1111_KBD 0x0a00 | 389 | #define SA1111_KBD 0x0a00 |
444 | #define SA1111_MSE 0x0c00 | 390 | #define SA1111_MSE 0x0c00 |
445 | 391 | ||
446 | /* | 392 | /* PCMCIA Interface */ |
447 | * These are offsets from the above bases. | 393 | #define SA1111_PCMCIA 0x1600 |
448 | */ | ||
449 | #define SA1111_PS2CR 0x0000 | ||
450 | #define SA1111_PS2STAT 0x0004 | ||
451 | #define SA1111_PS2DATA 0x0008 | ||
452 | #define SA1111_PS2CLKDIV 0x000c | ||
453 | #define SA1111_PS2PRECNT 0x0010 | ||
454 | |||
455 | #define PS2CR_ENA 0x08 | ||
456 | #define PS2CR_FKD 0x02 | ||
457 | #define PS2CR_FKC 0x01 | ||
458 | |||
459 | #define PS2STAT_STP 0x0100 | ||
460 | #define PS2STAT_TXE 0x0080 | ||
461 | #define PS2STAT_TXB 0x0040 | ||
462 | #define PS2STAT_RXF 0x0020 | ||
463 | #define PS2STAT_RXB 0x0010 | ||
464 | #define PS2STAT_ENA 0x0008 | ||
465 | #define PS2STAT_RXP 0x0004 | ||
466 | #define PS2STAT_KBD 0x0002 | ||
467 | #define PS2STAT_KBC 0x0001 | ||
468 | 394 | ||
469 | /* | ||
470 | * PCMCIA Interface | ||
471 | * | ||
472 | * Registers | ||
473 | * PCSR Status Register | ||
474 | * PCCR Control Register | ||
475 | * PCSSR Sleep State Register | ||
476 | */ | ||
477 | |||
478 | #define SA1111_PCMCIA 0x1600 | ||
479 | |||
480 | /* | ||
481 | * These are offsets from the above base. | ||
482 | */ | ||
483 | #define SA1111_PCCR 0x0000 | ||
484 | #define SA1111_PCSSR 0x0004 | ||
485 | #define SA1111_PCSR 0x0008 | ||
486 | |||
487 | #define PCSR_S0_READY (1<<0) | ||
488 | #define PCSR_S1_READY (1<<1) | ||
489 | #define PCSR_S0_DETECT (1<<2) | ||
490 | #define PCSR_S1_DETECT (1<<3) | ||
491 | #define PCSR_S0_VS1 (1<<4) | ||
492 | #define PCSR_S0_VS2 (1<<5) | ||
493 | #define PCSR_S1_VS1 (1<<6) | ||
494 | #define PCSR_S1_VS2 (1<<7) | ||
495 | #define PCSR_S0_WP (1<<8) | ||
496 | #define PCSR_S1_WP (1<<9) | ||
497 | #define PCSR_S0_BVD1 (1<<10) | ||
498 | #define PCSR_S0_BVD2 (1<<11) | ||
499 | #define PCSR_S1_BVD1 (1<<12) | ||
500 | #define PCSR_S1_BVD2 (1<<13) | ||
501 | |||
502 | #define PCCR_S0_RST (1<<0) | ||
503 | #define PCCR_S1_RST (1<<1) | ||
504 | #define PCCR_S0_FLT (1<<2) | ||
505 | #define PCCR_S1_FLT (1<<3) | ||
506 | #define PCCR_S0_PWAITEN (1<<4) | ||
507 | #define PCCR_S1_PWAITEN (1<<5) | ||
508 | #define PCCR_S0_PSE (1<<6) | ||
509 | #define PCCR_S1_PSE (1<<7) | ||
510 | |||
511 | #define PCSSR_S0_SLEEP (1<<0) | ||
512 | #define PCSSR_S1_SLEEP (1<<1) | ||
513 | 395 | ||
514 | 396 | ||
515 | 397 | ||
516 | 398 | ||
517 | extern struct bus_type sa1111_bus_type; | 399 | extern struct bus_type sa1111_bus_type; |
518 | 400 | ||
519 | #define SA1111_DEVID_SBI 0 | 401 | #define SA1111_DEVID_SBI (1 << 0) |
520 | #define SA1111_DEVID_SK 1 | 402 | #define SA1111_DEVID_SK (1 << 1) |
521 | #define SA1111_DEVID_USB 2 | 403 | #define SA1111_DEVID_USB (1 << 2) |
522 | #define SA1111_DEVID_SAC 3 | 404 | #define SA1111_DEVID_SAC (1 << 3) |
523 | #define SA1111_DEVID_SSP 4 | 405 | #define SA1111_DEVID_SSP (1 << 4) |
524 | #define SA1111_DEVID_PS2 5 | 406 | #define SA1111_DEVID_PS2 (3 << 5) |
525 | #define SA1111_DEVID_GPIO 6 | 407 | #define SA1111_DEVID_PS2_KBD (1 << 5) |
526 | #define SA1111_DEVID_INT 7 | 408 | #define SA1111_DEVID_PS2_MSE (1 << 6) |
527 | #define SA1111_DEVID_PCMCIA 8 | 409 | #define SA1111_DEVID_GPIO (1 << 7) |
410 | #define SA1111_DEVID_INT (1 << 8) | ||
411 | #define SA1111_DEVID_PCMCIA (1 << 9) | ||
528 | 412 | ||
529 | struct sa1111_dev { | 413 | struct sa1111_dev { |
530 | struct device dev; | 414 | struct device dev; |
@@ -548,6 +432,7 @@ struct sa1111_driver { | |||
548 | int (*remove)(struct sa1111_dev *); | 432 | int (*remove)(struct sa1111_dev *); |
549 | int (*suspend)(struct sa1111_dev *, pm_message_t); | 433 | int (*suspend)(struct sa1111_dev *, pm_message_t); |
550 | int (*resume)(struct sa1111_dev *); | 434 | int (*resume)(struct sa1111_dev *); |
435 | void (*shutdown)(struct sa1111_dev *); | ||
551 | }; | 436 | }; |
552 | 437 | ||
553 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) | 438 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) |
@@ -555,9 +440,10 @@ struct sa1111_driver { | |||
555 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) | 440 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) |
556 | 441 | ||
557 | /* | 442 | /* |
558 | * These frob the SKPCR register. | 443 | * These frob the SKPCR register, and call platform specific |
444 | * enable/disable functions. | ||
559 | */ | 445 | */ |
560 | void sa1111_enable_device(struct sa1111_dev *); | 446 | int sa1111_enable_device(struct sa1111_dev *); |
561 | void sa1111_disable_device(struct sa1111_dev *); | 447 | void sa1111_disable_device(struct sa1111_dev *); |
562 | 448 | ||
563 | unsigned int sa1111_pll_clock(struct sa1111_dev *); | 449 | unsigned int sa1111_pll_clock(struct sa1111_dev *); |
@@ -580,6 +466,10 @@ void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned i | |||
580 | 466 | ||
581 | struct sa1111_platform_data { | 467 | struct sa1111_platform_data { |
582 | int irq_base; /* base for cascaded on-chip IRQs */ | 468 | int irq_base; /* base for cascaded on-chip IRQs */ |
469 | unsigned disable_devs; | ||
470 | void *data; | ||
471 | int (*enable)(void *, unsigned); | ||
472 | void (*disable)(void *, unsigned); | ||
583 | }; | 473 | }; |
584 | 474 | ||
585 | #endif /* _ASM_ARCH_SA1111 */ | 475 | #endif /* _ASM_ARCH_SA1111 */ |