diff options
Diffstat (limited to 'arch/arm/boot/dts/pxa168.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/pxa168.dtsi | 67 |
1 files changed, 51 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index d32d5128f225..31a718696080 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi | |||
| @@ -18,13 +18,6 @@ | |||
| 18 | i2c1 = &twsi2; | 18 | i2c1 = &twsi2; |
| 19 | }; | 19 | }; |
| 20 | 20 | ||
| 21 | intc: intc-interrupt-controller@d4282000 { | ||
| 22 | compatible = "mrvl,mmp-intc", "mrvl,intc"; | ||
| 23 | interrupt-controller; | ||
| 24 | #interrupt-cells = <1>; | ||
| 25 | reg = <0xd4282000 0x1000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | soc { | 21 | soc { |
| 29 | #address-cells = <1>; | 22 | #address-cells = <1>; |
| 30 | #size-cells = <1>; | 23 | #size-cells = <1>; |
| @@ -32,6 +25,23 @@ | |||
| 32 | interrupt-parent = <&intc>; | 25 | interrupt-parent = <&intc>; |
| 33 | ranges; | 26 | ranges; |
| 34 | 27 | ||
| 28 | axi@d4200000 { /* AXI */ | ||
| 29 | compatible = "mrvl,axi-bus", "simple-bus"; | ||
| 30 | #address-cells = <1>; | ||
| 31 | #size-cells = <1>; | ||
| 32 | reg = <0xd4200000 0x00200000>; | ||
| 33 | ranges; | ||
| 34 | |||
| 35 | intc: interrupt-controller@d4282000 { | ||
| 36 | compatible = "mrvl,mmp-intc"; | ||
| 37 | interrupt-controller; | ||
| 38 | #interrupt-cells = <1>; | ||
| 39 | reg = <0xd4282000 0x1000>; | ||
| 40 | mrvl,intc-nr-irqs = <64>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | }; | ||
| 44 | |||
| 35 | apb@d4000000 { /* APB */ | 45 | apb@d4000000 { /* APB */ |
| 36 | compatible = "mrvl,apb-bus", "simple-bus"; | 46 | compatible = "mrvl,apb-bus", "simple-bus"; |
| 37 | #address-cells = <1>; | 47 | #address-cells = <1>; |
| @@ -39,40 +49,65 @@ | |||
| 39 | reg = <0xd4000000 0x00200000>; | 49 | reg = <0xd4000000 0x00200000>; |
| 40 | ranges; | 50 | ranges; |
| 41 | 51 | ||
| 52 | timer0: timer@d4014000 { | ||
| 53 | compatible = "mrvl,mmp-timer"; | ||
| 54 | reg = <0xd4014000 0x100>; | ||
| 55 | interrupts = <13>; | ||
| 56 | }; | ||
| 57 | |||
| 42 | uart1: uart@d4017000 { | 58 | uart1: uart@d4017000 { |
| 43 | compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; | 59 | compatible = "mrvl,mmp-uart"; |
| 44 | reg = <0xd4017000 0x1000>; | 60 | reg = <0xd4017000 0x1000>; |
| 45 | interrupts = <27>; | 61 | interrupts = <27>; |
| 46 | status = "disabled"; | 62 | status = "disabled"; |
| 47 | }; | 63 | }; |
| 48 | 64 | ||
| 49 | uart2: uart@d4018000 { | 65 | uart2: uart@d4018000 { |
| 50 | compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; | 66 | compatible = "mrvl,mmp-uart"; |
| 51 | reg = <0xd4018000 0x1000>; | 67 | reg = <0xd4018000 0x1000>; |
| 52 | interrupts = <28>; | 68 | interrupts = <28>; |
| 53 | status = "disabled"; | 69 | status = "disabled"; |
| 54 | }; | 70 | }; |
| 55 | 71 | ||
| 56 | uart3: uart@d4026000 { | 72 | uart3: uart@d4026000 { |
| 57 | compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; | 73 | compatible = "mrvl,mmp-uart"; |
| 58 | reg = <0xd4026000 0x1000>; | 74 | reg = <0xd4026000 0x1000>; |
| 59 | interrupts = <29>; | 75 | interrupts = <29>; |
| 60 | status = "disabled"; | 76 | status = "disabled"; |
| 61 | }; | 77 | }; |
| 62 | 78 | ||
| 63 | gpio: gpio@d4019000 { | 79 | gpio@d4019000 { |
| 64 | compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; | 80 | compatible = "mrvl,mmp-gpio"; |
| 81 | #address-cells = <1>; | ||
| 82 | #size-cells = <1>; | ||
| 65 | reg = <0xd4019000 0x1000>; | 83 | reg = <0xd4019000 0x1000>; |
| 84 | gpio-controller; | ||
| 85 | #gpio-cells = <2>; | ||
| 66 | interrupts = <49>; | 86 | interrupts = <49>; |
| 67 | interrupt-names = "gpio_mux"; | 87 | interrupt-names = "gpio_mux"; |
| 68 | gpio-controller; | ||
| 69 | #gpio-cells = <1>; | ||
| 70 | interrupt-controller; | 88 | interrupt-controller; |
| 71 | #interrupt-cells = <1>; | 89 | #interrupt-cells = <1>; |
| 90 | ranges; | ||
| 91 | |||
| 92 | gcb0: gpio@d4019000 { | ||
| 93 | reg = <0xd4019000 0x4>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | gcb1: gpio@d4019004 { | ||
| 97 | reg = <0xd4019004 0x4>; | ||
| 98 | }; | ||
| 99 | |||
| 100 | gcb2: gpio@d4019008 { | ||
| 101 | reg = <0xd4019008 0x4>; | ||
| 102 | }; | ||
| 103 | |||
| 104 | gcb3: gpio@d4019100 { | ||
| 105 | reg = <0xd4019100 0x4>; | ||
| 106 | }; | ||
| 72 | }; | 107 | }; |
| 73 | 108 | ||
| 74 | twsi1: i2c@d4011000 { | 109 | twsi1: i2c@d4011000 { |
| 75 | compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; | 110 | compatible = "mrvl,mmp-twsi"; |
| 76 | reg = <0xd4011000 0x1000>; | 111 | reg = <0xd4011000 0x1000>; |
| 77 | interrupts = <7>; | 112 | interrupts = <7>; |
| 78 | mrvl,i2c-fast-mode; | 113 | mrvl,i2c-fast-mode; |
| @@ -80,7 +115,7 @@ | |||
| 80 | }; | 115 | }; |
| 81 | 116 | ||
| 82 | twsi2: i2c@d4025000 { | 117 | twsi2: i2c@d4025000 { |
| 83 | compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; | 118 | compatible = "mrvl,mmp-twsi"; |
| 84 | reg = <0xd4025000 0x1000>; | 119 | reg = <0xd4025000 0x1000>; |
| 85 | interrupts = <58>; | 120 | interrupts = <58>; |
| 86 | status = "disabled"; | 121 | status = "disabled"; |