diff options
Diffstat (limited to 'arch/arm/boot/dts/armada-xp.dtsi')
-rw-r--r-- | arch/arm/boot/dts/armada-xp.dtsi | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi new file mode 100644 index 000000000000..e1fa7e6edfe8 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
@@ -0,0 +1,55 @@ | |||
1 | /* | ||
2 | * Device Tree Include file for Marvell Armada XP family SoC | ||
3 | * | ||
4 | * Copyright (C) 2012 Marvell | ||
5 | * | ||
6 | * Lior Amsalem <alior@marvell.com> | ||
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | ||
10 | * | ||
11 | * This file is licensed under the terms of the GNU General Public | ||
12 | * License version 2. This program is licensed "as is" without any | ||
13 | * warranty of any kind, whether express or implied. | ||
14 | * | ||
15 | * Contains definitions specific to the Armada 370 SoC that are not | ||
16 | * common to all Armada SoCs. | ||
17 | */ | ||
18 | |||
19 | /include/ "armada-370-xp.dtsi" | ||
20 | |||
21 | / { | ||
22 | model = "Marvell Armada XP family SoC"; | ||
23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | ||
24 | |||
25 | mpic: interrupt-controller@d0020000 { | ||
26 | reg = <0xd0020a00 0x1d0>, | ||
27 | <0xd0021870 0x58>; | ||
28 | }; | ||
29 | |||
30 | soc { | ||
31 | serial@d0012200 { | ||
32 | compatible = "ns16550"; | ||
33 | reg = <0xd0012200 0x100>; | ||
34 | reg-shift = <2>; | ||
35 | interrupts = <43>; | ||
36 | status = "disabled"; | ||
37 | }; | ||
38 | serial@d0012300 { | ||
39 | compatible = "ns16550"; | ||
40 | reg = <0xd0012300 0x100>; | ||
41 | reg-shift = <2>; | ||
42 | interrupts = <44>; | ||
43 | status = "disabled"; | ||
44 | }; | ||
45 | |||
46 | timer@d0020300 { | ||
47 | marvell,timer-25Mhz; | ||
48 | }; | ||
49 | |||
50 | system-controller@d0018200 { | ||
51 | compatible = "marvell,armada-370-xp-system-controller"; | ||
52 | reg = <0xd0018200 0x500>; | ||
53 | }; | ||
54 | }; | ||
55 | }; | ||