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-rw-r--r--Documentation/ABI/stable/sysfs-bus-firewire11
-rw-r--r--Documentation/ABI/testing/sysfs-devices-edac140
-rw-r--r--Documentation/ABI/testing/sysfs-platform-asus-wmi7
-rw-r--r--Documentation/DMA-attributes.txt42
-rw-r--r--Documentation/device-mapper/striped.txt7
-rw-r--r--Documentation/device-mapper/thin-provisioning.txt24
-rw-r--r--Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt15
-rw-r--r--Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt14
-rw-r--r--Documentation/devicetree/bindings/ata/cavium-compact-flash.txt30
-rw-r--r--Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt49
-rw-r--r--Documentation/devicetree/bindings/i2c/cavium-i2c.txt34
-rw-r--r--Documentation/devicetree/bindings/i2c/gpio-i2c.txt (renamed from Documentation/devicetree/bindings/gpio/gpio_i2c.txt)0
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mxs.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-ocores.txt33
-rw-r--r--Documentation/devicetree/bindings/i2c/mrvl-i2c.txt19
-rw-r--r--Documentation/devicetree/bindings/mfd/ab8500.txt123
-rw-r--r--Documentation/devicetree/bindings/mfd/max77686.txt59
-rw-r--r--Documentation/devicetree/bindings/mfd/tps65910.txt2
-rw-r--r--Documentation/devicetree/bindings/mfd/twl6040.txt2
-rw-r--r--Documentation/devicetree/bindings/mips/cavium/bootbus.txt126
-rw-r--r--Documentation/devicetree/bindings/mips/cavium/ciu.txt26
-rw-r--r--Documentation/devicetree/bindings/mips/cavium/ciu2.txt27
-rw-r--r--Documentation/devicetree/bindings/mips/cavium/dma-engine.txt21
-rw-r--r--Documentation/devicetree/bindings/mips/cavium/uctl.txt46
-rw-r--r--Documentation/devicetree/bindings/net/cavium-mdio.txt27
-rw-r--r--Documentation/devicetree/bindings/net/cavium-mix.txt39
-rw-r--r--Documentation/devicetree/bindings/net/cavium-pip.txt98
-rw-r--r--Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt12
-rw-r--r--Documentation/devicetree/bindings/pwm/mxs-pwm.txt17
-rw-r--r--Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt18
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm.txt57
-rw-r--r--Documentation/devicetree/bindings/serial/cavium-uart.txt19
-rw-r--r--Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt28
-rw-r--r--Documentation/dontdiff1
-rw-r--r--Documentation/edac.txt112
-rw-r--r--Documentation/input/edt-ft5x06.txt54
-rw-r--r--Documentation/kernel-parameters.txt2
-rw-r--r--Documentation/pwm.txt76
38 files changed, 1306 insertions, 114 deletions
diff --git a/Documentation/ABI/stable/sysfs-bus-firewire b/Documentation/ABI/stable/sysfs-bus-firewire
index 3d484e5dc846..41e5a0cd1e3e 100644
--- a/Documentation/ABI/stable/sysfs-bus-firewire
+++ b/Documentation/ABI/stable/sysfs-bus-firewire
@@ -39,6 +39,17 @@ Users: udev rules to set ownership and access permissions or ACLs of
39 /dev/fw[0-9]+ character device files 39 /dev/fw[0-9]+ character device files
40 40
41 41
42What: /sys/bus/firewire/devices/fw[0-9]+/is_local
43Date: July 2012
44KernelVersion: 3.6
45Contact: linux1394-devel@lists.sourceforge.net
46Description:
47 IEEE 1394 node device attribute.
48 Read-only and immutable.
49Values: 1: The sysfs entry represents a local node (a controller card).
50 0: The sysfs entry represents a remote node.
51
52
42What: /sys/bus/firewire/devices/fw[0-9]+[.][0-9]+/ 53What: /sys/bus/firewire/devices/fw[0-9]+[.][0-9]+/
43Date: May 2007 54Date: May 2007
44KernelVersion: 2.6.22 55KernelVersion: 2.6.22
diff --git a/Documentation/ABI/testing/sysfs-devices-edac b/Documentation/ABI/testing/sysfs-devices-edac
new file mode 100644
index 000000000000..30ee78aaed75
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-edac
@@ -0,0 +1,140 @@
1What: /sys/devices/system/edac/mc/mc*/reset_counters
2Date: January 2006
3Contact: linux-edac@vger.kernel.org
4Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
6 Zeroing the counters will also reset the timer indicating how
7 long since the last counter were reset. This is useful for
8 computing errors/time. Since the counters are always reset
9 at driver initialization time, no module/kernel parameter
10 is available.
11
12What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
13Date: January 2006
14Contact: linux-edac@vger.kernel.org
15Description: This attribute file displays how many seconds have elapsed
16 since the last counter reset. This can be used with the error
17 counters to measure error rates.
18
19What: /sys/devices/system/edac/mc/mc*/mc_name
20Date: January 2006
21Contact: linux-edac@vger.kernel.org
22Description: This attribute file displays the type of memory controller
23 that is being utilized.
24
25What: /sys/devices/system/edac/mc/mc*/size_mb
26Date: January 2006
27Contact: linux-edac@vger.kernel.org
28Description: This attribute file displays, in count of megabytes, of memory
29 that this memory controller manages.
30
31What: /sys/devices/system/edac/mc/mc*/ue_count
32Date: January 2006
33Contact: linux-edac@vger.kernel.org
34Description: This attribute file displays the total count of uncorrectable
35 errors that have occurred on this memory controller. If
36 panic_on_ue is set, this counter will not have a chance to
37 increment, since EDAC will panic the system
38
39What: /sys/devices/system/edac/mc/mc*/ue_noinfo_count
40Date: January 2006
41Contact: linux-edac@vger.kernel.org
42Description: This attribute file displays the number of UEs that have
43 occurred on this memory controller with no information as to
44 which DIMM slot is having errors.
45
46What: /sys/devices/system/edac/mc/mc*/ce_count
47Date: January 2006
48Contact: linux-edac@vger.kernel.org
49Description: This attribute file displays the total count of correctable
50 errors that have occurred on this memory controller. This
51 count is very important to examine. CEs provide early
52 indications that a DIMM is beginning to fail. This count
53 field should be monitored for non-zero values and report
54 such information to the system administrator.
55
56What: /sys/devices/system/edac/mc/mc*/ce_noinfo_count
57Date: January 2006
58Contact: linux-edac@vger.kernel.org
59Description: This attribute file displays the number of CEs that
60 have occurred on this memory controller wherewith no
61 information as to which DIMM slot is having errors. Memory is
62 handicapped, but operational, yet no information is available
63 to indicate which slot the failing memory is in. This count
64 field should be also be monitored for non-zero values.
65
66What: /sys/devices/system/edac/mc/mc*/sdram_scrub_rate
67Date: February 2007
68Contact: linux-edac@vger.kernel.org
69Description: Read/Write attribute file that controls memory scrubbing.
70 The scrubbing rate used by the memory controller is set by
71 writing a minimum bandwidth in bytes/sec to the attribute file.
72 The rate will be translated to an internal value that gives at
73 least the specified rate.
74 Reading the file will return the actual scrubbing rate employed.
75 If configuration fails or memory scrubbing is not implemented,
76 the value of the attribute file will be -1.
77
78What: /sys/devices/system/edac/mc/mc*/max_location
79Date: April 2012
80Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
81 linux-edac@vger.kernel.org
82Description: This attribute file displays the information about the last
83 available memory slot in this memory controller. It is used by
84 userspace tools in order to display the memory filling layout.
85
86What: /sys/devices/system/edac/mc/mc*/(dimm|rank)*/size
87Date: April 2012
88Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
89 linux-edac@vger.kernel.org
90Description: This attribute file will display the size of dimm or rank.
91 For dimm*/size, this is the size, in MB of the DIMM memory
92 stick. For rank*/size, this is the size, in MB for one rank
93 of the DIMM memory stick. On single rank memories (1R), this
94 is also the total size of the dimm. On dual rank (2R) memories,
95 this is half the size of the total DIMM memories.
96
97What: /sys/devices/system/edac/mc/mc*/(dimm|rank)*/dimm_dev_type
98Date: April 2012
99Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
100 linux-edac@vger.kernel.org
101Description: This attribute file will display what type of DRAM device is
102 being utilized on this DIMM (x1, x2, x4, x8, ...).
103
104What: /sys/devices/system/edac/mc/mc*/(dimm|rank)*/dimm_edac_mode
105Date: April 2012
106Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
107 linux-edac@vger.kernel.org
108Description: This attribute file will display what type of Error detection
109 and correction is being utilized. For example: S4ECD4ED would
110 mean a Chipkill with x4 DRAM.
111
112What: /sys/devices/system/edac/mc/mc*/(dimm|rank)*/dimm_label
113Date: April 2012
114Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
115 linux-edac@vger.kernel.org
116Description: This control file allows this DIMM to have a label assigned
117 to it. With this label in the module, when errors occur
118 the output can provide the DIMM label in the system log.
119 This becomes vital for panic events to isolate the
120 cause of the UE event.
121 DIMM Labels must be assigned after booting, with information
122 that correctly identifies the physical slot with its
123 silk screen label. This information is currently very
124 motherboard specific and determination of this information
125 must occur in userland at this time.
126
127What: /sys/devices/system/edac/mc/mc*/(dimm|rank)*/dimm_location
128Date: April 2012
129Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
130 linux-edac@vger.kernel.org
131Description: This attribute file will display the location (csrow/channel,
132 branch/channel/slot or channel/slot) of the dimm or rank.
133
134What: /sys/devices/system/edac/mc/mc*/(dimm|rank)*/dimm_mem_type
135Date: April 2012
136Contact: Mauro Carvalho Chehab <mchehab@redhat.com>
137 linux-edac@vger.kernel.org
138Description: This attribute file will display what type of memory is
139 currently on this csrow. Normally, either buffered or
140 unbuffered memory (for example, Unbuffered-DDR3).
diff --git a/Documentation/ABI/testing/sysfs-platform-asus-wmi b/Documentation/ABI/testing/sysfs-platform-asus-wmi
index 2e7df91620de..019e1e29370e 100644
--- a/Documentation/ABI/testing/sysfs-platform-asus-wmi
+++ b/Documentation/ABI/testing/sysfs-platform-asus-wmi
@@ -29,3 +29,10 @@ KernelVersion: 2.6.39
29Contact: "Corentin Chary" <corentincj@iksaif.net> 29Contact: "Corentin Chary" <corentincj@iksaif.net>
30Description: 30Description:
31 Control the card touchpad. 1 means on, 0 means off. 31 Control the card touchpad. 1 means on, 0 means off.
32
33What: /sys/devices/platform/<platform>/lid_resume
34Date: May 2012
35KernelVersion: 3.5
36Contact: "AceLan Kao" <acelan.kao@canonical.com>
37Description:
38 Resume on lid open. 1 means on, 0 means off.
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt
index 5c72eed89563..f50309081ac7 100644
--- a/Documentation/DMA-attributes.txt
+++ b/Documentation/DMA-attributes.txt
@@ -49,3 +49,45 @@ DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either
49consistent or non-consistent memory as it sees fit. By using this API, 49consistent or non-consistent memory as it sees fit. By using this API,
50you are guaranteeing to the platform that you have all the correct and 50you are guaranteeing to the platform that you have all the correct and
51necessary sync points for this memory in the driver. 51necessary sync points for this memory in the driver.
52
53DMA_ATTR_NO_KERNEL_MAPPING
54--------------------------
55
56DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
57virtual mapping for the allocated buffer. On some architectures creating
58such mapping is non-trivial task and consumes very limited resources
59(like kernel virtual address space or dma consistent address space).
60Buffers allocated with this attribute can be only passed to user space
61by calling dma_mmap_attrs(). By using this API, you are guaranteeing
62that you won't dereference the pointer returned by dma_alloc_attr(). You
63can threat it as a cookie that must be passed to dma_mmap_attrs() and
64dma_free_attrs(). Make sure that both of these also get this attribute
65set on each call.
66
67Since it is optional for platforms to implement
68DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
69attribute and exhibit default behavior.
70
71DMA_ATTR_SKIP_CPU_SYNC
72----------------------
73
74By default dma_map_{single,page,sg} functions family transfer a given
75buffer from CPU domain to device domain. Some advanced use cases might
76require sharing a buffer between more than one device. This requires
77having a mapping created separately for each device and is usually
78performed by calling dma_map_{single,page,sg} function more than once
79for the given buffer with device pointer to each device taking part in
80the buffer sharing. The first call transfers a buffer from 'CPU' domain
81to 'device' domain, what synchronizes CPU caches for the given region
82(usually it means that the cache has been flushed or invalidated
83depending on the dma direction). However, next calls to
84dma_map_{single,page,sg}() for other devices will perform exactly the
85same sychronization operation on the CPU cache. CPU cache sychronization
86might be a time consuming operation, especially if the buffers are
87large, so it is highly recommended to avoid it if possible.
88DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
89the CPU cache for the given buffer assuming that it has been already
90transferred to 'device' domain. This attribute can be also used for
91dma_unmap_{single,page,sg} functions family to force buffer to stay in
92device domain after releasing a mapping for it. Use this attribute with
93care!
diff --git a/Documentation/device-mapper/striped.txt b/Documentation/device-mapper/striped.txt
index f34d3236b9da..45f3b91ea4c3 100644
--- a/Documentation/device-mapper/striped.txt
+++ b/Documentation/device-mapper/striped.txt
@@ -9,15 +9,14 @@ devices in parallel.
9 9
10Parameters: <num devs> <chunk size> [<dev path> <offset>]+ 10Parameters: <num devs> <chunk size> [<dev path> <offset>]+
11 <num devs>: Number of underlying devices. 11 <num devs>: Number of underlying devices.
12 <chunk size>: Size of each chunk of data. Must be a power-of-2 and at 12 <chunk size>: Size of each chunk of data. Must be at least as
13 least as large as the system's PAGE_SIZE. 13 large as the system's PAGE_SIZE.
14 <dev path>: Full pathname to the underlying block-device, or a 14 <dev path>: Full pathname to the underlying block-device, or a
15 "major:minor" device-number. 15 "major:minor" device-number.
16 <offset>: Starting sector within the device. 16 <offset>: Starting sector within the device.
17 17
18One or more underlying devices can be specified. The striped device size must 18One or more underlying devices can be specified. The striped device size must
19be a multiple of the chunk size and a multiple of the number of underlying 19be a multiple of the chunk size multiplied by the number of underlying devices.
20devices.
21 20
22 21
23Example scripts 22Example scripts
diff --git a/Documentation/device-mapper/thin-provisioning.txt b/Documentation/device-mapper/thin-provisioning.txt
index f5cfc62b7ad3..30b8b83bd333 100644
--- a/Documentation/device-mapper/thin-provisioning.txt
+++ b/Documentation/device-mapper/thin-provisioning.txt
@@ -231,6 +231,9 @@ i) Constructor
231 no_discard_passdown: Don't pass discards down to the underlying 231 no_discard_passdown: Don't pass discards down to the underlying
232 data device, but just remove the mapping. 232 data device, but just remove the mapping.
233 233
234 read_only: Don't allow any changes to be made to the pool
235 metadata.
236
234 Data block size must be between 64KB (128 sectors) and 1GB 237 Data block size must be between 64KB (128 sectors) and 1GB
235 (2097152 sectors) inclusive. 238 (2097152 sectors) inclusive.
236 239
@@ -239,7 +242,7 @@ ii) Status
239 242
240 <transaction id> <used metadata blocks>/<total metadata blocks> 243 <transaction id> <used metadata blocks>/<total metadata blocks>
241 <used data blocks>/<total data blocks> <held metadata root> 244 <used data blocks>/<total data blocks> <held metadata root>
242 245 [no_]discard_passdown ro|rw
243 246
244 transaction id: 247 transaction id:
245 A 64-bit number used by userspace to help synchronise with metadata 248 A 64-bit number used by userspace to help synchronise with metadata
@@ -257,6 +260,21 @@ ii) Status
257 held root. This feature is not yet implemented so '-' is 260 held root. This feature is not yet implemented so '-' is
258 always returned. 261 always returned.
259 262
263 discard_passdown|no_discard_passdown
264 Whether or not discards are actually being passed down to the
265 underlying device. When this is enabled when loading the table,
266 it can get disabled if the underlying device doesn't support it.
267
268 ro|rw
269 If the pool encounters certain types of device failures it will
270 drop into a read-only metadata mode in which no changes to
271 the pool metadata (like allocating new blocks) are permitted.
272
273 In serious cases where even a read-only mode is deemed unsafe
274 no further I/O will be permitted and the status will just
275 contain the string 'Fail'. The userspace recovery tools
276 should then be used.
277
260iii) Messages 278iii) Messages
261 279
262 create_thin <dev id> 280 create_thin <dev id>
@@ -329,3 +347,7 @@ regain some space then send the 'trim' message to the pool.
329ii) Status 347ii) Status
330 348
331 <nr mapped sectors> <highest mapped sector> 349 <nr mapped sectors> <highest mapped sector>
350
351 If the pool has encountered device errors and failed, the status
352 will just contain the string 'Fail'. The userspace recovery
353 tools should then be used.
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
new file mode 100644
index 000000000000..94e642a33db0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
@@ -0,0 +1,15 @@
1Calxeda Highbank L2 cache ECC
2
3Properties:
4- compatible : Should be "calxeda,hb-sregs-l2-ecc"
5- reg : Address and size for ECC error interrupt clear registers.
6- interrupts : Should be single bit error interrupt, then double bit error
7 interrupt.
8
9Example:
10
11 sregs@fff3c200 {
12 compatible = "calxeda,hb-sregs-l2-ecc";
13 reg = <0xfff3c200 0x100>;
14 interrupts = <0 71 4 0 72 4>;
15 };
diff --git a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt
new file mode 100644
index 000000000000..f770ac0893d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt
@@ -0,0 +1,14 @@
1Calxeda DDR memory controller
2
3Properties:
4- compatible : Should be "calxeda,hb-ddr-ctrl"
5- reg : Address and size for DDR controller registers.
6- interrupts : Interrupt for DDR controller.
7
8Example:
9
10 memory-controller@fff00000 {
11 compatible = "calxeda,hb-ddr-ctrl";
12 reg = <0xfff00000 0x1000>;
13 interrupts = <0 91 4>;
14 };
diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
new file mode 100644
index 000000000000..93986a5a8018
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
@@ -0,0 +1,30 @@
1* Compact Flash
2
3The Cavium Compact Flash device is connected to the Octeon Boot Bus,
4and is thus a child of the Boot Bus device. It can read and write
5industry standard compact flash devices.
6
7Properties:
8- compatible: "cavium,ebt3000-compact-flash";
9
10 Compatibility with many Cavium evaluation boards.
11
12- reg: The base address of the the CF chip select banks. Depending on
13 the device configuration, there may be one or two banks.
14
15- cavium,bus-width: The width of the connection to the CF devices. Valid
16 values are 8 and 16.
17
18- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
19
20- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
21 to this device.
22
23Example:
24 compact-flash@5,0 {
25 compatible = "cavium,ebt3000-compact-flash";
26 reg = <5 0 0x10000>, <6 0 0x10000>;
27 cavium,bus-width = <16>;
28 cavium,true-ide;
29 cavium,dma-engine-handle = <&dma0>;
30 };
diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
new file mode 100644
index 000000000000..9d6dcd3fe7f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
@@ -0,0 +1,49 @@
1* General Purpose Input Output (GPIO) bus.
2
3Properties:
4- compatible: "cavium,octeon-3860-gpio"
5
6 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
7
8- reg: The base address of the GPIO unit's register bank.
9
10- gpio-controller: This is a GPIO controller.
11
12- #gpio-cells: Must be <2>. The first cell is the GPIO pin.
13
14- interrupt-controller: The GPIO controller is also an interrupt
15 controller, many of its pins may be configured as an interrupt
16 source.
17
18- #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19 connected to the interrupt source. The second cell is the interrupt
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
25
26- interrupts: Interrupt routing for each pin.
27
28Example:
29
30 gpio-controller@1070000000800 {
31 #gpio-cells = <2>;
32 compatible = "cavium,octeon-3860-gpio";
33 reg = <0x10700 0x00000800 0x0 0x100>;
34 gpio-controller;
35 /* Interrupts are specified by two parts:
36 * 1) GPIO pin number (0..15)
37 * 2) Triggering (1 - edge rising
38 * 2 - edge falling
39 * 4 - level active high
40 * 8 - level active low)
41 */
42 interrupt-controller;
43 #interrupt-cells = <2>;
44 /* The GPIO pin connect to 16 consecutive CUI bits */
45 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
46 <0 20>, <0 21>, <0 22>, <0 23>,
47 <0 24>, <0 25>, <0 26>, <0 27>,
48 <0 28>, <0 29>, <0 30>, <0 31>;
49 };
diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt
new file mode 100644
index 000000000000..dced82ebe31d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt
@@ -0,0 +1,34 @@
1* Two Wire Serial Interface (TWSI) / I2C
2
3- compatible: "cavium,octeon-3860-twsi"
4
5 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
6
7- reg: The base address of the TWSI/I2C bus controller register bank.
8
9- #address-cells: Must be <1>.
10
11- #size-cells: Must be <0>. I2C addresses have no size component.
12
13- interrupts: A single interrupt specifier.
14
15- clock-frequency: The I2C bus clock rate in Hz.
16
17Example:
18 twsi0: i2c@1180000001000 {
19 #address-cells = <1>;
20 #size-cells = <0>;
21 compatible = "cavium,octeon-3860-twsi";
22 reg = <0x11800 0x00001000 0x0 0x200>;
23 interrupts = <0 45>;
24 clock-frequency = <100000>;
25
26 rtc@68 {
27 compatible = "dallas,ds1337";
28 reg = <0x68>;
29 };
30 tmp@4c {
31 compatible = "ti,tmp421";
32 reg = <0x4c>;
33 };
34 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/i2c/gpio-i2c.txt
index 4f8ec947c6bd..4f8ec947c6bd 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/gpio-i2c.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
index 1bfc02de1b0c..30ac3a0557f7 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
@@ -4,6 +4,8 @@ Required properties:
4- compatible: Should be "fsl,<chip>-i2c" 4- compatible: Should be "fsl,<chip>-i2c"
5- reg: Should contain registers location and length 5- reg: Should contain registers location and length
6- interrupts: Should contain ERROR and DMA interrupts 6- interrupts: Should contain ERROR and DMA interrupts
7- clock-frequency: Desired I2C bus clock frequency in Hz.
8 Only 100000Hz and 400000Hz modes are supported.
7 9
8Examples: 10Examples:
9 11
@@ -13,4 +15,5 @@ i2c0: i2c@80058000 {
13 compatible = "fsl,imx28-i2c"; 15 compatible = "fsl,imx28-i2c";
14 reg = <0x80058000 2000>; 16 reg = <0x80058000 2000>;
15 interrupts = <111 68>; 17 interrupts = <111 68>;
18 clock-frequency = <100000>;
16}; 19};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
new file mode 100644
index 000000000000..c15781f4dc8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -0,0 +1,33 @@
1Device tree configuration for i2c-ocores
2
3Required properties:
4- compatible : "opencores,i2c-ocores"
5- reg : bus address start and address range size of device
6- interrupts : interrupt number
7- clock-frequency : frequency of bus clock in Hz
8- #address-cells : should be <1>
9- #size-cells : should be <0>
10
11Optional properties:
12- reg-shift : device register offsets are shifted by this value
13- reg-io-width : io register width in bytes (1, 2 or 4)
14- regstep : deprecated, use reg-shift above
15
16Example:
17
18 i2c0: ocores@a0000000 {
19 #address-cells = <1>;
20 #size-cells = <0>;
21 compatible = "opencores,i2c-ocores";
22 reg = <0xa0000000 0x8>;
23 interrupts = <10>;
24 clock-frequency = <20000000>;
25
26 reg-shift = <0>; /* 8 bit registers */
27 reg-io-width = <1>; /* 8 bit read/write */
28
29 dummy@60 {
30 compatible = "dummy";
31 reg = <0x60>;
32 };
33 };
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
index b891ee218354..0f7945019f6f 100644
--- a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
@@ -1,4 +1,4 @@
1* I2C 1* Marvell MMP I2C controller
2 2
3Required properties : 3Required properties :
4 4
@@ -32,3 +32,20 @@ Examples:
32 interrupts = <58>; 32 interrupts = <58>;
33 }; 33 };
34 34
35* Marvell MV64XXX I2C controller
36
37Required properties :
38
39 - reg : Offset and length of the register set for the device
40 - compatible : Should be "marvell,mv64xxx-i2c"
41 - interrupts : The interrupt number
42 - clock-frequency : Desired I2C bus clock frequency in Hz.
43
44Examples:
45
46 i2c@11000 {
47 compatible = "marvell,mv64xxx-i2c";
48 reg = <0x11000 0x20>;
49 interrupts = <29>;
50 clock-frequency = <100000>;
51 };
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
new file mode 100644
index 000000000000..69e757a657a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -0,0 +1,123 @@
1* AB8500 Multi-Functional Device (MFD)
2
3Required parent device properties:
4- compatible : contains "stericsson,ab8500";
5- interrupts : contains the IRQ line for the AB8500
6- interrupt-controller : describes the AB8500 as an Interrupt Controller (has its own domain)
7- #interrupt-cells : should be 2, for 2-cell format
8 - The first cell is the AB8500 local IRQ number
9 - The second cell is used to specify optional parameters
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered
12 2 = high-to-low edge triggered
13 4 = active high level-sensitive
14 8 = active low level-sensitive
15
16Optional parent device properties:
17- reg : contains the PRCMU mailbox address for the AB8500 i2c port
18
19The AB8500 consists of a large and varied group of sub-devices:
20
21Device IRQ Names Supply Names Description
22------ --------- ------------ -----------
23ab8500-bm : : : Battery Manager
24ab8500-btemp : : : Battery Temperature
25ab8500-charger : : : Battery Charger
26ab8500-fg : : : Fuel Gauge
27ab8500-gpadc : HW_CONV_END : vddadc : Analogue to Digital Converter
28 SW_CONV_END : :
29ab8500-gpio : : : GPIO Controller
30ab8500-ponkey : ONKEY_DBF : : Power-on Key
31 ONKEY_DBR : :
32ab8500-pwm : : : Pulse Width Modulator
33ab8500-regulator : : : Regulators
34ab8500-rtc : 60S : : Real Time Clock
35 : ALARM : :
36ab8500-sysctrl : : : System Control
37ab8500-usb : ID_WAKEUP_R : vddulpivio18 : Universal Serial Bus
38 : ID_WAKEUP_F : v-ape :
39 : VBUS_DET_F : musb_1v8 :
40 : VBUS_DET_R : :
41 : USB_LINK_STATUS : :
42 : USB_ADP_PROBE_PLUG : :
43 : USB_ADP_PROBE_UNPLUG : :
44
45Required child device properties:
46- compatible : "stericsson,ab8500-[bm|btemp|charger|fg|gpadc|gpio|ponkey|
47 pwm|regulator|rtc|sysctrl|usb]";
48
49Optional child device properties:
50- interrupts : contains the device IRQ(s) using the 2-cell format (see above)
51- interrupt-names : contains names of IRQ resource in the order in which they were
52 supplied in the interrupts property
53- <supply_name>-supply : contains a phandle to the regulator supply node in Device Tree
54
55ab8500@5 {
56 compatible = "stericsson,ab8500";
57 reg = <5>; /* mailbox 5 is i2c */
58 interrupts = <0 40 0x4>;
59 interrupt-controller;
60 #interrupt-cells = <2>;
61
62 ab8500-rtc {
63 compatible = "stericsson,ab8500-rtc";
64 interrupts = <17 0x4
65 18 0x4>;
66 interrupt-names = "60S", "ALARM";
67 };
68
69 ab8500-gpadc {
70 compatible = "stericsson,ab8500-gpadc";
71 interrupts = <32 0x4
72 39 0x4>;
73 interrupt-names = "HW_CONV_END", "SW_CONV_END";
74 vddadc-supply = <&ab8500_ldo_tvout_reg>;
75 };
76
77 ab8500-usb {
78 compatible = "stericsson,ab8500-usb";
79 interrupts = < 90 0x4
80 96 0x4
81 14 0x4
82 15 0x4
83 79 0x4
84 74 0x4
85 75 0x4>;
86 interrupt-names = "ID_WAKEUP_R",
87 "ID_WAKEUP_F",
88 "VBUS_DET_F",
89 "VBUS_DET_R",
90 "USB_LINK_STATUS",
91 "USB_ADP_PROBE_PLUG",
92 "USB_ADP_PROBE_UNPLUG";
93 vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
94 v-ape-supply = <&db8500_vape_reg>;
95 musb_1v8-supply = <&db8500_vsmps2_reg>;
96 };
97
98 ab8500-ponkey {
99 compatible = "stericsson,ab8500-ponkey";
100 interrupts = <6 0x4
101 7 0x4>;
102 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
103 };
104
105 ab8500-sysctrl {
106 compatible = "stericsson,ab8500-sysctrl";
107 };
108
109 ab8500-pwm {
110 compatible = "stericsson,ab8500-pwm";
111 };
112
113 ab8500-regulators {
114 compatible = "stericsson,ab8500-regulator";
115
116 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
117 /*
118 * See: Documentation/devicetree/bindings/regulator/regulator.txt
119 * for more information on regulators
120 */
121 };
122 };
123};
diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt
new file mode 100644
index 000000000000..c6a3469d3436
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77686.txt
@@ -0,0 +1,59 @@
1Maxim MAX77686 multi-function device
2
3MAX77686 is a Mulitifunction device with PMIC, RTC and Charger on chip. It is
4interfaced to host controller using i2c interface. PMIC and Charger submodules
5are addressed using same i2c slave address whereas RTC submodule uses
6different i2c slave address,presently for which we are statically creating i2c
7client while probing.This document describes the binding for mfd device and
8PMIC submodule.
9
10Required properties:
11- compatible : Must be "maxim,max77686";
12- reg : Specifies the i2c slave address of PMIC block.
13- interrupts : This i2c device has an IRQ line connected to the main SoC.
14- interrupt-parent : The parent interrupt controller.
15
16Optional node:
17- voltage-regulators : The regulators of max77686 have to be instantiated
18 under subnode named "voltage-regulators" using the following format.
19
20 regulator_name {
21 regulator-compatible = LDOn/BUCKn
22 standard regulator constraints....
23 };
24 refer Documentation/devicetree/bindings/regulator/regulator.txt
25
26 The regulator-compatible property of regulator should initialized with string
27to get matched with their hardware counterparts as follow:
28
29 -LDOn : for LDOs, where n can lie in range 1 to 26.
30 example: LDO1, LDO2, LDO26.
31 -BUCKn : for BUCKs, where n can lie in range 1 to 9.
32 example: BUCK1, BUCK5, BUCK9.
33
34Example:
35
36 max77686@09 {
37 compatible = "maxim,max77686";
38 interrupt-parent = <&wakeup_eint>;
39 interrupts = <26 0>;
40 reg = <0x09>;
41
42 voltage-regulators {
43 ldo11_reg {
44 regulator-compatible = "LDO11";
45 regulator-name = "vdd_ldo11";
46 regulator-min-microvolt = <1900000>;
47 regulator-max-microvolt = <1900000>;
48 regulator-always-on;
49 };
50
51 buck1_reg {
52 regulator-compatible = "BUCK1";
53 regulator-name = "vdd_mif";
54 regulator-min-microvolt = <950000>;
55 regulator-max-microvolt = <1300000>;
56 regulator-always-on;
57 regulator-boot-on;
58 };
59 }
diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt b/Documentation/devicetree/bindings/mfd/tps65910.txt
index d2802d4717bc..db03599ae4dc 100644
--- a/Documentation/devicetree/bindings/mfd/tps65910.txt
+++ b/Documentation/devicetree/bindings/mfd/tps65910.txt
@@ -81,7 +81,7 @@ Example:
81 81
82 ti,vmbch-threshold = 0; 82 ti,vmbch-threshold = 0;
83 ti,vmbch2-threshold = 0; 83 ti,vmbch2-threshold = 0;
84 84 ti,en-ck32k-xtal;
85 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; 85 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
86 86
87 vcc1-supply = <&reg_parent>; 87 vcc1-supply = <&reg_parent>;
diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt
index bc67c6f424aa..c855240f3a0e 100644
--- a/Documentation/devicetree/bindings/mfd/twl6040.txt
+++ b/Documentation/devicetree/bindings/mfd/twl6040.txt
@@ -6,7 +6,7 @@ They are connected ot the host processor via i2c for commands, McPDM for audio
6data and commands. 6data and commands.
7 7
8Required properties: 8Required properties:
9- compatible : Must be "ti,twl6040"; 9- compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041
10- reg: must be 0x4b for i2c address 10- reg: must be 0x4b for i2c address
11- interrupts: twl6040 has one interrupt line connecteded to the main SoC 11- interrupts: twl6040 has one interrupt line connecteded to the main SoC
12- interrupt-parent: The parent interrupt controller 12- interrupt-parent: The parent interrupt controller
diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
new file mode 100644
index 000000000000..6581478225a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
@@ -0,0 +1,126 @@
1* Boot Bus
2
3The Octeon Boot Bus is a configurable parallel bus with 8 chip
4selects. Each chip select is independently configurable.
5
6Properties:
7- compatible: "cavium,octeon-3860-bootbus"
8
9 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
10
11- reg: The base address of the Boot Bus' register bank.
12
13- #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
15
16- #size-cells: Must be <1>.
17
18- ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
21 making it inactive.
22
23The configuration parameters for each chip select are stored in child
24nodes.
25
26Configuration Properties:
27- compatible: "cavium,octeon-3860-bootbus-config"
28
29- cavium,cs-index: A single cell indicating the chip select that
30 corresponds to this configuration.
31
32- cavium,t-adr: A cell specifying the ADR timing (in nS).
33
34- cavium,t-ce: A cell specifying the CE timing (in nS).
35
36- cavium,t-oe: A cell specifying the OE timing (in nS).
37
38- cavium,t-we: A cell specifying the WE timing (in nS).
39
40- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
41
42- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
43
44- cavium,t-pause: A cell specifying the PAUSE timing (in nS).
45
46- cavium,t-wait: A cell specifying the WAIT timing (in nS).
47
48- cavium,t-page: A cell specifying the PAGE timing (in nS).
49
50- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
51
52- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
53 = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
54
55- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected.
56
57- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected.
58
59- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
60 the bus for this chip select.
61
62- cavium,ale-mode: Optional. If present, ALE mode is selected.
63
64- cavium,sam-mode: Optional. If present, SAM mode is selected.
65
66- cavium,or-mode: Optional. If present, OR mode is selected.
67
68Example:
69 bootbus: bootbus@1180000000000 {
70 compatible = "cavium,octeon-3860-bootbus";
71 reg = <0x11800 0x00000000 0x0 0x200>;
72 /* The chip select number and offset */
73 #address-cells = <2>;
74 /* The size of the chip select region */
75 #size-cells = <1>;
76 ranges = <0 0 0x0 0x1f400000 0xc00000>,
77 <1 0 0x10000 0x30000000 0>,
78 <2 0 0x10000 0x40000000 0>,
79 <3 0 0x10000 0x50000000 0>,
80 <4 0 0x0 0x1d020000 0x10000>,
81 <5 0 0x0 0x1d040000 0x10000>,
82 <6 0 0x0 0x1d050000 0x10000>,
83 <7 0 0x10000 0x90000000 0>;
84
85 cavium,cs-config@0 {
86 compatible = "cavium,octeon-3860-bootbus-config";
87 cavium,cs-index = <0>;
88 cavium,t-adr = <20>;
89 cavium,t-ce = <60>;
90 cavium,t-oe = <60>;
91 cavium,t-we = <45>;
92 cavium,t-rd-hld = <35>;
93 cavium,t-wr-hld = <45>;
94 cavium,t-pause = <0>;
95 cavium,t-wait = <0>;
96 cavium,t-page = <35>;
97 cavium,t-rd-dly = <0>;
98
99 cavium,pages = <0>;
100 cavium,bus-width = <8>;
101 };
102 .
103 .
104 .
105 cavium,cs-config@6 {
106 compatible = "cavium,octeon-3860-bootbus-config";
107 cavium,cs-index = <6>;
108 cavium,t-adr = <5>;
109 cavium,t-ce = <300>;
110 cavium,t-oe = <270>;
111 cavium,t-we = <150>;
112 cavium,t-rd-hld = <100>;
113 cavium,t-wr-hld = <70>;
114 cavium,t-pause = <0>;
115 cavium,t-wait = <0>;
116 cavium,t-page = <320>;
117 cavium,t-rd-dly = <0>;
118
119 cavium,pages = <0>;
120 cavium,wait-mode;
121 cavium,bus-width = <16>;
122 };
123 .
124 .
125 .
126 };
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
new file mode 100644
index 000000000000..2c2d0746b43d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
@@ -0,0 +1,26 @@
1* Central Interrupt Unit
2
3Properties:
4- compatible: "cavium,octeon-3860-ciu"
5
6 Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
7
8- interrupt-controller: This is an interrupt controller.
9
10- reg: The base address of the CIU's register bank.
11
12- #interrupt-cells: Must be <2>. The first cell is the bank within
13 the CIU and may have a value of 0 or 1. The second cell is the bit
14 within the bank and may have a value between 0 and 63.
15
16Example:
17 interrupt-controller@1070000000000 {
18 compatible = "cavium,octeon-3860-ciu";
19 interrupt-controller;
20 /* Interrupts are specified by two parts:
21 * 1) Controller register (0 or 1)
22 * 2) Bit within the register (0..63)
23 */
24 #interrupt-cells = <2>;
25 reg = <0x10700 0x00000000 0x0 0x7000>;
26 };
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt
new file mode 100644
index 000000000000..0ec7ba8bbbcb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt
@@ -0,0 +1,27 @@
1* Central Interrupt Unit
2
3Properties:
4- compatible: "cavium,octeon-6880-ciu2"
5
6 Compatibility with 68XX SOCs.
7
8- interrupt-controller: This is an interrupt controller.
9
10- reg: The base address of the CIU's register bank.
11
12- #interrupt-cells: Must be <2>. The first cell is the bank within
13 the CIU and may have a value between 0 and 63. The second cell is
14 the bit within the bank and may also have a value between 0 and 63.
15
16Example:
17 interrupt-controller@1070100000000 {
18 compatible = "cavium,octeon-6880-ciu2";
19 interrupt-controller;
20 /* Interrupts are specified by two parts:
21 * 1) Controller register (0..63)
22 * 2) Bit within the register (0..63)
23 */
24 #address-cells = <0>;
25 #interrupt-cells = <2>;
26 reg = <0x10701 0x00000000 0x0 0x4000000>;
27 };
diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
new file mode 100644
index 000000000000..cb4291e3b1d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
@@ -0,0 +1,21 @@
1* DMA Engine.
2
3The Octeon DMA Engine transfers between the Boot Bus and main memory.
4The DMA Engine will be refered to by phandle by any device that is
5connected to it.
6
7Properties:
8- compatible: "cavium,octeon-5750-bootbus-dma"
9
10 Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.
11
12- reg: The base address of the DMA Engine's register bank.
13
14- interrupts: A single interrupt specifier.
15
16Example:
17 dma0: dma-engine@1180000000100 {
18 compatible = "cavium,octeon-5750-bootbus-dma";
19 reg = <0x11800 0x00000100 0x0 0x8>;
20 interrupts = <0 63>;
21 };
diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt
new file mode 100644
index 000000000000..aa66b9b8d801
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt
@@ -0,0 +1,46 @@
1* UCTL USB controller glue
2
3Properties:
4- compatible: "cavium,octeon-6335-uctl"
5
6 Compatibility with all cn6XXX SOCs.
7
8- reg: The base address of the UCTL register bank.
9
10- #address-cells: Must be <2>.
11
12- #size-cells: Must be <2>.
13
14- ranges: Empty to signify direct mapping of the children.
15
16- refclk-frequency: A single cell containing the reference clock
17 frequency in Hz.
18
19- refclk-type: A string describing the reference clock connection
20 either "crystal" or "external".
21
22Example:
23 uctl@118006f000000 {
24 compatible = "cavium,octeon-6335-uctl";
25 reg = <0x11800 0x6f000000 0x0 0x100>;
26 ranges; /* Direct mapping */
27 #address-cells = <2>;
28 #size-cells = <2>;
29 /* 12MHz, 24MHz and 48MHz allowed */
30 refclk-frequency = <24000000>;
31 /* Either "crystal" or "external" */
32 refclk-type = "crystal";
33
34 ehci@16f0000000000 {
35 compatible = "cavium,octeon-6335-ehci","usb-ehci";
36 reg = <0x16f00 0x00000000 0x0 0x100>;
37 interrupts = <0 56>;
38 big-endian-regs;
39 };
40 ohci@16f0000000400 {
41 compatible = "cavium,octeon-6335-ohci","usb-ohci";
42 reg = <0x16f00 0x00000400 0x0 0x100>;
43 interrupts = <0 56>;
44 big-endian-regs;
45 };
46 };
diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt
new file mode 100644
index 000000000000..04cb7491d232
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt
@@ -0,0 +1,27 @@
1* System Management Interface (SMI) / MDIO
2
3Properties:
4- compatible: "cavium,octeon-3860-mdio"
5
6 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
7
8- reg: The base address of the MDIO bus controller register bank.
9
10- #address-cells: Must be <1>.
11
12- #size-cells: Must be <0>. MDIO addresses have no size component.
13
14Typically an MDIO bus might have several children.
15
16Example:
17 mdio@1180000001800 {
18 compatible = "cavium,octeon-3860-mdio";
19 #address-cells = <1>;
20 #size-cells = <0>;
21 reg = <0x11800 0x00001800 0x0 0x40>;
22
23 ethernet-phy@0 {
24 ...
25 reg = <0>;
26 };
27 };
diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt
new file mode 100644
index 000000000000..5da628db68bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-mix.txt
@@ -0,0 +1,39 @@
1* MIX Ethernet controller.
2
3Properties:
4- compatible: "cavium,octeon-5750-mix"
5
6 Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
7 devices.
8
9- reg: The base addresses of four separate register banks. The first
10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
13 all MIX devices present.
14
15- cell-index: A single cell specifying which portion of the shared
16 register banks corresponds to this MIX device.
17
18- interrupts: Two interrupt specifiers. The first is the MIX
19 interrupt routing and the second the routing for the AGL interrupts.
20
21- mac-address: Optional, the MAC address to assign to the device.
22
23- local-mac-address: Optional, the MAC address to assign to the device
24 if mac-address is not specified.
25
26- phy-handle: Optional, a phandle for the PHY device connected to this device.
27
28Example:
29 ethernet@1070000100800 {
30 compatible = "cavium,octeon-5750-mix";
31 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
32 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
33 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
34 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
35 cell-index = <1>;
36 interrupts = <1 18>, < 1 46>;
37 local-mac-address = [ 00 0f b7 10 63 54 ];
38 phy-handle = <&phy1>;
39 };
diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt
new file mode 100644
index 000000000000..d4c53ba04b3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-pip.txt
@@ -0,0 +1,98 @@
1* PIP Ethernet nexus.
2
3The PIP Ethernet nexus can control several data packet input/output
4devices. The devices have a two level grouping scheme. There may be
5several interfaces, and each interface may have several ports. These
6ports might be an individual Ethernet PHY.
7
8
9Properties for the PIP nexus:
10- compatible: "cavium,octeon-3860-pip"
11
12 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
13
14- reg: The base address of the PIP's register bank.
15
16- #address-cells: Must be <1>.
17
18- #size-cells: Must be <0>.
19
20Properties for PIP interfaces which is a child the PIP nexus:
21- compatible: "cavium,octeon-3860-pip-interface"
22
23 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
24
25- reg: The interface number.
26
27- #address-cells: Must be <1>.
28
29- #size-cells: Must be <0>.
30
31Properties for PIP port which is a child the PIP interface:
32- compatible: "cavium,octeon-3860-pip-port"
33
34 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
35
36- reg: The port number within the interface group.
37
38- mac-address: Optional, the MAC address to assign to the device.
39
40- local-mac-address: Optional, the MAC address to assign to the device
41 if mac-address is not specified.
42
43- phy-handle: Optional, a phandle for the PHY device connected to this device.
44
45Example:
46
47 pip@11800a0000000 {
48 compatible = "cavium,octeon-3860-pip";
49 #address-cells = <1>;
50 #size-cells = <0>;
51 reg = <0x11800 0xa0000000 0x0 0x2000>;
52
53 interface@0 {
54 compatible = "cavium,octeon-3860-pip-interface";
55 #address-cells = <1>;
56 #size-cells = <0>;
57 reg = <0>; /* interface */
58
59 ethernet@0 {
60 compatible = "cavium,octeon-3860-pip-port";
61 reg = <0x0>; /* Port */
62 local-mac-address = [ 00 0f b7 10 63 60 ];
63 phy-handle = <&phy2>;
64 };
65 ethernet@1 {
66 compatible = "cavium,octeon-3860-pip-port";
67 reg = <0x1>; /* Port */
68 local-mac-address = [ 00 0f b7 10 63 61 ];
69 phy-handle = <&phy3>;
70 };
71 ethernet@2 {
72 compatible = "cavium,octeon-3860-pip-port";
73 reg = <0x2>; /* Port */
74 local-mac-address = [ 00 0f b7 10 63 62 ];
75 phy-handle = <&phy4>;
76 };
77 ethernet@3 {
78 compatible = "cavium,octeon-3860-pip-port";
79 reg = <0x3>; /* Port */
80 local-mac-address = [ 00 0f b7 10 63 63 ];
81 phy-handle = <&phy5>;
82 };
83 };
84
85 interface@1 {
86 compatible = "cavium,octeon-3860-pip-interface";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <1>; /* interface */
90
91 ethernet@0 {
92 compatible = "cavium,octeon-3860-pip-port";
93 reg = <0x0>; /* Port */
94 local-mac-address = [ 00 0f b7 10 63 64 ];
95 phy-handle = <&phy6>;
96 };
97 };
98 };
diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
new file mode 100644
index 000000000000..cfe1db3bb6e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
@@ -0,0 +1,12 @@
1LPC32XX PWM controller
2
3Required properties:
4- compatible: should be "nxp,lpc3220-pwm"
5- reg: physical base address and length of the controller's registers
6
7Examples:
8
9pwm@0x4005C000 {
10 compatible = "nxp,lpc3220-pwm";
11 reg = <0x4005C000 0x8>;
12};
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
new file mode 100644
index 000000000000..b16f4a57d111
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
@@ -0,0 +1,17 @@
1Freescale MXS PWM controller
2
3Required properties:
4- compatible: should be "fsl,imx23-pwm"
5- reg: physical base address and length of the controller's registers
6- #pwm-cells: should be 2. The first cell specifies the per-chip index
7 of the PWM to use and the second cell is the duty cycle in nanoseconds.
8- fsl,pwm-number: the number of PWM devices
9
10Example:
11
12pwm: pwm@80064000 {
13 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
14 reg = <0x80064000 2000>;
15 #pwm-cells = <2>;
16 fsl,pwm-number = <8>;
17};
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
new file mode 100644
index 000000000000..bbbeedb4ec05
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -0,0 +1,18 @@
1Tegra SoC PWFM controller
2
3Required properties:
4- compatible: should be one of:
5 - "nvidia,tegra20-pwm"
6 - "nvidia,tegra30-pwm"
7- reg: physical base address and length of the controller's registers
8- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
9 first cell specifies the per-chip index of the PWM to use and the second
10 cell is the duty cycle in nanoseconds.
11
12Example:
13
14 pwm: pwm@7000a000 {
15 compatible = "nvidia,tegra20-pwm";
16 reg = <0x7000a000 0x100>;
17 #pwm-cells = <2>;
18 };
diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt
new file mode 100644
index 000000000000..73ec962bfe8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm.txt
@@ -0,0 +1,57 @@
1Specifying PWM information for devices
2======================================
3
41) PWM user nodes
5-----------------
6
7PWM users should specify a list of PWM devices that they want to use
8with a property containing a 'pwm-list':
9
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
14 (controller specific)
15
16PWM properties should be named "pwms". The exact meaning of each pwms
17property must be documented in the device tree binding for each device.
18An optional property "pwm-names" may contain a list of strings to label
19each of the PWM devices listed in the "pwms" property. If no "pwm-names"
20property is given, the name of the user node will be used as fallback.
21
22Drivers for devices that use more than a single PWM device can use the
23"pwm-names" property to map the name of the PWM device requested by the
24pwm_get() call to an index into the list given by the "pwms" property.
25
26The following example could be used to describe a PWM-based backlight
27device:
28
29 pwm: pwm {
30 #pwm-cells = <2>;
31 };
32
33 [...]
34
35 bl: backlight {
36 pwms = <&pwm 0 5000000>;
37 pwm-names = "backlight";
38 };
39
40pwm-specifier typically encodes the chip-relative PWM number and the PWM
41period in nanoseconds. Note that in the example above, specifying the
42"pwm-names" is redundant because the name "backlight" would be used as
43fallback anyway.
44
452) PWM controller nodes
46-----------------------
47
48PWM controller nodes must specify the number of cells used for the
49specifier using the '#pwm-cells' property.
50
51An example PWM controller might look like this:
52
53 pwm: pwm@7000a000 {
54 compatible = "nvidia,tegra20-pwm";
55 reg = <0x7000a000 0x100>;
56 #pwm-cells = <2>;
57 };
diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt
new file mode 100644
index 000000000000..87a6c375cd44
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/cavium-uart.txt
@@ -0,0 +1,19 @@
1* Universal Asynchronous Receiver/Transmitter (UART)
2
3- compatible: "cavium,octeon-3860-uart"
4
5 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
6
7- reg: The base address of the UART register bank.
8
9- interrupts: A single interrupt specifier.
10
11- current-speed: Optional, the current bit rate in bits per second.
12
13Example:
14 uart1: serial@1180000000c00 {
15 compatible = "cavium,octeon-3860-uart","ns16550";
16 reg = <0x11800 0x00000c00 0x0 0x400>;
17 current-speed = <115200>;
18 interrupts = <0 35>;
19 };
diff --git a/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt b/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt
new file mode 100644
index 000000000000..1e4fc727f3b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt
@@ -0,0 +1,28 @@
1pwm-backlight bindings
2
3Required properties:
4 - compatible: "pwm-backlight"
5 - pwms: OF device-tree PWM specification (see PWM binding[0])
6 - brightness-levels: Array of distinct brightness levels. Typically these
7 are in the range from 0 to 255, but any range starting at 0 will do.
8 The actual brightness level (PWM duty cycle) will be interpolated
9 from these values. 0 means a 0% duty cycle (darkest/off), while the
10 last value in the array represents a 100% duty cycle (brightest).
11 - default-brightness-level: the default brightness level (index into the
12 array defined by the "brightness-levels" property)
13
14Optional properties:
15 - pwm-names: a list of names for the PWM devices specified in the
16 "pwms" property (see PWM binding[0])
17
18[0]: Documentation/devicetree/bindings/pwm/pwm.txt
19
20Example:
21
22 backlight {
23 compatible = "pwm-backlight";
24 pwms = <&pwm 0 5000000>;
25
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
28 };
diff --git a/Documentation/dontdiff b/Documentation/dontdiff
index b4a898f43c37..39462cf35cd4 100644
--- a/Documentation/dontdiff
+++ b/Documentation/dontdiff
@@ -150,7 +150,6 @@ keywords.c
150ksym.c* 150ksym.c*
151ksym.h* 151ksym.h*
152kxgettext 152kxgettext
153lkc_defs.h
154lex.c 153lex.c
155lex.*.c 154lex.*.c
156linux 155linux
diff --git a/Documentation/edac.txt b/Documentation/edac.txt
index 03df2b020332..56c7e936430f 100644
--- a/Documentation/edac.txt
+++ b/Documentation/edac.txt
@@ -232,116 +232,20 @@ EDAC control and attribute files.
232 232
233 233
234In 'mcX' directories are EDAC control and attribute files for 234In 'mcX' directories are EDAC control and attribute files for
235this 'X' instance of the memory controllers: 235this 'X' instance of the memory controllers.
236
237
238Counter reset control file:
239
240 'reset_counters'
241
242 This write-only control file will zero all the statistical counters
243 for UE and CE errors. Zeroing the counters will also reset the timer
244 indicating how long since the last counter zero. This is useful
245 for computing errors/time. Since the counters are always reset at
246 driver initialization time, no module/kernel parameter is available.
247
248 RUN TIME: echo "anything" >/sys/devices/system/edac/mc/mc0/counter_reset
249
250 This resets the counters on memory controller 0
251
252
253Seconds since last counter reset control file:
254
255 'seconds_since_reset'
256
257 This attribute file displays how many seconds have elapsed since the
258 last counter reset. This can be used with the error counters to
259 measure error rates.
260
261
262
263Memory Controller name attribute file:
264
265 'mc_name'
266
267 This attribute file displays the type of memory controller
268 that is being utilized.
269
270
271Total memory managed by this memory controller attribute file:
272
273 'size_mb'
274
275 This attribute file displays, in count of megabytes, of memory
276 that this instance of memory controller manages.
277
278
279Total Uncorrectable Errors count attribute file:
280
281 'ue_count'
282
283 This attribute file displays the total count of uncorrectable
284 errors that have occurred on this memory controller. If panic_on_ue
285 is set this counter will not have a chance to increment,
286 since EDAC will panic the system.
287
288
289Total UE count that had no information attribute fileY:
290
291 'ue_noinfo_count'
292
293 This attribute file displays the number of UEs that have occurred
294 with no information as to which DIMM slot is having errors.
295
296
297Total Correctable Errors count attribute file:
298
299 'ce_count'
300
301 This attribute file displays the total count of correctable
302 errors that have occurred on this memory controller. This
303 count is very important to examine. CEs provide early
304 indications that a DIMM is beginning to fail. This count
305 field should be monitored for non-zero values and report
306 such information to the system administrator.
307
308
309Total Correctable Errors count attribute file:
310
311 'ce_noinfo_count'
312
313 This attribute file displays the number of CEs that
314 have occurred wherewith no information as to which DIMM slot
315 is having errors. Memory is handicapped, but operational,
316 yet no information is available to indicate which slot
317 the failing memory is in. This count field should be also
318 be monitored for non-zero values.
319
320Device Symlink:
321
322 'device'
323
324 Symlink to the memory controller device.
325
326Sdram memory scrubbing rate:
327
328 'sdram_scrub_rate'
329
330 Read/Write attribute file that controls memory scrubbing. The scrubbing
331 rate is set by writing a minimum bandwidth in bytes/sec to the attribute
332 file. The rate will be translated to an internal value that gives at
333 least the specified rate.
334
335 Reading the file will return the actual scrubbing rate employed.
336
337 If configuration fails or memory scrubbing is not implemented, accessing
338 that attribute will fail.
339 236
237For a description of the sysfs API, please see:
238 Documentation/ABI/testing/sysfs/devices-edac
340 239
341 240
342============================================================================ 241============================================================================
343'csrowX' DIRECTORIES 242'csrowX' DIRECTORIES
344 243
244When CONFIG_EDAC_LEGACY_SYSFS is enabled, the sysfs will contain the
245csrowX directories. As this API doesn't work properly for Rambus, FB-DIMMs
246and modern Intel Memory Controllers, this is being deprecated in favor
247of dimmX directories.
248
345In the 'csrowX' directories are EDAC control and attribute files for 249In the 'csrowX' directories are EDAC control and attribute files for
346this 'X' instance of csrow: 250this 'X' instance of csrow:
347 251
diff --git a/Documentation/input/edt-ft5x06.txt b/Documentation/input/edt-ft5x06.txt
new file mode 100644
index 000000000000..2032f0b7a8fa
--- /dev/null
+++ b/Documentation/input/edt-ft5x06.txt
@@ -0,0 +1,54 @@
1EDT ft5x06 based Polytouch devices
2----------------------------------
3
4The edt-ft5x06 driver is useful for the EDT "Polytouch" family of capacitive
5touch screens. Note that it is *not* suitable for other devices based on the
6focaltec ft5x06 devices, since they contain vendor-specific firmware. In
7particular this driver is not suitable for the Nook tablet.
8
9It has been tested with the following devices:
10 * EP0350M06
11 * EP0430M06
12 * EP0570M06
13 * EP0700M06
14
15The driver allows configuration of the touch screen via a set of sysfs files:
16
17/sys/class/input/eventX/device/device/threshold:
18 allows setting the "click"-threshold in the range from 20 to 80.
19
20/sys/class/input/eventX/device/device/gain:
21 allows setting the sensitivity in the range from 0 to 31. Note that
22 lower values indicate higher sensitivity.
23
24/sys/class/input/eventX/device/device/offset:
25 allows setting the edge compensation in the range from 0 to 31.
26
27/sys/class/input/eventX/device/device/report_rate:
28 allows setting the report rate in the range from 3 to 14.
29
30
31For debugging purposes the driver provides a few files in the debug
32filesystem (if available in the kernel). In /sys/kernel/debug/edt_ft5x06
33you'll find the following files:
34
35num_x, num_y:
36 (readonly) contains the number of sensor fields in X- and
37 Y-direction.
38
39mode:
40 allows switching the sensor between "factory mode" and "operation
41 mode" by writing "1" or "0" to it. In factory mode (1) it is
42 possible to get the raw data from the sensor. Note that in factory
43 mode regular events don't get delivered and the options described
44 above are unavailable.
45
46raw_data:
47 contains num_x * num_y big endian 16 bit values describing the raw
48 values for each sensor field. Note that each read() call on this
49 files triggers a new readout. It is recommended to provide a buffer
50 big enough to contain num_x * num_y * 2 bytes.
51
52Note that reading raw_data gives a I/O error when the device is not in factory
53mode. The same happens when reading/writing to the parameter files when the
54device is not in regular operation mode.
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c2619ef44a72..ad7e2e5088c1 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -526,7 +526,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
526 526
527 coherent_pool=nn[KMG] [ARM,KNL] 527 coherent_pool=nn[KMG] [ARM,KNL]
528 Sets the size of memory pool for coherent, atomic dma 528 Sets the size of memory pool for coherent, atomic dma
529 allocations if Contiguous Memory Allocator (CMA) is used. 529 allocations, by default set to 256K.
530 530
531 code_bytes [X86] How many bytes of object code to print 531 code_bytes [X86] How many bytes of object code to print
532 in an oops report. 532 in an oops report.
diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
new file mode 100644
index 000000000000..554290ebab94
--- /dev/null
+++ b/Documentation/pwm.txt
@@ -0,0 +1,76 @@
1Pulse Width Modulation (PWM) interface
2
3This provides an overview about the Linux PWM interface
4
5PWMs are commonly used for controlling LEDs, fans or vibrators in
6cell phones. PWMs with a fixed purpose have no need implementing
7the Linux PWM API (although they could). However, PWMs are often
8found as discrete devices on SoCs which have no fixed purpose. It's
9up to the board designer to connect them to LEDs or fans. To provide
10this kind of flexibility the generic PWM API exists.
11
12Identifying PWMs
13----------------
14
15Users of the legacy PWM API use unique IDs to refer to PWM devices.
16
17Instead of referring to a PWM device via its unique ID, board setup code
18should instead register a static mapping that can be used to match PWM
19consumers to providers, as given in the following example:
20
21 static struct pwm_lookup board_pwm_lookup[] = {
22 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL),
23 };
24
25 static void __init board_init(void)
26 {
27 ...
28 pwm_add_table(board_pwm_lookup, ARRAY_SIZE(board_pwm_lookup));
29 ...
30 }
31
32Using PWMs
33----------
34
35Legacy users can request a PWM device using pwm_request() and free it
36after usage with pwm_free().
37
38New users should use the pwm_get() function and pass to it the consumer
39device or a consumer name. pwm_put() is used to free the PWM device.
40
41After being requested a PWM has to be configured using:
42
43int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
44
45To start/stop toggling the PWM output use pwm_enable()/pwm_disable().
46
47Implementing a PWM driver
48-------------------------
49
50Currently there are two ways to implement pwm drivers. Traditionally
51there only has been the barebone API meaning that each driver has
52to implement the pwm_*() functions itself. This means that it's impossible
53to have multiple PWM drivers in the system. For this reason it's mandatory
54for new drivers to use the generic PWM framework.
55
56A new PWM controller/chip can be added using pwmchip_add() and removed
57again with pwmchip_remove(). pwmchip_add() takes a filled in struct
58pwm_chip as argument which provides a description of the PWM chip, the
59number of PWM devices provider by the chip and the chip-specific
60implementation of the supported PWM operations to the framework.
61
62Locking
63-------
64
65The PWM core list manipulations are protected by a mutex, so pwm_request()
66and pwm_free() may not be called from an atomic context. Currently the
67PWM core does not enforce any locking to pwm_enable(), pwm_disable() and
68pwm_config(), so the calling context is currently driver specific. This
69is an issue derived from the former barebone API and should be fixed soon.
70
71Helpers
72-------
73
74Currently a PWM can only be configured with period_ns and duty_ns. For several
75use cases freq_hz and duty_percent might be better. Instead of calculating
76this in your driver please consider adding appropriate helpers to the framework.
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 04:27:57 -0500