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-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt22
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c16
2 files changed, 19 insertions, 19 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index b23cfbdbcd6d..20b8479c2760 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -6,14 +6,14 @@ This binding uses the common clock binding[1].
6 6
7Required properties: 7Required properties:
8- compatible : shall be one of the following: 8- compatible : shall be one of the following:
9 "allwinner,sunxi-osc-clk" - for a gatable oscillator 9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sunxi-pll1-clk" - for the main PLL clock 10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock 11 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
12 "allwinner,sunxi-axi-clk" - for the sunxi AXI clock 12 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sunxi-ahb-clk" - for the sunxi AHB clock 13 "allwinner,sun4i-ahb-clk" - for the AHB clock
14 "allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock 14 "allwinner,sun4i-apb0-clk" - for the APB0 clock
15 "allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock 15 "allwinner,sun4i-apb1-clk" - for the APB1 clock
16 "allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing 16 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
17 17
18Required properties for all clocks: 18Required properties for all clocks:
19- reg : shall be the control register address for the clock. 19- reg : shall be the control register address for the clock.
@@ -24,21 +24,21 @@ For example:
24 24
25osc24M: osc24M@01c20050 { 25osc24M: osc24M@01c20050 {
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 compatible = "allwinner,sunxi-osc-clk"; 27 compatible = "allwinner,sun4i-osc-clk";
28 reg = <0x01c20050 0x4>; 28 reg = <0x01c20050 0x4>;
29 clocks = <&osc24M_fixed>; 29 clocks = <&osc24M_fixed>;
30}; 30};
31 31
32pll1: pll1@01c20000 { 32pll1: pll1@01c20000 {
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 compatible = "allwinner,sunxi-pll1-clk"; 34 compatible = "allwinner,sun4i-pll1-clk";
35 reg = <0x01c20000 0x4>; 35 reg = <0x01c20000 0x4>;
36 clocks = <&osc24M>; 36 clocks = <&osc24M>;
37}; 37};
38 38
39cpu: cpu@01c20054 { 39cpu: cpu@01c20054 {
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 compatible = "allwinner,sunxi-cpu-clk"; 41 compatible = "allwinner,sun4i-cpu-clk";
42 reg = <0x01c20054 0x4>; 42 reg = <0x01c20054 0x4>;
43 clocks = <&osc32k>, <&osc24M>, <&pll1>; 43 clocks = <&osc32k>, <&osc24M>, <&pll1>;
44}; 44};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index d4ad1c22859e..d528a2496690 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -305,29 +305,29 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
305/* Matches for of_clk_init */ 305/* Matches for of_clk_init */
306static const __initconst struct of_device_id clk_match[] = { 306static const __initconst struct of_device_id clk_match[] = {
307 {.compatible = "fixed-clock", .data = of_fixed_clk_setup,}, 307 {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
308 {.compatible = "allwinner,sunxi-osc-clk", .data = sunxi_osc_clk_setup,}, 308 {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
309 {} 309 {}
310}; 310};
311 311
312/* Matches for factors clocks */ 312/* Matches for factors clocks */
313static const __initconst struct of_device_id clk_factors_match[] = { 313static const __initconst struct of_device_id clk_factors_match[] = {
314 {.compatible = "allwinner,sunxi-pll1-clk", .data = &pll1_data,}, 314 {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,},
315 {.compatible = "allwinner,sunxi-apb1-clk", .data = &apb1_data,}, 315 {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,},
316 {} 316 {}
317}; 317};
318 318
319/* Matches for divider clocks */ 319/* Matches for divider clocks */
320static const __initconst struct of_device_id clk_div_match[] = { 320static const __initconst struct of_device_id clk_div_match[] = {
321 {.compatible = "allwinner,sunxi-axi-clk", .data = &axi_data,}, 321 {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,},
322 {.compatible = "allwinner,sunxi-ahb-clk", .data = &ahb_data,}, 322 {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,},
323 {.compatible = "allwinner,sunxi-apb0-clk", .data = &apb0_data,}, 323 {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,},
324 {} 324 {}
325}; 325};
326 326
327/* Matches for mux clocks */ 327/* Matches for mux clocks */
328static const __initconst struct of_device_id clk_mux_match[] = { 328static const __initconst struct of_device_id clk_mux_match[] = {
329 {.compatible = "allwinner,sunxi-cpu-clk", .data = &cpu_data,}, 329 {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_data,},
330 {.compatible = "allwinner,sunxi-apb1-mux-clk", .data = &apb1_mux_data,}, 330 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
331 {} 331 {}
332}; 332};
333 333