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-rw-r--r--MAINTAINERS3
-rw-r--r--arch/arm/configs/ap4evb_defconfig71
-rw-r--r--arch/arm/configs/g3evm_defconfig73
-rw-r--r--arch/arm/configs/g4evm_defconfig72
-rw-r--r--arch/arm/mach-shmobile/Kconfig13
-rw-r--r--arch/arm/mach-shmobile/Makefile6
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c248
-rw-r--r--arch/arm/mach-shmobile/board-g3evm.c56
-rw-r--r--arch/arm/mach-shmobile/board-g4evm.c151
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c357
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c395
-rw-r--r--arch/arm/mach-shmobile/clock-sh7377.c369
-rw-r--r--arch/arm/mach-shmobile/clock.c44
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h10
-rw-r--r--arch/arm/mach-shmobile/include/mach/irqs.h6
-rw-r--r--arch/arm/mach-shmobile/include/mach/memory.h3
-rw-r--r--arch/arm/mach-shmobile/include/mach/vmalloc.h3
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c178
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c232
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c300
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c30
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c98
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c34
-rw-r--r--drivers/dma/Kconfig2
-rw-r--r--drivers/dma/shdma.c8
-rw-r--r--drivers/i2c/busses/Kconfig2
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c121
-rw-r--r--drivers/serial/sh-sci.c42
-rw-r--r--drivers/serial/sh-sci.h29
-rw-r--r--drivers/sh/Makefile5
-rw-r--r--drivers/video/Kconfig8
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/sh_mipi_dsi.c505
-rw-r--r--include/linux/serial_core.h3
-rw-r--r--include/linux/serial_sci.h2
-rw-r--r--include/video/mipi_display.h130
-rw-r--r--include/video/sh_mipi_dsi.h35
-rw-r--r--include/video/sh_mobile_lcdc.h39
38 files changed, 3435 insertions, 249 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 13608bd2e791..25b4159fa132 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -948,8 +948,9 @@ ARM/SHMOBILE ARM ARCHITECTURE
948M: Paul Mundt <lethal@linux-sh.org> 948M: Paul Mundt <lethal@linux-sh.org>
949M: Magnus Damm <magnus.damm@gmail.com> 949M: Magnus Damm <magnus.damm@gmail.com>
950L: linux-sh@vger.kernel.org 950L: linux-sh@vger.kernel.org
951T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
952W: http://oss.renesas.com 951W: http://oss.renesas.com
952Q: http://patchwork.kernel.org/project/linux-sh/list/
953T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
953S: Supported 954S: Supported
954F: arch/arm/mach-shmobile/ 955F: arch/arm/mach-shmobile/
955F: drivers/sh/ 956F: drivers/sh/
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
index e14229be7676..eb38098545d3 100644
--- a/arch/arm/configs/ap4evb_defconfig
+++ b/arch/arm/configs/ap4evb_defconfig
@@ -1,12 +1,15 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.33-rc7 3# Linux kernel version: 2.6.34
4# Mon Feb 8 12:25:36 2010 4# Thu May 20 12:18:56 2010
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
8CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
9CONFIG_GENERIC_CLOCKEVENTS=y 11CONFIG_GENERIC_CLOCKEVENTS=y
12CONFIG_HAVE_PROC_CPU=y
10CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
11CONFIG_STACKTRACE_SUPPORT=y 14CONFIG_STACKTRACE_SUPPORT=y
12CONFIG_HAVE_LATENCYTOP_SUPPORT=y 15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
17CONFIG_RWSEM_GENERIC_SPINLOCK=y 20CONFIG_RWSEM_GENERIC_SPINLOCK=y
18CONFIG_GENERIC_HWEIGHT=y 21CONFIG_GENERIC_HWEIGHT=y
19CONFIG_GENERIC_CALIBRATE_DELAY=y 22CONFIG_GENERIC_CALIBRATE_DELAY=y
23CONFIG_NEED_DMA_MAP_STATE=y
20CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
21CONFIG_VECTORS_BASE=0xffff0000 25CONFIG_VECTORS_BASE=0xffff0000
22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -31,6 +35,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
31CONFIG_LOCALVERSION="" 35CONFIG_LOCALVERSION=""
32CONFIG_LOCALVERSION_AUTO=y 36CONFIG_LOCALVERSION_AUTO=y
33CONFIG_HAVE_KERNEL_GZIP=y 37CONFIG_HAVE_KERNEL_GZIP=y
38CONFIG_HAVE_KERNEL_LZMA=y
34CONFIG_HAVE_KERNEL_LZO=y 39CONFIG_HAVE_KERNEL_LZO=y
35CONFIG_KERNEL_GZIP=y 40CONFIG_KERNEL_GZIP=y
36# CONFIG_KERNEL_BZIP2 is not set 41# CONFIG_KERNEL_BZIP2 is not set
@@ -54,11 +59,6 @@ CONFIG_RCU_FANOUT=32
54CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
55CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
56CONFIG_LOG_BUF_SHIFT=16 61CONFIG_LOG_BUF_SHIFT=16
57CONFIG_GROUP_SCHED=y
58CONFIG_FAIR_GROUP_SCHED=y
59# CONFIG_RT_GROUP_SCHED is not set
60CONFIG_USER_SCHED=y
61# CONFIG_CGROUP_SCHED is not set
62# CONFIG_CGROUPS is not set 62# CONFIG_CGROUPS is not set
63# CONFIG_SYSFS_DEPRECATED_V2 is not set 63# CONFIG_SYSFS_DEPRECATED_V2 is not set
64# CONFIG_RELAY is not set 64# CONFIG_RELAY is not set
@@ -94,10 +94,14 @@ CONFIG_TIMERFD=y
94CONFIG_EVENTFD=y 94CONFIG_EVENTFD=y
95CONFIG_SHMEM=y 95CONFIG_SHMEM=y
96CONFIG_AIO=y 96CONFIG_AIO=y
97CONFIG_HAVE_PERF_EVENTS=y
98CONFIG_PERF_USE_VMALLOC=y
97 99
98# 100#
99# Kernel Performance Events And Counters 101# Kernel Performance Events And Counters
100# 102#
103# CONFIG_PERF_EVENTS is not set
104# CONFIG_PERF_COUNTERS is not set
101CONFIG_VM_EVENT_COUNTERS=y 105CONFIG_VM_EVENT_COUNTERS=y
102CONFIG_COMPAT_BRK=y 106CONFIG_COMPAT_BRK=y
103CONFIG_SLAB=y 107CONFIG_SLAB=y
@@ -172,8 +176,11 @@ CONFIG_MMU=y
172# CONFIG_ARCH_INTEGRATOR is not set 176# CONFIG_ARCH_INTEGRATOR is not set
173# CONFIG_ARCH_REALVIEW is not set 177# CONFIG_ARCH_REALVIEW is not set
174# CONFIG_ARCH_VERSATILE is not set 178# CONFIG_ARCH_VERSATILE is not set
179# CONFIG_ARCH_VEXPRESS is not set
175# CONFIG_ARCH_AT91 is not set 180# CONFIG_ARCH_AT91 is not set
181# CONFIG_ARCH_BCMRING is not set
176# CONFIG_ARCH_CLPS711X is not set 182# CONFIG_ARCH_CLPS711X is not set
183# CONFIG_ARCH_CNS3XXX is not set
177# CONFIG_ARCH_GEMINI is not set 184# CONFIG_ARCH_GEMINI is not set
178# CONFIG_ARCH_EBSA110 is not set 185# CONFIG_ARCH_EBSA110 is not set
179# CONFIG_ARCH_EP93XX is not set 186# CONFIG_ARCH_EP93XX is not set
@@ -182,7 +189,6 @@ CONFIG_MMU=y
182# CONFIG_ARCH_STMP3XXX is not set 189# CONFIG_ARCH_STMP3XXX is not set
183# CONFIG_ARCH_NETX is not set 190# CONFIG_ARCH_NETX is not set
184# CONFIG_ARCH_H720X is not set 191# CONFIG_ARCH_H720X is not set
185# CONFIG_ARCH_NOMADIK is not set
186# CONFIG_ARCH_IOP13XX is not set 192# CONFIG_ARCH_IOP13XX is not set
187# CONFIG_ARCH_IOP32X is not set 193# CONFIG_ARCH_IOP32X is not set
188# CONFIG_ARCH_IOP33X is not set 194# CONFIG_ARCH_IOP33X is not set
@@ -199,6 +205,7 @@ CONFIG_MMU=y
199# CONFIG_ARCH_KS8695 is not set 205# CONFIG_ARCH_KS8695 is not set
200# CONFIG_ARCH_NS9XXX is not set 206# CONFIG_ARCH_NS9XXX is not set
201# CONFIG_ARCH_W90X900 is not set 207# CONFIG_ARCH_W90X900 is not set
208# CONFIG_ARCH_NUC93X is not set
202# CONFIG_ARCH_PNX4008 is not set 209# CONFIG_ARCH_PNX4008 is not set
203# CONFIG_ARCH_PXA is not set 210# CONFIG_ARCH_PXA is not set
204# CONFIG_ARCH_MSM is not set 211# CONFIG_ARCH_MSM is not set
@@ -207,14 +214,18 @@ CONFIG_ARCH_SHMOBILE=y
207# CONFIG_ARCH_SA1100 is not set 214# CONFIG_ARCH_SA1100 is not set
208# CONFIG_ARCH_S3C2410 is not set 215# CONFIG_ARCH_S3C2410 is not set
209# CONFIG_ARCH_S3C64XX is not set 216# CONFIG_ARCH_S3C64XX is not set
217# CONFIG_ARCH_S5P6440 is not set
218# CONFIG_ARCH_S5P6442 is not set
210# CONFIG_ARCH_S5PC1XX is not set 219# CONFIG_ARCH_S5PC1XX is not set
220# CONFIG_ARCH_S5PV210 is not set
211# CONFIG_ARCH_SHARK is not set 221# CONFIG_ARCH_SHARK is not set
212# CONFIG_ARCH_LH7A40X is not set 222# CONFIG_ARCH_LH7A40X is not set
213# CONFIG_ARCH_U300 is not set 223# CONFIG_ARCH_U300 is not set
224# CONFIG_ARCH_U8500 is not set
225# CONFIG_ARCH_NOMADIK is not set
214# CONFIG_ARCH_DAVINCI is not set 226# CONFIG_ARCH_DAVINCI is not set
215# CONFIG_ARCH_OMAP is not set 227# CONFIG_ARCH_OMAP is not set
216# CONFIG_ARCH_BCMRING is not set 228# CONFIG_PLAT_SPEAR is not set
217# CONFIG_ARCH_U8500 is not set
218 229
219# 230#
220# SH-Mobile System Type 231# SH-Mobile System Type
@@ -242,6 +253,8 @@ CONFIG_MEMORY_SIZE=0x10000000
242# Timer and clock configuration 253# Timer and clock configuration
243# 254#
244CONFIG_SH_TIMER_CMT=y 255CONFIG_SH_TIMER_CMT=y
256CONFIG_SH_TIMER_TMU=y
257CONFIG_SH_CLK_CPG=y
245 258
246# 259#
247# Processor Type 260# Processor Type
@@ -269,6 +282,8 @@ CONFIG_ARM_THUMB=y
269# CONFIG_CPU_BPREDICT_DISABLE is not set 282# CONFIG_CPU_BPREDICT_DISABLE is not set
270CONFIG_HAS_TLS_REG=y 283CONFIG_HAS_TLS_REG=y
271CONFIG_ARM_L1_CACHE_SHIFT=5 284CONFIG_ARM_L1_CACHE_SHIFT=5
285CONFIG_ARM_DMA_MEM_BUFFERABLE=y
286CONFIG_CPU_HAS_PMU=y
272# CONFIG_ARM_ERRATA_430973 is not set 287# CONFIG_ARM_ERRATA_430973 is not set
273# CONFIG_ARM_ERRATA_458693 is not set 288# CONFIG_ARM_ERRATA_458693 is not set
274# CONFIG_ARM_ERRATA_460075 is not set 289# CONFIG_ARM_ERRATA_460075 is not set
@@ -322,7 +337,7 @@ CONFIG_ALIGNMENT_TRAP=y
322# 337#
323CONFIG_ZBOOT_ROM_TEXT=0x0 338CONFIG_ZBOOT_ROM_TEXT=0x0
324CONFIG_ZBOOT_ROM_BSS=0x0 339CONFIG_ZBOOT_ROM_BSS=0x0
325CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200" 340CONFIG_CMDLINE="console=ttySC0,115200"
326# CONFIG_XIP_KERNEL is not set 341# CONFIG_XIP_KERNEL is not set
327CONFIG_KEXEC=y 342CONFIG_KEXEC=y
328CONFIG_ATAGS_PROC=y 343CONFIG_ATAGS_PROC=y
@@ -452,10 +467,12 @@ CONFIG_MTD_NAND=y
452# CONFIG_MTD_NAND_VERIFY_WRITE is not set 467# CONFIG_MTD_NAND_VERIFY_WRITE is not set
453# CONFIG_MTD_NAND_ECC_SMC is not set 468# CONFIG_MTD_NAND_ECC_SMC is not set
454# CONFIG_MTD_NAND_MUSEUM_IDS is not set 469# CONFIG_MTD_NAND_MUSEUM_IDS is not set
470# CONFIG_MTD_NAND_GPIO is not set
455CONFIG_MTD_NAND_IDS=y 471CONFIG_MTD_NAND_IDS=y
456# CONFIG_MTD_NAND_DISKONCHIP is not set 472# CONFIG_MTD_NAND_DISKONCHIP is not set
457# CONFIG_MTD_NAND_NANDSIM is not set 473# CONFIG_MTD_NAND_NANDSIM is not set
458# CONFIG_MTD_NAND_PLATFORM is not set 474# CONFIG_MTD_NAND_PLATFORM is not set
475# CONFIG_MTD_NAND_SH_FLCTL is not set
459# CONFIG_MTD_ONENAND is not set 476# CONFIG_MTD_ONENAND is not set
460 477
461# 478#
@@ -476,6 +493,7 @@ CONFIG_HAVE_IDE=y
476# 493#
477# SCSI device support 494# SCSI device support
478# 495#
496CONFIG_SCSI_MOD=y
479# CONFIG_RAID_ATTRS is not set 497# CONFIG_RAID_ATTRS is not set
480# CONFIG_SCSI is not set 498# CONFIG_SCSI is not set
481# CONFIG_SCSI_DMA is not set 499# CONFIG_SCSI_DMA is not set
@@ -543,6 +561,7 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
543CONFIG_SERIAL_SH_SCI_CONSOLE=y 561CONFIG_SERIAL_SH_SCI_CONSOLE=y
544CONFIG_SERIAL_CORE=y 562CONFIG_SERIAL_CORE=y
545CONFIG_SERIAL_CORE_CONSOLE=y 563CONFIG_SERIAL_CORE_CONSOLE=y
564# CONFIG_SERIAL_TIMBERDALE is not set
546CONFIG_UNIX98_PTYS=y 565CONFIG_UNIX98_PTYS=y
547# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 566# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
548# CONFIG_LEGACY_PTYS is not set 567# CONFIG_LEGACY_PTYS is not set
@@ -558,6 +577,31 @@ CONFIG_UNIX98_PTYS=y
558# PPS support 577# PPS support
559# 578#
560# CONFIG_PPS is not set 579# CONFIG_PPS is not set
580CONFIG_ARCH_REQUIRE_GPIOLIB=y
581CONFIG_GPIOLIB=y
582# CONFIG_DEBUG_GPIO is not set
583# CONFIG_GPIO_SYSFS is not set
584
585#
586# Memory mapped GPIO expanders:
587#
588# CONFIG_GPIO_IT8761E is not set
589
590#
591# I2C GPIO expanders:
592#
593
594#
595# PCI GPIO expanders:
596#
597
598#
599# SPI GPIO expanders:
600#
601
602#
603# AC97 GPIO expanders:
604#
561# CONFIG_W1 is not set 605# CONFIG_W1 is not set
562# CONFIG_POWER_SUPPLY is not set 606# CONFIG_POWER_SUPPLY is not set
563# CONFIG_HWMON is not set 607# CONFIG_HWMON is not set
@@ -575,10 +619,14 @@ CONFIG_SSB_POSSIBLE=y
575# 619#
576# CONFIG_MFD_CORE is not set 620# CONFIG_MFD_CORE is not set
577# CONFIG_MFD_SM501 is not set 621# CONFIG_MFD_SM501 is not set
622# CONFIG_MFD_ASIC3 is not set
623# CONFIG_MFD_SH_MOBILE_SDHI is not set
624# CONFIG_HTC_EGPIO is not set
578# CONFIG_HTC_PASIC3 is not set 625# CONFIG_HTC_PASIC3 is not set
579# CONFIG_MFD_TMIO is not set 626# CONFIG_MFD_TMIO is not set
580# CONFIG_MFD_T7L66XB is not set 627# CONFIG_MFD_T7L66XB is not set
581# CONFIG_MFD_TC6387XB is not set 628# CONFIG_MFD_TC6387XB is not set
629# CONFIG_MFD_TC6393XB is not set
582# CONFIG_REGULATOR is not set 630# CONFIG_REGULATOR is not set
583# CONFIG_MEDIA_SUPPORT is not set 631# CONFIG_MEDIA_SUPPORT is not set
584 632
@@ -733,6 +781,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
733CONFIG_HAVE_FUNCTION_TRACER=y 781CONFIG_HAVE_FUNCTION_TRACER=y
734CONFIG_TRACING_SUPPORT=y 782CONFIG_TRACING_SUPPORT=y
735# CONFIG_FTRACE is not set 783# CONFIG_FTRACE is not set
784# CONFIG_ATOMIC64_SELFTEST is not set
736# CONFIG_SAMPLES is not set 785# CONFIG_SAMPLES is not set
737CONFIG_HAVE_ARCH_KGDB=y 786CONFIG_HAVE_ARCH_KGDB=y
738# CONFIG_KGDB is not set 787# CONFIG_KGDB is not set
diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig
index 3c19031961db..549e46064a29 100644
--- a/arch/arm/configs/g3evm_defconfig
+++ b/arch/arm/configs/g3evm_defconfig
@@ -1,12 +1,15 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.33-rc7 3# Linux kernel version: 2.6.34
4# Mon Feb 8 12:20:01 2010 4# Thu May 20 12:21:19 2010
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
8CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
9CONFIG_GENERIC_CLOCKEVENTS=y 11CONFIG_GENERIC_CLOCKEVENTS=y
12CONFIG_HAVE_PROC_CPU=y
10CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
11CONFIG_STACKTRACE_SUPPORT=y 14CONFIG_STACKTRACE_SUPPORT=y
12CONFIG_HAVE_LATENCYTOP_SUPPORT=y 15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
17CONFIG_RWSEM_GENERIC_SPINLOCK=y 20CONFIG_RWSEM_GENERIC_SPINLOCK=y
18CONFIG_GENERIC_HWEIGHT=y 21CONFIG_GENERIC_HWEIGHT=y
19CONFIG_GENERIC_CALIBRATE_DELAY=y 22CONFIG_GENERIC_CALIBRATE_DELAY=y
23CONFIG_NEED_DMA_MAP_STATE=y
20CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
21CONFIG_VECTORS_BASE=0xffff0000 25CONFIG_VECTORS_BASE=0xffff0000
22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -31,6 +35,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
31CONFIG_LOCALVERSION="" 35CONFIG_LOCALVERSION=""
32CONFIG_LOCALVERSION_AUTO=y 36CONFIG_LOCALVERSION_AUTO=y
33CONFIG_HAVE_KERNEL_GZIP=y 37CONFIG_HAVE_KERNEL_GZIP=y
38CONFIG_HAVE_KERNEL_LZMA=y
34CONFIG_HAVE_KERNEL_LZO=y 39CONFIG_HAVE_KERNEL_LZO=y
35CONFIG_KERNEL_GZIP=y 40CONFIG_KERNEL_GZIP=y
36# CONFIG_KERNEL_BZIP2 is not set 41# CONFIG_KERNEL_BZIP2 is not set
@@ -54,11 +59,6 @@ CONFIG_RCU_FANOUT=32
54CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
55CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
56CONFIG_LOG_BUF_SHIFT=16 61CONFIG_LOG_BUF_SHIFT=16
57CONFIG_GROUP_SCHED=y
58CONFIG_FAIR_GROUP_SCHED=y
59# CONFIG_RT_GROUP_SCHED is not set
60CONFIG_USER_SCHED=y
61# CONFIG_CGROUP_SCHED is not set
62# CONFIG_CGROUPS is not set 62# CONFIG_CGROUPS is not set
63# CONFIG_SYSFS_DEPRECATED_V2 is not set 63# CONFIG_SYSFS_DEPRECATED_V2 is not set
64# CONFIG_RELAY is not set 64# CONFIG_RELAY is not set
@@ -94,10 +94,14 @@ CONFIG_TIMERFD=y
94CONFIG_EVENTFD=y 94CONFIG_EVENTFD=y
95CONFIG_SHMEM=y 95CONFIG_SHMEM=y
96CONFIG_AIO=y 96CONFIG_AIO=y
97CONFIG_HAVE_PERF_EVENTS=y
98CONFIG_PERF_USE_VMALLOC=y
97 99
98# 100#
99# Kernel Performance Events And Counters 101# Kernel Performance Events And Counters
100# 102#
103# CONFIG_PERF_EVENTS is not set
104# CONFIG_PERF_COUNTERS is not set
101CONFIG_VM_EVENT_COUNTERS=y 105CONFIG_VM_EVENT_COUNTERS=y
102CONFIG_COMPAT_BRK=y 106CONFIG_COMPAT_BRK=y
103CONFIG_SLAB=y 107CONFIG_SLAB=y
@@ -172,8 +176,11 @@ CONFIG_MMU=y
172# CONFIG_ARCH_INTEGRATOR is not set 176# CONFIG_ARCH_INTEGRATOR is not set
173# CONFIG_ARCH_REALVIEW is not set 177# CONFIG_ARCH_REALVIEW is not set
174# CONFIG_ARCH_VERSATILE is not set 178# CONFIG_ARCH_VERSATILE is not set
179# CONFIG_ARCH_VEXPRESS is not set
175# CONFIG_ARCH_AT91 is not set 180# CONFIG_ARCH_AT91 is not set
181# CONFIG_ARCH_BCMRING is not set
176# CONFIG_ARCH_CLPS711X is not set 182# CONFIG_ARCH_CLPS711X is not set
183# CONFIG_ARCH_CNS3XXX is not set
177# CONFIG_ARCH_GEMINI is not set 184# CONFIG_ARCH_GEMINI is not set
178# CONFIG_ARCH_EBSA110 is not set 185# CONFIG_ARCH_EBSA110 is not set
179# CONFIG_ARCH_EP93XX is not set 186# CONFIG_ARCH_EP93XX is not set
@@ -182,7 +189,6 @@ CONFIG_MMU=y
182# CONFIG_ARCH_STMP3XXX is not set 189# CONFIG_ARCH_STMP3XXX is not set
183# CONFIG_ARCH_NETX is not set 190# CONFIG_ARCH_NETX is not set
184# CONFIG_ARCH_H720X is not set 191# CONFIG_ARCH_H720X is not set
185# CONFIG_ARCH_NOMADIK is not set
186# CONFIG_ARCH_IOP13XX is not set 192# CONFIG_ARCH_IOP13XX is not set
187# CONFIG_ARCH_IOP32X is not set 193# CONFIG_ARCH_IOP32X is not set
188# CONFIG_ARCH_IOP33X is not set 194# CONFIG_ARCH_IOP33X is not set
@@ -199,6 +205,7 @@ CONFIG_MMU=y
199# CONFIG_ARCH_KS8695 is not set 205# CONFIG_ARCH_KS8695 is not set
200# CONFIG_ARCH_NS9XXX is not set 206# CONFIG_ARCH_NS9XXX is not set
201# CONFIG_ARCH_W90X900 is not set 207# CONFIG_ARCH_W90X900 is not set
208# CONFIG_ARCH_NUC93X is not set
202# CONFIG_ARCH_PNX4008 is not set 209# CONFIG_ARCH_PNX4008 is not set
203# CONFIG_ARCH_PXA is not set 210# CONFIG_ARCH_PXA is not set
204# CONFIG_ARCH_MSM is not set 211# CONFIG_ARCH_MSM is not set
@@ -207,14 +214,18 @@ CONFIG_ARCH_SHMOBILE=y
207# CONFIG_ARCH_SA1100 is not set 214# CONFIG_ARCH_SA1100 is not set
208# CONFIG_ARCH_S3C2410 is not set 215# CONFIG_ARCH_S3C2410 is not set
209# CONFIG_ARCH_S3C64XX is not set 216# CONFIG_ARCH_S3C64XX is not set
217# CONFIG_ARCH_S5P6440 is not set
218# CONFIG_ARCH_S5P6442 is not set
210# CONFIG_ARCH_S5PC1XX is not set 219# CONFIG_ARCH_S5PC1XX is not set
220# CONFIG_ARCH_S5PV210 is not set
211# CONFIG_ARCH_SHARK is not set 221# CONFIG_ARCH_SHARK is not set
212# CONFIG_ARCH_LH7A40X is not set 222# CONFIG_ARCH_LH7A40X is not set
213# CONFIG_ARCH_U300 is not set 223# CONFIG_ARCH_U300 is not set
224# CONFIG_ARCH_U8500 is not set
225# CONFIG_ARCH_NOMADIK is not set
214# CONFIG_ARCH_DAVINCI is not set 226# CONFIG_ARCH_DAVINCI is not set
215# CONFIG_ARCH_OMAP is not set 227# CONFIG_ARCH_OMAP is not set
216# CONFIG_ARCH_BCMRING is not set 228# CONFIG_PLAT_SPEAR is not set
217# CONFIG_ARCH_U8500 is not set
218 229
219# 230#
220# SH-Mobile System Type 231# SH-Mobile System Type
@@ -242,6 +253,7 @@ CONFIG_MEMORY_SIZE=0x08000000
242# Timer and clock configuration 253# Timer and clock configuration
243# 254#
244CONFIG_SH_TIMER_CMT=y 255CONFIG_SH_TIMER_CMT=y
256CONFIG_SH_TIMER_TMU=y
245 257
246# 258#
247# Processor Type 259# Processor Type
@@ -267,6 +279,8 @@ CONFIG_ARM_THUMB=y
267# CONFIG_CPU_DCACHE_DISABLE is not set 279# CONFIG_CPU_DCACHE_DISABLE is not set
268# CONFIG_CPU_BPREDICT_DISABLE is not set 280# CONFIG_CPU_BPREDICT_DISABLE is not set
269CONFIG_ARM_L1_CACHE_SHIFT=5 281CONFIG_ARM_L1_CACHE_SHIFT=5
282CONFIG_ARM_DMA_MEM_BUFFERABLE=y
283CONFIG_CPU_HAS_PMU=y
270# CONFIG_ARM_ERRATA_411920 is not set 284# CONFIG_ARM_ERRATA_411920 is not set
271CONFIG_COMMON_CLKDEV=y 285CONFIG_COMMON_CLKDEV=y
272 286
@@ -317,7 +331,7 @@ CONFIG_ALIGNMENT_TRAP=y
317# 331#
318CONFIG_ZBOOT_ROM_TEXT=0x0 332CONFIG_ZBOOT_ROM_TEXT=0x0
319CONFIG_ZBOOT_ROM_BSS=0x0 333CONFIG_ZBOOT_ROM_BSS=0x0
320CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200" 334CONFIG_CMDLINE="console=ttySC1,115200"
321# CONFIG_XIP_KERNEL is not set 335# CONFIG_XIP_KERNEL is not set
322CONFIG_KEXEC=y 336CONFIG_KEXEC=y
323CONFIG_ATAGS_PROC=y 337CONFIG_ATAGS_PROC=y
@@ -447,10 +461,12 @@ CONFIG_MTD_NAND=y
447# CONFIG_MTD_NAND_VERIFY_WRITE is not set 461# CONFIG_MTD_NAND_VERIFY_WRITE is not set
448# CONFIG_MTD_NAND_ECC_SMC is not set 462# CONFIG_MTD_NAND_ECC_SMC is not set
449# CONFIG_MTD_NAND_MUSEUM_IDS is not set 463# CONFIG_MTD_NAND_MUSEUM_IDS is not set
464# CONFIG_MTD_NAND_GPIO is not set
450CONFIG_MTD_NAND_IDS=y 465CONFIG_MTD_NAND_IDS=y
451# CONFIG_MTD_NAND_DISKONCHIP is not set 466# CONFIG_MTD_NAND_DISKONCHIP is not set
452# CONFIG_MTD_NAND_NANDSIM is not set 467# CONFIG_MTD_NAND_NANDSIM is not set
453# CONFIG_MTD_NAND_PLATFORM is not set 468# CONFIG_MTD_NAND_PLATFORM is not set
469CONFIG_MTD_NAND_SH_FLCTL=y
454# CONFIG_MTD_ONENAND is not set 470# CONFIG_MTD_ONENAND is not set
455 471
456# 472#
@@ -471,6 +487,7 @@ CONFIG_HAVE_IDE=y
471# 487#
472# SCSI device support 488# SCSI device support
473# 489#
490CONFIG_SCSI_MOD=y
474# CONFIG_RAID_ATTRS is not set 491# CONFIG_RAID_ATTRS is not set
475# CONFIG_SCSI is not set 492# CONFIG_SCSI is not set
476# CONFIG_SCSI_DMA is not set 493# CONFIG_SCSI_DMA is not set
@@ -538,6 +555,7 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
538CONFIG_SERIAL_SH_SCI_CONSOLE=y 555CONFIG_SERIAL_SH_SCI_CONSOLE=y
539CONFIG_SERIAL_CORE=y 556CONFIG_SERIAL_CORE=y
540CONFIG_SERIAL_CORE_CONSOLE=y 557CONFIG_SERIAL_CORE_CONSOLE=y
558# CONFIG_SERIAL_TIMBERDALE is not set
541CONFIG_UNIX98_PTYS=y 559CONFIG_UNIX98_PTYS=y
542# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 560# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
543# CONFIG_LEGACY_PTYS is not set 561# CONFIG_LEGACY_PTYS is not set
@@ -553,6 +571,31 @@ CONFIG_UNIX98_PTYS=y
553# PPS support 571# PPS support
554# 572#
555# CONFIG_PPS is not set 573# CONFIG_PPS is not set
574CONFIG_ARCH_REQUIRE_GPIOLIB=y
575CONFIG_GPIOLIB=y
576# CONFIG_DEBUG_GPIO is not set
577# CONFIG_GPIO_SYSFS is not set
578
579#
580# Memory mapped GPIO expanders:
581#
582# CONFIG_GPIO_IT8761E is not set
583
584#
585# I2C GPIO expanders:
586#
587
588#
589# PCI GPIO expanders:
590#
591
592#
593# SPI GPIO expanders:
594#
595
596#
597# AC97 GPIO expanders:
598#
556# CONFIG_W1 is not set 599# CONFIG_W1 is not set
557# CONFIG_POWER_SUPPLY is not set 600# CONFIG_POWER_SUPPLY is not set
558# CONFIG_HWMON is not set 601# CONFIG_HWMON is not set
@@ -568,12 +611,16 @@ CONFIG_SSB_POSSIBLE=y
568# 611#
569# Multifunction device drivers 612# Multifunction device drivers
570# 613#
571# CONFIG_MFD_CORE is not set 614CONFIG_MFD_CORE=y
572# CONFIG_MFD_SM501 is not set 615# CONFIG_MFD_SM501 is not set
616# CONFIG_MFD_ASIC3 is not set
617CONFIG_MFD_SH_MOBILE_SDHI=y
618# CONFIG_HTC_EGPIO is not set
573# CONFIG_HTC_PASIC3 is not set 619# CONFIG_HTC_PASIC3 is not set
574# CONFIG_MFD_TMIO is not set 620# CONFIG_MFD_TMIO is not set
575# CONFIG_MFD_T7L66XB is not set 621# CONFIG_MFD_T7L66XB is not set
576# CONFIG_MFD_TC6387XB is not set 622# CONFIG_MFD_TC6387XB is not set
623# CONFIG_MFD_TC6393XB is not set
577# CONFIG_REGULATOR is not set 624# CONFIG_REGULATOR is not set
578# CONFIG_MEDIA_SUPPORT is not set 625# CONFIG_MEDIA_SUPPORT is not set
579 626
@@ -728,6 +775,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
728CONFIG_HAVE_FUNCTION_TRACER=y 775CONFIG_HAVE_FUNCTION_TRACER=y
729CONFIG_TRACING_SUPPORT=y 776CONFIG_TRACING_SUPPORT=y
730# CONFIG_FTRACE is not set 777# CONFIG_FTRACE is not set
778# CONFIG_ATOMIC64_SELFTEST is not set
731# CONFIG_SAMPLES is not set 779# CONFIG_SAMPLES is not set
732CONFIG_HAVE_ARCH_KGDB=y 780CONFIG_HAVE_ARCH_KGDB=y
733# CONFIG_KGDB is not set 781# CONFIG_KGDB is not set
@@ -772,3 +820,4 @@ CONFIG_DECOMPRESS_LZO=y
772CONFIG_HAS_IOMEM=y 820CONFIG_HAS_IOMEM=y
773CONFIG_HAS_IOPORT=y 821CONFIG_HAS_IOPORT=y
774CONFIG_HAS_DMA=y 822CONFIG_HAS_DMA=y
823CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig
index 8ee79a537134..3841bc609d41 100644
--- a/arch/arm/configs/g4evm_defconfig
+++ b/arch/arm/configs/g4evm_defconfig
@@ -1,12 +1,15 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.33-rc7 3# Linux kernel version: 2.6.34
4# Mon Feb 8 12:21:35 2010 4# Thu May 20 12:37:38 2010
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
8CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
9CONFIG_GENERIC_CLOCKEVENTS=y 11CONFIG_GENERIC_CLOCKEVENTS=y
12CONFIG_HAVE_PROC_CPU=y
10CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
11CONFIG_STACKTRACE_SUPPORT=y 14CONFIG_STACKTRACE_SUPPORT=y
12CONFIG_HAVE_LATENCYTOP_SUPPORT=y 15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
17CONFIG_RWSEM_GENERIC_SPINLOCK=y 20CONFIG_RWSEM_GENERIC_SPINLOCK=y
18CONFIG_GENERIC_HWEIGHT=y 21CONFIG_GENERIC_HWEIGHT=y
19CONFIG_GENERIC_CALIBRATE_DELAY=y 22CONFIG_GENERIC_CALIBRATE_DELAY=y
23CONFIG_NEED_DMA_MAP_STATE=y
20CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
21CONFIG_VECTORS_BASE=0xffff0000 25CONFIG_VECTORS_BASE=0xffff0000
22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -31,6 +35,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
31CONFIG_LOCALVERSION="" 35CONFIG_LOCALVERSION=""
32CONFIG_LOCALVERSION_AUTO=y 36CONFIG_LOCALVERSION_AUTO=y
33CONFIG_HAVE_KERNEL_GZIP=y 37CONFIG_HAVE_KERNEL_GZIP=y
38CONFIG_HAVE_KERNEL_LZMA=y
34CONFIG_HAVE_KERNEL_LZO=y 39CONFIG_HAVE_KERNEL_LZO=y
35CONFIG_KERNEL_GZIP=y 40CONFIG_KERNEL_GZIP=y
36# CONFIG_KERNEL_BZIP2 is not set 41# CONFIG_KERNEL_BZIP2 is not set
@@ -54,11 +59,6 @@ CONFIG_RCU_FANOUT=32
54CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
55CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
56CONFIG_LOG_BUF_SHIFT=16 61CONFIG_LOG_BUF_SHIFT=16
57CONFIG_GROUP_SCHED=y
58CONFIG_FAIR_GROUP_SCHED=y
59# CONFIG_RT_GROUP_SCHED is not set
60CONFIG_USER_SCHED=y
61# CONFIG_CGROUP_SCHED is not set
62# CONFIG_CGROUPS is not set 62# CONFIG_CGROUPS is not set
63# CONFIG_SYSFS_DEPRECATED_V2 is not set 63# CONFIG_SYSFS_DEPRECATED_V2 is not set
64# CONFIG_RELAY is not set 64# CONFIG_RELAY is not set
@@ -94,10 +94,14 @@ CONFIG_TIMERFD=y
94CONFIG_EVENTFD=y 94CONFIG_EVENTFD=y
95CONFIG_SHMEM=y 95CONFIG_SHMEM=y
96CONFIG_AIO=y 96CONFIG_AIO=y
97CONFIG_HAVE_PERF_EVENTS=y
98CONFIG_PERF_USE_VMALLOC=y
97 99
98# 100#
99# Kernel Performance Events And Counters 101# Kernel Performance Events And Counters
100# 102#
103# CONFIG_PERF_EVENTS is not set
104# CONFIG_PERF_COUNTERS is not set
101CONFIG_VM_EVENT_COUNTERS=y 105CONFIG_VM_EVENT_COUNTERS=y
102CONFIG_COMPAT_BRK=y 106CONFIG_COMPAT_BRK=y
103CONFIG_SLAB=y 107CONFIG_SLAB=y
@@ -172,8 +176,11 @@ CONFIG_MMU=y
172# CONFIG_ARCH_INTEGRATOR is not set 176# CONFIG_ARCH_INTEGRATOR is not set
173# CONFIG_ARCH_REALVIEW is not set 177# CONFIG_ARCH_REALVIEW is not set
174# CONFIG_ARCH_VERSATILE is not set 178# CONFIG_ARCH_VERSATILE is not set
179# CONFIG_ARCH_VEXPRESS is not set
175# CONFIG_ARCH_AT91 is not set 180# CONFIG_ARCH_AT91 is not set
181# CONFIG_ARCH_BCMRING is not set
176# CONFIG_ARCH_CLPS711X is not set 182# CONFIG_ARCH_CLPS711X is not set
183# CONFIG_ARCH_CNS3XXX is not set
177# CONFIG_ARCH_GEMINI is not set 184# CONFIG_ARCH_GEMINI is not set
178# CONFIG_ARCH_EBSA110 is not set 185# CONFIG_ARCH_EBSA110 is not set
179# CONFIG_ARCH_EP93XX is not set 186# CONFIG_ARCH_EP93XX is not set
@@ -182,7 +189,6 @@ CONFIG_MMU=y
182# CONFIG_ARCH_STMP3XXX is not set 189# CONFIG_ARCH_STMP3XXX is not set
183# CONFIG_ARCH_NETX is not set 190# CONFIG_ARCH_NETX is not set
184# CONFIG_ARCH_H720X is not set 191# CONFIG_ARCH_H720X is not set
185# CONFIG_ARCH_NOMADIK is not set
186# CONFIG_ARCH_IOP13XX is not set 192# CONFIG_ARCH_IOP13XX is not set
187# CONFIG_ARCH_IOP32X is not set 193# CONFIG_ARCH_IOP32X is not set
188# CONFIG_ARCH_IOP33X is not set 194# CONFIG_ARCH_IOP33X is not set
@@ -199,6 +205,7 @@ CONFIG_MMU=y
199# CONFIG_ARCH_KS8695 is not set 205# CONFIG_ARCH_KS8695 is not set
200# CONFIG_ARCH_NS9XXX is not set 206# CONFIG_ARCH_NS9XXX is not set
201# CONFIG_ARCH_W90X900 is not set 207# CONFIG_ARCH_W90X900 is not set
208# CONFIG_ARCH_NUC93X is not set
202# CONFIG_ARCH_PNX4008 is not set 209# CONFIG_ARCH_PNX4008 is not set
203# CONFIG_ARCH_PXA is not set 210# CONFIG_ARCH_PXA is not set
204# CONFIG_ARCH_MSM is not set 211# CONFIG_ARCH_MSM is not set
@@ -207,14 +214,18 @@ CONFIG_ARCH_SHMOBILE=y
207# CONFIG_ARCH_SA1100 is not set 214# CONFIG_ARCH_SA1100 is not set
208# CONFIG_ARCH_S3C2410 is not set 215# CONFIG_ARCH_S3C2410 is not set
209# CONFIG_ARCH_S3C64XX is not set 216# CONFIG_ARCH_S3C64XX is not set
217# CONFIG_ARCH_S5P6440 is not set
218# CONFIG_ARCH_S5P6442 is not set
210# CONFIG_ARCH_S5PC1XX is not set 219# CONFIG_ARCH_S5PC1XX is not set
220# CONFIG_ARCH_S5PV210 is not set
211# CONFIG_ARCH_SHARK is not set 221# CONFIG_ARCH_SHARK is not set
212# CONFIG_ARCH_LH7A40X is not set 222# CONFIG_ARCH_LH7A40X is not set
213# CONFIG_ARCH_U300 is not set 223# CONFIG_ARCH_U300 is not set
224# CONFIG_ARCH_U8500 is not set
225# CONFIG_ARCH_NOMADIK is not set
214# CONFIG_ARCH_DAVINCI is not set 226# CONFIG_ARCH_DAVINCI is not set
215# CONFIG_ARCH_OMAP is not set 227# CONFIG_ARCH_OMAP is not set
216# CONFIG_ARCH_BCMRING is not set 228# CONFIG_PLAT_SPEAR is not set
217# CONFIG_ARCH_U8500 is not set
218 229
219# 230#
220# SH-Mobile System Type 231# SH-Mobile System Type
@@ -242,6 +253,7 @@ CONFIG_MEMORY_SIZE=0x08000000
242# Timer and clock configuration 253# Timer and clock configuration
243# 254#
244CONFIG_SH_TIMER_CMT=y 255CONFIG_SH_TIMER_CMT=y
256CONFIG_SH_TIMER_TMU=y
245 257
246# 258#
247# Processor Type 259# Processor Type
@@ -269,6 +281,8 @@ CONFIG_ARM_THUMB=y
269# CONFIG_CPU_BPREDICT_DISABLE is not set 281# CONFIG_CPU_BPREDICT_DISABLE is not set
270CONFIG_HAS_TLS_REG=y 282CONFIG_HAS_TLS_REG=y
271CONFIG_ARM_L1_CACHE_SHIFT=5 283CONFIG_ARM_L1_CACHE_SHIFT=5
284CONFIG_ARM_DMA_MEM_BUFFERABLE=y
285CONFIG_CPU_HAS_PMU=y
272# CONFIG_ARM_ERRATA_430973 is not set 286# CONFIG_ARM_ERRATA_430973 is not set
273# CONFIG_ARM_ERRATA_458693 is not set 287# CONFIG_ARM_ERRATA_458693 is not set
274# CONFIG_ARM_ERRATA_460075 is not set 288# CONFIG_ARM_ERRATA_460075 is not set
@@ -322,7 +336,7 @@ CONFIG_ALIGNMENT_TRAP=y
322# 336#
323CONFIG_ZBOOT_ROM_TEXT=0x0 337CONFIG_ZBOOT_ROM_TEXT=0x0
324CONFIG_ZBOOT_ROM_BSS=0x0 338CONFIG_ZBOOT_ROM_BSS=0x0
325CONFIG_CMDLINE="console=ttySC4,115200 earlyprintk=sh-sci.4,115200" 339CONFIG_CMDLINE="console=ttySC4,115200"
326# CONFIG_XIP_KERNEL is not set 340# CONFIG_XIP_KERNEL is not set
327CONFIG_KEXEC=y 341CONFIG_KEXEC=y
328CONFIG_ATAGS_PROC=y 342CONFIG_ATAGS_PROC=y
@@ -452,10 +466,12 @@ CONFIG_MTD_NAND=y
452# CONFIG_MTD_NAND_VERIFY_WRITE is not set 466# CONFIG_MTD_NAND_VERIFY_WRITE is not set
453# CONFIG_MTD_NAND_ECC_SMC is not set 467# CONFIG_MTD_NAND_ECC_SMC is not set
454# CONFIG_MTD_NAND_MUSEUM_IDS is not set 468# CONFIG_MTD_NAND_MUSEUM_IDS is not set
469# CONFIG_MTD_NAND_GPIO is not set
455CONFIG_MTD_NAND_IDS=y 470CONFIG_MTD_NAND_IDS=y
456# CONFIG_MTD_NAND_DISKONCHIP is not set 471# CONFIG_MTD_NAND_DISKONCHIP is not set
457# CONFIG_MTD_NAND_NANDSIM is not set 472# CONFIG_MTD_NAND_NANDSIM is not set
458# CONFIG_MTD_NAND_PLATFORM is not set 473# CONFIG_MTD_NAND_PLATFORM is not set
474CONFIG_MTD_NAND_SH_FLCTL=y
459# CONFIG_MTD_ONENAND is not set 475# CONFIG_MTD_ONENAND is not set
460 476
461# 477#
@@ -476,6 +492,7 @@ CONFIG_HAVE_IDE=y
476# 492#
477# SCSI device support 493# SCSI device support
478# 494#
495CONFIG_SCSI_MOD=y
479# CONFIG_RAID_ATTRS is not set 496# CONFIG_RAID_ATTRS is not set
480# CONFIG_SCSI is not set 497# CONFIG_SCSI is not set
481# CONFIG_SCSI_DMA is not set 498# CONFIG_SCSI_DMA is not set
@@ -543,6 +560,7 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
543CONFIG_SERIAL_SH_SCI_CONSOLE=y 560CONFIG_SERIAL_SH_SCI_CONSOLE=y
544CONFIG_SERIAL_CORE=y 561CONFIG_SERIAL_CORE=y
545CONFIG_SERIAL_CORE_CONSOLE=y 562CONFIG_SERIAL_CORE_CONSOLE=y
563# CONFIG_SERIAL_TIMBERDALE is not set
546CONFIG_UNIX98_PTYS=y 564CONFIG_UNIX98_PTYS=y
547# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 565# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
548# CONFIG_LEGACY_PTYS is not set 566# CONFIG_LEGACY_PTYS is not set
@@ -558,6 +576,31 @@ CONFIG_UNIX98_PTYS=y
558# PPS support 576# PPS support
559# 577#
560# CONFIG_PPS is not set 578# CONFIG_PPS is not set
579CONFIG_ARCH_REQUIRE_GPIOLIB=y
580CONFIG_GPIOLIB=y
581# CONFIG_DEBUG_GPIO is not set
582# CONFIG_GPIO_SYSFS is not set
583
584#
585# Memory mapped GPIO expanders:
586#
587# CONFIG_GPIO_IT8761E is not set
588
589#
590# I2C GPIO expanders:
591#
592
593#
594# PCI GPIO expanders:
595#
596
597#
598# SPI GPIO expanders:
599#
600
601#
602# AC97 GPIO expanders:
603#
561# CONFIG_W1 is not set 604# CONFIG_W1 is not set
562# CONFIG_POWER_SUPPLY is not set 605# CONFIG_POWER_SUPPLY is not set
563# CONFIG_HWMON is not set 606# CONFIG_HWMON is not set
@@ -573,12 +616,16 @@ CONFIG_SSB_POSSIBLE=y
573# 616#
574# Multifunction device drivers 617# Multifunction device drivers
575# 618#
576# CONFIG_MFD_CORE is not set 619CONFIG_MFD_CORE=y
577# CONFIG_MFD_SM501 is not set 620# CONFIG_MFD_SM501 is not set
621# CONFIG_MFD_ASIC3 is not set
622CONFIG_MFD_SH_MOBILE_SDHI=y
623# CONFIG_HTC_EGPIO is not set
578# CONFIG_HTC_PASIC3 is not set 624# CONFIG_HTC_PASIC3 is not set
579# CONFIG_MFD_TMIO is not set 625# CONFIG_MFD_TMIO is not set
580# CONFIG_MFD_T7L66XB is not set 626# CONFIG_MFD_T7L66XB is not set
581# CONFIG_MFD_TC6387XB is not set 627# CONFIG_MFD_TC6387XB is not set
628# CONFIG_MFD_TC6393XB is not set
582# CONFIG_REGULATOR is not set 629# CONFIG_REGULATOR is not set
583# CONFIG_MEDIA_SUPPORT is not set 630# CONFIG_MEDIA_SUPPORT is not set
584 631
@@ -733,6 +780,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
733CONFIG_HAVE_FUNCTION_TRACER=y 780CONFIG_HAVE_FUNCTION_TRACER=y
734CONFIG_TRACING_SUPPORT=y 781CONFIG_TRACING_SUPPORT=y
735# CONFIG_FTRACE is not set 782# CONFIG_FTRACE is not set
783# CONFIG_ATOMIC64_SELFTEST is not set
736# CONFIG_SAMPLES is not set 784# CONFIG_SAMPLES is not set
737CONFIG_HAVE_ARCH_KGDB=y 785CONFIG_HAVE_ARCH_KGDB=y
738# CONFIG_KGDB is not set 786# CONFIG_KGDB is not set
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f2b88c5fe142..1de8d171c6e9 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -7,6 +7,7 @@ config ARCH_SH7367
7 select CPU_V6 7 select CPU_V6
8 select HAVE_CLK 8 select HAVE_CLK
9 select COMMON_CLKDEV 9 select COMMON_CLKDEV
10 select SH_CLK_CPG
10 select GENERIC_CLOCKEVENTS 11 select GENERIC_CLOCKEVENTS
11 12
12config ARCH_SH7377 13config ARCH_SH7377
@@ -14,6 +15,7 @@ config ARCH_SH7377
14 select CPU_V7 15 select CPU_V7
15 select HAVE_CLK 16 select HAVE_CLK
16 select COMMON_CLKDEV 17 select COMMON_CLKDEV
18 select SH_CLK_CPG
17 select GENERIC_CLOCKEVENTS 19 select GENERIC_CLOCKEVENTS
18 20
19config ARCH_SH7372 21config ARCH_SH7372
@@ -21,6 +23,7 @@ config ARCH_SH7372
21 select CPU_V7 23 select CPU_V7
22 select HAVE_CLK 24 select HAVE_CLK
23 select COMMON_CLKDEV 25 select COMMON_CLKDEV
26 select SH_CLK_CPG
24 select GENERIC_CLOCKEVENTS 27 select GENERIC_CLOCKEVENTS
25 28
26comment "SH-Mobile Board Type" 29comment "SH-Mobile Board Type"
@@ -39,6 +42,7 @@ config MACH_AP4EVB
39 bool "AP4EVB board" 42 bool "AP4EVB board"
40 depends on ARCH_SH7372 43 depends on ARCH_SH7372
41 select ARCH_REQUIRE_GPIOLIB 44 select ARCH_REQUIRE_GPIOLIB
45 select SH_LCD_MIPI_DSI
42 46
43comment "SH-Mobile System Configuration" 47comment "SH-Mobile System Configuration"
44 48
@@ -76,6 +80,15 @@ config SH_TIMER_CMT
76 help 80 help
77 This enables build of the CMT timer driver. 81 This enables build of the CMT timer driver.
78 82
83config SH_TIMER_TMU
84 bool "TMU timer driver"
85 default y
86 help
87 This enables build of the TMU timer driver.
88
79endmenu 89endmenu
80 90
91config SH_CLK_CPG
92 bool
93
81endif 94endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 6d385d371c33..5e16b4c69222 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -3,12 +3,12 @@
3# 3#
4 4
5# Common objects 5# Common objects
6obj-y := timer.o console.o 6obj-y := timer.o console.o clock.o
7 7
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o 9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12 12
13# Pinmux setup 13# Pinmux setup
14pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o 14pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 1c2ec96ce261..353ff8d120b1 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -17,6 +17,7 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20#include <linux/clk.h>
20#include <linux/kernel.h> 21#include <linux/kernel.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/interrupt.h> 23#include <linux/interrupt.h>
@@ -26,16 +27,26 @@
26#include <linux/mtd/mtd.h> 27#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h> 28#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h> 29#include <linux/mtd/physmap.h>
30#include <linux/i2c.h>
31#include <linux/i2c/tsc2007.h>
29#include <linux/io.h> 32#include <linux/io.h>
30#include <linux/smsc911x.h> 33#include <linux/smsc911x.h>
31#include <linux/gpio.h> 34#include <linux/gpio.h>
32#include <linux/input.h> 35#include <linux/input.h>
33#include <linux/input/sh_keysc.h> 36#include <linux/input/sh_keysc.h>
37#include <linux/usb/r8a66597.h>
38
39#include <video/sh_mobile_lcdc.h>
40#include <video/sh_mipi_dsi.h>
41
34#include <mach/common.h> 42#include <mach/common.h>
43#include <mach/irqs.h>
35#include <mach/sh7372.h> 44#include <mach/sh7372.h>
45
36#include <asm/mach-types.h> 46#include <asm/mach-types.h>
37#include <asm/mach/arch.h> 47#include <asm/mach/arch.h>
38#include <asm/mach/map.h> 48#include <asm/mach/map.h>
49#include <asm/mach/time.h>
39 50
40/* 51/*
41 * Address Interface BusWidth note 52 * Address Interface BusWidth note
@@ -80,12 +91,25 @@
80 */ 91 */
81 92
82/* 93/*
83 * KEYSC 94 * LCD / IRQ / KEYSC / IrDA
95 *
96 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (TouchScreen)
97 * LCD = 2nd LCDC
98 *
99 * | SW43 |
100 * SW3 | ON | OFF |
101 * -------------+-----------------------+---------------+
102 * ON | KEY / IrDA | LCD |
103 * OFF | KEY / IrDA / IRQ | IRQ |
104 */
105
106/*
107 * USB
84 * 108 *
85 * SW43 KEYSC 109 * J7 : 1-2 MAX3355E VBUS
86 * ------------------------- 110 * 2-3 DC 5.0V
87 * ON enable 111 *
88 * OFF disable 112 * S39: bit2: off
89 */ 113 */
90 114
91/* MTD */ 115/* MTD */
@@ -148,7 +172,7 @@ static struct resource smc911x_resources[] = {
148 .end = 0x16000000 - 1, 172 .end = 0x16000000 - 1,
149 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
150 }, { 174 }, {
151 .start = 6, 175 .start = evt2irq(0x02c0) /* IRQ6A */,
152 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 176 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
153 }, 177 },
154}; 178};
@@ -191,7 +215,7 @@ static struct resource keysc_resources[] = {
191 .flags = IORESOURCE_MEM, 215 .flags = IORESOURCE_MEM,
192 }, 216 },
193 [1] = { 217 [1] = {
194 .start = 79, 218 .start = evt2irq(0x0be0), /* KEYSC_KEY */
195 .flags = IORESOURCE_IRQ, 219 .flags = IORESOURCE_IRQ,
196 }, 220 },
197}; 221};
@@ -215,7 +239,7 @@ static struct resource sdhi0_resources[] = {
215 .flags = IORESOURCE_MEM, 239 .flags = IORESOURCE_MEM,
216 }, 240 },
217 [1] = { 241 [1] = {
218 .start = 96, 242 .start = evt2irq(0x0e00) /* SDHI0 */,
219 .flags = IORESOURCE_IRQ, 243 .flags = IORESOURCE_IRQ,
220 }, 244 },
221}; 245};
@@ -227,11 +251,147 @@ static struct platform_device sdhi0_device = {
227 .id = 0, 251 .id = 0,
228}; 252};
229 253
254/* USB1 */
255void usb1_host_port_power(int port, int power)
256{
257 if (!power) /* only power-on supported for now */
258 return;
259
260 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
261 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
262}
263
264static struct r8a66597_platdata usb1_host_data = {
265 .on_chip = 1,
266 .port_power = usb1_host_port_power,
267};
268
269static struct resource usb1_host_resources[] = {
270 [0] = {
271 .name = "USBHS",
272 .start = 0xE68B0000,
273 .end = 0xE68B00E6 - 1,
274 .flags = IORESOURCE_MEM,
275 },
276 [1] = {
277 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device usb1_host_device = {
283 .name = "r8a66597_hcd",
284 .id = 1,
285 .dev = {
286 .dma_mask = NULL, /* not use dma */
287 .coherent_dma_mask = 0xffffffff,
288 .platform_data = &usb1_host_data,
289 },
290 .num_resources = ARRAY_SIZE(usb1_host_resources),
291 .resource = usb1_host_resources,
292};
293
294static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
295 .clock_source = LCDC_CLK_PERIPHERAL, /* One of interface clocks */
296 .ch[0] = {
297 .chan = LCDC_CHAN_MAINLCD,
298 .bpp = 16,
299 .interface_type = RGB24,
300 .clock_divider = 1,
301 .flags = LCDC_FLAGS_DWPOL,
302 .lcd_cfg = {
303 .name = "R63302(QHD)",
304 .xres = 544,
305 .yres = 961,
306 .left_margin = 72,
307 .right_margin = 600,
308 .hsync_len = 16,
309 .upper_margin = 8,
310 .lower_margin = 8,
311 .vsync_len = 2,
312 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
313 },
314 .lcd_size_cfg = {
315 .width = 44,
316 .height = 79,
317 },
318 }
319};
320
321static struct resource lcdc_resources[] = {
322 [0] = {
323 .name = "LCDC",
324 .start = 0xfe940000, /* P4-only space */
325 .end = 0xfe943fff,
326 .flags = IORESOURCE_MEM,
327 },
328 [1] = {
329 .start = intcs_evt2irq(0x580),
330 .flags = IORESOURCE_IRQ,
331 },
332};
333
334static struct platform_device lcdc_device = {
335 .name = "sh_mobile_lcdc_fb",
336 .num_resources = ARRAY_SIZE(lcdc_resources),
337 .resource = lcdc_resources,
338 .dev = {
339 .platform_data = &sh_mobile_lcdc_info,
340 .coherent_dma_mask = ~0,
341 },
342};
343
344static struct resource mipidsi0_resources[] = {
345 [0] = {
346 .start = 0xffc60000,
347 .end = 0xffc68fff,
348 .flags = IORESOURCE_MEM,
349 },
350};
351
352static struct sh_mipi_dsi_info mipidsi0_info = {
353 .data_format = MIPI_RGB888,
354 .lcd_chan = &sh_mobile_lcdc_info.ch[0],
355};
356
357static struct platform_device mipidsi0_device = {
358 .name = "sh-mipi-dsi",
359 .num_resources = ARRAY_SIZE(mipidsi0_resources),
360 .resource = mipidsi0_resources,
361 .id = 0,
362 .dev = {
363 .platform_data = &mipidsi0_info,
364 },
365};
366
230static struct platform_device *ap4evb_devices[] __initdata = { 367static struct platform_device *ap4evb_devices[] __initdata = {
231 &nor_flash_device, 368 &nor_flash_device,
232 &smc911x_device, 369 &smc911x_device,
233 &keysc_device, 370 &keysc_device,
234 &sdhi0_device, 371 &sdhi0_device,
372 &usb1_host_device,
373 &lcdc_device,
374 &mipidsi0_device,
375};
376
377/* TouchScreen (Needs SW3 set to OFF) */
378#define IRQ28 evt2irq(0x3380) /* IRQ28A */
379struct tsc2007_platform_data tsc2007_info = {
380 .model = 2007,
381 .x_plate_ohms = 180,
382};
383
384/* I2C */
385static struct i2c_board_info i2c1_devices[] = {
386 {
387 I2C_BOARD_INFO("r2025sd", 0x32),
388 },
389 {
390 I2C_BOARD_INFO("tsc2007", 0x48),
391 .type = "tsc2007",
392 .platform_data = &tsc2007_info,
393 .irq = IRQ28,
394 },
235}; 395};
236 396
237static struct map_desc ap4evb_io_desc[] __initdata = { 397static struct map_desc ap4evb_io_desc[] __initdata = {
@@ -250,12 +410,50 @@ static void __init ap4evb_map_io(void)
250{ 410{
251 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); 411 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
252 412
253 /* setup early devices, clocks and console here as well */ 413 /* setup early devices and console here as well */
254 sh7372_add_early_devices(); 414 sh7372_add_early_devices();
255 sh7367_clock_init(); /* use g3 clocks for now */
256 shmobile_setup_console(); 415 shmobile_setup_console();
257} 416}
258 417
418/* This function will disappear when we switch to (runtime) PM */
419static int __init ap4evb_init_display_clk(void)
420{
421 struct clk *lcdc_clk;
422 struct clk *dsitx_clk;
423 int ret;
424
425 lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0");
426 if (IS_ERR(lcdc_clk))
427 return PTR_ERR(lcdc_clk);
428
429 dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0");
430 if (IS_ERR(dsitx_clk)) {
431 ret = PTR_ERR(dsitx_clk);
432 goto eclkdsitxget;
433 }
434
435 ret = clk_enable(lcdc_clk);
436 if (ret < 0)
437 goto eclklcdcon;
438
439 ret = clk_enable(dsitx_clk);
440 if (ret < 0)
441 goto eclkdsitxon;
442
443 return 0;
444
445eclkdsitxon:
446 clk_disable(lcdc_clk);
447eclklcdcon:
448 clk_put(dsitx_clk);
449eclkdsitxget:
450 clk_put(lcdc_clk);
451
452 return ret;
453}
454
455device_initcall(ap4evb_init_display_clk);
456
259static void __init ap4evb_init(void) 457static void __init ap4evb_init(void)
260{ 458{
261 sh7372_pinmux_init(); 459 sh7372_pinmux_init();
@@ -318,16 +516,44 @@ static void __init ap4evb_init(void)
318 gpio_request(GPIO_FN_SDHID0_1, NULL); 516 gpio_request(GPIO_FN_SDHID0_1, NULL);
319 gpio_request(GPIO_FN_SDHID0_0, NULL); 517 gpio_request(GPIO_FN_SDHID0_0, NULL);
320 518
519 /* enable TouchScreen */
520 gpio_request(GPIO_FN_IRQ28_123, NULL);
521 set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
522
523 i2c_register_board_info(1, i2c1_devices,
524 ARRAY_SIZE(i2c1_devices));
525
526 /* USB enable */
527 gpio_request(GPIO_FN_VBUS0_1, NULL);
528 gpio_request(GPIO_FN_IDIN_1_18, NULL);
529 gpio_request(GPIO_FN_PWEN_1_115, NULL);
530 gpio_request(GPIO_FN_OVCN_1_114, NULL);
531 gpio_request(GPIO_FN_EXTLP_1, NULL);
532 gpio_request(GPIO_FN_OVCN2_1, NULL);
533
534 /* setup USB phy */
535 __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */
536
321 sh7372_add_standard_devices(); 537 sh7372_add_standard_devices();
322 538
323 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); 539 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
324} 540}
325 541
542static void __init ap4evb_timer_init(void)
543{
544 sh7372_clock_init();
545 shmobile_timer.init();
546}
547
548static struct sys_timer ap4evb_timer = {
549 .init = ap4evb_timer_init,
550};
551
326MACHINE_START(AP4EVB, "ap4evb") 552MACHINE_START(AP4EVB, "ap4evb")
327 .phys_io = 0xe6000000, 553 .phys_io = 0xe6000000,
328 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, 554 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
329 .map_io = ap4evb_map_io, 555 .map_io = ap4evb_map_io,
330 .init_irq = sh7372_init_irq, 556 .init_irq = sh7372_init_irq,
331 .init_machine = ap4evb_init, 557 .init_machine = ap4evb_init,
332 .timer = &shmobile_timer, 558 .timer = &ap4evb_timer,
333MACHINE_END 559MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 9247503296c4..a8f20cb0b7d2 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -37,6 +37,15 @@
37#include <asm/mach-types.h> 37#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
39#include <asm/mach/map.h> 39#include <asm/mach/map.h>
40#include <asm/mach/time.h>
41
42/*
43 * IrDA
44 *
45 * S67: 5bit : ON power
46 * : 6bit : ON remote control
47 * OFF IrDA
48 */
40 49
41static struct mtd_partition nor_flash_partitions[] = { 50static struct mtd_partition nor_flash_partitions[] = {
42 { 51 {
@@ -113,7 +122,7 @@ static struct resource usb_host_resources[] = {
113 .flags = IORESOURCE_MEM, 122 .flags = IORESOURCE_MEM,
114 }, 123 },
115 [1] = { 124 [1] = {
116 .start = 65, 125 .start = evt2irq(0xa20), /* USBHS_USHI0 */
117 .flags = IORESOURCE_IRQ, 126 .flags = IORESOURCE_IRQ,
118 }, 127 },
119}; 128};
@@ -153,7 +162,7 @@ static struct resource keysc_resources[] = {
153 .flags = IORESOURCE_MEM, 162 .flags = IORESOURCE_MEM,
154 }, 163 },
155 [1] = { 164 [1] = {
156 .start = 79, 165 .start = evt2irq(0xbe0), /* KEYSC_KEY */
157 .flags = IORESOURCE_IRQ, 166 .flags = IORESOURCE_IRQ,
158 }, 167 },
159}; 168};
@@ -209,11 +218,30 @@ static struct platform_device nand_flash_device = {
209 }, 218 },
210}; 219};
211 220
221static struct resource irda_resources[] = {
222 [0] = {
223 .start = 0xE6D00000,
224 .end = 0xE6D01FD4 - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = evt2irq(0x480), /* IRDA */
229 .flags = IORESOURCE_IRQ,
230 },
231};
232
233static struct platform_device irda_device = {
234 .name = "sh_irda",
235 .resource = irda_resources,
236 .num_resources = ARRAY_SIZE(irda_resources),
237};
238
212static struct platform_device *g3evm_devices[] __initdata = { 239static struct platform_device *g3evm_devices[] __initdata = {
213 &nor_flash_device, 240 &nor_flash_device,
214 &usb_host_device, 241 &usb_host_device,
215 &keysc_device, 242 &keysc_device,
216 &nand_flash_device, 243 &nand_flash_device,
244 &irda_device,
217}; 245};
218 246
219static struct map_desc g3evm_io_desc[] __initdata = { 247static struct map_desc g3evm_io_desc[] __initdata = {
@@ -232,9 +260,8 @@ static void __init g3evm_map_io(void)
232{ 260{
233 iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); 261 iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
234 262
235 /* setup early devices, clocks and console here as well */ 263 /* setup early devices and console here as well */
236 sh7367_add_early_devices(); 264 sh7367_add_early_devices();
237 sh7367_clock_init();
238 shmobile_setup_console(); 265 shmobile_setup_console();
239} 266}
240 267
@@ -271,9 +298,6 @@ static void __init g3evm_init(void)
271 gpio_request(GPIO_FN_EXTLP, NULL); 298 gpio_request(GPIO_FN_EXTLP, NULL);
272 gpio_request(GPIO_FN_IDIN, NULL); 299 gpio_request(GPIO_FN_IDIN, NULL);
273 300
274 /* enable clock in SYMSTPCR2 */
275 __raw_writel(__raw_readl(0xe6158048) & ~(1 << 22), 0xe6158048);
276
277 /* setup USB phy */ 301 /* setup USB phy */
278 __raw_writew(0x0300, 0xe605810a); /* USBCR1 */ 302 __raw_writew(0x0300, 0xe605810a); /* USBCR1 */
279 __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ 303 __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
@@ -318,16 +342,32 @@ static void __init g3evm_init(void)
318 /* FOE, FCDE, FSC on dedicated pins */ 342 /* FOE, FCDE, FSC on dedicated pins */
319 __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048); 343 __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
320 344
345 /* IrDA */
346 gpio_request(GPIO_FN_IRDA_OUT, NULL);
347 gpio_request(GPIO_FN_IRDA_IN, NULL);
348 gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
349 set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
350
321 sh7367_add_standard_devices(); 351 sh7367_add_standard_devices();
322 352
323 platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); 353 platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
324} 354}
325 355
356static void __init g3evm_timer_init(void)
357{
358 sh7367_clock_init();
359 shmobile_timer.init();
360}
361
362static struct sys_timer g3evm_timer = {
363 .init = g3evm_timer_init,
364};
365
326MACHINE_START(G3EVM, "g3evm") 366MACHINE_START(G3EVM, "g3evm")
327 .phys_io = 0xe6000000, 367 .phys_io = 0xe6000000,
328 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, 368 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
329 .map_io = g3evm_map_io, 369 .map_io = g3evm_map_io,
330 .init_irq = sh7367_init_irq, 370 .init_irq = sh7367_init_irq,
331 .init_machine = g3evm_init, 371 .init_machine = g3evm_init,
332 .timer = &shmobile_timer, 372 .timer = &g3evm_timer,
333MACHINE_END 373MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 10673a90be52..e256b7cc4275 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -30,12 +30,39 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/input.h> 31#include <linux/input.h>
32#include <linux/input/sh_keysc.h> 32#include <linux/input/sh_keysc.h>
33#include <linux/mfd/sh_mobile_sdhi.h>
33#include <linux/gpio.h> 34#include <linux/gpio.h>
34#include <mach/sh7377.h> 35#include <mach/sh7377.h>
35#include <mach/common.h> 36#include <mach/common.h>
36#include <asm/mach-types.h> 37#include <asm/mach-types.h>
37#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
38#include <asm/mach/map.h> 39#include <asm/mach/map.h>
40#include <asm/mach/time.h>
41
42/*
43 * SDHI
44 *
45 * SDHI0 : card detection is possible
46 * SDHI1 : card detection is impossible
47 *
48 * [G4-MAIN-BOARD]
49 * JP74 : short # DBG_2V8A for SDHI0
50 * JP75 : NC # DBG_3V3A for SDHI0
51 * JP76 : NC # DBG_3V3A_SD for SDHI0
52 * JP77 : NC # 3V3A_SDIO for SDHI1
53 * JP78 : short # DBG_2V8A for SDHI1
54 * JP79 : NC # DBG_3V3A for SDHI1
55 * JP80 : NC # DBG_3V3A_SD for SDHI1
56 *
57 * [G4-CORE-BOARD]
58 * S32 : all off # to dissever from G3-CORE_DBG board
59 * S33 : all off # to dissever from G3-CORE_DBG board
60 *
61 * [G3-CORE_DBG-BOARD]
62 * S1 : all off # to dissever from G3-CORE_DBG board
63 * S3 : all off # to dissever from G3-CORE_DBG board
64 * S4 : all off # to dissever from G3-CORE_DBG board
65 */
39 66
40static struct mtd_partition nor_flash_partitions[] = { 67static struct mtd_partition nor_flash_partitions[] = {
41 { 68 {
@@ -112,8 +139,7 @@ static struct resource usb_host_resources[] = {
112 .flags = IORESOURCE_MEM, 139 .flags = IORESOURCE_MEM,
113 }, 140 },
114 [1] = { 141 [1] = {
115 .start = 65, 142 .start = evt2irq(0x0a20), /* USBHS_USHI0 */
116 .end = 65,
117 .flags = IORESOURCE_IRQ, 143 .flags = IORESOURCE_IRQ,
118 }, 144 },
119}; 145};
@@ -154,7 +180,7 @@ static struct resource keysc_resources[] = {
154 .flags = IORESOURCE_MEM, 180 .flags = IORESOURCE_MEM,
155 }, 181 },
156 [1] = { 182 [1] = {
157 .start = 79, 183 .start = evt2irq(0x0be0), /* KEYSC_KEY */
158 .flags = IORESOURCE_IRQ, 184 .flags = IORESOURCE_IRQ,
159 }, 185 },
160}; 186};
@@ -169,10 +195,53 @@ static struct platform_device keysc_device = {
169 }, 195 },
170}; 196};
171 197
198/* SDHI */
199static struct resource sdhi0_resources[] = {
200 [0] = {
201 .name = "SDHI0",
202 .start = 0xe6d50000,
203 .end = 0xe6d501ff,
204 .flags = IORESOURCE_MEM,
205 },
206 [1] = {
207 .start = evt2irq(0x0e00), /* SDHI0 */
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct platform_device sdhi0_device = {
213 .name = "sh_mobile_sdhi",
214 .num_resources = ARRAY_SIZE(sdhi0_resources),
215 .resource = sdhi0_resources,
216 .id = 0,
217};
218
219static struct resource sdhi1_resources[] = {
220 [0] = {
221 .name = "SDHI1",
222 .start = 0xe6d60000,
223 .end = 0xe6d601ff,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = evt2irq(0x0e80), /* SDHI1 */
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device sdhi1_device = {
233 .name = "sh_mobile_sdhi",
234 .num_resources = ARRAY_SIZE(sdhi1_resources),
235 .resource = sdhi1_resources,
236 .id = 1,
237};
238
172static struct platform_device *g4evm_devices[] __initdata = { 239static struct platform_device *g4evm_devices[] __initdata = {
173 &nor_flash_device, 240 &nor_flash_device,
174 &usb_host_device, 241 &usb_host_device,
175 &keysc_device, 242 &keysc_device,
243 &sdhi0_device,
244 &sdhi1_device,
176}; 245};
177 246
178static struct map_desc g4evm_io_desc[] __initdata = { 247static struct map_desc g4evm_io_desc[] __initdata = {
@@ -191,12 +260,41 @@ static void __init g4evm_map_io(void)
191{ 260{
192 iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); 261 iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
193 262
194 /* setup early devices, clocks and console here as well */ 263 /* setup early devices and console here as well */
195 sh7377_add_early_devices(); 264 sh7377_add_early_devices();
196 sh7367_clock_init(); /* use g3 clocks for now */
197 shmobile_setup_console(); 265 shmobile_setup_console();
198} 266}
199 267
268#define GPIO_SDHID0_D0 0xe60520fc
269#define GPIO_SDHID0_D1 0xe60520fd
270#define GPIO_SDHID0_D2 0xe60520fe
271#define GPIO_SDHID0_D3 0xe60520ff
272#define GPIO_SDHICMD0 0xe6052100
273
274#define GPIO_SDHID1_D0 0xe6052103
275#define GPIO_SDHID1_D1 0xe6052104
276#define GPIO_SDHID1_D2 0xe6052105
277#define GPIO_SDHID1_D3 0xe6052106
278#define GPIO_SDHICMD1 0xe6052107
279
280/*
281 * FIXME !!
282 *
283 * gpio_pull_up is quick_hack.
284 *
285 * current gpio frame work doesn't have
286 * the method to control only pull up/down/free.
287 * this function should be replaced by correct gpio function
288 */
289static void __init gpio_pull_up(u32 addr)
290{
291 u8 data = __raw_readb(addr);
292
293 data &= 0x0F;
294 data |= 0xC0;
295 __raw_writeb(data, addr);
296}
297
200static void __init g4evm_init(void) 298static void __init g4evm_init(void)
201{ 299{
202 sh7377_pinmux_init(); 300 sh7377_pinmux_init();
@@ -229,9 +327,6 @@ static void __init g4evm_init(void)
229 gpio_request(GPIO_FN_EXTLP, NULL); 327 gpio_request(GPIO_FN_EXTLP, NULL);
230 gpio_request(GPIO_FN_IDIN, NULL); 328 gpio_request(GPIO_FN_IDIN, NULL);
231 329
232 /* enable clock in SMSTPCR3 */
233 __raw_writel(__raw_readl(0xe615013c) & ~(1 << 22), 0xe615013c);
234
235 /* setup USB phy */ 330 /* setup USB phy */
236 __raw_writew(0x0200, 0xe605810a); /* USBCR1 */ 331 __raw_writew(0x0200, 0xe605810a); /* USBCR1 */
237 __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ 332 __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
@@ -253,16 +348,54 @@ static void __init g4evm_init(void)
253 gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL); 348 gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
254 gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL); 349 gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
255 350
351 /* SDHI0 */
352 gpio_request(GPIO_FN_SDHICLK0, NULL);
353 gpio_request(GPIO_FN_SDHICD0, NULL);
354 gpio_request(GPIO_FN_SDHID0_0, NULL);
355 gpio_request(GPIO_FN_SDHID0_1, NULL);
356 gpio_request(GPIO_FN_SDHID0_2, NULL);
357 gpio_request(GPIO_FN_SDHID0_3, NULL);
358 gpio_request(GPIO_FN_SDHICMD0, NULL);
359 gpio_request(GPIO_FN_SDHIWP0, NULL);
360 gpio_pull_up(GPIO_SDHID0_D0);
361 gpio_pull_up(GPIO_SDHID0_D1);
362 gpio_pull_up(GPIO_SDHID0_D2);
363 gpio_pull_up(GPIO_SDHID0_D3);
364 gpio_pull_up(GPIO_SDHICMD0);
365
366 /* SDHI1 */
367 gpio_request(GPIO_FN_SDHICLK1, NULL);
368 gpio_request(GPIO_FN_SDHID1_0, NULL);
369 gpio_request(GPIO_FN_SDHID1_1, NULL);
370 gpio_request(GPIO_FN_SDHID1_2, NULL);
371 gpio_request(GPIO_FN_SDHID1_3, NULL);
372 gpio_request(GPIO_FN_SDHICMD1, NULL);
373 gpio_pull_up(GPIO_SDHID1_D0);
374 gpio_pull_up(GPIO_SDHID1_D1);
375 gpio_pull_up(GPIO_SDHID1_D2);
376 gpio_pull_up(GPIO_SDHID1_D3);
377 gpio_pull_up(GPIO_SDHICMD1);
378
256 sh7377_add_standard_devices(); 379 sh7377_add_standard_devices();
257 380
258 platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); 381 platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
259} 382}
260 383
384static void __init g4evm_timer_init(void)
385{
386 sh7377_clock_init();
387 shmobile_timer.init();
388}
389
390static struct sys_timer g4evm_timer = {
391 .init = g4evm_timer_init,
392};
393
261MACHINE_START(G4EVM, "g4evm") 394MACHINE_START(G4EVM, "g4evm")
262 .phys_io = 0xe6000000, 395 .phys_io = 0xe6000000,
263 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, 396 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
264 .map_io = g4evm_map_io, 397 .map_io = g4evm_map_io,
265 .init_irq = sh7377_init_irq, 398 .init_irq = sh7377_init_irq,
266 .init_machine = g4evm_init, 399 .init_machine = g4evm_init,
267 .timer = &shmobile_timer, 400 .timer = &g4evm_timer,
268MACHINE_END 401MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index bb940c6e4e6c..b6454c9f2abb 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Preliminary clock framework support for sh7367 2 * SH7367 clock framework support
3 * 3 *
4 * Copyright (C) 2010 Magnus Damm 4 * Copyright (C) 2010 Magnus Damm
5 * 5 *
@@ -17,87 +17,342 @@
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 18 */
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/kernel.h> 20#include <linux/kernel.h>
22#include <linux/list.h> 21#include <linux/io.h>
23#include <linux/clk.h> 22#include <linux/sh_clk.h>
23#include <mach/common.h>
24#include <asm/clkdev.h>
25
26/* SH7367 registers */
27#define RTFRQCR 0xe6150000
28#define SYFRQCR 0xe6150004
29#define CMFRQCR 0xe61500E0
30#define VCLKCR1 0xe6150008
31#define VCLKCR2 0xe615000C
32#define VCLKCR3 0xe615001C
33#define SCLKACR 0xe6150010
34#define SCLKBCR 0xe6150014
35#define SUBUSBCKCR 0xe6158080
36#define SPUCKCR 0xe6150084
37#define MSUCKCR 0xe6150088
38#define MVI3CKCR 0xe6150090
39#define VOUCKCR 0xe6150094
40#define MFCK1CR 0xe6150098
41#define MFCK2CR 0xe615009C
42#define PLLC1CR 0xe6150028
43#define PLLC2CR 0xe615002C
44#define RTMSTPCR0 0xe6158030
45#define RTMSTPCR2 0xe6158038
46#define SYMSTPCR0 0xe6158040
47#define SYMSTPCR2 0xe6158048
48#define CMMSTPCR0 0xe615804c
24 49
25struct clk { 50/* Fixed 32 KHz root clock from EXTALR pin */
26 const char *name; 51static struct clk r_clk = {
27 unsigned long rate; 52 .rate = 32768,
28}; 53};
29 54
30#include <asm/clkdev.h> 55/*
56 * 26MHz default rate for the EXTALB1 root input clock.
57 * If needed, reset this with clk_set_rate() from the platform code.
58 */
59struct clk sh7367_extalb1_clk = {
60 .rate = 26666666,
61};
31 62
32int __clk_get(struct clk *clk) 63/*
33{ 64 * 48MHz default rate for the EXTAL2 root input clock.
34 return 1; 65 * If needed, reset this with clk_set_rate() from the platform code.
35} 66 */
36EXPORT_SYMBOL(__clk_get); 67struct clk sh7367_extal2_clk = {
68 .rate = 48000000,
69};
37 70
38void __clk_put(struct clk *clk) 71/* A fixed divide-by-2 block */
72static unsigned long div2_recalc(struct clk *clk)
39{ 73{
74 return clk->parent->rate / 2;
40} 75}
41EXPORT_SYMBOL(__clk_put);
42 76
77static struct clk_ops div2_clk_ops = {
78 .recalc = div2_recalc,
79};
80
81/* Divide extalb1 by two */
82static struct clk extalb1_div2_clk = {
83 .ops = &div2_clk_ops,
84 .parent = &sh7367_extalb1_clk,
85};
86
87/* Divide extal2 by two */
88static struct clk extal2_div2_clk = {
89 .ops = &div2_clk_ops,
90 .parent = &sh7367_extal2_clk,
91};
43 92
44int clk_enable(struct clk *clk) 93/* PLLC1 */
94static unsigned long pllc1_recalc(struct clk *clk)
45{ 95{
46 return 0; 96 unsigned long mult = 1;
97
98 if (__raw_readl(PLLC1CR) & (1 << 14))
99 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
100
101 return clk->parent->rate * mult;
47} 102}
48EXPORT_SYMBOL(clk_enable);
49 103
50void clk_disable(struct clk *clk) 104static struct clk_ops pllc1_clk_ops = {
105 .recalc = pllc1_recalc,
106};
107
108static struct clk pllc1_clk = {
109 .ops = &pllc1_clk_ops,
110 .flags = CLK_ENABLE_ON_INIT,
111 .parent = &extalb1_div2_clk,
112};
113
114/* Divide PLLC1 by two */
115static struct clk pllc1_div2_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &pllc1_clk,
118};
119
120/* PLLC2 */
121static unsigned long pllc2_recalc(struct clk *clk)
51{ 122{
123 unsigned long mult = 1;
124
125 if (__raw_readl(PLLC2CR) & (1 << 31))
126 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
127
128 return clk->parent->rate * mult;
52} 129}
53EXPORT_SYMBOL(clk_disable);
54 130
55unsigned long clk_get_rate(struct clk *clk) 131static struct clk_ops pllc2_clk_ops = {
132 .recalc = pllc2_recalc,
133};
134
135static struct clk pllc2_clk = {
136 .ops = &pllc2_clk_ops,
137 .flags = CLK_ENABLE_ON_INIT,
138 .parent = &extalb1_div2_clk,
139};
140
141static struct clk *main_clks[] = {
142 &r_clk,
143 &sh7367_extalb1_clk,
144 &sh7367_extal2_clk,
145 &extalb1_div2_clk,
146 &extal2_div2_clk,
147 &pllc1_clk,
148 &pllc1_div2_clk,
149 &pllc2_clk,
150};
151
152static void div4_kick(struct clk *clk)
56{ 153{
57 return clk ? clk->rate : 0; 154 unsigned long value;
155
156 /* set KICK bit in SYFRQCR to update hardware setting */
157 value = __raw_readl(SYFRQCR);
158 value |= (1 << 31);
159 __raw_writel(value, SYFRQCR);
58} 160}
59EXPORT_SYMBOL(clk_get_rate);
60 161
61/* a static peripheral clock for now - enough to get sh-sci working */ 162static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
62static struct clk peripheral_clk = { 163 24, 32, 36, 48, 0, 72, 0, 0 };
63 .name = "peripheral_clk", 164
64 .rate = 48000000, 165static struct clk_div_mult_table div4_div_mult_table = {
166 .divisors = divisors,
167 .nr_divisors = ARRAY_SIZE(divisors),
65}; 168};
66 169
67/* a static rclk for now - enough to get sh_cmt working */ 170static struct clk_div4_table div4_table = {
68static struct clk r_clk = { 171 .div_mult_table = &div4_div_mult_table,
69 .name = "r_clk", 172 .kick = div4_kick,
70 .rate = 32768, 173};
174
175enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
176 DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
177 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
178
179#define DIV4(_reg, _bit, _mask, _flags) \
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
181
182static struct clk div4_clks[DIV4_NR] = {
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
187 [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
188 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
189 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
190 [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
191 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
192 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
193 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
194 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
195 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
71}; 196};
72 197
73/* a static usb0 for now - enough to get r8a66597 working */ 198enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
74static struct clk usb0_clk = { 199 DIV6_MVI3, DIV6_MF1, DIV6_MF2,
75 .name = "usb0", 200 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
201 DIV6_NR };
202
203static struct clk div6_clks[DIV6_NR] = {
204 [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
205 [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
206 [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
207 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
208 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
209 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
210 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
211 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
212 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
213 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
214 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
215 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
76}; 216};
77 217
78/* a static keysc0 clk for now - enough to get sh_keysc working */ 218enum { RTMSTP001,
79static struct clk keysc0_clk = { 219 RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
80 .name = "keysc0", 220 RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
221 SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
222 SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
223 SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
224 SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
225 CMMSTP003,
226 MSTP_NR };
227
228#define MSTP(_parent, _reg, _bit, _flags) \
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
230
231static struct clk mstp_clks[MSTP_NR] = {
232 [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
233 [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
234 [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
235 [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
236 [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
237 [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
238 [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
239 [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
240 [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
241 [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
242 [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
243 [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
244 [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
245 [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
246 [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
247 [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
248 [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
249 [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
250 [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
251 [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
252 [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
253 [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
254 [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
255 [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
256 [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
257 [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
258 [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
259 [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
81}; 260};
82 261
262#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
263#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
264
83static struct clk_lookup lookups[] = { 265static struct clk_lookup lookups[] = {
84 { 266 /* main clocks */
85 .clk = &peripheral_clk, 267 CLKDEV_CON_ID("r_clk", &r_clk),
86 }, { 268 CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
87 .clk = &r_clk, 269 CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
88 }, { 270 CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
89 .clk = &usb0_clk, 271 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
90 }, { 272 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
91 .clk = &keysc0_clk, 273 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
92 } 274 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
275
276 /* DIV4 clocks */
277 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
278 CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
279 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
280 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
281 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
282 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
283 CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
284 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
285 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
286 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
287 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
288 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
289
290 /* DIV6 clocks */
291 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
292 CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
293 CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
294 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
295 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
296 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
297 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
298 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
299 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
300 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
301 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
302 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
303
304 /* MSTP32 clocks */
305 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
306 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
307 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
308 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
309 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
310 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
311 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
312 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
313 CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
314 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
315 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
316 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
317 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
318 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
319 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
320 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
321 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
322 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
323 CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
324 CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */
325 CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
326 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
327 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
328 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
329 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
330 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
331 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
332 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
333 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
93}; 334};
94 335
95void __init sh7367_clock_init(void) 336void __init sh7367_clock_init(void)
96{ 337{
97 int i; 338 int k, ret = 0;
339
340 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
341 ret = clk_register(main_clks[k]);
342
343 if (!ret)
344 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
345
346 if (!ret)
347 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
348
349 if (!ret)
350 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
351
352 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
98 353
99 for (i = 0; i < ARRAY_SIZE(lookups); i++) { 354 if (!ret)
100 lookups[i].con_id = lookups[i].clk->name; 355 clk_init();
101 clkdev_add(&lookups[i]); 356 else
102 } 357 panic("failed to setup sh7367 clocks\n");
103} 358}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
new file mode 100644
index 000000000000..f2f9a4ad53a4
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -0,0 +1,395 @@
1/*
2 * SH7372 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <mach/common.h>
24#include <asm/clkdev.h>
25
26/* SH7372 registers */
27#define FRQCRA 0xe6150000
28#define FRQCRB 0xe6150004
29#define FRQCRC 0xe61500e0
30#define FRQCRD 0xe61500e4
31#define VCLKCR1 0xe6150008
32#define VCLKCR2 0xe615000c
33#define VCLKCR3 0xe615001c
34#define FMSICKCR 0xe6150010
35#define FMSOCKCR 0xe6150014
36#define FSIACKCR 0xe6150018
37#define FSIBCKCR 0xe6150090
38#define SUBCKCR 0xe6150080
39#define SPUCKCR 0xe6150084
40#define VOUCKCR 0xe6150088
41#define HDMICKCR 0xe6150094
42#define DSITCKCR 0xe6150060
43#define DSI0PCKCR 0xe6150064
44#define DSI1PCKCR 0xe6150098
45#define PLLC01CR 0xe6150028
46#define PLLC2CR 0xe615002c
47#define SMSTPCR0 0xe6150130
48#define SMSTPCR1 0xe6150134
49#define SMSTPCR2 0xe6150138
50#define SMSTPCR3 0xe615013c
51#define SMSTPCR4 0xe6150140
52
53/* Fixed 32 KHz root clock from EXTALR pin */
54static struct clk r_clk = {
55 .rate = 32768,
56};
57
58/*
59 * 26MHz default rate for the EXTAL1 root input clock.
60 * If needed, reset this with clk_set_rate() from the platform code.
61 */
62struct clk sh7372_extal1_clk = {
63 .rate = 26666666,
64};
65
66/*
67 * 48MHz default rate for the EXTAL2 root input clock.
68 * If needed, reset this with clk_set_rate() from the platform code.
69 */
70struct clk sh7372_extal2_clk = {
71 .rate = 48000000,
72};
73
74/* A fixed divide-by-2 block */
75static unsigned long div2_recalc(struct clk *clk)
76{
77 return clk->parent->rate / 2;
78}
79
80static struct clk_ops div2_clk_ops = {
81 .recalc = div2_recalc,
82};
83
84/* Divide extal1 by two */
85static struct clk extal1_div2_clk = {
86 .ops = &div2_clk_ops,
87 .parent = &sh7372_extal1_clk,
88};
89
90/* Divide extal2 by two */
91static struct clk extal2_div2_clk = {
92 .ops = &div2_clk_ops,
93 .parent = &sh7372_extal2_clk,
94};
95
96/* Divide extal2 by four */
97static struct clk extal2_div4_clk = {
98 .ops = &div2_clk_ops,
99 .parent = &extal2_div2_clk,
100};
101
102/* PLLC0 and PLLC1 */
103static unsigned long pllc01_recalc(struct clk *clk)
104{
105 unsigned long mult = 1;
106
107 if (__raw_readl(PLLC01CR) & (1 << 14))
108 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
109
110 return clk->parent->rate * mult;
111}
112
113static struct clk_ops pllc01_clk_ops = {
114 .recalc = pllc01_recalc,
115};
116
117static struct clk pllc0_clk = {
118 .ops = &pllc01_clk_ops,
119 .flags = CLK_ENABLE_ON_INIT,
120 .parent = &extal1_div2_clk,
121 .enable_reg = (void __iomem *)FRQCRC,
122};
123
124static struct clk pllc1_clk = {
125 .ops = &pllc01_clk_ops,
126 .flags = CLK_ENABLE_ON_INIT,
127 .parent = &extal1_div2_clk,
128 .enable_reg = (void __iomem *)FRQCRA,
129};
130
131/* Divide PLLC1 by two */
132static struct clk pllc1_div2_clk = {
133 .ops = &div2_clk_ops,
134 .parent = &pllc1_clk,
135};
136
137/* PLLC2 */
138static unsigned long pllc2_recalc(struct clk *clk)
139{
140 unsigned long mult = 1;
141
142 if (__raw_readl(PLLC2CR) & (1 << 31))
143 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
144
145 return clk->parent->rate * mult;
146}
147
148static struct clk_ops pllc2_clk_ops = {
149 .recalc = pllc2_recalc,
150};
151
152static struct clk pllc2_clk = {
153 .ops = &pllc2_clk_ops,
154 .flags = CLK_ENABLE_ON_INIT,
155 .parent = &extal1_div2_clk,
156};
157
158static struct clk *main_clks[] = {
159 &r_clk,
160 &sh7372_extal1_clk,
161 &sh7372_extal2_clk,
162 &extal1_div2_clk,
163 &extal2_div2_clk,
164 &extal2_div4_clk,
165 &pllc0_clk,
166 &pllc1_clk,
167 &pllc1_div2_clk,
168 &pllc2_clk,
169};
170
171static void div4_kick(struct clk *clk)
172{
173 unsigned long value;
174
175 /* set KICK bit in FRQCRB to update hardware setting */
176 value = __raw_readl(FRQCRB);
177 value |= (1 << 31);
178 __raw_writel(value, FRQCRB);
179}
180
181static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
182 24, 32, 36, 48, 0, 72, 96, 0 };
183
184static struct clk_div_mult_table div4_div_mult_table = {
185 .divisors = divisors,
186 .nr_divisors = ARRAY_SIZE(divisors),
187};
188
189static struct clk_div4_table div4_table = {
190 .div_mult_table = &div4_div_mult_table,
191 .kick = div4_kick,
192};
193
194enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
195 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
196 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
197 DIV4_DDRP, DIV4_NR };
198
199#define DIV4(_reg, _bit, _mask, _flags) \
200 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
201
202static struct clk div4_clks[DIV4_NR] = {
203 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
204 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
205 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
206 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
207 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
208 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
209 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
210 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
211 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
212 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
213 [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
214 [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
215 [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
216 [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
217 [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
218};
219
220enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
221 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
222 DIV6_VOU, DIV6_HDMI, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
223 DIV6_NR };
224
225static struct clk div6_clks[DIV6_NR] = {
226 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
227 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
228 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
229 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
230 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
231 [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
232 [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
233 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
234 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
235 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
236 [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
237 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
238 [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
239 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
240};
241
242enum { MSTP001,
243 MSTP131, MSTP130,
244 MSTP129, MSTP128,
245 MSTP118, MSTP117, MSTP116,
246 MSTP106, MSTP101, MSTP100,
247 MSTP223,
248 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
249 MSTP329, MSTP323, MSTP322, MSTP314, MSTP313,
250 MSTP415, MSTP410, MSTP411, MSTP406, MSTP403,
251 MSTP_NR };
252
253#define MSTP(_parent, _reg, _bit, _flags) \
254 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
255
256static struct clk mstp_clks[MSTP_NR] = {
257 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
258 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
259 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
260 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
261 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
262 [MSTP118] = MSTP(&div6_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
263 [MSTP117] = MSTP(&div6_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
264 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
265 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
266 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
267 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
268 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
269 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
270 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
271 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
272 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
273 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
274 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
275 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
276 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
277 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
278 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
279 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
280 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
281 [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
282 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
283 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
284 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
285 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
286};
287
288#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
289#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
290
291static struct clk_lookup lookups[] = {
292 /* main clocks */
293 CLKDEV_CON_ID("r_clk", &r_clk),
294 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
295 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
296 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
297 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
298 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
299 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
300 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
301 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
302 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
303
304 /* DIV4 clocks */
305 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
306 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
307 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
308 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
309 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
310 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
311 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
312 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
313 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
314 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
315 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
316 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
317 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
318 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
319 CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
320
321 /* DIV6 clocks */
322 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
323 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
324 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
325 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
326 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
327 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
328 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
329 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
330 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
331 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
332 CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
333 CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
334 CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
335 CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
336
337 /* MSTP32 clocks */
338 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
339 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
340 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
341 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
342 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
343 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
344 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
345 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
346 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
347 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
348 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
349 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
350 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
351 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
352 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
353 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
354 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
355 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
356 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
357 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
358 CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
359 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
360 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
361 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
362 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
363 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
364 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
365 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
366 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
367 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
368 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
369 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
370};
371
372void __init sh7372_clock_init(void)
373{
374 int k, ret = 0;
375
376 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
377 ret = clk_register(main_clks[k]);
378
379 if (!ret)
380 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
381
382 if (!ret)
383 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
384
385 if (!ret)
386 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
387
388 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
389
390 if (!ret)
391 clk_init();
392 else
393 panic("failed to setup sh7372 clocks\n");
394
395}
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
new file mode 100644
index 000000000000..e007c28cf0a8
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -0,0 +1,369 @@
1/*
2 * SH7377 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <mach/common.h>
24#include <asm/clkdev.h>
25
26/* SH7377 registers */
27#define RTFRQCR 0xe6150000
28#define SYFRQCR 0xe6150004
29#define CMFRQCR 0xe61500E0
30#define VCLKCR1 0xe6150008
31#define VCLKCR2 0xe615000C
32#define VCLKCR3 0xe615001C
33#define FMSICKCR 0xe6150010
34#define FMSOCKCR 0xe6150014
35#define FSICKCR 0xe6150018
36#define PLLC1CR 0xe6150028
37#define PLLC2CR 0xe615002C
38#define SUBUSBCKCR 0xe6150080
39#define SPUCKCR 0xe6150084
40#define MSUCKCR 0xe6150088
41#define MVI3CKCR 0xe6150090
42#define HDMICKCR 0xe6150094
43#define MFCK1CR 0xe6150098
44#define MFCK2CR 0xe615009C
45#define DSITCKCR 0xe6150060
46#define DSIPCKCR 0xe6150064
47#define SMSTPCR0 0xe6150130
48#define SMSTPCR1 0xe6150134
49#define SMSTPCR2 0xe6150138
50#define SMSTPCR3 0xe615013C
51#define SMSTPCR4 0xe6150140
52
53/* Fixed 32 KHz root clock from EXTALR pin */
54static struct clk r_clk = {
55 .rate = 32768,
56};
57
58/*
59 * 26MHz default rate for the EXTALC1 root input clock.
60 * If needed, reset this with clk_set_rate() from the platform code.
61 */
62struct clk sh7377_extalc1_clk = {
63 .rate = 26666666,
64};
65
66/*
67 * 48MHz default rate for the EXTAL2 root input clock.
68 * If needed, reset this with clk_set_rate() from the platform code.
69 */
70struct clk sh7377_extal2_clk = {
71 .rate = 48000000,
72};
73
74/* A fixed divide-by-2 block */
75static unsigned long div2_recalc(struct clk *clk)
76{
77 return clk->parent->rate / 2;
78}
79
80static struct clk_ops div2_clk_ops = {
81 .recalc = div2_recalc,
82};
83
84/* Divide extalc1 by two */
85static struct clk extalc1_div2_clk = {
86 .ops = &div2_clk_ops,
87 .parent = &sh7377_extalc1_clk,
88};
89
90/* Divide extal2 by two */
91static struct clk extal2_div2_clk = {
92 .ops = &div2_clk_ops,
93 .parent = &sh7377_extal2_clk,
94};
95
96/* Divide extal2 by four */
97static struct clk extal2_div4_clk = {
98 .ops = &div2_clk_ops,
99 .parent = &extal2_div2_clk,
100};
101
102/* PLLC1 */
103static unsigned long pllc1_recalc(struct clk *clk)
104{
105 unsigned long mult = 1;
106
107 if (__raw_readl(PLLC1CR) & (1 << 14))
108 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
109
110 return clk->parent->rate * mult;
111}
112
113static struct clk_ops pllc1_clk_ops = {
114 .recalc = pllc1_recalc,
115};
116
117static struct clk pllc1_clk = {
118 .ops = &pllc1_clk_ops,
119 .flags = CLK_ENABLE_ON_INIT,
120 .parent = &extalc1_div2_clk,
121};
122
123/* Divide PLLC1 by two */
124static struct clk pllc1_div2_clk = {
125 .ops = &div2_clk_ops,
126 .parent = &pllc1_clk,
127};
128
129/* PLLC2 */
130static unsigned long pllc2_recalc(struct clk *clk)
131{
132 unsigned long mult = 1;
133
134 if (__raw_readl(PLLC2CR) & (1 << 31))
135 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
136
137 return clk->parent->rate * mult;
138}
139
140static struct clk_ops pllc2_clk_ops = {
141 .recalc = pllc2_recalc,
142};
143
144static struct clk pllc2_clk = {
145 .ops = &pllc2_clk_ops,
146 .flags = CLK_ENABLE_ON_INIT,
147 .parent = &extalc1_div2_clk,
148};
149
150static struct clk *main_clks[] = {
151 &r_clk,
152 &sh7377_extalc1_clk,
153 &sh7377_extal2_clk,
154 &extalc1_div2_clk,
155 &extal2_div2_clk,
156 &extal2_div4_clk,
157 &pllc1_clk,
158 &pllc1_div2_clk,
159 &pllc2_clk,
160};
161
162static void div4_kick(struct clk *clk)
163{
164 unsigned long value;
165
166 /* set KICK bit in SYFRQCR to update hardware setting */
167 value = __raw_readl(SYFRQCR);
168 value |= (1 << 31);
169 __raw_writel(value, SYFRQCR);
170}
171
172static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
173 24, 32, 36, 48, 0, 72, 96, 0 };
174
175static struct clk_div_mult_table div4_div_mult_table = {
176 .divisors = divisors,
177 .nr_divisors = ARRAY_SIZE(divisors),
178};
179
180static struct clk_div4_table div4_table = {
181 .div_mult_table = &div4_div_mult_table,
182 .kick = div4_kick,
183};
184
185enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
186 DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
187 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
188
189#define DIV4(_reg, _bit, _mask, _flags) \
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
191
192static struct clk div4_clks[DIV4_NR] = {
193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
194 [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
196 [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
197 [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
198 [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
199 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
200 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
201 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
202 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
203 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
204 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
205 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
206};
207
208enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
209 DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
210 DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
211 DIV6_NR };
212
213static struct clk div6_clks[] = {
214 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
215 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
216 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
217 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
218 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
219 [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
220 [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
221 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
222 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
223 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
224 [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
225 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
226 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
227 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
228 [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
229};
230
231enum { MSTP001,
232 MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
233 MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
234 MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
235 MSTP315, MSTP314, MSTP313,
236 MSTP403,
237 MSTP_NR };
238
239#define MSTP(_parent, _reg, _bit, _flags) \
240 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
241
242static struct clk mstp_clks[] = {
243 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
244 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
245 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
246 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
247 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
248 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
249 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
250 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
251 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
252 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
253 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
254 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
255 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
256 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
257 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
258 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
259 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
260 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
261 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
262 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
263 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
264 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
265 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
266 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
267 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
268};
269
270#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
271#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
272
273static struct clk_lookup lookups[] = {
274 /* main clocks */
275 CLKDEV_CON_ID("r_clk", &r_clk),
276 CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
277 CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
278 CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
279 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
280 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
281 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
282 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
283 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
284
285 /* DIV4 clocks */
286 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
287 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
288 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
289 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
290 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
291 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
292 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
293 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
294 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
295 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
296 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
297 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
298 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
299
300 /* DIV6 clocks */
301 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
302 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
303 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
304 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
305 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
306 CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
307 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
308 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
309 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
310 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
311 CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
312 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
313 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
314 CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
315 CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
316
317 /* MSTP32 clocks */
318 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
319 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
320 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
321 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
322 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
323 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
324 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
325 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
326 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
327 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
328 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
329 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
330 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
331 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
332 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
333 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
334 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
335 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
336 CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
337 CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
338 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
339 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
340 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
341 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
342 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
343 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
344 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
345};
346
347void __init sh7377_clock_init(void)
348{
349 int k, ret = 0;
350
351 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
352 ret = clk_register(main_clks[k]);
353
354 if (!ret)
355 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
356
357 if (!ret)
358 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
359
360 if (!ret)
361 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
362
363 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
364
365 if (!ret)
366 clk_init();
367 else
368 panic("failed to setup sh7377 clocks\n");
369}
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
new file mode 100644
index 000000000000..b7c705a213a2
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock.c
@@ -0,0 +1,44 @@
1/*
2 * SH-Mobile Timer
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/sh_clk.h>
23
24int __init clk_init(void)
25{
26 /* Kick the child clocks.. */
27 recalculate_root_clocks();
28
29 /* Enable the necessary init clocks */
30 clk_enable_init_clocks();
31
32 return 0;
33}
34
35int __clk_get(struct clk *clk)
36{
37 return 1;
38}
39EXPORT_SYMBOL(__clk_get);
40
41void __clk_put(struct clk *clk)
42{
43}
44EXPORT_SYMBOL(__clk_put);
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 57903605cc51..efeef778a875 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -3,21 +3,31 @@
3 3
4extern struct sys_timer shmobile_timer; 4extern struct sys_timer shmobile_timer;
5extern void shmobile_setup_console(void); 5extern void shmobile_setup_console(void);
6struct clk;
7extern int clk_init(void);
6 8
7extern void sh7367_init_irq(void); 9extern void sh7367_init_irq(void);
8extern void sh7367_add_early_devices(void); 10extern void sh7367_add_early_devices(void);
9extern void sh7367_add_standard_devices(void); 11extern void sh7367_add_standard_devices(void);
10extern void sh7367_clock_init(void); 12extern void sh7367_clock_init(void);
11extern void sh7367_pinmux_init(void); 13extern void sh7367_pinmux_init(void);
14extern struct clk sh7367_extalb1_clk;
15extern struct clk sh7367_extal2_clk;
12 16
13extern void sh7377_init_irq(void); 17extern void sh7377_init_irq(void);
14extern void sh7377_add_early_devices(void); 18extern void sh7377_add_early_devices(void);
15extern void sh7377_add_standard_devices(void); 19extern void sh7377_add_standard_devices(void);
20extern void sh7377_clock_init(void);
16extern void sh7377_pinmux_init(void); 21extern void sh7377_pinmux_init(void);
22extern struct clk sh7377_extalc1_clk;
23extern struct clk sh7377_extal2_clk;
17 24
18extern void sh7372_init_irq(void); 25extern void sh7372_init_irq(void);
19extern void sh7372_add_early_devices(void); 26extern void sh7372_add_early_devices(void);
20extern void sh7372_add_standard_devices(void); 27extern void sh7372_add_standard_devices(void);
28extern void sh7372_clock_init(void);
21extern void sh7372_pinmux_init(void); 29extern void sh7372_pinmux_init(void);
30extern struct clk sh7372_extal1_clk;
31extern struct clk sh7372_extal2_clk;
22 32
23#endif /* __ARCH_MACH_COMMON_H */ 33#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 5179b72e1ee3..e881797648a9 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -4,7 +4,13 @@
4#define NR_IRQS 512 4#define NR_IRQS 512
5#define NR_IRQS_LEGACY 8 5#define NR_IRQS_LEGACY 8
6 6
7/* INTCA */
7#define evt2irq(evt) (((evt) >> 5) - 16) 8#define evt2irq(evt) (((evt) >> 5) - 16)
8#define irq2evt(irq) (((irq) + 16) << 5) 9#define irq2evt(irq) (((irq) + 16) << 5)
9 10
11/* INTCS */
12#define INTCS_VECT_BASE 0x2200
13#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
14#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
15
10#endif /* __ASM_MACH_IRQS_H */ 16#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
index e188183f4dce..377584e57e03 100644
--- a/arch/arm/mach-shmobile/include/mach/memory.h
+++ b/arch/arm/mach-shmobile/include/mach/memory.h
@@ -4,4 +4,7 @@
4#define PHYS_OFFSET UL(CONFIG_MEMORY_START) 4#define PHYS_OFFSET UL(CONFIG_MEMORY_START)
5#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) 5#define MEM_SIZE UL(CONFIG_MEMORY_SIZE)
6 6
7/* DMA memory at 0xf6000000 - 0xffdfffff */
8#define CONSISTENT_DMA_SIZE (158 << 20)
9
7#endif /* __ASM_MACH_MEMORY_H */ 10#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
index fb3c4f1ab252..4aecf6e3a859 100644
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -1,6 +1,7 @@
1#ifndef __ASM_MACH_VMALLOC_H 1#ifndef __ASM_MACH_VMALLOC_H
2#define __ASM_MACH_VMALLOC_H 2#define __ASM_MACH_VMALLOC_H
3 3
4#define VMALLOC_END (PAGE_OFFSET + 0x24000000) 4/* Vmalloc at ... - 0xe5ffffff */
5#define VMALLOC_END 0xe6000000
5 6
6#endif /* __ASM_MACH_VMALLOC_H */ 7#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index 5ff70cadfc32..1a20c489b20d 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -75,7 +75,7 @@ enum {
75 ETM11, ARM11, USBHS, FLCTL, IIC1 75 ETM11, ARM11, USBHS, FLCTL, IIC1
76}; 76};
77 77
78static struct intc_vect intca_vectors[] = { 78static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), 79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), 80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), 81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
@@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = {
162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
163}; 163};
164 164
165static struct intc_mask_reg intca_mask_registers[] = { 165static struct intc_mask_reg intca_mask_registers[] __initdata = {
166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ 166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ 168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
@@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
211 MISTY, CMT3, RWDT1, RWDT0 } }, 211 MISTY, CMT3, RWDT1, RWDT0 } },
212}; 212};
213 213
214static struct intc_prio_reg intca_prio_registers[] = { 214static struct intc_prio_reg intca_prio_registers[] __initdata = {
215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */ 215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */ 217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
@@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = {
263 intca_sense_registers, intca_ack_registers), 263 intca_sense_registers, intca_ack_registers),
264}; 264};
265 265
266enum {
267 UNUSED_INTCS = 0,
268
269 INTCS,
270
271 /* interrupt sources INTCS */
272 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
273 VIO3_VOU,
274 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
275 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
276 VPU,
277 SGX530,
278 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
279 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
280 IPMMU_IPMMUB, IPMMU_IPMMUS,
281 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
282 MSIOF,
283 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
284 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
285 CMT,
286 TSIF,
287 IPMMUI,
288 MVI3,
289 ICB,
290 PEP,
291 ASA,
292 BEM,
293 VE2HO,
294 HQE,
295 JPEG,
296 LCDC,
297
298 /* interrupt groups INTCS */
299 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
300};
301
302static struct intc_vect intcs_vectors[] = {
303 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
304 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
305 INTCS_VECT(VIO3_VOU, 0x780),
306 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
307 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
308 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
309 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
310 INTCS_VECT(VPU, 0x980),
311 INTCS_VECT(SGX530, 0x9e0),
312 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
313 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
314 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
315 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
316 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
317 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
318 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
319 INTCS_VECT(MSIOF, 0xd20),
320 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
321 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
322 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
323 INTCS_VECT(TMU_TUNI2, 0xec0),
324 INTCS_VECT(CMT, 0xf00),
325 INTCS_VECT(TSIF, 0xf20),
326 INTCS_VECT(IPMMUI, 0xf60),
327 INTCS_VECT(MVI3, 0x420),
328 INTCS_VECT(ICB, 0x480),
329 INTCS_VECT(PEP, 0x4a0),
330 INTCS_VECT(ASA, 0x4c0),
331 INTCS_VECT(BEM, 0x4e0),
332 INTCS_VECT(VE2HO, 0x520),
333 INTCS_VECT(HQE, 0x540),
334 INTCS_VECT(JPEG, 0x560),
335 INTCS_VECT(LCDC, 0x580),
336
337 INTC_VECT(INTCS, 0xf80),
338};
339
340static struct intc_group intcs_groups[] __initdata = {
341 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
342 _2DDMAC_2DDM2, _2DDMAC_2DDM3),
343 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
344 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
345 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
346 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
347 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
348 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
349 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
350 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
351};
352
353static struct intc_mask_reg intcs_mask_registers[] = {
354 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
355 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
356 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
357 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
358 { VIO3_VOU, 0, VE2HO, VPU,
359 0, 0, 0, 0 } },
360 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
361 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
362 BEM, ASA, PEP, ICB } },
363 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
364 { 0, 0, MVI3, 0,
365 JPEG, HQE, 0, LCDC } },
366 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
367 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
368 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
369 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
370 { 0, 0, MSIOF, 0,
371 SGX530, 0, 0, 0 } },
372 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
373 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
374 0, 0, 0, 0 } },
375 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
376 { 0, 0, 0, CMT,
377 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
378 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
379 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
380 0, 0, 0, 0 } },
381 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
382 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
383 0, 0, IPMMUI, TSIF } },
384 { 0xffd20104, 0, 16, /* INTAMASK */
385 { 0, 0, 0, 0, 0, 0, 0, 0,
386 0, 0, 0, 0, 0, 0, 0, INTCS } },
387};
388
389/* Priority is needed for INTCA to receive the INTCS interrupt */
390static struct intc_prio_reg intcs_prio_registers[] = {
391 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
392 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
393 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
394 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
395 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
396 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
397 TMU_TUNI2, 0 } },
398 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
399 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
400 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
401 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
402 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
403 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
404};
405
406static struct resource intcs_resources[] __initdata = {
407 [0] = {
408 .start = 0xffd20000,
409 .end = 0xffd2ffff,
410 .flags = IORESOURCE_MEM,
411 }
412};
413
414static struct intc_desc intcs_desc __initdata = {
415 .name = "sh7367-intcs",
416 .resource = intcs_resources,
417 .num_resources = ARRAY_SIZE(intcs_resources),
418 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
419 intcs_prio_registers, NULL, NULL),
420};
421
422static void intcs_demux(unsigned int irq, struct irq_desc *desc)
423{
424 void __iomem *reg = (void *)get_irq_data(irq);
425 unsigned int evtcodeas = ioread32(reg);
426
427 generic_handle_irq(intcs_evt2irq(evtcodeas));
428}
429
266void __init sh7367_init_irq(void) 430void __init sh7367_init_irq(void)
267{ 431{
268 /* INTCA */ 432 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
433
269 register_intc_controller(&intca_desc); 434 register_intc_controller(&intca_desc);
435 register_intc_controller(&intcs_desc);
436
437 /* demux using INTEVTSA */
438 set_irq_data(evt2irq(0xf80), (void *)intevtsa);
439 set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
270} 440}
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 3ce9d9bd5899..e3551b56cd03 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
319 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, 319 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
320 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, 320 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
321 CMT14, CMT15 } }, 321 CMT14, CMT15 } },
322 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, 322 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
323 MMC_MMC_ERR, MMC_MMC_NOR } }, 323 MMC_MMC_ERR, MMC_MMC_NOR } },
324 { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, 324 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
325 IIC4_WAITI4, IIC4_DTEI4 } }, 325 IIC4_WAITI4, IIC4_DTEI4 } },
326 { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, 326 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
327 IIC3_WAITI3, IIC3_DTEI3 } }, 327 IIC3_WAITI3, IIC3_DTEI3 } },
328 { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, 328 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
329 0/*TXI*/, 0/*TEI*/} }, 329 0/*TXI*/, 0/*TEI*/} },
330 { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, 330 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
331 USB1_USB1I1, USB1_USB1I0 } }, 331 USB1_USB1I1, USB1_USB1I0 } },
332 { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, 332 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
333}; 333};
334 334
335static struct intc_sense_reg intca_sense_registers[] __initdata = { 335static struct intc_sense_reg intca_sense_registers[] __initdata = {
@@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = {
363 intca_sense_registers, intca_ack_registers), 363 intca_sense_registers, intca_ack_registers),
364}; 364};
365 365
366enum {
367 UNUSED_INTCS = 0,
368
369 INTCS,
370
371 /* interrupt sources INTCS */
372 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
373 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
374 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
375 VPU,
376 TSIF1,
377 _3DG_SGX530,
378 _2DDMAC,
379 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
380 IPMMU_IPMMUR, IPMMU_IPMMUR2,
381 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
382 MSIOF,
383 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
384 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
385 CMT0,
386 TSIF0,
387 LMB,
388 CTI,
389 ICB,
390 JPU_JPEG,
391 LCDC,
392 LCRC,
393 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
394 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
395 ISP,
396 LCDC1,
397 CSIRX,
398 DSITX_DSITX0,
399 DSITX_DSITX1,
400 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
401 CMT4,
402 DSITX1_DSITX1_0,
403 DSITX1_DSITX1_1,
404 CPORTS2R,
405 JPU6E,
406
407 /* interrupt groups INTCS */
408 RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
409 RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
410};
411
412static struct intc_vect intcs_vectors[] = {
413 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
414 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
415 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
416 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
417 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
418 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
419 INTCS_VECT(VPU, 0x980),
420 INTCS_VECT(TSIF1, 0x9a0),
421 INTCS_VECT(_3DG_SGX530, 0x9e0),
422 INTCS_VECT(_2DDMAC, 0xa00),
423 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
424 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
425 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
426 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
427 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
428 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
429 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
430 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
431 INTCS_VECT(TMU_TUNI2, 0xec0),
432 INTCS_VECT(CMT0, 0xf00),
433 INTCS_VECT(TSIF0, 0xf20),
434 INTCS_VECT(LMB, 0xf60),
435 INTCS_VECT(CTI, 0x400),
436 INTCS_VECT(ICB, 0x480),
437 INTCS_VECT(JPU_JPEG, 0x560),
438 INTCS_VECT(LCDC, 0x580),
439 INTCS_VECT(LCRC, 0x5a0),
440 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
441 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
442 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
443 INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
444 INTCS_VECT(ISP, 0x1720),
445 INTCS_VECT(LCDC1, 0x1780),
446 INTCS_VECT(CSIRX, 0x17a0),
447 INTCS_VECT(DSITX_DSITX0, 0x17c0),
448 INTCS_VECT(DSITX_DSITX1, 0x17e0),
449 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
450 INTCS_VECT(TMU1_TUNI2, 0x1940),
451 INTCS_VECT(CMT4, 0x1980),
452 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
453 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
454 INTCS_VECT(CPORTS2R, 0x1a20),
455 INTCS_VECT(JPU6E, 0x1a80),
456
457 INTC_VECT(INTCS, 0xf80),
458};
459
460static struct intc_group intcs_groups[] __initdata = {
461 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
462 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
463 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
464 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
465 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
466 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
467 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
468 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
469 INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
470 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
471 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
472 RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
473 INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
474 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
475};
476
477static struct intc_mask_reg intcs_mask_registers[] = {
478 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
479 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
480 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
481 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
482 { 0, 0, 0, VPU,
483 0, 0, 0, 0 } },
484 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
485 { 0, 0, 0, _2DDMAC,
486 0, 0, 0, ICB } },
487 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
488 { 0, 0, 0, CTI,
489 JPU_JPEG, 0, LCRC, LCDC } },
490 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
491 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
492 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
493 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
494 { 0, 0, MSIOF, 0,
495 _3DG_SGX530, 0, 0, 0 } },
496 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
497 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
498 0, 0, 0, 0 } },
499 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
500 { 0, 0, 0, CMT0,
501 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
502 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
503 { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
504 0, 0, 0, 0 } },
505 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
506 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
507 0, TSIF1, LMB, TSIF0 } },
508 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
509 { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
510 RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
511 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
512 { 0, ISP, 0, 0,
513 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
514 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
515 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
516 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
517 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
518 { 0, CPORTS2R, 0, 0,
519 JPU6E, 0, 0, 0 } },
520 { 0xffd20104, 0, 16, /* INTAMASK */
521 { 0, 0, 0, 0, 0, 0, 0, 0,
522 0, 0, 0, 0, 0, 0, 0, INTCS } },
523};
524
525/* Priority is needed for INTCA to receive the INTCS interrupt */
526static struct intc_prio_reg intcs_prio_registers[] = {
527 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
528 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
529 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
530 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
531 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
532 TMU_TUNI2, TSIF1 } },
533 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
534 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
535 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
536 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
537 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
538 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
539 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
540 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
541 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
542 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
543 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
544 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
545 DSITX1_DSITX1_1, 0 } },
546 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
547 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
548};
549
550static struct resource intcs_resources[] __initdata = {
551 [0] = {
552 .start = 0xffd20000,
553 .end = 0xffd201ff,
554 .flags = IORESOURCE_MEM,
555 },
556 [1] = {
557 .start = 0xffd50000,
558 .end = 0xffd501ff,
559 .flags = IORESOURCE_MEM,
560 }
561};
562
563static struct intc_desc intcs_desc __initdata = {
564 .name = "sh7372-intcs",
565 .resource = intcs_resources,
566 .num_resources = ARRAY_SIZE(intcs_resources),
567 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
568 intcs_prio_registers, NULL, NULL),
569};
570
571static void intcs_demux(unsigned int irq, struct irq_desc *desc)
572{
573 void __iomem *reg = (void *)get_irq_data(irq);
574 unsigned int evtcodeas = ioread32(reg);
575
576 generic_handle_irq(intcs_evt2irq(evtcodeas));
577}
578
366void __init sh7372_init_irq(void) 579void __init sh7372_init_irq(void)
367{ 580{
581 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
582
368 register_intc_controller(&intca_desc); 583 register_intc_controller(&intca_desc);
584 register_intc_controller(&intcs_desc);
585
586 /* demux using INTEVTSA */
587 set_irq_data(evt2irq(0xf80), (void *)intevtsa);
588 set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
369} 589}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index 5c781e2d1897..2cdeb8ccd821 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -90,7 +90,7 @@ enum {
90 ICUSB, ICUDMC 90 ICUSB, ICUDMC
91}; 91};
92 92
93static struct intc_vect intca_vectors[] = { 93static struct intc_vect intca_vectors[] __initdata = {
94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), 94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), 95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), 96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
@@ -202,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = {
202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), 202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
203}; 203};
204 204
205static struct intc_mask_reg intca_mask_registers[] = { 205static struct intc_mask_reg intca_mask_registers[] __initdata = {
206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ 206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ 208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
@@ -272,7 +272,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
272 SCIFA6, 0, 0, 0 } }, 272 SCIFA6, 0, 0, 0 } },
273}; 273};
274 274
275static struct intc_prio_reg intca_prio_registers[] = { 275static struct intc_prio_reg intca_prio_registers[] __initdata = {
276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */ 276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */ 278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
@@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = {
346 intca_sense_registers, intca_ack_registers), 346 intca_sense_registers, intca_ack_registers),
347}; 347};
348 348
349/* this macro ignore entry which is also in INTCA */
350#define __IGNORE(a...)
351#define __IGNORE0(a...) 0
352
353enum {
354 UNUSED_INTCS = 0,
355
356 INTCS,
357
358 /* interrupt sources INTCS */
359 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
360 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
361 CEU,
362 BEU_BEU0, BEU_BEU1, BEU_BEU2,
363 __IGNORE(MFI)
364 __IGNORE(BBIF2)
365 VPU,
366 TSIF1,
367 __IGNORE(SGX540)
368 _2DDMAC,
369 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
370 IPMMU_IPMMUR, IPMMU_IPMMUR2,
371 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
372 __IGNORE(KEYSC)
373 __IGNORE(TTI20)
374 __IGNORE(MSIOF)
375 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
376 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
377 CMT0,
378 TSIF0,
379 __IGNORE(CMT2)
380 LMB,
381 __IGNORE(MSUG)
382 __IGNORE(MSU_MSU, MSU_MSU2)
383 __IGNORE(CTI)
384 MVI3,
385 __IGNORE(RWDT0)
386 __IGNORE(RWDT1)
387 ICB,
388 PEP,
389 ASA,
390 __IGNORE(_2DG)
391 HQE,
392 JPU,
393 LCDC0,
394 __IGNORE(LCRC)
395 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
396 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
397 FRC,
398 LCDC1,
399 CSIRX,
400 DSITX_DSITX0, DSITX_DSITX1,
401 __IGNORE(SPU2_SPU0, SPU2_SPU1)
402 __IGNORE(FSI)
403 __IGNORE(FMSI)
404 __IGNORE(SCUV)
405 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
406 TSIF2,
407 CMT4,
408 __IGNORE(MFIS2)
409 CPORTS2R,
410
411 /* interrupt groups INTCS */
412 RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
413 IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
414};
415
416#define INTCS_INTVECT 0x0F80
417static struct intc_vect intcs_vectors[] __initdata = {
418 INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
419 INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
420 INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
421 INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
422 INTCS_VECT(CEU, 0x0880),
423 INTCS_VECT(BEU_BEU0, 0x08A0),
424 INTCS_VECT(BEU_BEU1, 0x08C0),
425 INTCS_VECT(BEU_BEU2, 0x08E0),
426 __IGNORE(INTCS_VECT(MFI, 0x0900))
427 __IGNORE(INTCS_VECT(BBIF2, 0x0960))
428 INTCS_VECT(VPU, 0x0980),
429 INTCS_VECT(TSIF1, 0x09A0),
430 __IGNORE(INTCS_VECT(SGX540, 0x09E0))
431 INTCS_VECT(_2DDMAC, 0x0A00),
432 INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
433 INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
434 INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
435 INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
436 INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
437 INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
438 __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
439 __IGNORE(INTCS_VECT(TTI20, 0x0C80))
440 __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
441 INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
442 INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
443 INTCS_VECT(TMU_TUNI0, 0x0E80),
444 INTCS_VECT(TMU_TUNI1, 0x0EA0),
445 INTCS_VECT(TMU_TUNI2, 0x0EC0),
446 INTCS_VECT(CMT0, 0x0F00),
447 INTCS_VECT(TSIF0, 0x0F20),
448 __IGNORE(INTCS_VECT(CMT2, 0x0F40))
449 INTCS_VECT(LMB, 0x0F60),
450 __IGNORE(INTCS_VECT(MSUG, 0x0F80))
451 __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
452 __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
453 __IGNORE(INTCS_VECT(CTI, 0x0400))
454 INTCS_VECT(MVI3, 0x0420),
455 __IGNORE(INTCS_VECT(RWDT0, 0x0440))
456 __IGNORE(INTCS_VECT(RWDT1, 0x0460))
457 INTCS_VECT(ICB, 0x0480),
458 INTCS_VECT(PEP, 0x04A0),
459 INTCS_VECT(ASA, 0x04C0),
460 __IGNORE(INTCS_VECT(_2DG, 0x04E0))
461 INTCS_VECT(HQE, 0x0540),
462 INTCS_VECT(JPU, 0x0560),
463 INTCS_VECT(LCDC0, 0x0580),
464 __IGNORE(INTCS_VECT(LCRC, 0x05A0))
465 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
466 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
467 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
468 INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
469 INTCS_VECT(FRC, 0x1700),
470 INTCS_VECT(LCDC1, 0x1780),
471 INTCS_VECT(CSIRX, 0x17A0),
472 INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
473 __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
474 __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
475 __IGNORE(INTCS_VECT(FSI, 0x1840))
476 __IGNORE(INTCS_VECT(FMSI, 0x1860))
477 __IGNORE(INTCS_VECT(SCUV, 0x1880))
478 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
479 INTCS_VECT(TMU1_TUNI12, 0x1940),
480 INTCS_VECT(TSIF2, 0x1960),
481 INTCS_VECT(CMT4, 0x1980),
482 __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
483 INTCS_VECT(CPORTS2R, 0x1A20),
484
485 INTC_VECT(INTCS, INTCS_INTVECT),
486};
487
488static struct intc_group intcs_groups[] __initdata = {
489 INTC_GROUP(RTDMAC1_1,
490 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
491 RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
492 INTC_GROUP(RTDMAC1_2,
493 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
494 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
495 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
496 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
497 __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
498 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
499 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
500 INTC_GROUP(RTDMAC2_1,
501 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
502 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
503 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
504 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
505 __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
506 INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
507};
508
509static struct intc_mask_reg intcs_mask_registers[] __initdata = {
510 { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
511 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
512 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
513 { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
514 { 0, 0, 0, VPU,
515 __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
516 { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
517 { 0, 0, 0, _2DDMAC,
518 __IGNORE0(_2DG), ASA, PEP, ICB } },
519 { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
520 { 0, 0, MVI3, __IGNORE0(CTI),
521 JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
522 { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
523 { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
524 RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
525 __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
526 { 0, 0, MSIOF, 0,
527 SGX540, 0, TTI20, 0 } })
528 { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
529 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
530 0, 0, 0, 0 } },
531 __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
532 { 0, 0, 0, 0,
533 0, MSU_MSU, MSU_MSU2, MSUG } })
534 { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
535 { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
536 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
537 { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
538 { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
539 0, 0, 0, 0 } },
540 { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
541 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
542 0, TSIF1, LMB, TSIF0 } },
543 { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
544 { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
545 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
546 { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
547 { FRC, 0, 0, 0,
548 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
549 __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
550 {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
551 SCUV, 0, 0, 0 } })
552 { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
553 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
554 CMT4, 0, 0, 0 } },
555 { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
556 { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
557 0, 0, 0, 0 } },
558 { 0xFFD20104, 0, 16, /* INTAMASK */
559 { 0, 0, 0, 0, 0, 0, 0, 0,
560 0, 0, 0, 0, 0, 0, 0, INTCS } }
561};
562
563static struct intc_prio_reg intcs_prio_registers[] __initdata = {
564 /* IPRAS */
565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
566 /* IPRBS */
567 { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
568 /* IPRCS */
569 __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
570 /* IPRES */
571 { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
572 /* IPRFS */
573 { 0xFFD20014, 0, 16, 4,
574 { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
575 /* IPRGS */
576 { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
577 /* IPRHS */
578 { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
579 /* IPRIS */
580 { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
581 /* IPRJS */
582 __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
583 /* IPRKS */
584 { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
585 /* IPRLS */
586 { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
587 /* IPRMS */
588 { 0xFFD20030, 0, 16, 4,
589 { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
590 /* IPRAS3 */
591 { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
592 /* IPRBS3 */
593 { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
594 /* IPRIS3 */
595 { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
596 /* IPRJS3 */
597 { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
598 /* IPRKS3 */
599 __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
600 /* IPRLS3 */
601 __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
602 /* IPRMS3 */
603 { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
604 /* IPRNS3 */
605 { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
606 /* IPROS3 */
607 { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
608};
609
610static struct resource intcs_resources[] __initdata = {
611 [0] = {
612 .start = 0xffd20000,
613 .end = 0xffd500ff,
614 .flags = IORESOURCE_MEM,
615 }
616};
617
618static struct intc_desc intcs_desc __initdata = {
619 .name = "sh7377-intcs",
620 .resource = intcs_resources,
621 .num_resources = ARRAY_SIZE(intcs_resources),
622 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
623 intcs_mask_registers, intcs_prio_registers,
624 NULL, NULL),
625};
626
627static void intcs_demux(unsigned int irq, struct irq_desc *desc)
628{
629 void __iomem *reg = (void *)get_irq_data(irq);
630 unsigned int evtcodeas = ioread32(reg);
631
632 generic_handle_irq(intcs_evt2irq(evtcodeas));
633}
634
635#define INTEVTSA 0xFFD20100
349void __init sh7377_init_irq(void) 636void __init sh7377_init_irq(void)
350{ 637{
638 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
639
351 register_intc_controller(&intca_desc); 640 register_intc_controller(&intca_desc);
641 register_intc_controller(&intcs_desc);
642
643 /* demux using INTEVTSA */
644 set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645 set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
352} 646}
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index eca90716140e..3148c11a550e 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -31,11 +31,13 @@
31#include <asm/mach-types.h> 31#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33 33
34/* SCIFA0 */
34static struct plat_sci_port scif0_platform_data = { 35static struct plat_sci_port scif0_platform_data = {
35 .mapbase = 0xe6c40000, 36 .mapbase = 0xe6c40000,
36 .flags = UPF_BOOT_AUTOCONF, 37 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 38 .type = PORT_SCIF,
38 .irqs = { 80, 80, 80, 80 }, 39 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
40 evt2irq(0xc00), evt2irq(0xc00) },
39}; 41};
40 42
41static struct platform_device scif0_device = { 43static struct platform_device scif0_device = {
@@ -46,11 +48,13 @@ static struct platform_device scif0_device = {
46 }, 48 },
47}; 49};
48 50
51/* SCIFA1 */
49static struct plat_sci_port scif1_platform_data = { 52static struct plat_sci_port scif1_platform_data = {
50 .mapbase = 0xe6c50000, 53 .mapbase = 0xe6c50000,
51 .flags = UPF_BOOT_AUTOCONF, 54 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF, 55 .type = PORT_SCIF,
53 .irqs = { 81, 81, 81, 81 }, 56 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
57 evt2irq(0xc20), evt2irq(0xc20) },
54}; 58};
55 59
56static struct platform_device scif1_device = { 60static struct platform_device scif1_device = {
@@ -61,11 +65,13 @@ static struct platform_device scif1_device = {
61 }, 65 },
62}; 66};
63 67
68/* SCIFA2 */
64static struct plat_sci_port scif2_platform_data = { 69static struct plat_sci_port scif2_platform_data = {
65 .mapbase = 0xe6c60000, 70 .mapbase = 0xe6c60000,
66 .flags = UPF_BOOT_AUTOCONF, 71 .flags = UPF_BOOT_AUTOCONF,
67 .type = PORT_SCIF, 72 .type = PORT_SCIF,
68 .irqs = { 82, 82, 82, 82 }, 73 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
74 evt2irq(0xc40), evt2irq(0xc40) },
69}; 75};
70 76
71static struct platform_device scif2_device = { 77static struct platform_device scif2_device = {
@@ -76,11 +82,13 @@ static struct platform_device scif2_device = {
76 }, 82 },
77}; 83};
78 84
85/* SCIFA3 */
79static struct plat_sci_port scif3_platform_data = { 86static struct plat_sci_port scif3_platform_data = {
80 .mapbase = 0xe6c70000, 87 .mapbase = 0xe6c70000,
81 .flags = UPF_BOOT_AUTOCONF, 88 .flags = UPF_BOOT_AUTOCONF,
82 .type = PORT_SCIF, 89 .type = PORT_SCIF,
83 .irqs = { 83, 83, 83, 83 }, 90 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
91 evt2irq(0xc60), evt2irq(0xc60) },
84}; 92};
85 93
86static struct platform_device scif3_device = { 94static struct platform_device scif3_device = {
@@ -91,11 +99,13 @@ static struct platform_device scif3_device = {
91 }, 99 },
92}; 100};
93 101
102/* SCIFA4 */
94static struct plat_sci_port scif4_platform_data = { 103static struct plat_sci_port scif4_platform_data = {
95 .mapbase = 0xe6c80000, 104 .mapbase = 0xe6c80000,
96 .flags = UPF_BOOT_AUTOCONF, 105 .flags = UPF_BOOT_AUTOCONF,
97 .type = PORT_SCIF, 106 .type = PORT_SCIF,
98 .irqs = { 89, 89, 89, 89 }, 107 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
108 evt2irq(0xd20), evt2irq(0xd20) },
99}; 109};
100 110
101static struct platform_device scif4_device = { 111static struct platform_device scif4_device = {
@@ -106,11 +116,13 @@ static struct platform_device scif4_device = {
106 }, 116 },
107}; 117};
108 118
119/* SCIFA5 */
109static struct plat_sci_port scif5_platform_data = { 120static struct plat_sci_port scif5_platform_data = {
110 .mapbase = 0xe6cb0000, 121 .mapbase = 0xe6cb0000,
111 .flags = UPF_BOOT_AUTOCONF, 122 .flags = UPF_BOOT_AUTOCONF,
112 .type = PORT_SCIF, 123 .type = PORT_SCIF,
113 .irqs = { 90, 90, 90, 90 }, 124 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
125 evt2irq(0xd40), evt2irq(0xd40) },
114}; 126};
115 127
116static struct platform_device scif5_device = { 128static struct platform_device scif5_device = {
@@ -121,11 +133,13 @@ static struct platform_device scif5_device = {
121 }, 133 },
122}; 134};
123 135
136/* SCIFB */
124static struct plat_sci_port scif6_platform_data = { 137static struct plat_sci_port scif6_platform_data = {
125 .mapbase = 0xe6c30000, 138 .mapbase = 0xe6c30000,
126 .flags = UPF_BOOT_AUTOCONF, 139 .flags = UPF_BOOT_AUTOCONF,
127 .type = PORT_SCIF, 140 .type = PORT_SCIF,
128 .irqs = { 91, 91, 91, 91 }, 141 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
142 evt2irq(0xd60), evt2irq(0xd60) },
129}; 143};
130 144
131static struct platform_device scif6_device = { 145static struct platform_device scif6_device = {
@@ -153,7 +167,7 @@ static struct resource cmt10_resources[] = {
153 .flags = IORESOURCE_MEM, 167 .flags = IORESOURCE_MEM,
154 }, 168 },
155 [1] = { 169 [1] = {
156 .start = 72, 170 .start = evt2irq(0xb00), /* CMT1_CMT10 */
157 .flags = IORESOURCE_IRQ, 171 .flags = IORESOURCE_IRQ,
158 }, 172 },
159}; 173};
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 1d1153290f59..d1a8095a19eb 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -32,11 +32,13 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34 34
35/* SCIFA0 */
35static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
36 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
37 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF, 39 .type = PORT_SCIFA,
39 .irqs = { 80, 80, 80, 80 }, 40 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
41 evt2irq(0x0c00), evt2irq(0x0c00) },
40}; 42};
41 43
42static struct platform_device scif0_device = { 44static struct platform_device scif0_device = {
@@ -47,11 +49,13 @@ static struct platform_device scif0_device = {
47 }, 49 },
48}; 50};
49 51
52/* SCIFA1 */
50static struct plat_sci_port scif1_platform_data = { 53static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xe6c50000, 54 .mapbase = 0xe6c50000,
52 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
53 .type = PORT_SCIF, 56 .type = PORT_SCIFA,
54 .irqs = { 81, 81, 81, 81 }, 57 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
58 evt2irq(0x0c20), evt2irq(0x0c20) },
55}; 59};
56 60
57static struct platform_device scif1_device = { 61static struct platform_device scif1_device = {
@@ -62,11 +66,13 @@ static struct platform_device scif1_device = {
62 }, 66 },
63}; 67};
64 68
69/* SCIFA2 */
65static struct plat_sci_port scif2_platform_data = { 70static struct plat_sci_port scif2_platform_data = {
66 .mapbase = 0xe6c60000, 71 .mapbase = 0xe6c60000,
67 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
68 .type = PORT_SCIF, 73 .type = PORT_SCIFA,
69 .irqs = { 82, 82, 82, 82 }, 74 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
75 evt2irq(0x0c40), evt2irq(0x0c40) },
70}; 76};
71 77
72static struct platform_device scif2_device = { 78static struct platform_device scif2_device = {
@@ -77,11 +83,13 @@ static struct platform_device scif2_device = {
77 }, 83 },
78}; 84};
79 85
86/* SCIFA3 */
80static struct plat_sci_port scif3_platform_data = { 87static struct plat_sci_port scif3_platform_data = {
81 .mapbase = 0xe6c70000, 88 .mapbase = 0xe6c70000,
82 .flags = UPF_BOOT_AUTOCONF, 89 .flags = UPF_BOOT_AUTOCONF,
83 .type = PORT_SCIF, 90 .type = PORT_SCIFA,
84 .irqs = { 83, 83, 83, 83 }, 91 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
92 evt2irq(0x0c60), evt2irq(0x0c60) },
85}; 93};
86 94
87static struct platform_device scif3_device = { 95static struct platform_device scif3_device = {
@@ -92,11 +100,13 @@ static struct platform_device scif3_device = {
92 }, 100 },
93}; 101};
94 102
103/* SCIFA4 */
95static struct plat_sci_port scif4_platform_data = { 104static struct plat_sci_port scif4_platform_data = {
96 .mapbase = 0xe6c80000, 105 .mapbase = 0xe6c80000,
97 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
98 .type = PORT_SCIF, 107 .type = PORT_SCIFA,
99 .irqs = { 89, 89, 89, 89 }, 108 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
109 evt2irq(0x0d20), evt2irq(0x0d20) },
100}; 110};
101 111
102static struct platform_device scif4_device = { 112static struct platform_device scif4_device = {
@@ -107,11 +117,13 @@ static struct platform_device scif4_device = {
107 }, 117 },
108}; 118};
109 119
120/* SCIFA5 */
110static struct plat_sci_port scif5_platform_data = { 121static struct plat_sci_port scif5_platform_data = {
111 .mapbase = 0xe6cb0000, 122 .mapbase = 0xe6cb0000,
112 .flags = UPF_BOOT_AUTOCONF, 123 .flags = UPF_BOOT_AUTOCONF,
113 .type = PORT_SCIF, 124 .type = PORT_SCIFA,
114 .irqs = { 90, 90, 90, 90 }, 125 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
126 evt2irq(0x0d40), evt2irq(0x0d40) },
115}; 127};
116 128
117static struct platform_device scif5_device = { 129static struct platform_device scif5_device = {
@@ -122,11 +134,13 @@ static struct platform_device scif5_device = {
122 }, 134 },
123}; 135};
124 136
137/* SCIFB */
125static struct plat_sci_port scif6_platform_data = { 138static struct plat_sci_port scif6_platform_data = {
126 .mapbase = 0xe6c30000, 139 .mapbase = 0xe6c30000,
127 .flags = UPF_BOOT_AUTOCONF, 140 .flags = UPF_BOOT_AUTOCONF,
128 .type = PORT_SCIF, 141 .type = PORT_SCIFB,
129 .irqs = { 91, 91, 91, 91 }, 142 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
143 evt2irq(0x0d60), evt2irq(0x0d60) },
130}; 144};
131 145
132static struct platform_device scif6_device = { 146static struct platform_device scif6_device = {
@@ -137,11 +151,12 @@ static struct platform_device scif6_device = {
137 }, 151 },
138}; 152};
139 153
154/* CMT */
140static struct sh_timer_config cmt10_platform_data = { 155static struct sh_timer_config cmt10_platform_data = {
141 .name = "CMT10", 156 .name = "CMT10",
142 .channel_offset = 0x10, 157 .channel_offset = 0x10,
143 .timer_bit = 0, 158 .timer_bit = 0,
144 .clk = "r_clk", 159 .clk = "cmt1",
145 .clockevent_rating = 125, 160 .clockevent_rating = 125,
146 .clocksource_rating = 125, 161 .clocksource_rating = 125,
147}; 162};
@@ -154,7 +169,7 @@ static struct resource cmt10_resources[] = {
154 .flags = IORESOURCE_MEM, 169 .flags = IORESOURCE_MEM,
155 }, 170 },
156 [1] = { 171 [1] = {
157 .start = 72, 172 .start = evt2irq(0x0b00), /* CMT1_CMT10 */
158 .flags = IORESOURCE_IRQ, 173 .flags = IORESOURCE_IRQ,
159 }, 174 },
160}; 175};
@@ -169,6 +184,49 @@ static struct platform_device cmt10_device = {
169 .num_resources = ARRAY_SIZE(cmt10_resources), 184 .num_resources = ARRAY_SIZE(cmt10_resources),
170}; 185};
171 186
187/* I2C */
188static struct resource iic0_resources[] = {
189 [0] = {
190 .name = "IIC0",
191 .start = 0xFFF20000,
192 .end = 0xFFF20425 - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
197 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device iic0_device = {
203 .name = "i2c-sh_mobile",
204 .id = 0, /* "i2c0" clock */
205 .num_resources = ARRAY_SIZE(iic0_resources),
206 .resource = iic0_resources,
207};
208
209static struct resource iic1_resources[] = {
210 [0] = {
211 .name = "IIC1",
212 .start = 0xE6C20000,
213 .end = 0xE6C20425 - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .start = evt2irq(0x780), /* IIC1_ALI1 */
218 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device iic1_device = {
224 .name = "i2c-sh_mobile",
225 .id = 1, /* "i2c1" clock */
226 .num_resources = ARRAY_SIZE(iic1_resources),
227 .resource = iic1_resources,
228};
229
172static struct platform_device *sh7372_early_devices[] __initdata = { 230static struct platform_device *sh7372_early_devices[] __initdata = {
173 &scif0_device, 231 &scif0_device,
174 &scif1_device, 232 &scif1_device,
@@ -178,6 +236,8 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
178 &scif5_device, 236 &scif5_device,
179 &scif6_device, 237 &scif6_device,
180 &cmt10_device, 238 &cmt10_device,
239 &iic0_device,
240 &iic1_device,
181}; 241};
182 242
183void __init sh7372_add_standard_devices(void) 243void __init sh7372_add_standard_devices(void)
@@ -186,14 +246,8 @@ void __init sh7372_add_standard_devices(void)
186 ARRAY_SIZE(sh7372_early_devices)); 246 ARRAY_SIZE(sh7372_early_devices));
187} 247}
188 248
189#define SMSTPCR3 0xe615013c
190#define SMSTPCR3_CMT1 (1 << 29)
191
192void __init sh7372_add_early_devices(void) 249void __init sh7372_add_early_devices(void)
193{ 250{
194 /* enable clock to CMT1 */
195 __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
196
197 early_platform_add_devices(sh7372_early_devices, 251 early_platform_add_devices(sh7372_early_devices,
198 ARRAY_SIZE(sh7372_early_devices)); 252 ARRAY_SIZE(sh7372_early_devices));
199} 253}
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 60e37774c35c..bb4adf17dbf4 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -32,11 +32,13 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34 34
35/* SCIFA0 */
35static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
36 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
37 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF, 39 .type = PORT_SCIF,
39 .irqs = { 80, 80, 80, 80 }, 40 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
41 evt2irq(0xc00), evt2irq(0xc00) },
40}; 42};
41 43
42static struct platform_device scif0_device = { 44static struct platform_device scif0_device = {
@@ -47,11 +49,13 @@ static struct platform_device scif0_device = {
47 }, 49 },
48}; 50};
49 51
52/* SCIFA1 */
50static struct plat_sci_port scif1_platform_data = { 53static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xe6c50000, 54 .mapbase = 0xe6c50000,
52 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
53 .type = PORT_SCIF, 56 .type = PORT_SCIF,
54 .irqs = { 81, 81, 81, 81 }, 57 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
58 evt2irq(0xc20), evt2irq(0xc20) },
55}; 59};
56 60
57static struct platform_device scif1_device = { 61static struct platform_device scif1_device = {
@@ -62,11 +66,13 @@ static struct platform_device scif1_device = {
62 }, 66 },
63}; 67};
64 68
69/* SCIFA2 */
65static struct plat_sci_port scif2_platform_data = { 70static struct plat_sci_port scif2_platform_data = {
66 .mapbase = 0xe6c60000, 71 .mapbase = 0xe6c60000,
67 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
68 .type = PORT_SCIF, 73 .type = PORT_SCIF,
69 .irqs = { 82, 82, 82, 82 }, 74 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
75 evt2irq(0xc40), evt2irq(0xc40) },
70}; 76};
71 77
72static struct platform_device scif2_device = { 78static struct platform_device scif2_device = {
@@ -77,11 +83,13 @@ static struct platform_device scif2_device = {
77 }, 83 },
78}; 84};
79 85
86/* SCIFA3 */
80static struct plat_sci_port scif3_platform_data = { 87static struct plat_sci_port scif3_platform_data = {
81 .mapbase = 0xe6c70000, 88 .mapbase = 0xe6c70000,
82 .flags = UPF_BOOT_AUTOCONF, 89 .flags = UPF_BOOT_AUTOCONF,
83 .type = PORT_SCIF, 90 .type = PORT_SCIF,
84 .irqs = { 83, 83, 83, 83 }, 91 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
92 evt2irq(0xc60), evt2irq(0xc60) },
85}; 93};
86 94
87static struct platform_device scif3_device = { 95static struct platform_device scif3_device = {
@@ -92,11 +100,13 @@ static struct platform_device scif3_device = {
92 }, 100 },
93}; 101};
94 102
103/* SCIFA4 */
95static struct plat_sci_port scif4_platform_data = { 104static struct plat_sci_port scif4_platform_data = {
96 .mapbase = 0xe6c80000, 105 .mapbase = 0xe6c80000,
97 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
98 .type = PORT_SCIF, 107 .type = PORT_SCIF,
99 .irqs = { 89, 89, 89, 89 }, 108 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
109 evt2irq(0xd20), evt2irq(0xd20) },
100}; 110};
101 111
102static struct platform_device scif4_device = { 112static struct platform_device scif4_device = {
@@ -107,11 +117,13 @@ static struct platform_device scif4_device = {
107 }, 117 },
108}; 118};
109 119
120/* SCIFA5 */
110static struct plat_sci_port scif5_platform_data = { 121static struct plat_sci_port scif5_platform_data = {
111 .mapbase = 0xe6cb0000, 122 .mapbase = 0xe6cb0000,
112 .flags = UPF_BOOT_AUTOCONF, 123 .flags = UPF_BOOT_AUTOCONF,
113 .type = PORT_SCIF, 124 .type = PORT_SCIF,
114 .irqs = { 90, 90, 90, 90 }, 125 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
126 evt2irq(0xd40), evt2irq(0xd40) },
115}; 127};
116 128
117static struct platform_device scif5_device = { 129static struct platform_device scif5_device = {
@@ -122,11 +134,13 @@ static struct platform_device scif5_device = {
122 }, 134 },
123}; 135};
124 136
137/* SCIFA6 */
125static struct plat_sci_port scif6_platform_data = { 138static struct plat_sci_port scif6_platform_data = {
126 .mapbase = 0xe6cc0000, 139 .mapbase = 0xe6cc0000,
127 .flags = UPF_BOOT_AUTOCONF, 140 .flags = UPF_BOOT_AUTOCONF,
128 .type = PORT_SCIF, 141 .type = PORT_SCIF,
129 .irqs = { 196, 196, 196, 196 }, 142 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
143 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
130}; 144};
131 145
132static struct platform_device scif6_device = { 146static struct platform_device scif6_device = {
@@ -137,11 +151,13 @@ static struct platform_device scif6_device = {
137 }, 151 },
138}; 152};
139 153
154/* SCIFB */
140static struct plat_sci_port scif7_platform_data = { 155static struct plat_sci_port scif7_platform_data = {
141 .mapbase = 0xe6c30000, 156 .mapbase = 0xe6c30000,
142 .flags = UPF_BOOT_AUTOCONF, 157 .flags = UPF_BOOT_AUTOCONF,
143 .type = PORT_SCIF, 158 .type = PORT_SCIF,
144 .irqs = { 91, 91, 91, 91 }, 159 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
160 evt2irq(0xd60), evt2irq(0xd60) },
145}; 161};
146 162
147static struct platform_device scif7_device = { 163static struct platform_device scif7_device = {
@@ -169,7 +185,7 @@ static struct resource cmt10_resources[] = {
169 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
170 }, 186 },
171 [1] = { 187 [1] = {
172 .start = 72, 188 .start = evt2irq(0xb00), /* CMT1_CMT10 */
173 .flags = IORESOURCE_IRQ, 189 .flags = IORESOURCE_IRQ,
174 }, 190 },
175}; 191};
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 9e01e96fee94..8344375dc015 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -128,7 +128,7 @@ config TXX9_DMAC
128 128
129config SH_DMAE 129config SH_DMAE
130 tristate "Renesas SuperH DMAC support" 130 tristate "Renesas SuperH DMAC support"
131 depends on SUPERH && SH_DMA 131 depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
132 depends on !SH_DMA_API 132 depends on !SH_DMA_API
133 select DMA_ENGINE 133 select DMA_ENGINE
134 help 134 help
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index a2a519fd2a24..fb64cf36ba61 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -816,7 +816,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
816 return ret; 816 return ret;
817} 817}
818 818
819#if defined(CONFIG_CPU_SH4) 819#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
820static irqreturn_t sh_dmae_err(int irq, void *data) 820static irqreturn_t sh_dmae_err(int irq, void *data)
821{ 821{
822 struct sh_dmae_device *shdev = (struct sh_dmae_device *)data; 822 struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
@@ -1057,7 +1057,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1057 /* Default transfer size of 32 bytes requires 32-byte alignment */ 1057 /* Default transfer size of 32 bytes requires 32-byte alignment */
1058 shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; 1058 shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1059 1059
1060#if defined(CONFIG_CPU_SH4) 1060#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1061 chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 1061 chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1062 1062
1063 if (!chanirq_res) 1063 if (!chanirq_res)
@@ -1082,7 +1082,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1082 1082
1083#else 1083#else
1084 chanirq_res = errirq_res; 1084 chanirq_res = errirq_res;
1085#endif /* CONFIG_CPU_SH4 */ 1085#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1086 1086
1087 if (chanirq_res->start == chanirq_res->end && 1087 if (chanirq_res->start == chanirq_res->end &&
1088 !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { 1088 !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
@@ -1129,7 +1129,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1129chan_probe_err: 1129chan_probe_err:
1130 sh_dmae_chan_remove(shdev); 1130 sh_dmae_chan_remove(shdev);
1131eirqres: 1131eirqres:
1132#if defined(CONFIG_CPU_SH4) 1132#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1133 free_irq(errirq, shdev); 1133 free_irq(errirq, shdev);
1134eirq_err: 1134eirq_err:
1135#endif 1135#endif
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 87ab0568bb0e..dec387d3f04d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -529,7 +529,7 @@ config I2C_SH7760
529 529
530config I2C_SH_MOBILE 530config I2C_SH_MOBILE
531 tristate "SuperH Mobile I2C Controller" 531 tristate "SuperH Mobile I2C Controller"
532 depends on SUPERH 532 depends on SUPERH || ARCH_SHMOBILE
533 help 533 help
534 If you say yes to this option, support will be included for the 534 If you say yes to this option, support will be included for the
535 built-in I2C interface on the Renesas SH-Mobile processor. 535 built-in I2C interface on the Renesas SH-Mobile processor.
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index ffb405d7c6f2..598c49acaeb5 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -119,8 +119,10 @@ struct sh_mobile_i2c_data {
119 struct i2c_adapter adap; 119 struct i2c_adapter adap;
120 120
121 struct clk *clk; 121 struct clk *clk;
122 u_int8_t icic;
122 u_int8_t iccl; 123 u_int8_t iccl;
123 u_int8_t icch; 124 u_int8_t icch;
125 u_int8_t flags;
124 126
125 spinlock_t lock; 127 spinlock_t lock;
126 wait_queue_head_t wait; 128 wait_queue_head_t wait;
@@ -129,15 +131,17 @@ struct sh_mobile_i2c_data {
129 int sr; 131 int sr;
130}; 132};
131 133
134#define IIC_FLAG_HAS_ICIC67 (1 << 0)
135
132#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */ 136#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
133 137
134/* Register offsets */ 138/* Register offsets */
135#define ICDR(pd) (pd->reg + 0x00) 139#define ICDR 0x00
136#define ICCR(pd) (pd->reg + 0x04) 140#define ICCR 0x04
137#define ICSR(pd) (pd->reg + 0x08) 141#define ICSR 0x08
138#define ICIC(pd) (pd->reg + 0x0c) 142#define ICIC 0x0c
139#define ICCL(pd) (pd->reg + 0x10) 143#define ICCL 0x10
140#define ICCH(pd) (pd->reg + 0x14) 144#define ICCH 0x14
141 145
142/* Register bits */ 146/* Register bits */
143#define ICCR_ICE 0x80 147#define ICCR_ICE 0x80
@@ -155,11 +159,32 @@ struct sh_mobile_i2c_data {
155#define ICSR_WAIT 0x02 159#define ICSR_WAIT 0x02
156#define ICSR_DTE 0x01 160#define ICSR_DTE 0x01
157 161
162#define ICIC_ICCLB8 0x80
163#define ICIC_ICCHB8 0x40
158#define ICIC_ALE 0x08 164#define ICIC_ALE 0x08
159#define ICIC_TACKE 0x04 165#define ICIC_TACKE 0x04
160#define ICIC_WAITE 0x02 166#define ICIC_WAITE 0x02
161#define ICIC_DTEE 0x01 167#define ICIC_DTEE 0x01
162 168
169static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
170{
171 if (offs == ICIC)
172 data |= pd->icic;
173
174 iowrite8(data, pd->reg + offs);
175}
176
177static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
178{
179 return ioread8(pd->reg + offs);
180}
181
182static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
183 unsigned char set, unsigned char clr)
184{
185 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
186}
187
163static void activate_ch(struct sh_mobile_i2c_data *pd) 188static void activate_ch(struct sh_mobile_i2c_data *pd)
164{ 189{
165 unsigned long i2c_clk; 190 unsigned long i2c_clk;
@@ -187,6 +212,14 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
187 else 212 else
188 pd->iccl = (u_int8_t)(num/denom); 213 pd->iccl = (u_int8_t)(num/denom);
189 214
215 /* one more bit of ICCL in ICIC */
216 if (pd->flags & IIC_FLAG_HAS_ICIC67) {
217 if ((num/denom) > 0xff)
218 pd->icic |= ICIC_ICCLB8;
219 else
220 pd->icic &= ~ICIC_ICCLB8;
221 }
222
190 /* Calculate the value for icch. From the data sheet: 223 /* Calculate the value for icch. From the data sheet:
191 icch = (p clock / transfer rate) * (H / (L + H)) */ 224 icch = (p clock / transfer rate) * (H / (L + H)) */
192 num = i2c_clk * 4; 225 num = i2c_clk * 4;
@@ -196,25 +229,33 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
196 else 229 else
197 pd->icch = (u_int8_t)(num/denom); 230 pd->icch = (u_int8_t)(num/denom);
198 231
232 /* one more bit of ICCH in ICIC */
233 if (pd->flags & IIC_FLAG_HAS_ICIC67) {
234 if ((num/denom) > 0xff)
235 pd->icic |= ICIC_ICCHB8;
236 else
237 pd->icic &= ~ICIC_ICCHB8;
238 }
239
199 /* Enable channel and configure rx ack */ 240 /* Enable channel and configure rx ack */
200 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); 241 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
201 242
202 /* Mask all interrupts */ 243 /* Mask all interrupts */
203 iowrite8(0, ICIC(pd)); 244 iic_wr(pd, ICIC, 0);
204 245
205 /* Set the clock */ 246 /* Set the clock */
206 iowrite8(pd->iccl, ICCL(pd)); 247 iic_wr(pd, ICCL, pd->iccl);
207 iowrite8(pd->icch, ICCH(pd)); 248 iic_wr(pd, ICCH, pd->icch);
208} 249}
209 250
210static void deactivate_ch(struct sh_mobile_i2c_data *pd) 251static void deactivate_ch(struct sh_mobile_i2c_data *pd)
211{ 252{
212 /* Clear/disable interrupts */ 253 /* Clear/disable interrupts */
213 iowrite8(0, ICSR(pd)); 254 iic_wr(pd, ICSR, 0);
214 iowrite8(0, ICIC(pd)); 255 iic_wr(pd, ICIC, 0);
215 256
216 /* Disable channel */ 257 /* Disable channel */
217 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 258 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
218 259
219 /* Disable clock and mark device as idle */ 260 /* Disable clock and mark device as idle */
220 clk_disable(pd->clk); 261 clk_disable(pd->clk);
@@ -233,35 +274,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
233 274
234 switch (op) { 275 switch (op) {
235 case OP_START: /* issue start and trigger DTE interrupt */ 276 case OP_START: /* issue start and trigger DTE interrupt */
236 iowrite8(0x94, ICCR(pd)); 277 iic_wr(pd, ICCR, 0x94);
237 break; 278 break;
238 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 279 case OP_TX_FIRST: /* disable DTE interrupt and write data */
239 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd)); 280 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
240 iowrite8(data, ICDR(pd)); 281 iic_wr(pd, ICDR, data);
241 break; 282 break;
242 case OP_TX: /* write data */ 283 case OP_TX: /* write data */
243 iowrite8(data, ICDR(pd)); 284 iic_wr(pd, ICDR, data);
244 break; 285 break;
245 case OP_TX_STOP: /* write data and issue a stop afterwards */ 286 case OP_TX_STOP: /* write data and issue a stop afterwards */
246 iowrite8(data, ICDR(pd)); 287 iic_wr(pd, ICDR, data);
247 iowrite8(0x90, ICCR(pd)); 288 iic_wr(pd, ICCR, 0x90);
248 break; 289 break;
249 case OP_TX_TO_RX: /* select read mode */ 290 case OP_TX_TO_RX: /* select read mode */
250 iowrite8(0x81, ICCR(pd)); 291 iic_wr(pd, ICCR, 0x81);
251 break; 292 break;
252 case OP_RX: /* just read data */ 293 case OP_RX: /* just read data */
253 ret = ioread8(ICDR(pd)); 294 ret = iic_rd(pd, ICDR);
254 break; 295 break;
255 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 296 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
256 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, 297 iic_wr(pd, ICIC,
257 ICIC(pd)); 298 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
258 iowrite8(0xc0, ICCR(pd)); 299 iic_wr(pd, ICCR, 0xc0);
259 break; 300 break;
260 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 301 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
261 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, 302 iic_wr(pd, ICIC,
262 ICIC(pd)); 303 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
263 ret = ioread8(ICDR(pd)); 304 ret = iic_rd(pd, ICDR);
264 iowrite8(0xc0, ICCR(pd)); 305 iic_wr(pd, ICCR, 0xc0);
265 break; 306 break;
266 } 307 }
267 308
@@ -367,7 +408,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
367 unsigned char sr; 408 unsigned char sr;
368 int wakeup; 409 int wakeup;
369 410
370 sr = ioread8(ICSR(pd)); 411 sr = iic_rd(pd, ICSR);
371 pd->sr |= sr; /* remember state */ 412 pd->sr |= sr; /* remember state */
372 413
373 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 414 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
@@ -376,7 +417,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
376 417
377 if (sr & (ICSR_AL | ICSR_TACK)) { 418 if (sr & (ICSR_AL | ICSR_TACK)) {
378 /* don't interrupt transaction - continue to issue stop */ 419 /* don't interrupt transaction - continue to issue stop */
379 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd)); 420 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
380 wakeup = 0; 421 wakeup = 0;
381 } else if (pd->msg->flags & I2C_M_RD) 422 } else if (pd->msg->flags & I2C_M_RD)
382 wakeup = sh_mobile_i2c_isr_rx(pd); 423 wakeup = sh_mobile_i2c_isr_rx(pd);
@@ -384,7 +425,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
384 wakeup = sh_mobile_i2c_isr_tx(pd); 425 wakeup = sh_mobile_i2c_isr_tx(pd);
385 426
386 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 427 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
387 iowrite8(sr & ~ICSR_WAIT, ICSR(pd)); 428 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
388 429
389 if (wakeup) { 430 if (wakeup) {
390 pd->sr |= SW_DONE; 431 pd->sr |= SW_DONE;
@@ -402,21 +443,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
402 } 443 }
403 444
404 /* Initialize channel registers */ 445 /* Initialize channel registers */
405 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 446 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
406 447
407 /* Enable channel and configure rx ack */ 448 /* Enable channel and configure rx ack */
408 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); 449 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
409 450
410 /* Set the clock */ 451 /* Set the clock */
411 iowrite8(pd->iccl, ICCL(pd)); 452 iic_wr(pd, ICCL, pd->iccl);
412 iowrite8(pd->icch, ICCH(pd)); 453 iic_wr(pd, ICCH, pd->icch);
413 454
414 pd->msg = usr_msg; 455 pd->msg = usr_msg;
415 pd->pos = -1; 456 pd->pos = -1;
416 pd->sr = 0; 457 pd->sr = 0;
417 458
418 /* Enable all interrupts to begin with */ 459 /* Enable all interrupts to begin with */
419 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd)); 460 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
420 return 0; 461 return 0;
421} 462}
422 463
@@ -451,7 +492,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
451 492
452 retry_count = 1000; 493 retry_count = 1000;
453again: 494again:
454 val = ioread8(ICSR(pd)); 495 val = iic_rd(pd, ICSR);
455 496
456 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 497 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
457 498
@@ -576,6 +617,12 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
576 goto err_irq; 617 goto err_irq;
577 } 618 }
578 619
620 /* The IIC blocks on SH-Mobile ARM processors
621 * come with two new bits in ICIC.
622 */
623 if (size > 0x17)
624 pd->flags |= IIC_FLAG_HAS_ICIC67;
625
579 /* Enable Runtime PM for this device. 626 /* Enable Runtime PM for this device.
580 * 627 *
581 * Also tell the Runtime PM core to ignore children 628 * Also tell the Runtime PM core to ignore children
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 5f90fcd7d107..c291b3add1d2 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -346,6 +346,27 @@ static int scif_rxfill(struct uart_port *port)
346 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 346 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
347 } 347 }
348} 348}
349#elif defined(CONFIG_ARCH_SH7372)
350static int scif_txfill(struct uart_port *port)
351{
352 if (port->type == PORT_SCIFA)
353 return sci_in(port, SCFDR) >> 8;
354 else
355 return sci_in(port, SCTFDR);
356}
357
358static int scif_txroom(struct uart_port *port)
359{
360 return port->fifosize - scif_txfill(port);
361}
362
363static int scif_rxfill(struct uart_port *port)
364{
365 if (port->type == PORT_SCIFA)
366 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
367 else
368 return sci_in(port, SCRFDR);
369}
349#else 370#else
350static int scif_txfill(struct uart_port *port) 371static int scif_txfill(struct uart_port *port)
351{ 372{
@@ -683,7 +704,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
683 u16 ssr = sci_in(port, SCxSR); 704 u16 ssr = sci_in(port, SCxSR);
684 705
685 /* Disable future Rx interrupts */ 706 /* Disable future Rx interrupts */
686 if (port->type == PORT_SCIFA) { 707 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
687 disable_irq_nosync(irq); 708 disable_irq_nosync(irq);
688 scr |= 0x4000; 709 scr |= 0x4000;
689 } else { 710 } else {
@@ -928,7 +949,7 @@ static void sci_dma_tx_complete(void *arg)
928 949
929 if (!uart_circ_empty(xmit)) { 950 if (!uart_circ_empty(xmit)) {
930 schedule_work(&s->work_tx); 951 schedule_work(&s->work_tx);
931 } else if (port->type == PORT_SCIFA) { 952 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
932 u16 ctrl = sci_in(port, SCSCR); 953 u16 ctrl = sci_in(port, SCSCR);
933 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE); 954 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
934 } 955 }
@@ -1184,7 +1205,7 @@ static void sci_start_tx(struct uart_port *port)
1184 unsigned short ctrl; 1205 unsigned short ctrl;
1185 1206
1186#ifdef CONFIG_SERIAL_SH_SCI_DMA 1207#ifdef CONFIG_SERIAL_SH_SCI_DMA
1187 if (port->type == PORT_SCIFA) { 1208 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1188 u16 new, scr = sci_in(port, SCSCR); 1209 u16 new, scr = sci_in(port, SCSCR);
1189 if (s->chan_tx) 1210 if (s->chan_tx)
1190 new = scr | 0x8000; 1211 new = scr | 0x8000;
@@ -1197,7 +1218,7 @@ static void sci_start_tx(struct uart_port *port)
1197 s->cookie_tx < 0) 1218 s->cookie_tx < 0)
1198 schedule_work(&s->work_tx); 1219 schedule_work(&s->work_tx);
1199#endif 1220#endif
1200 if (!s->chan_tx || port->type == PORT_SCIFA) { 1221 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1201 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1222 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1202 ctrl = sci_in(port, SCSCR); 1223 ctrl = sci_in(port, SCSCR);
1203 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE); 1224 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
@@ -1210,7 +1231,7 @@ static void sci_stop_tx(struct uart_port *port)
1210 1231
1211 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1232 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1212 ctrl = sci_in(port, SCSCR); 1233 ctrl = sci_in(port, SCSCR);
1213 if (port->type == PORT_SCIFA) 1234 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1214 ctrl &= ~0x8000; 1235 ctrl &= ~0x8000;
1215 ctrl &= ~SCI_CTRL_FLAGS_TIE; 1236 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1216 sci_out(port, SCSCR, ctrl); 1237 sci_out(port, SCSCR, ctrl);
@@ -1222,7 +1243,7 @@ static void sci_start_rx(struct uart_port *port)
1222 1243
1223 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 1244 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1224 ctrl |= sci_in(port, SCSCR); 1245 ctrl |= sci_in(port, SCSCR);
1225 if (port->type == PORT_SCIFA) 1246 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1226 ctrl &= ~0x4000; 1247 ctrl &= ~0x4000;
1227 sci_out(port, SCSCR, ctrl); 1248 sci_out(port, SCSCR, ctrl);
1228} 1249}
@@ -1233,7 +1254,7 @@ static void sci_stop_rx(struct uart_port *port)
1233 1254
1234 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 1255 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1235 ctrl = sci_in(port, SCSCR); 1256 ctrl = sci_in(port, SCSCR);
1236 if (port->type == PORT_SCIFA) 1257 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1237 ctrl &= ~0x4000; 1258 ctrl &= ~0x4000;
1238 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 1259 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1239 sci_out(port, SCSCR, ctrl); 1260 sci_out(port, SCSCR, ctrl);
@@ -1271,7 +1292,7 @@ static void rx_timer_fn(unsigned long arg)
1271 struct uart_port *port = &s->port; 1292 struct uart_port *port = &s->port;
1272 u16 scr = sci_in(port, SCSCR); 1293 u16 scr = sci_in(port, SCSCR);
1273 1294
1274 if (port->type == PORT_SCIFA) { 1295 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1275 scr &= ~0x4000; 1296 scr &= ~0x4000;
1276 enable_irq(s->irqs[1]); 1297 enable_irq(s->irqs[1]);
1277 } 1298 }
@@ -1524,6 +1545,8 @@ static const char *sci_type(struct uart_port *port)
1524 return "scif"; 1545 return "scif";
1525 case PORT_SCIFA: 1546 case PORT_SCIFA:
1526 return "scifa"; 1547 return "scifa";
1548 case PORT_SCIFB:
1549 return "scifb";
1527 } 1550 }
1528 1551
1529 return NULL; 1552 return NULL;
@@ -1612,6 +1635,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
1612 port->line = index; 1635 port->line = index;
1613 1636
1614 switch (p->type) { 1637 switch (p->type) {
1638 case PORT_SCIFB:
1639 port->fifosize = 256;
1640 break;
1615 case PORT_SCIFA: 1641 case PORT_SCIFA:
1616 port->fifosize = 64; 1642 port->fifosize = 64;
1617 break; 1643 break;
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index f70c49f915fa..9b52f77a9305 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -322,7 +322,7 @@
322#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 322#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
323 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 323 static inline unsigned int sci_##name##_in(struct uart_port *port) \
324 { \ 324 { \
325 if (port->type == PORT_SCIF) { \ 325 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
326 SCI_IN(scif_size, scif_offset) \ 326 SCI_IN(scif_size, scif_offset) \
327 } else { /* PORT_SCI or PORT_SCIFA */ \ 327 } else { /* PORT_SCI or PORT_SCIFA */ \
328 SCI_IN(sci_size, sci_offset); \ 328 SCI_IN(sci_size, sci_offset); \
@@ -330,7 +330,7 @@
330 } \ 330 } \
331 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 331 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
332 { \ 332 { \
333 if (port->type == PORT_SCIF) { \ 333 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
334 SCI_OUT(scif_size, scif_offset, value) \ 334 SCI_OUT(scif_size, scif_offset, value) \
335 } else { /* PORT_SCI or PORT_SCIFA */ \ 335 } else { /* PORT_SCI or PORT_SCIFA */ \
336 SCI_OUT(sci_size, sci_offset, value); \ 336 SCI_OUT(sci_size, sci_offset, value); \
@@ -384,8 +384,12 @@
384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
386 defined(CONFIG_ARCH_SH7367) || \ 386 defined(CONFIG_ARCH_SH7367) || \
387 defined(CONFIG_ARCH_SH7377) || \ 387 defined(CONFIG_ARCH_SH7377)
388 defined(CONFIG_ARCH_SH7372) 388#define SCIF_FNS(name, scif_offset, scif_size) \
389 CPU_SCIF_FNS(name, scif_offset, scif_size)
390#elif defined(CONFIG_ARCH_SH7372)
391#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
392 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
389#define SCIF_FNS(name, scif_offset, scif_size) \ 393#define SCIF_FNS(name, scif_offset, scif_size) \
390 CPU_SCIF_FNS(name, scif_offset, scif_size) 394 CPU_SCIF_FNS(name, scif_offset, scif_size)
391#else 395#else
@@ -422,8 +426,7 @@
422 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 426 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
423 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 427 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
424 defined(CONFIG_ARCH_SH7367) || \ 428 defined(CONFIG_ARCH_SH7367) || \
425 defined(CONFIG_ARCH_SH7377) || \ 429 defined(CONFIG_ARCH_SH7377)
426 defined(CONFIG_ARCH_SH7372)
427 430
428SCIF_FNS(SCSMR, 0x00, 16) 431SCIF_FNS(SCSMR, 0x00, 16)
429SCIF_FNS(SCBRR, 0x04, 8) 432SCIF_FNS(SCBRR, 0x04, 8)
@@ -436,6 +439,20 @@ SCIF_FNS(SCFDR, 0x1c, 16)
436SCIF_FNS(SCxTDR, 0x20, 8) 439SCIF_FNS(SCxTDR, 0x20, 8)
437SCIF_FNS(SCxRDR, 0x24, 8) 440SCIF_FNS(SCxRDR, 0x24, 8)
438SCIF_FNS(SCLSR, 0x00, 0) 441SCIF_FNS(SCLSR, 0x00, 0)
442#elif defined(CONFIG_ARCH_SH7372)
443SCIF_FNS(SCSMR, 0x00, 16)
444SCIF_FNS(SCBRR, 0x04, 8)
445SCIF_FNS(SCSCR, 0x08, 16)
446SCIF_FNS(SCTDSR, 0x0c, 16)
447SCIF_FNS(SCFER, 0x10, 16)
448SCIF_FNS(SCxSR, 0x14, 16)
449SCIF_FNS(SCFCR, 0x18, 16)
450SCIF_FNS(SCFDR, 0x1c, 16)
451SCIF_FNS(SCTFDR, 0x38, 16)
452SCIF_FNS(SCRFDR, 0x3c, 16)
453SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
454SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
455SCIF_FNS(SCLSR, 0x00, 0)
439#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 456#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
440 defined(CONFIG_CPU_SUBTYPE_SH7724) 457 defined(CONFIG_CPU_SUBTYPE_SH7724)
441SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 458SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index 78bb5127abd0..08fc653a825c 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -1,9 +1,10 @@
1# 1#
2# Makefile for the SuperH specific drivers. 2# Makefile for the SuperH specific drivers.
3# 3#
4obj-y := clk.o intc.o
5
4obj-$(CONFIG_SUPERHYWAY) += superhyway/ 6obj-$(CONFIG_SUPERHYWAY) += superhyway/
5obj-$(CONFIG_MAPLE) += maple/ 7obj-$(CONFIG_MAPLE) += maple/
8
6obj-$(CONFIG_GENERIC_GPIO) += pfc.o 9obj-$(CONFIG_GENERIC_GPIO) += pfc.o
7obj-$(CONFIG_SUPERH) += clk.o
8obj-$(CONFIG_SH_CLK_CPG) += clk-cpg.o 10obj-$(CONFIG_SH_CLK_CPG) += clk-cpg.o
9obj-y += intc.o
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1e6fec487973..3dc10381e0c2 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1895,6 +1895,13 @@ config FB_W100
1895 1895
1896 If unsure, say N. 1896 If unsure, say N.
1897 1897
1898config SH_MIPI_DSI
1899 tristate
1900 depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
1901
1902config SH_LCD_MIPI_DSI
1903 bool
1904
1898config FB_SH_MOBILE_LCDC 1905config FB_SH_MOBILE_LCDC
1899 tristate "SuperH Mobile LCDC framebuffer support" 1906 tristate "SuperH Mobile LCDC framebuffer support"
1900 depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK 1907 depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
@@ -1903,6 +1910,7 @@ config FB_SH_MOBILE_LCDC
1903 select FB_SYS_IMAGEBLIT 1910 select FB_SYS_IMAGEBLIT
1904 select FB_SYS_FOPS 1911 select FB_SYS_FOPS
1905 select FB_DEFERRED_IO 1912 select FB_DEFERRED_IO
1913 select SH_MIPI_DSI if SH_LCD_MIPI_DSI
1906 ---help--- 1914 ---help---
1907 Frame buffer driver for the on-chip SH-Mobile LCD controller. 1915 Frame buffer driver for the on-chip SH-Mobile LCD controller.
1908 1916
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ddc2af2ba45b..3c3bf867ef18 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
123obj-$(CONFIG_FB_PS3) += ps3fb.o 123obj-$(CONFIG_FB_PS3) += ps3fb.o
124obj-$(CONFIG_FB_SM501) += sm501fb.o 124obj-$(CONFIG_FB_SM501) += sm501fb.o
125obj-$(CONFIG_FB_XILINX) += xilinxfb.o 125obj-$(CONFIG_FB_XILINX) += xilinxfb.o
126obj-$(CONFIG_SH_MIPI_DSI) += sh_mipi_dsi.o
126obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o 127obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
127obj-$(CONFIG_FB_OMAP) += omap/ 128obj-$(CONFIG_FB_OMAP) += omap/
128obj-y += omap2/ 129obj-y += omap2/
diff --git a/drivers/video/sh_mipi_dsi.c b/drivers/video/sh_mipi_dsi.c
new file mode 100644
index 000000000000..017ae9f47d36
--- /dev/null
+++ b/drivers/video/sh_mipi_dsi.c
@@ -0,0 +1,505 @@
1/*
2 * Renesas SH-mobile MIPI DSI support
3 *
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/string.h>
18#include <linux/types.h>
19
20#include <video/mipi_display.h>
21#include <video/sh_mipi_dsi.h>
22#include <video/sh_mobile_lcdc.h>
23
24#define CMTSRTCTR 0x80d0
25#define CMTSRTREQ 0x8070
26
27#define DSIINTE 0x0060
28
29/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
30#define MAX_SH_MIPI_DSI 2
31
32struct sh_mipi {
33 void __iomem *base;
34 struct clk *dsit_clk;
35 struct clk *dsip_clk;
36};
37
38static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
39
40/* Protect the above array */
41static DEFINE_MUTEX(array_lock);
42
43static struct sh_mipi *sh_mipi_by_handle(int handle)
44{
45 if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
46 return NULL;
47
48 return mipi_dsi[handle];
49}
50
51static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
52 u8 cmd, u8 param)
53{
54 u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
55 int cnt = 100;
56
57 /* transmit a short packet to LCD panel */
58 iowrite32(1 | data, mipi->base + 0x80d0); /* CMTSRTCTR */
59 iowrite32(1, mipi->base + 0x8070); /* CMTSRTREQ */
60
61 while ((ioread32(mipi->base + 0x8070) & 1) && --cnt)
62 udelay(1);
63
64 return cnt ? 0 : -ETIMEDOUT;
65}
66
67#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
68 -EINVAL : (c) - 1)
69
70static int sh_mipi_dcs(int handle, u8 cmd)
71{
72 struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
73 if (!mipi)
74 return -ENODEV;
75 return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
76}
77
78static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
79{
80 struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
81 if (!mipi)
82 return -ENODEV;
83 return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
84 param);
85}
86
87static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
88{
89 /*
90 * enable LCDC data tx, transition to LPS after completion of each HS
91 * packet
92 */
93 iowrite32(0x00000002 | enable, mipi->base + 0x8000); /* DTCTR */
94}
95
96static void sh_mipi_shutdown(struct platform_device *pdev)
97{
98 struct sh_mipi *mipi = platform_get_drvdata(pdev);
99
100 sh_mipi_dsi_enable(mipi, false);
101}
102
103static void mipi_display_on(void *arg)
104{
105 struct sh_mipi *mipi = arg;
106
107 sh_mipi_dsi_enable(mipi, true);
108}
109
110static void mipi_display_off(void *arg)
111{
112 struct sh_mipi *mipi = arg;
113
114 sh_mipi_dsi_enable(mipi, false);
115}
116
117static int __init sh_mipi_setup(struct sh_mipi *mipi,
118 struct sh_mipi_dsi_info *pdata)
119{
120 void __iomem *base = mipi->base;
121 struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
122 u32 pctype, datatype, pixfmt;
123 u32 linelength;
124 bool yuv;
125
126 /* Select data format */
127 switch (pdata->data_format) {
128 case MIPI_RGB888:
129 pctype = 0;
130 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
131 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
132 linelength = ch->lcd_cfg.xres * 3;
133 yuv = false;
134 break;
135 case MIPI_RGB565:
136 pctype = 1;
137 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
138 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
139 linelength = ch->lcd_cfg.xres * 2;
140 yuv = false;
141 break;
142 case MIPI_RGB666_LP:
143 pctype = 2;
144 datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
145 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
146 linelength = ch->lcd_cfg.xres * 3;
147 yuv = false;
148 break;
149 case MIPI_RGB666:
150 pctype = 3;
151 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
152 pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
153 linelength = (ch->lcd_cfg.xres * 18 + 7) / 8;
154 yuv = false;
155 break;
156 case MIPI_BGR888:
157 pctype = 8;
158 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
159 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
160 linelength = ch->lcd_cfg.xres * 3;
161 yuv = false;
162 break;
163 case MIPI_BGR565:
164 pctype = 9;
165 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
166 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
167 linelength = ch->lcd_cfg.xres * 2;
168 yuv = false;
169 break;
170 case MIPI_BGR666_LP:
171 pctype = 0xa;
172 datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
173 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
174 linelength = ch->lcd_cfg.xres * 3;
175 yuv = false;
176 break;
177 case MIPI_BGR666:
178 pctype = 0xb;
179 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
180 pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
181 linelength = (ch->lcd_cfg.xres * 18 + 7) / 8;
182 yuv = false;
183 break;
184 case MIPI_YUYV:
185 pctype = 4;
186 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
187 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
188 linelength = ch->lcd_cfg.xres * 2;
189 yuv = true;
190 break;
191 case MIPI_UYVY:
192 pctype = 5;
193 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
194 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
195 linelength = ch->lcd_cfg.xres * 2;
196 yuv = true;
197 break;
198 case MIPI_YUV420_L:
199 pctype = 6;
200 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
201 pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
202 linelength = (ch->lcd_cfg.xres * 12 + 7) / 8;
203 yuv = true;
204 break;
205 case MIPI_YUV420:
206 pctype = 7;
207 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
208 pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
209 /* Length of U/V line */
210 linelength = (ch->lcd_cfg.xres + 1) / 2;
211 yuv = true;
212 break;
213 default:
214 return -EINVAL;
215 }
216
217 if ((yuv && ch->interface_type != YUV422) ||
218 (!yuv && ch->interface_type != RGB24))
219 return -EINVAL;
220
221 /* reset DSI link */
222 iowrite32(0x00000001, base); /* SYSCTRL */
223 /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
224 udelay(50);
225 iowrite32(0x00000000, base); /* SYSCTRL */
226
227 /* setup DSI link */
228
229 /*
230 * Default = ULPS enable |
231 * Contention detection enabled |
232 * EoT packet transmission enable |
233 * CRC check enable |
234 * ECC check enable
235 * additionally enable first two lanes
236 */
237 iowrite32(0x00003703, base + 0x04); /* SYSCONF */
238 /*
239 * T_wakeup = 0x7000
240 * T_hs-trail = 3
241 * T_hs-prepare = 3
242 * T_clk-trail = 3
243 * T_clk-prepare = 2
244 */
245 iowrite32(0x70003332, base + 0x08); /* TIMSET */
246 /* no responses requested */
247 iowrite32(0x00000000, base + 0x18); /* RESREQSET0 */
248 /* request response to packets of type 0x28 */
249 iowrite32(0x00000100, base + 0x1c); /* RESREQSET1 */
250 /* High-speed transmission timeout, default 0xffffffff */
251 iowrite32(0x0fffffff, base + 0x20); /* HSTTOVSET */
252 /* LP reception timeout, default 0xffffffff */
253 iowrite32(0x0fffffff, base + 0x24); /* LPRTOVSET */
254 /* Turn-around timeout, default 0xffffffff */
255 iowrite32(0x0fffffff, base + 0x28); /* TATOVSET */
256 /* Peripheral reset timeout, default 0xffffffff */
257 iowrite32(0x0fffffff, base + 0x2c); /* PRTOVSET */
258 /* Enable timeout counters */
259 iowrite32(0x00000f00, base + 0x30); /* DSICTRL */
260 /* Interrupts not used, disable all */
261 iowrite32(0, base + DSIINTE);
262 /* DSI-Tx bias on */
263 iowrite32(0x00000001, base + 0x70); /* PHYCTRL */
264 udelay(200);
265 /* Deassert resets, power on, set multiplier */
266 iowrite32(0x03070b01, base + 0x70); /* PHYCTRL */
267
268 /* setup l-bridge */
269
270 /*
271 * Enable transmission of all packets,
272 * transmit LPS after each HS packet completion
273 */
274 iowrite32(0x00000006, base + 0x8000); /* DTCTR */
275 /* VSYNC width = 2 (<< 17) */
276 iowrite32(0x00040000 | (pctype << 12) | datatype, base + 0x8020); /* VMCTR1 */
277 /*
278 * Non-burst mode with sync pulses: VSE and HSE are output,
279 * HSA period allowed, no commands in LP
280 */
281 iowrite32(0x00e00000, base + 0x8024); /* VMCTR2 */
282 /*
283 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
284 * sh_mobile_lcdc_info.ch[0].lcd_cfg.xres), HSALEN = 1 - default
285 * (unused, since VMCTR2[HSABM] = 0)
286 */
287 iowrite32(1 | (linelength << 16), base + 0x8028); /* VMLEN1 */
288
289 msleep(5);
290
291 /* setup LCD panel */
292
293 /* cf. drivers/video/omap/lcd_mipid.c */
294 sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
295 msleep(120);
296 /*
297 * [7] - Page Address Mode
298 * [6] - Column Address Mode
299 * [5] - Page / Column Address Mode
300 * [4] - Display Device Line Refresh Order
301 * [3] - RGB/BGR Order
302 * [2] - Display Data Latch Data Order
303 * [1] - Flip Horizontal
304 * [0] - Flip Vertical
305 */
306 sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
307 /* cf. set_data_lines() */
308 sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
309 pixfmt << 4);
310 sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
311
312 return 0;
313}
314
315static int __init sh_mipi_probe(struct platform_device *pdev)
316{
317 struct sh_mipi *mipi;
318 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
319 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
320 unsigned long rate, f_current;
321 int idx = pdev->id, ret;
322 char dsip_clk[] = "dsi.p_clk";
323
324 if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
325 return -ENODEV;
326
327 mutex_lock(&array_lock);
328 if (idx < 0)
329 for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
330 ;
331
332 if (idx == ARRAY_SIZE(mipi_dsi)) {
333 ret = -EBUSY;
334 goto efindslot;
335 }
336
337 mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
338 if (!mipi) {
339 ret = -ENOMEM;
340 goto ealloc;
341 }
342
343 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
344 dev_err(&pdev->dev, "MIPI register region already claimed\n");
345 ret = -EBUSY;
346 goto ereqreg;
347 }
348
349 mipi->base = ioremap(res->start, resource_size(res));
350 if (!mipi->base) {
351 ret = -ENOMEM;
352 goto emap;
353 }
354
355 mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
356 if (IS_ERR(mipi->dsit_clk)) {
357 ret = PTR_ERR(mipi->dsit_clk);
358 goto eclktget;
359 }
360
361 f_current = clk_get_rate(mipi->dsit_clk);
362 /* 80MHz required by the datasheet */
363 rate = clk_round_rate(mipi->dsit_clk, 80000000);
364 if (rate > 0 && rate != f_current)
365 ret = clk_set_rate(mipi->dsit_clk, rate);
366 else
367 ret = rate;
368 if (ret < 0)
369 goto esettrate;
370
371 dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
372
373 sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
374 mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
375 if (IS_ERR(mipi->dsip_clk)) {
376 ret = PTR_ERR(mipi->dsip_clk);
377 goto eclkpget;
378 }
379
380 f_current = clk_get_rate(mipi->dsip_clk);
381 /* Between 10 and 50MHz */
382 rate = clk_round_rate(mipi->dsip_clk, 24000000);
383 if (rate > 0 && rate != f_current)
384 ret = clk_set_rate(mipi->dsip_clk, rate);
385 else
386 ret = rate;
387 if (ret < 0)
388 goto esetprate;
389
390 dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
391
392 msleep(10);
393
394 ret = clk_enable(mipi->dsit_clk);
395 if (ret < 0)
396 goto eclkton;
397
398 ret = clk_enable(mipi->dsip_clk);
399 if (ret < 0)
400 goto eclkpon;
401
402 mipi_dsi[idx] = mipi;
403
404 ret = sh_mipi_setup(mipi, pdata);
405 if (ret < 0)
406 goto emipisetup;
407
408 mutex_unlock(&array_lock);
409 platform_set_drvdata(pdev, mipi);
410
411 /* Set up LCDC callbacks */
412 pdata->lcd_chan->board_cfg.board_data = mipi;
413 pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
414 pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
415
416 return 0;
417
418emipisetup:
419 mipi_dsi[idx] = NULL;
420 clk_disable(mipi->dsip_clk);
421eclkpon:
422 clk_disable(mipi->dsit_clk);
423eclkton:
424esetprate:
425 clk_put(mipi->dsip_clk);
426eclkpget:
427esettrate:
428 clk_put(mipi->dsit_clk);
429eclktget:
430 iounmap(mipi->base);
431emap:
432 release_mem_region(res->start, resource_size(res));
433ereqreg:
434 kfree(mipi);
435ealloc:
436efindslot:
437 mutex_unlock(&array_lock);
438
439 return ret;
440}
441
442static int __exit sh_mipi_remove(struct platform_device *pdev)
443{
444 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
445 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
446 struct sh_mipi *mipi = platform_get_drvdata(pdev);
447 int i, ret;
448
449 mutex_lock(&array_lock);
450
451 for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
452 ;
453
454 if (i == ARRAY_SIZE(mipi_dsi)) {
455 ret = -EINVAL;
456 } else {
457 ret = 0;
458 mipi_dsi[i] = NULL;
459 }
460
461 mutex_unlock(&array_lock);
462
463 if (ret < 0)
464 return ret;
465
466 pdata->lcd_chan->board_cfg.display_on = NULL;
467 pdata->lcd_chan->board_cfg.display_off = NULL;
468 pdata->lcd_chan->board_cfg.board_data = NULL;
469
470 clk_disable(mipi->dsip_clk);
471 clk_disable(mipi->dsit_clk);
472 clk_put(mipi->dsit_clk);
473 clk_put(mipi->dsip_clk);
474 iounmap(mipi->base);
475 if (res)
476 release_mem_region(res->start, resource_size(res));
477 platform_set_drvdata(pdev, NULL);
478 kfree(mipi);
479
480 return 0;
481}
482
483static struct platform_driver sh_mipi_driver = {
484 .remove = __exit_p(sh_mipi_remove),
485 .shutdown = sh_mipi_shutdown,
486 .driver = {
487 .name = "sh-mipi-dsi",
488 },
489};
490
491static int __init sh_mipi_init(void)
492{
493 return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
494}
495module_init(sh_mipi_init);
496
497static void __exit sh_mipi_exit(void)
498{
499 platform_driver_unregister(&sh_mipi_driver);
500}
501module_exit(sh_mipi_exit);
502
503MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
504MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
505MODULE_LICENSE("GPL v2");
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index f10db6e5f3b5..522832023a69 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -186,6 +186,9 @@
186#define PORT_ALTERA_JTAGUART 91 186#define PORT_ALTERA_JTAGUART 91
187#define PORT_ALTERA_UART 92 187#define PORT_ALTERA_UART 92
188 188
189/* SH-SCI */
190#define PORT_SCIFB 93
191
189#ifdef __KERNEL__ 192#ifdef __KERNEL__
190 193
191#include <linux/compiler.h> 194#include <linux/compiler.h>
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index f5364a1de68b..837efa4e63c2 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -3,7 +3,7 @@
3 3
4#include <linux/serial_core.h> 4#include <linux/serial_core.h>
5#ifdef CONFIG_SERIAL_SH_SCI_DMA 5#ifdef CONFIG_SERIAL_SH_SCI_DMA
6#include <asm/dmaengine.h> 6#include <linux/sh_dma.h>
7#endif 7#endif
8 8
9/* 9/*
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
new file mode 100644
index 000000000000..ddcc8ca7316b
--- /dev/null
+++ b/include/video/mipi_display.h
@@ -0,0 +1,130 @@
1/*
2 * Defines for Mobile Industry Processor Interface (MIPI(R))
3 * Display Working Group standards: DSI, DCS, DBI, DPI
4 *
5 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 * Copyright (C) 2006 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef MIPI_DISPLAY_H
14#define MIPI_DISPLAY_H
15
16/* MIPI DSI Processor-to-Peripheral transaction types */
17enum {
18 MIPI_DSI_V_SYNC_START = 0x01,
19 MIPI_DSI_V_SYNC_END = 0x11,
20 MIPI_DSI_H_SYNC_START = 0x21,
21 MIPI_DSI_H_SYNC_END = 0x31,
22
23 MIPI_DSI_COLOR_MODE_OFF = 0x02,
24 MIPI_DSI_COLOR_MODE_ON = 0x12,
25 MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
26 MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
27
28 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
29 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
30 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
31
32 MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
33 MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
34 MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
35
36 MIPI_DSI_DCS_SHORT_WRITE = 0x05,
37 MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
38
39 MIPI_DSI_DCS_READ = 0x06,
40
41 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
42
43 MIPI_DSI_END_OF_TRANSMISSION = 0x08,
44
45 MIPI_DSI_NULL_PACKET = 0x09,
46 MIPI_DSI_BLANKING_PACKET = 0x19,
47 MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
48 MIPI_DSI_DCS_LONG_WRITE = 0x39,
49
50 MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
51 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
52 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
53
54 MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
55 MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
56 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
57
58 MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
59 MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
60 MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
61 MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
62};
63
64/* MIPI DSI Peripheral-to-Processor transaction types */
65enum {
66 MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
67 MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
68 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
69 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
70 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
71 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
72 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
73 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
74};
75
76/* MIPI DCS commands */
77enum {
78 MIPI_DCS_NOP = 0x00,
79 MIPI_DCS_SOFT_RESET = 0x01,
80 MIPI_DCS_GET_DISPLAY_ID = 0x04,
81 MIPI_DCS_GET_RED_CHANNEL = 0x06,
82 MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
83 MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
84 MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
85 MIPI_DCS_GET_POWER_MODE = 0x0A,
86 MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
87 MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
88 MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
89 MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
90 MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
91 MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
92 MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
93 MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
94 MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
95 MIPI_DCS_EXIT_INVERT_MODE = 0x20,
96 MIPI_DCS_ENTER_INVERT_MODE = 0x21,
97 MIPI_DCS_SET_GAMMA_CURVE = 0x26,
98 MIPI_DCS_SET_DISPLAY_OFF = 0x28,
99 MIPI_DCS_SET_DISPLAY_ON = 0x29,
100 MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
101 MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
102 MIPI_DCS_WRITE_MEMORY_START = 0x2C,
103 MIPI_DCS_WRITE_LUT = 0x2D,
104 MIPI_DCS_READ_MEMORY_START = 0x2E,
105 MIPI_DCS_SET_PARTIAL_AREA = 0x30,
106 MIPI_DCS_SET_SCROLL_AREA = 0x33,
107 MIPI_DCS_SET_TEAR_OFF = 0x34,
108 MIPI_DCS_SET_TEAR_ON = 0x35,
109 MIPI_DCS_SET_ADDRESS_MODE = 0x36,
110 MIPI_DCS_SET_SCROLL_START = 0x37,
111 MIPI_DCS_EXIT_IDLE_MODE = 0x38,
112 MIPI_DCS_ENTER_IDLE_MODE = 0x39,
113 MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
114 MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
115 MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
116 MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
117 MIPI_DCS_GET_SCANLINE = 0x45,
118 MIPI_DCS_READ_DDB_START = 0xA1,
119 MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
120};
121
122/* MIPI DCS pixel formats */
123#define MIPI_DCS_PIXEL_FMT_24BIT 7
124#define MIPI_DCS_PIXEL_FMT_18BIT 6
125#define MIPI_DCS_PIXEL_FMT_16BIT 5
126#define MIPI_DCS_PIXEL_FMT_12BIT 3
127#define MIPI_DCS_PIXEL_FMT_8BIT 2
128#define MIPI_DCS_PIXEL_FMT_3BIT 1
129
130#endif
diff --git a/include/video/sh_mipi_dsi.h b/include/video/sh_mipi_dsi.h
new file mode 100644
index 000000000000..18bca08f9f59
--- /dev/null
+++ b/include/video/sh_mipi_dsi.h
@@ -0,0 +1,35 @@
1/*
2 * Public SH-mobile MIPI DSI header
3 *
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef VIDEO_SH_MIPI_DSI_H
11#define VIDEO_SH_MIPI_DSI_H
12
13enum sh_mipi_dsi_data_fmt {
14 MIPI_RGB888,
15 MIPI_RGB565,
16 MIPI_RGB666_LP,
17 MIPI_RGB666,
18 MIPI_BGR888,
19 MIPI_BGR565,
20 MIPI_BGR666_LP,
21 MIPI_BGR666,
22 MIPI_YUYV,
23 MIPI_UYVY,
24 MIPI_YUV420_L,
25 MIPI_YUV420,
26};
27
28struct sh_mobile_lcdc_chan_cfg;
29
30struct sh_mipi_dsi_info {
31 enum sh_mipi_dsi_data_fmt data_format;
32 struct sh_mobile_lcdc_chan_cfg *lcd_chan;
33};
34
35#endif
diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h
index 288205457713..24393449960f 100644
--- a/include/video/sh_mobile_lcdc.h
+++ b/include/video/sh_mobile_lcdc.h
@@ -3,24 +3,27 @@
3 3
4#include <linux/fb.h> 4#include <linux/fb.h>
5 5
6enum { RGB8, /* 24bpp, 8:8:8 */ 6enum {
7 RGB9, /* 18bpp, 9:9 */ 7 RGB8, /* 24bpp, 8:8:8 */
8 RGB12A, /* 24bpp, 12:12 */ 8 RGB9, /* 18bpp, 9:9 */
9 RGB12B, /* 12bpp */ 9 RGB12A, /* 24bpp, 12:12 */
10 RGB16, /* 16bpp */ 10 RGB12B, /* 12bpp */
11 RGB18, /* 18bpp */ 11 RGB16, /* 16bpp */
12 RGB24, /* 24bpp */ 12 RGB18, /* 18bpp */
13 SYS8A, /* 24bpp, 8:8:8 */ 13 RGB24, /* 24bpp */
14 SYS8B, /* 18bpp, 8:8:2 */ 14 YUV422, /* 16bpp */
15 SYS8C, /* 18bpp, 2:8:8 */ 15 SYS8A, /* 24bpp, 8:8:8 */
16 SYS8D, /* 16bpp, 8:8 */ 16 SYS8B, /* 18bpp, 8:8:2 */
17 SYS9, /* 18bpp, 9:9 */ 17 SYS8C, /* 18bpp, 2:8:8 */
18 SYS12, /* 24bpp, 12:12 */ 18 SYS8D, /* 16bpp, 8:8 */
19 SYS16A, /* 16bpp */ 19 SYS9, /* 18bpp, 9:9 */
20 SYS16B, /* 18bpp, 16:2 */ 20 SYS12, /* 24bpp, 12:12 */
21 SYS16C, /* 18bpp, 2:16 */ 21 SYS16A, /* 16bpp */
22 SYS18, /* 18bpp */ 22 SYS16B, /* 18bpp, 16:2 */
23 SYS24 };/* 24bpp */ 23 SYS16C, /* 18bpp, 2:16 */
24 SYS18, /* 18bpp */
25 SYS24, /* 24bpp */
26};
24 27
25enum { LCDC_CHAN_DISABLED = 0, 28enum { LCDC_CHAN_DISABLED = 0,
26 LCDC_CHAN_MAINLCD, 29 LCDC_CHAN_MAINLCD,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 07:27:25 -0500