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-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 9f883bf76953..33b72144db31 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -30,6 +30,7 @@
30 * measurement, and debugging facilities. 30 * measurement, and debugging facilities.
31 */ 31 */
32 32
33#include <linux/compiler.h>
33#include <linux/irqflags.h> 34#include <linux/irqflags.h>
34#include <asm/octeon/cvmx.h> 35#include <asm/octeon/cvmx.h>
35#include <asm/octeon/cvmx-l2c.h> 36#include <asm/octeon/cvmx-l2c.h>
@@ -285,22 +286,22 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
285 */ 286 */
286static void fault_in(uint64_t addr, int len) 287static void fault_in(uint64_t addr, int len)
287{ 288{
288 volatile char *ptr; 289 char *ptr;
289 volatile char dummy; 290
290 /* 291 /*
291 * Adjust addr and length so we get all cache lines even for 292 * Adjust addr and length so we get all cache lines even for
292 * small ranges spanning two cache lines. 293 * small ranges spanning two cache lines.
293 */ 294 */
294 len += addr & CVMX_CACHE_LINE_MASK; 295 len += addr & CVMX_CACHE_LINE_MASK;
295 addr &= ~CVMX_CACHE_LINE_MASK; 296 addr &= ~CVMX_CACHE_LINE_MASK;
296 ptr = (volatile char *)cvmx_phys_to_ptr(addr); 297 ptr = cvmx_phys_to_ptr(addr);
297 /* 298 /*
298 * Invalidate L1 cache to make sure all loads result in data 299 * Invalidate L1 cache to make sure all loads result in data
299 * being in L2. 300 * being in L2.
300 */ 301 */
301 CVMX_DCACHE_INVALIDATE; 302 CVMX_DCACHE_INVALIDATE;
302 while (len > 0) { 303 while (len > 0) {
303 dummy += *ptr; 304 ACCESS_ONCE(*ptr);
304 len -= CVMX_CACHE_LINE_SIZE; 305 len -= CVMX_CACHE_LINE_SIZE;
305 ptr += CVMX_CACHE_LINE_SIZE; 306 ptr += CVMX_CACHE_LINE_SIZE;
306 } 307 }