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-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c51
1 files changed, 35 insertions, 16 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index bcffee001bfa..e069a9be93df 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -46,10 +46,19 @@
46 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 46 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
47 47
48/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 48/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
49#define DPLL_FINT_BAND1_MIN 750000 49#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
50#define DPLL_FINT_BAND1_MAX 2100000 50#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
51#define DPLL_FINT_BAND2_MIN 7500000 51#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
52#define DPLL_FINT_BAND2_MAX 21000000 52#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
53
54/*
55 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
56 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 */
58#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
59#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
60#define OMAP3PLUS_DPLL_FINT_MIN 32000
61#define OMAP3PLUS_DPLL_FINT_MAX 52000000
53 62
54/* _dpll_test_fint() return codes */ 63/* _dpll_test_fint() return codes */
55#define DPLL_FINT_UNDERFLOW -1 64#define DPLL_FINT_UNDERFLOW -1
@@ -71,33 +80,43 @@
71static int _dpll_test_fint(struct clk *clk, u8 n) 80static int _dpll_test_fint(struct clk *clk, u8 n)
72{ 81{
73 struct dpll_data *dd; 82 struct dpll_data *dd;
74 long fint; 83 long fint, fint_min, fint_max;
75 int ret = 0; 84 int ret = 0;
76 85
77 dd = clk->dpll_data; 86 dd = clk->dpll_data;
78 87
79 /* DPLL divider must result in a valid jitter correction val */ 88 /* DPLL divider must result in a valid jitter correction val */
80 fint = clk->parent->rate / n; 89 fint = clk->parent->rate / n;
81 if (fint < DPLL_FINT_BAND1_MIN) {
82 90
91 if (cpu_is_omap24xx()) {
92 /* Should not be called for OMAP2, so warn if it is called */
93 WARN(1, "No fint limits available for OMAP2!\n");
94 return DPLL_FINT_INVALID;
95 } else if (cpu_is_omap3430()) {
96 fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
97 fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
98 } else if (dd->flags & DPLL_J_TYPE) {
99 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
100 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
101 } else {
102 fint_min = OMAP3PLUS_DPLL_FINT_MIN;
103 fint_max = OMAP3PLUS_DPLL_FINT_MAX;
104 }
105
106 if (fint < fint_min) {
83 pr_debug("rejecting n=%d due to Fint failure, " 107 pr_debug("rejecting n=%d due to Fint failure, "
84 "lowering max_divider\n", n); 108 "lowering max_divider\n", n);
85 dd->max_divider = n; 109 dd->max_divider = n;
86 ret = DPLL_FINT_UNDERFLOW; 110 ret = DPLL_FINT_UNDERFLOW;
87 111 } else if (fint > fint_max) {
88 } else if (fint > DPLL_FINT_BAND1_MAX &&
89 fint < DPLL_FINT_BAND2_MIN) {
90
91 pr_debug("rejecting n=%d due to Fint failure\n", n);
92 ret = DPLL_FINT_INVALID;
93
94 } else if (fint > DPLL_FINT_BAND2_MAX) {
95
96 pr_debug("rejecting n=%d due to Fint failure, " 112 pr_debug("rejecting n=%d due to Fint failure, "
97 "boosting min_divider\n", n); 113 "boosting min_divider\n", n);
98 dd->min_divider = n; 114 dd->min_divider = n;
99 ret = DPLL_FINT_INVALID; 115 ret = DPLL_FINT_INVALID;
100 116 } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
117 fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
118 pr_debug("rejecting n=%d due to Fint failure\n", n);
119 ret = DPLL_FINT_INVALID;
101 } 120 }
102 121
103 return ret; 122 return ret;