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-rw-r--r--drivers/sh/clk/cpg.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index ed8bc70730f5..e4a2edf139f7 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -252,7 +252,7 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
252 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 252 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
253 table, &clk->arch_flags); 253 table, &clk->arch_flags);
254 254
255 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f; 255 idx = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0x000f;
256 256
257 return clk->freq_table[idx].frequency; 257 return clk->freq_table[idx].frequency;
258} 258}
@@ -270,15 +270,15 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
270 */ 270 */
271 271
272 if (parent->flags & CLK_ENABLE_ON_INIT) 272 if (parent->flags & CLK_ENABLE_ON_INIT)
273 value = __raw_readl(clk->enable_reg) & ~(1 << 7); 273 value = ioread32(clk->mapped_reg) & ~(1 << 7);
274 else 274 else
275 value = __raw_readl(clk->enable_reg) | (1 << 7); 275 value = ioread32(clk->mapped_reg) | (1 << 7);
276 276
277 ret = clk_reparent(clk, parent); 277 ret = clk_reparent(clk, parent);
278 if (ret < 0) 278 if (ret < 0)
279 return ret; 279 return ret;
280 280
281 __raw_writel(value, clk->enable_reg); 281 iowrite32(value, clk->mapped_reg);
282 282
283 /* Rebiuld the frequency table */ 283 /* Rebiuld the frequency table */
284 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 284 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -295,10 +295,10 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
295 if (idx < 0) 295 if (idx < 0)
296 return idx; 296 return idx;
297 297
298 value = __raw_readl(clk->enable_reg); 298 value = ioread32(clk->mapped_reg);
299 value &= ~(0xf << clk->enable_bit); 299 value &= ~(0xf << clk->enable_bit);
300 value |= (idx << clk->enable_bit); 300 value |= (idx << clk->enable_bit);
301 __raw_writel(value, clk->enable_reg); 301 iowrite32(value, clk->mapped_reg);
302 302
303 if (d4t->kick) 303 if (d4t->kick)
304 d4t->kick(clk); 304 d4t->kick(clk);
@@ -308,13 +308,13 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
308 308
309static int sh_clk_div4_enable(struct clk *clk) 309static int sh_clk_div4_enable(struct clk *clk)
310{ 310{
311 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg); 311 iowrite32(ioread32(clk->mapped_reg) & ~(1 << 8), clk->mapped_reg);
312 return 0; 312 return 0;
313} 313}
314 314
315static void sh_clk_div4_disable(struct clk *clk) 315static void sh_clk_div4_disable(struct clk *clk)
316{ 316{
317 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg); 317 iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg);
318} 318}
319 319
320static struct clk_ops sh_clk_div4_clk_ops = { 320static struct clk_ops sh_clk_div4_clk_ops = {