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authorNicolin Chen <b42378@freescale.com>2013-08-05 02:19:15 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:01:00 -0400
commit5a81c3c745925b5bc3c38ca02786f17982b962ee (patch)
tree08076c8ce4becb71d44c6e829de84c4ae80eba17 /sound/soc/fsl/fsl_ssi.c
parent9c5e14c463b81d1bc34f2e9605db30f302b4cff5 (diff)
ENGR00273838-2 ASoC: fsl: Enable and disable Tx/Rx DMA symmetrically
Enable DMA when TRIGGER_START, and disable it when TRIGGER_STOP, otherwise the hardware dma request would not be clearred even if SSI is disabled. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
Diffstat (limited to 'sound/soc/fsl/fsl_ssi.c')
-rw-r--r--sound/soc/fsl/fsl_ssi.c22
1 files changed, 13 insertions, 9 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index fd171fdcf932..888feb6cdd1c 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -105,10 +105,9 @@ void dump_reg(struct ccsr_ssi __iomem *ssi) {}
105#endif 105#endif
106 106
107/* SIER bitflag of interrupts to enable */ 107/* SIER bitflag of interrupts to enable */
108#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ 108#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TIE | \
109 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ 109 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TUE1_EN | \
110 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ 110 CCSR_SSI_SIER_RFRC_EN | CCSR_SSI_SIER_RIE | \
111 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
112 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) 111 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
113 112
114/** 113/**
@@ -512,22 +511,27 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
512 switch (cmd) { 511 switch (cmd) {
513 case SNDRV_PCM_TRIGGER_START: 512 case SNDRV_PCM_TRIGGER_START:
514 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 513 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
515 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 514 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
516 write_ssi_mask(&ssi->scr, 0, 515 write_ssi_mask(&ssi->scr, 0,
517 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); 516 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
518 else 517 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TDMAE);
518 } else {
519 write_ssi_mask(&ssi->scr, 0, 519 write_ssi_mask(&ssi->scr, 0,
520 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); 520 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
521 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RDMAE);
522 }
521 dump_reg(ssi); 523 dump_reg(ssi);
522 break; 524 break;
523 525
524 case SNDRV_PCM_TRIGGER_STOP: 526 case SNDRV_PCM_TRIGGER_STOP:
525 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 527 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
526 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 528 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
527 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0); 529 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
528 else 530 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TDMAE, 0);
531 } else {
529 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0); 532 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
530 533 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RDMAE, 0);
534 }
531 if ((read_ssi(&ssi->scr) & (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) 535 if ((read_ssi(&ssi->scr) & (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
532 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); 536 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
533 break; 537 break;