ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streams

We only enable one side interrupt for each stream since over/underrun
on the opposite stream would be resulted from what we previously did,
enabling TERE but remaining FRDE disabled, even though the xrun on the
opposite direction will not break the current stream.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 20ea0d31528f7a461a4ecfb5924ca228bf3ca3c5)

1 files changed, 6 insertions, 2 deletions

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index bdfd497811bd..d64c33f32bf9 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -396,6 +396,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
                 }
 
                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+                                   FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
+                regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
                                    FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
                 break;
         case SNDRV_PCM_TRIGGER_STOP:
@@ -403,6 +405,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
                                    FSL_SAI_CSR_FRDE, 0);
+                regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+                                   FSL_SAI_CSR_xIE_MASK, 0);
 
                 if (!(tcsr & FSL_SAI_CSR_FRDE || rcsr & FSL_SAI_CSR_FRDE)) {
                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
@@ -463,8 +467,8 @@ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
 {
         struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
 
-        regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, FSL_SAI_FLAGS);
-        regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, FSL_SAI_FLAGS);
+        regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
+        regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
         regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
                            FSL_SAI_MAXBURST_TX * 2);
         regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,