edac: move dimm properties to struct dimm_info

On systems based on chip select rows, all channels need to use memories
with the same properties, otherwise the memories on channels A and B
won't be recognized.

However, such assumption is not true for all types of memory
controllers.

Controllers for FB-DIMM's don't have such requirements.

Also, modern Intel controllers seem to be capable of handling such
differences.

So, we need to get rid of storing the DIMM information into a per-csrow
data, storing it, instead at the right place.

The first step is to move grain, mtype, dtype and edac_mode to the
per-dimm struct.

Reviewed-by: Aristeu Rozanski <arozansk@redhat.com>
Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
Cc: Mark Gross <mark.gross@intel.com>
Cc: Jason Uhlenkott <juhlenko@akamai.com>
Cc: Tim Small <tim@buttersideup.com>
Cc: Ranganathan Desikan <ravi@jetztechnologies.com>
Cc: "Arvind R." <arvino55@gmail.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Egor Martovetsky <egor@pasemi.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Joe Perches <joe@perches.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Hitoshi Mitake <h.mitake@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: James Bottomley <James.Bottomley@parallels.com>
Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Mike Williams <mike@mikebwilliams.com>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

1 files changed, 12 insertions, 5 deletions

diff --git a/drivers/edac/i82875p_edac.c b/drivers/edac/i82875p_edac.c
index 10f15d85fb5e..eac574285da8 100644
--- a/drivers/edac/i82875p_edac.c
+++ b/drivers/edac/i82875p_edac.c
@@ -342,11 +342,13 @@ static void i82875p_init_csrows(struct mem_ctl_info *mci,
                                 void __iomem * ovrfl_window, u32 drc)
 {
         struct csrow_info *csrow;
+        struct dimm_info *dimm;
+        unsigned nr_chans = dual_channel_active(drc) + 1;
         unsigned long last_cumul_size;
         u8 value;
         u32 drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
         u32 cumul_size;
-        int index;
+        int index, j;
 
         drc_ddim = (drc >> 18) & 0x1;
         last_cumul_size = 0;
@@ -371,10 +373,15 @@ static void i82875p_init_csrows(struct mem_ctl_info *mci,
                 csrow->last_page = cumul_size - 1;
                 csrow->nr_pages = cumul_size - last_cumul_size;
                 last_cumul_size = cumul_size;
-                csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
-                csrow->mtype = MEM_DDR;
-                csrow->dtype = DEV_UNKNOWN;
-                csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
+
+                for (j = 0; j < nr_chans; j++) {
+                        dimm = csrow->channels[j].dimm;
+
+                        dimm->grain = 1 << 12;  /* I82875P_EAP has 4KiB reolution */
+                        dimm->mtype = MEM_DDR;
+                        dimm->dtype = DEV_UNKNOWN;
+                        dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
+                }
         }
 }