edac: move dimm properties to struct dimm_info

On systems based on chip select rows, all channels need to use memories
with the same properties, otherwise the memories on channels A and B
won't be recognized.

However, such assumption is not true for all types of memory
controllers.

Controllers for FB-DIMM's don't have such requirements.

Also, modern Intel controllers seem to be capable of handling such
differences.

So, we need to get rid of storing the DIMM information into a per-csrow
data, storing it, instead at the right place.

The first step is to move grain, mtype, dtype and edac_mode to the
per-dimm struct.

Reviewed-by: Aristeu Rozanski <arozansk@redhat.com>
Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
Cc: Mark Gross <mark.gross@intel.com>
Cc: Jason Uhlenkott <juhlenko@akamai.com>
Cc: Tim Small <tim@buttersideup.com>
Cc: Ranganathan Desikan <ravi@jetztechnologies.com>
Cc: "Arvind R." <arvino55@gmail.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Egor Martovetsky <egor@pasemi.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Joe Perches <joe@perches.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Hitoshi Mitake <h.mitake@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: James Bottomley <James.Bottomley@parallels.com>
Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Mike Williams <mike@mikebwilliams.com>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

1 files changed, 15 insertions, 10 deletions

diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index 3bafa3bca148..4bfcb3da3f01 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -618,6 +618,7 @@ static int decode_mtr(struct i7300_pvt *pvt,
                       int slot, int ch, int branch,
                       struct i7300_dimm_info *dinfo,
                       struct csrow_info *p_csrow,
+                      struct dimm_info *dimm,
                       u32 *nr_pages)
 {
         int mtr, ans, addrBits, channel;
@@ -663,10 +664,7 @@ static int decode_mtr(struct i7300_pvt *pvt,
         debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
         debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
 
-        p_csrow->grain = 8;
-        p_csrow->mtype = MEM_FB_DDR2;
         p_csrow->csrow_idx = slot;
-        p_csrow->page_mask = 0;
 
         /*
          * The type of error detection actually depends of the
@@ -677,15 +675,17 @@ static int decode_mtr(struct i7300_pvt *pvt,
          * See datasheet Sections 7.3.6 to 7.3.8
          */
 
+        dimm->grain = 8;
+        dimm->mtype = MEM_FB_DDR2;
         if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
-                p_csrow->edac_mode = EDAC_SECDED;
+                dimm->edac_mode = EDAC_SECDED;
                 debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
         } else {
                 debugf2("\t\tECC code is on Lockstep mode\n");
                 if (MTR_DRAM_WIDTH(mtr) == 8)
-                        p_csrow->edac_mode = EDAC_S8ECD8ED;
+                        dimm->edac_mode = EDAC_S8ECD8ED;
                 else
-                        p_csrow->edac_mode = EDAC_S4ECD4ED;
+                        dimm->edac_mode = EDAC_S4ECD4ED;
         }
 
         /* ask what device type on this row */
@@ -694,9 +694,9 @@ static int decode_mtr(struct i7300_pvt *pvt,
                         IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
                                             "enhanced" : "normal");
 
-                p_csrow->dtype = DEV_X8;
+                dimm->dtype = DEV_X8;
         } else
-                p_csrow->dtype = DEV_X4;
+                dimm->dtype = DEV_X4;
 
         return mtr;
 }
@@ -779,6 +779,7 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
         int mtr;
         int ch, branch, slot, channel;
         u32 last_page = 0, nr_pages;
+        struct dimm_info *dimm;
 
         pvt = mci->pvt_info;
 
@@ -803,20 +804,24 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
         }
 
         /* Get the set of MTR[0-7] regs by each branch */
+        nr_pages = 0;
         for (slot = 0; slot < MAX_SLOTS; slot++) {
                 int where = mtr_regs[slot];
                 for (branch = 0; branch < MAX_BRANCHES; branch++) {
                         pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
                                         where,
                                         &pvt->mtr[slot][branch]);
-                        for (ch = 0; ch < MAX_BRANCHES; ch++) {
+                        for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) {
                                 int channel = to_channel(ch, branch);
 
                                 dinfo = &pvt->dimm_info[slot][channel];
                                 p_csrow = &mci->csrows[slot];
 
+                                dimm = p_csrow->channels[branch * MAX_CH_PER_BRANCH + ch].dimm;
+
                                 mtr = decode_mtr(pvt, slot, ch, branch,
-                                                 dinfo, p_csrow, &nr_pages);
+                                                 dinfo, p_csrow, dimm,
+                                                 &nr_pages);
                                 /* if no DIMMS on this row, continue */
                                 if (!MTR_DIMMS_PRESENT(mtr))
                                         continue;