Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next

Daniel Vetter wrote
First pull request for 3.5-next, slightly large than usual because new
things kept coming in since the last pull for 3.4.
Highlights:
- first batch of hw enablement for vlv (Jesse et al) and hsw (Eugeni). pci
 ids are not yet added, and there's still quite a few patches to merge
 (mostly modesetting). To make QA easier I've decided to merge this stuff
 in pieces.
- loads of cleanups and prep patches spurred by the above. Especially vlv
 is a real frankenstein chip, but also hsw is stretching our driver's
 code design. Expect more to come in this area for 3.5.
- more gmbus fixes, cleanups and improvements by Daniel Kurtz. Again,
 there are more patches needed (and some already queued up), but I wanted
 to split this a bit for better testing.
- pwrite/pread rework and retuning. This series has been in the works for
 a few months already and a lot of i-g-t tests have been created for it.
 Now it's finally ready to be merged.  Note that one patch in this series
 touches include/pagemap.h, that patch is acked-by akpm.
- reduce mappable pressure and relocation throughput improvements from
 Chris.
- mmap offset exhaustion mitigation by Chris Wilson.
- a start at figuring out which codepaths in our messy dri1/ums+gem/kms
 driver we actually need to support by bailing out of unsupported case.
 The driver now refuses to load without kms on gen6+ and disallows a few
 ioctls that userspace never used in certain cases. More of this will
 definitely come.
- More decoupling of global gtt and ppgtt.
- Improved dual-link lvds detection by Takashi Iwai.
- Shut up the compiler + plus fix the fallout (Ben)
- Inverted panel brightness handling (mostly Acer manages to break things
 in this way).
- Small fixlets and adjustements and some minor things to help debugging.

Regression-wise QA reported quite a few issues on ivb, but all of them
turned out to be hw stability issues which are already fixed in
drm-intel-fixes (QA runs the nightly regression tests on -next alone,
without -fixes automatically merged in). There's still one issue open on
snb, it looks like occlusion query writes are not quite as cache coherent
as we've expected. With some of the pwrite adjustements we can now
reliably hit this. Kernel workaround for it is in the works."

* 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits)
  drm/i915: VCS is not the last ring
  drm/i915: Add a dual link lvds quirk for MacBook Pro 8,2
  drm/i915: make quirks more verbose
  drm/i915: dump the DMA fetch addr register on pre-gen6
  drm/i915/sdvo: Include YRPB as an additional TV output type
  drm/i915: disallow gem init ioctl on ilk
  drm/i915: refuse to load on gen6+ without kms
  drm/i915: extract gt interrupt handler
  drm/i915: use render gen to switch ring irq functions
  drm/i915: rip out old HWSTAM missed irq WA for vlv
  drm/i915: open code gen6+ ring irqs
  drm/i915: ring irq cleanups
  drm/i915: add SFUSE_STRAP registers for digital port detection
  drm/i915: add WM_LINETIME registers
  drm/i915: add WRPLL clocks
  drm/i915: add LCPLL control registers
  drm/i915: add SSC offsets for SBI access
  drm/i915: add port clock selection support for HSW
  drm/i915: add S PLL control
  drm/i915: add PIXCLK_GATE register
  ...

Conflicts:
	drivers/char/agp/intel-agp.h
	drivers/char/agp/intel-gtt.c
	drivers/gpu/drm/i915/i915_debugfs.c

1 files changed, 44 insertions, 1 deletions

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 7f025fb620de..1237e7575c3f 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1179,6 +1179,20 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
         writel(addr | pte_flags, intel_private.gtt + entry);
 }
 
+static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
+                                   unsigned int flags)
+{
+        u32 pte_flags;
+
+        pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+
+        /* gen6 has bit11-4 for physical addr bit39-32 */
+        addr |= (addr >> 28) & 0xff0;
+        writel(addr | pte_flags, intel_private.gtt + entry);
+
+        writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
+}
+
 static void gen6_cleanup(void)
 {
 }
@@ -1205,12 +1219,16 @@ static inline int needs_idle_maps(void)
 static int i9xx_setup(void)
 {
         u32 reg_addr;
+        int size = KB(512);
 
         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
 
         reg_addr &= 0xfff80000;
 
-        intel_private.registers = ioremap(reg_addr, 128 * 4096);
+        if (INTEL_GTT_GEN >= 7)
+                size = MB(2);
+
+        intel_private.registers = ioremap(reg_addr, size);
         if (!intel_private.registers)
                 return -ENOMEM;
 
@@ -1354,6 +1372,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
         .check_flags = gen6_check_flags,
         .chipset_flush = i9xx_chipset_flush,
 };
+static const struct intel_gtt_driver valleyview_gtt_driver = {
+        .gen = 7,
+        .setup = i9xx_setup,
+        .cleanup = gen6_cleanup,
+        .write_entry = valleyview_write_entry,
+        .dma_mask_size = 40,
+        .check_flags = gen6_check_flags,
+        .chipset_flush = i9xx_chipset_flush,
+};
 
 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
  * driver and gmch_driver must be non-null, and find_gmch will determine
@@ -1460,6 +1487,22 @@ static const struct intel_gtt_driver_description {
             "Ivybridge", &sandybridge_gtt_driver },
         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
             "Ivybridge", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
+            "ValleyView", &valleyview_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV,
+            "Haswell", &sandybridge_gtt_driver },
         { 0, NULL, NULL }
 };