diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-03-28 16:39:34 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-03-28 18:07:38 -0400 |
commit | 64757876215fcc515403639fa0bd19e8da7ab06b (patch) | |
tree | d0d9c58d6ea73a50181b62f431a1e517a7816643 /drivers/char/agp/intel-gtt.c | |
parent | 4b60d29ee00cb2114075e8b5c2c23928bbd76c28 (diff) |
agp/intel: add ValleyView AGP driver
... and bind it right to the PCI id.
Note that there are still a few things to fix here:
- we need to move the tlb flush to a better place in drm/i915.
- we need to check snoop support on vlv and implement it.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: squash follow-on patch and add todo items to commit msg.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r-- | drivers/char/agp/intel-gtt.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 269cb0287b10..08336ba18cac 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c | |||
@@ -1179,6 +1179,20 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, | |||
1179 | writel(addr | pte_flags, intel_private.gtt + entry); | 1179 | writel(addr | pte_flags, intel_private.gtt + entry); |
1180 | } | 1180 | } |
1181 | 1181 | ||
1182 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, | ||
1183 | unsigned int flags) | ||
1184 | { | ||
1185 | u32 pte_flags; | ||
1186 | |||
1187 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; | ||
1188 | |||
1189 | /* gen6 has bit11-4 for physical addr bit39-32 */ | ||
1190 | addr |= (addr >> 28) & 0xff0; | ||
1191 | writel(addr | pte_flags, intel_private.gtt + entry); | ||
1192 | |||
1193 | writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV); | ||
1194 | } | ||
1195 | |||
1182 | static void gen6_cleanup(void) | 1196 | static void gen6_cleanup(void) |
1183 | { | 1197 | { |
1184 | } | 1198 | } |
@@ -1359,6 +1373,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = { | |||
1359 | .check_flags = gen6_check_flags, | 1373 | .check_flags = gen6_check_flags, |
1360 | .chipset_flush = i9xx_chipset_flush, | 1374 | .chipset_flush = i9xx_chipset_flush, |
1361 | }; | 1375 | }; |
1376 | static const struct intel_gtt_driver valleyview_gtt_driver = { | ||
1377 | .gen = 7, | ||
1378 | .setup = i9xx_setup, | ||
1379 | .cleanup = gen6_cleanup, | ||
1380 | .write_entry = valleyview_write_entry, | ||
1381 | .dma_mask_size = 40, | ||
1382 | .check_flags = gen6_check_flags, | ||
1383 | .chipset_flush = i9xx_chipset_flush, | ||
1384 | }; | ||
1362 | 1385 | ||
1363 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of | 1386 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1364 | * driver and gmch_driver must be non-null, and find_gmch will determine | 1387 | * driver and gmch_driver must be non-null, and find_gmch will determine |
@@ -1463,6 +1486,8 @@ static const struct intel_gtt_driver_description { | |||
1463 | "Ivybridge", &sandybridge_gtt_driver }, | 1486 | "Ivybridge", &sandybridge_gtt_driver }, |
1464 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, | 1487 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, |
1465 | "Ivybridge", &sandybridge_gtt_driver }, | 1488 | "Ivybridge", &sandybridge_gtt_driver }, |
1489 | { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, | ||
1490 | "ValleyView", &valleyview_gtt_driver }, | ||
1466 | { 0, NULL, NULL } | 1491 | { 0, NULL, NULL } |
1467 | }; | 1492 | }; |
1468 | 1493 | ||