perf/x86/intel/P4: Robistify P4 PMU types

Linus found, while extending integer type extension checks in the
sparse static code checker, various fragile patterns of mixed
signed/unsigned  64-bit/32-bit integer use in perf_events_p4.c.

The relevant hardware register ABI is 64 bit wide on 32-bit
kernels as  well, so clean it all up a bit, remove unnecessary
casts, and make sure we  use 64-bit unsigned integers in these
places.

[ Unfortunately this patch was not tested on real P4 hardware,
  those are pretty rare already. If this patch causes any
  problems on P4 hardware then please holler ... ]

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: David Miller <davem@davemloft.net>
Cc: Theodore Ts'o <tytso@mit.edu>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20130424072630.GB1780@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 4 insertions, 5 deletions

diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 92c7e39a079f..3486e6660357 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void)
          * So at moment let leave metrics turned on forever -- it's
          * ok for now but need to be revisited!
          *
-         * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0);
-         * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
+         * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0);
+         * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0);
          */
 }
 
@@ -910,8 +910,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event)
          * asserted again and again
          */
         (void)wrmsrl_safe(hwc->config_base,
-                (u64)(p4_config_unpack_cccr(hwc->config)) &
-                        ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
+                p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
 }
 
 static void p4_pmu_disable_all(void)
@@ -957,7 +956,7 @@ static void p4_pmu_enable_event(struct perf_event *event)
         u64 escr_addr, cccr;
 
         bind = &p4_event_bind_map[idx];
-        escr_addr = (u64)bind->escr_msr[thread];
+        escr_addr = bind->escr_msr[thread];
 
         /*
          * - we dont support cascaded counters yet