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authorRobin Gong <b38343@freescale.com>2014-03-06 06:36:02 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:57:56 -0400
commitbdf22c3391a474e17e3f7e2859d050f44f6fea2b (patch)
treec1d2e41bd14a594e69ed2ff5e302634021c23c7d
parent32e4e161b087bfdcea74bd80f0b24c341092c96b (diff)
ENGR00301078-2: ARM: dts: imx6sl-evk: add support for pfuze200 on imx6sl-evk
move pmic device node from imx6sl-evk.dtsi to upper-level, and add another layer on imx6sl-evk to diff pfuze100 or pfuze200. Meanwhile only works in ldo-enable mode if using pfuze200, since 'SW1C' switch regulator is cut for cost-down which means VDDARM_IN and VDDSOC_IN have to share the same switch regulator Signed-off-by: Robin Gong <b38343@freescale.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/imx6sl-evk-common.dtsi504
-rw-r--r--arch/arm/boot/dts/imx6sl-evk-pf200.dts122
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts497
4 files changed, 630 insertions, 494 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 577b183bef36..02e3d4a48f01 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
135 imx6sl-evk.dtb \ 135 imx6sl-evk.dtb \
136 imx6sl-evk-csi.dtb \ 136 imx6sl-evk-csi.dtb \
137 imx6sl-evk-ldo.dtb \ 137 imx6sl-evk-ldo.dtb \
138 imx6sl-evk-pf200.dtb \
138 imx6sx-17x17-arm2.dtb \ 139 imx6sx-17x17-arm2.dtb \
139 imx6sx-19x19-arm2.dtb \ 140 imx6sx-19x19-arm2.dtb \
140 imx6sx-sdb.dtb \ 141 imx6sx-sdb.dtb \
diff --git a/arch/arm/boot/dts/imx6sl-evk-common.dtsi b/arch/arm/boot/dts/imx6sl-evk-common.dtsi
new file mode 100644
index 000000000000..a1a39694e5b8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk-common.dtsi
@@ -0,0 +1,504 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/ {
10 memory {
11 reg = <0x80000000 0x40000000>;
12 };
13
14 battery: max8903@0 {
15 compatible = "fsl,max8903-charger";
16 pinctrl-names = "default";
17 dok_input = <&gpio4 13 1>;
18 uok_input = <&gpio4 13 1>;
19 chg_input = <&gpio4 15 1>;
20 flt_input = <&gpio4 14 1>;
21 fsl,dcm_always_high;
22 fsl,dc_valid;
23 fsl,adc_disable;
24 status = "okay";
25 };
26
27 regulators {
28 compatible = "simple-bus";
29
30 reg_lcd_3v3: lcd-3v3 {
31 compatible = "regulator-fixed";
32 regulator-name = "lcd-3v3";
33 gpio = <&gpio4 3 0>;
34 enable-active-high;
35 };
36
37 reg_aud3v: wm8962_supply_3v15 {
38 compatible = "regulator-fixed";
39 regulator-name = "wm8962-supply-3v15";
40 regulator-min-microvolt = <3150000>;
41 regulator-max-microvolt = <3150000>;
42 regulator-boot-on;
43 };
44
45 reg_aud4v: wm8962_supply_4v2 {
46 compatible = "regulator-fixed";
47 regulator-name = "wm8962-supply-4v2";
48 regulator-min-microvolt = <4325000>;
49 regulator-max-microvolt = <4325000>;
50 regulator-boot-on;
51 };
52
53 reg_usb_otg1_vbus: usb_otg1_vbus {
54 compatible = "regulator-fixed";
55 regulator-name = "usb_otg1_vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 gpio = <&gpio4 0 0>;
59 enable-active-high;
60 };
61
62 reg_usb_otg2_vbus: usb_otg2_vbus {
63 compatible = "regulator-fixed";
64 regulator-name = "usb_otg2_vbus";
65 regulator-min-microvolt = <5000000>;
66 regulator-max-microvolt = <5000000>;
67 gpio = <&gpio4 2 0>;
68 enable-active-high;
69 };
70 };
71
72 backlight {
73 compatible = "pwm-backlight";
74 pwms = <&pwm1 0 5000000>;
75 brightness-levels = <0 4 8 16 32 64 128 255>;
76 default-brightness-level = <6>;
77 };
78
79 csi_v4l2_cap {
80 compatible = "fsl,imx6sl-csi-v4l2";
81 status = "disabled";
82 };
83
84 pxp_v4l2_out {
85 compatible = "fsl,imx6sl-pxp-v4l2";
86 status = "okay";
87 };
88
89 sound {
90 compatible = "fsl,imx6q-sabresd-wm8962",
91 "fsl,imx-audio-wm8962";
92 model = "wm8962-audio";
93 ssi-controller = <&ssi2>;
94 audio-codec = <&codec>;
95 audio-routing =
96 "Headphone Jack", "HPOUTL",
97 "Headphone Jack", "HPOUTR",
98 "Ext Spk", "SPKOUTL",
99 "Ext Spk", "SPKOUTR",
100 "AMIC", "MICBIAS",
101 "IN3R", "AMIC";
102 amic-mono;
103 mux-int-port = <2>;
104 mux-ext-port = <3>;
105 hp-det-gpios = <&gpio4 19 1>;
106 };
107
108 sound-spdif {
109 compatible = "fsl,imx-audio-spdif",
110 "fsl,imx6sl-evk-spdif";
111 model = "imx-spdif";
112 spdif-controller = <&spdif>;
113 spdif-out;
114 };
115
116 sii902x_reset: sii902x-reset {
117 compatible = "gpio-reset";
118 reset-gpios = <&gpio2 19 1>;
119 reset-delay-us = <100000>;
120 #reset-cells = <0>;
121 };
122};
123
124&audmux {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_audmux_1>;
127 status = "okay";
128};
129
130&csi {
131 status = "disabled";
132};
133
134&ecspi1 {
135 fsl,spi-num-chipselects = <1>;
136 cs-gpios = <&gpio4 11 0>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ecspi1_1>;
139 status = "okay";
140
141 flash: m25p80@0 {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "st,m25p32";
145 spi-max-frequency = <20000000>;
146 reg = <0>;
147 };
148};
149
150&epdc {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_epdc_0>;
153 V3P3-supply = <&V3P3_reg>;
154 VCOM-supply = <&VCOM_reg>;
155 DISPLAY-supply = <&DISPLAY_reg>;
156 status = "okay";
157};
158
159&cpu0 {
160 arm-supply = <&sw1a_reg>;
161 soc-supply = <&sw1c_reg>;
162 pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
163};
164
165&fec {
166 pinctrl-names = "default", "sleep";
167 pinctrl-0 = <&pinctrl_fec_1>;
168 pinctrl-1 = <&pinctrl_fec_1_sleep>;
169 phy-mode = "rmii";
170 phy-reset-gpios = <&gpio4 21 0>; /* GPIO4_21 */
171 phy-reset-duration = <1>;
172 status = "okay";
173};
174
175&gpc {
176 fsl,cpu_pupscr_sw2iso = <0xf>;
177 fsl,cpu_pupscr_sw = <0xf>;
178 fsl,cpu_pdnscr_iso2sw = <0x1>;
179 fsl,cpu_pdnscr_iso = <0x1>;
180 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
181 fsl,wdog-reset = <1>; /* watchdog select of reset source */
182 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
183};
184
185&gpu {
186 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
187};
188
189&i2c1 {
190 clock-frequency = <100000>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_i2c1_1>;
193 status = "okay";
194
195 elan@10 {
196 compatible = "elan,elan-touch";
197 reg = <0x10>;
198 interrupt-parent = <&gpio2>;
199 interrupts = <10 2>;
200 gpio_elan_cs = <&gpio2 9 0>;
201 gpio_elan_rst = <&gpio4 4 0>;
202 gpio_intr = <&gpio2 10 0>;
203 status = "okay";
204 };
205
206 max17135@48 {
207 compatible = "maxim,max17135";
208 reg = <0x48>;
209 vneg_pwrup = <1>;
210 gvee_pwrup = <2>;
211 vpos_pwrup = <10>;
212 gvdd_pwrup = <12>;
213 gvdd_pwrdn = <1>;
214 vpos_pwrdn = <2>;
215 gvee_pwrdn = <8>;
216 vneg_pwrdn = <10>;
217 gpio_pmic_pwrgood = <&gpio2 13 0>;
218 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
219 gpio_pmic_wakeup = <&gpio2 14 0>;
220 gpio_pmic_v3p3 = <&gpio2 7 0>;
221 gpio_pmic_intr = <&gpio2 12 0>;
222
223 regulators {
224 DISPLAY_reg: DISPLAY {
225 regulator-name = "DISPLAY";
226 };
227
228 GVDD_reg: GVDD {
229 /* 20v */
230 regulator-name = "GVDD";
231 };
232
233 GVEE_reg: GVEE {
234 /* -22v */
235 regulator-name = "GVEE";
236 };
237
238 HVINN_reg: HVINN {
239 /* -22v */
240 regulator-name = "HVINN";
241 };
242
243 HVINP_reg: HVINP {
244 /* 20v */
245 regulator-name = "HVINP";
246 };
247
248 VCOM_reg: VCOM {
249 regulator-name = "VCOM";
250 /* 2's-compliment, -4325000 */
251 regulator-min-microvolt = <0xffbe0178>;
252 /* 2's-compliment, -500000 */
253 regulator-max-microvolt = <0xfff85ee0>;
254 };
255
256 VNEG_reg: VNEG {
257 /* -15v */
258 regulator-name = "VNEG";
259 };
260
261 VPOS_reg: VPOS {
262 /* 15v */
263 regulator-name = "VPOS";
264 };
265
266 V3P3_reg: V3P3 {
267 regulator-name = "V3P3";
268 };
269 };
270 };
271
272 mma8450@1c {
273 compatible = "fsl,mma8450";
274 reg = <0x1c>;
275 };
276};
277
278&i2c2 {
279 clock-frequency = <100000>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_i2c2_1>;
282 status = "okay";
283
284 codec: wm8962@1a {
285 compatible = "wlf,wm8962";
286 reg = <0x1a>;
287 clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
288 DCVDD-supply = <&vgen3_reg>;
289 DBVDD-supply = <&reg_aud3v>;
290 AVDD-supply = <&vgen3_reg>;
291 CPVDD-supply = <&vgen3_reg>;
292 MICVDD-supply = <&reg_aud3v>;
293 PLLVDD-supply = <&vgen3_reg>;
294 SPKVDD1-supply = <&reg_aud4v>;
295 SPKVDD2-supply = <&reg_aud4v>;
296 amic-mono;
297 };
298
299 sii902x@39 {
300 compatible = "SiI,sii902x";
301 interrupt-parent = <&gpio2>;
302 interrupts = <10 2>;
303 mode_str ="1280x720M@60";
304 bits-per-pixel = <32>;
305 resets = <&sii902x_reset>;
306 reg = <0x39>;
307 };
308};
309
310&i2c3 {
311 clock-frequency = <100000>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_i2c3_1>;
314 status = "disabled";
315
316 ov564x: ov564x@3c {
317 compatible = "ovti,ov564x";
318 reg = <0x3c>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_csi_0>;
321 clocks = <&clks IMX6SL_CLK_CSI>;
322 clock-names = "csi_mclk";
323 AVDD-supply = <&vgen6_reg>; /* 2.8v */
324 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
325 pwn-gpios = <&gpio1 25 1>;
326 rst-gpios = <&gpio1 26 0>;
327 csi_id = <0>;
328 mclk = <24000000>;
329 mclk_source = <0>;
330 };
331};
332
333&iomuxc {
334 pinctrl-names = "default", "sleep";
335 pinctrl-0 = <&pinctrl_hog>;
336 pinctrl-1 = <&pinctrl_hog_sleep>;
337
338 hog {
339 pinctrl_hog: hoggrp {
340 fsl,pins = <
341 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
342 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
343 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
344 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
345 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
346 MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x80000000
347 MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x110b0
348 MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000
349 MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x80000000
350 MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x80000000
351 MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x80000000
352 MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x80000000
353 MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x170b0
354 MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
355 MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
356 MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
357 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
358 MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
359 MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
360 MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
361 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
362 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
363 >;
364 };
365
366 pinctrl_hog_sleep: hoggrp_sleep {
367 fsl,pins = <
368 MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x3080
369 MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x3080
370 MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x3080
371 >;
372 };
373 };
374};
375
376&kpp {
377 pinctrl-names = "default", "sleep";
378 pinctrl-0 = <&pinctrl_kpp_1>;
379 pinctrl-1 = <&pinctrl_kpp_1_sleep>;
380 linux,keymap = <
381 0x00000067 /* KEY_UP */
382 0x0001006c /* KEY_DOWN */
383 0x0002001c /* KEY_ENTER */
384 0x01000066 /* KEY_HOME */
385 0x0101006a /* KEY_RIGHT */
386 0x01020069 /* KEY_LEFT */
387 0x02000072 /* KEY_VOLUMEDOWN */
388 0x02010073 /* KEY_VOLUMEUP */
389 >;
390 status = "okay";
391};
392
393&lcdif {
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_lcdif_dat_0
396 &pinctrl_lcdif_ctrl_0>;
397 lcd-supply = <&reg_lcd_3v3>;
398 display = <&display>;
399 status = "okay";
400
401 display: display {
402 bits-per-pixel = <16>;
403 bus-width = <24>;
404
405 display-timings {
406 native-mode = <&timing0>;
407 timing0: timing0 {
408 clock-frequency = <33500000>;
409 hactive = <800>;
410 vactive = <480>;
411 hback-porch = <89>;
412 hfront-porch = <164>;
413 vback-porch = <23>;
414 vfront-porch = <10>;
415 hsync-len = <10>;
416 vsync-len = <10>;
417 hsync-active = <0>;
418 vsync-active = <0>;
419 de-active = <1>;
420 pixelclk-active = <0>;
421 };
422 };
423 };
424};
425
426&pwm1 {
427 pinctrl-names = "default", "sleep";
428 pinctrl-0 = <&pinctrl_pwm1_0>;
429 pinctrl-1 = <&pinctrl_pwm1_0_sleep>;
430 status = "okay";
431};
432
433&pxp {
434 status = "okay";
435};
436
437&spdif {
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_spdif_1>;
440 status = "okay";
441};
442
443&ssi2 {
444 fsl,mode = "i2s-slave";
445 status = "okay";
446};
447
448&uart1 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_uart1_1>;
451 status = "okay";
452};
453
454&usbotg1 {
455 vbus-supply = <&reg_usb_otg1_vbus>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_usbotg1_1>;
458 disable-over-current;
459 imx6-usb-charger-detection;
460 status = "okay";
461};
462
463&usbotg2 {
464 vbus-supply = <&reg_usb_otg2_vbus>;
465 dr_mode = "host";
466 disable-over-current;
467 status = "okay";
468};
469
470&usdhc1 {
471 pinctrl-names = "default", "state_100mhz", "state_200mhz";
472 pinctrl-0 = <&pinctrl_usdhc1_1>;
473 pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
474 pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
475 bus-width = <8>;
476 cd-gpios = <&gpio4 7 0>;
477 wp-gpios = <&gpio4 6 0>;
478 keep-power-in-suspend;
479 enable-sdio-wakeup;
480 status = "okay";
481};
482
483&usdhc2 {
484 pinctrl-names = "default", "state_100mhz", "state_200mhz";
485 pinctrl-0 = <&pinctrl_usdhc2_1>;
486 pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
487 pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
488 cd-gpios = <&gpio5 0 0>;
489 wp-gpios = <&gpio4 29 0>;
490 keep-power-in-suspend;
491 enable-sdio-wakeup;
492 status = "okay";
493};
494
495&usdhc3 {
496 pinctrl-names = "default", "state_100mhz", "state_200mhz";
497 pinctrl-0 = <&pinctrl_usdhc3_1>;
498 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
499 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
500 cd-gpios = <&gpio3 22 0>;
501 keep-power-in-suspend;
502 enable-sdio-wakeup;
503 status = "okay";
504};
diff --git a/arch/arm/boot/dts/imx6sl-evk-pf200.dts b/arch/arm/boot/dts/imx6sl-evk-pf200.dts
new file mode 100644
index 000000000000..55d308160b8b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk-pf200.dts
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sl.dtsi"
12#include "imx6sl-evk-common.dtsi"
13
14/ {
15 model = "Freescale i.MX6 SoloLite EVK Board(PFUZE200)";
16 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
17};
18
19&cpu0 {
20 arm-supply = <&reg_arm>;
21 soc-supply = <&reg_soc>;
22 pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
23};
24
25&gpc {
26 fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
27 fsl,wdog-reset = <1>; /* watchdog select of reset source */
28 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
29};
30
31&gpu {
32 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
33};
34
35&i2c1 {
36 pmic: pfuze200@08 {
37 compatible = "fsl,pfuze200";
38 reg = <0x08>;
39
40 regulators {
41 sw1a_reg: sw1ab {
42 regulator-min-microvolt = <300000>;
43 regulator-max-microvolt = <1875000>;
44 regulator-boot-on;
45 regulator-always-on;
46 regulator-ramp-delay = <6250>;
47 };
48
49 sw2_reg: sw2 {
50 regulator-min-microvolt = <800000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
56 sw3a_reg: sw3a {
57 regulator-min-microvolt = <400000>;
58 regulator-max-microvolt = <1975000>;
59 regulator-boot-on;
60 regulator-always-on;
61 };
62
63 sw3b_reg: sw3b {
64 regulator-min-microvolt = <400000>;
65 regulator-max-microvolt = <1975000>;
66 regulator-boot-on;
67 regulator-always-on;
68 };
69
70 swbst_reg: swbst {
71 regulator-min-microvolt = <5000000>;
72 regulator-max-microvolt = <5150000>;
73 };
74
75 snvs_reg: vsnvs {
76 regulator-min-microvolt = <1000000>;
77 regulator-max-microvolt = <3000000>;
78 regulator-boot-on;
79 regulator-always-on;
80 };
81
82 vref_reg: vrefddr {
83 regulator-boot-on;
84 regulator-always-on;
85 };
86
87 vgen1_reg: vgen1 {
88 regulator-min-microvolt = <800000>;
89 regulator-max-microvolt = <1550000>;
90 };
91
92 vgen2_reg: vgen2 {
93 regulator-min-microvolt = <800000>;
94 regulator-max-microvolt = <1550000>;
95 };
96
97 vgen3_reg: vgen3 {
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <3300000>;
100 regulator-always-on;
101 };
102
103 vgen4_reg: vgen4 {
104 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <3300000>;
106 regulator-always-on;
107 };
108
109 vgen5_reg: vgen5 {
110 regulator-min-microvolt = <1800000>;
111 regulator-max-microvolt = <3300000>;
112 regulator-always-on;
113 };
114
115 vgen6_reg: vgen6 {
116 regulator-min-microvolt = <1800000>;
117 regulator-max-microvolt = <3300000>;
118 regulator-always-on;
119 };
120 };
121 };
122};
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 4966f38fa2bb..ed0ce8918bfe 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -9,195 +9,14 @@
9/dts-v1/; 9/dts-v1/;
10 10
11#include "imx6sl.dtsi" 11#include "imx6sl.dtsi"
12#include "imx6sl-evk-common.dtsi"
12 13
13/ { 14/ {
14 model = "Freescale i.MX6 SoloLite EVK Board"; 15 model = "Freescale i.MX6 SoloLite EVK Board(PFUZE100)";
15 compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; 16 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
16
17 memory {
18 reg = <0x80000000 0x40000000>;
19 };
20
21 battery: max8903@0 {
22 compatible = "fsl,max8903-charger";
23 pinctrl-names = "default";
24 dok_input = <&gpio4 13 1>;
25 uok_input = <&gpio4 13 1>;
26 chg_input = <&gpio4 15 1>;
27 flt_input = <&gpio4 14 1>;
28 fsl,dcm_always_high;
29 fsl,dc_valid;
30 fsl,adc_disable;
31 status = "okay";
32 };
33 regulators {
34 compatible = "simple-bus";
35
36 reg_lcd_3v3: lcd-3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "lcd-3v3";
39 gpio = <&gpio4 3 0>;
40 enable-active-high;
41 };
42
43 reg_aud3v: wm8962_supply_3v15 {
44 compatible = "regulator-fixed";
45 regulator-name = "wm8962-supply-3v15";
46 regulator-min-microvolt = <3150000>;
47 regulator-max-microvolt = <3150000>;
48 regulator-boot-on;
49 };
50
51 reg_aud4v: wm8962_supply_4v2 {
52 compatible = "regulator-fixed";
53 regulator-name = "wm8962-supply-4v2";
54 regulator-min-microvolt = <4325000>;
55 regulator-max-microvolt = <4325000>;
56 regulator-boot-on;
57 };
58
59 reg_usb_otg1_vbus: usb_otg1_vbus {
60 compatible = "regulator-fixed";
61 regulator-name = "usb_otg1_vbus";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 gpio = <&gpio4 0 0>;
65 enable-active-high;
66 };
67
68 reg_usb_otg2_vbus: usb_otg2_vbus {
69 compatible = "regulator-fixed";
70 regulator-name = "usb_otg2_vbus";
71 regulator-min-microvolt = <5000000>;
72 regulator-max-microvolt = <5000000>;
73 gpio = <&gpio4 2 0>;
74 enable-active-high;
75 };
76 };
77
78 backlight {
79 compatible = "pwm-backlight";
80 pwms = <&pwm1 0 5000000>;
81 brightness-levels = <0 4 8 16 32 64 128 255>;
82 default-brightness-level = <6>;
83 };
84
85 csi_v4l2_cap {
86 compatible = "fsl,imx6sl-csi-v4l2";
87 status = "disabled";
88 };
89
90 pxp_v4l2_out {
91 compatible = "fsl,imx6sl-pxp-v4l2";
92 status = "okay";
93 };
94
95 sound {
96 compatible = "fsl,imx6q-sabresd-wm8962",
97 "fsl,imx-audio-wm8962";
98 model = "wm8962-audio";
99 ssi-controller = <&ssi2>;
100 audio-codec = <&codec>;
101 audio-routing =
102 "Headphone Jack", "HPOUTL",
103 "Headphone Jack", "HPOUTR",
104 "Ext Spk", "SPKOUTL",
105 "Ext Spk", "SPKOUTR",
106 "AMIC", "MICBIAS",
107 "IN3R", "AMIC";
108 amic-mono;
109 mux-int-port = <2>;
110 mux-ext-port = <3>;
111 hp-det-gpios = <&gpio4 19 1>;
112 };
113
114 sound-spdif {
115 compatible = "fsl,imx-audio-spdif",
116 "fsl,imx6sl-evk-spdif";
117 model = "imx-spdif";
118 spdif-controller = <&spdif>;
119 spdif-out;
120 };
121
122 sii902x_reset: sii902x-reset {
123 compatible = "gpio-reset";
124 reset-gpios = <&gpio2 19 1>;
125 reset-delay-us = <100000>;
126 #reset-cells = <0>;
127 };
128};
129
130&audmux {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_audmux_1>;
133 status = "okay";
134};
135
136&csi {
137 status = "disabled";
138};
139
140&ecspi1 {
141 fsl,spi-num-chipselects = <1>;
142 cs-gpios = <&gpio4 11 0>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_ecspi1_1>;
145 status = "okay";
146
147 flash: m25p80@0 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "st,m25p32";
151 spi-max-frequency = <20000000>;
152 reg = <0>;
153 };
154};
155
156&epdc {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_epdc_0>;
159 V3P3-supply = <&V3P3_reg>;
160 VCOM-supply = <&VCOM_reg>;
161 DISPLAY-supply = <&DISPLAY_reg>;
162 status = "okay";
163};
164
165&cpu0 {
166 arm-supply = <&sw1a_reg>;
167 soc-supply = <&sw1c_reg>;
168 pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
169};
170
171&fec {
172 pinctrl-names = "default", "sleep";
173 pinctrl-0 = <&pinctrl_fec_1>;
174 pinctrl-1 = <&pinctrl_fec_1_sleep>;
175 phy-mode = "rmii";
176 phy-reset-gpios = <&gpio4 21 0>; /* GPIO4_21 */
177 phy-reset-duration = <1>;
178 status = "okay";
179};
180
181&gpc {
182 fsl,cpu_pupscr_sw2iso = <0xf>;
183 fsl,cpu_pupscr_sw = <0xf>;
184 fsl,cpu_pdnscr_iso2sw = <0x1>;
185 fsl,cpu_pdnscr_iso = <0x1>;
186 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
187 fsl,wdog-reset = <1>; /* watchdog select of reset source */
188 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
189};
190
191&gpu {
192 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
193}; 17};
194 18
195&i2c1 { 19&i2c1 {
196 clock-frequency = <100000>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_i2c1_1>;
199 status = "okay";
200
201 pmic: pfuze100@08 { 20 pmic: pfuze100@08 {
202 compatible = "fsl,pfuze100"; 21 compatible = "fsl,pfuze100";
203 reg = <0x08>; 22 reg = <0x08>;
@@ -297,314 +116,4 @@
297 }; 116 };
298 }; 117 };
299 }; 118 };
300
301 elan@10 {
302 compatible = "elan,elan-touch";
303 reg = <0x10>;
304 interrupt-parent = <&gpio2>;
305 interrupts = <10 2>;
306 gpio_elan_cs = <&gpio2 9 0>;
307 gpio_elan_rst = <&gpio4 4 0>;
308 gpio_intr = <&gpio2 10 0>;
309 status = "okay";
310 };
311
312 max17135@48 {
313 compatible = "maxim,max17135";
314 reg = <0x48>;
315 vneg_pwrup = <1>;
316 gvee_pwrup = <2>;
317 vpos_pwrup = <10>;
318 gvdd_pwrup = <12>;
319 gvdd_pwrdn = <1>;
320 vpos_pwrdn = <2>;
321 gvee_pwrdn = <8>;
322 vneg_pwrdn = <10>;
323 gpio_pmic_pwrgood = <&gpio2 13 0>;
324 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
325 gpio_pmic_wakeup = <&gpio2 14 0>;
326 gpio_pmic_v3p3 = <&gpio2 7 0>;
327 gpio_pmic_intr = <&gpio2 12 0>;
328
329 regulators {
330 DISPLAY_reg: DISPLAY {
331 regulator-name = "DISPLAY";
332 };
333
334 GVDD_reg: GVDD {
335 /* 20v */
336 regulator-name = "GVDD";
337 };
338
339 GVEE_reg: GVEE {
340 /* -22v */
341 regulator-name = "GVEE";
342 };
343
344 HVINN_reg: HVINN {
345 /* -22v */
346 regulator-name = "HVINN";
347 };
348
349 HVINP_reg: HVINP {
350 /* 20v */
351 regulator-name = "HVINP";
352 };
353
354 VCOM_reg: VCOM {
355 regulator-name = "VCOM";
356 /* 2's-compliment, -4325000 */
357 regulator-min-microvolt = <0xffbe0178>;
358 /* 2's-compliment, -500000 */
359 regulator-max-microvolt = <0xfff85ee0>;
360 };
361
362 VNEG_reg: VNEG {
363 /* -15v */
364 regulator-name = "VNEG";
365 };
366
367 VPOS_reg: VPOS {
368 /* 15v */
369 regulator-name = "VPOS";
370 };
371
372 V3P3_reg: V3P3 {
373 regulator-name = "V3P3";
374 };
375 };
376 };
377
378 mma8450@1c {
379 compatible = "fsl,mma8450";
380 reg = <0x1c>;
381 };
382};
383
384&i2c2 {
385 clock-frequency = <100000>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_i2c2_1>;
388 status = "okay";
389
390 codec: wm8962@1a {
391 compatible = "wlf,wm8962";
392 reg = <0x1a>;
393 clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
394 DCVDD-supply = <&vgen3_reg>;
395 DBVDD-supply = <&reg_aud3v>;
396 AVDD-supply = <&vgen3_reg>;
397 CPVDD-supply = <&vgen3_reg>;
398 MICVDD-supply = <&reg_aud3v>;
399 PLLVDD-supply = <&vgen3_reg>;
400 SPKVDD1-supply = <&reg_aud4v>;
401 SPKVDD2-supply = <&reg_aud4v>;
402 amic-mono;
403 };
404
405 sii902x@39 {
406 compatible = "SiI,sii902x";
407 interrupt-parent = <&gpio2>;
408 interrupts = <10 2>;
409 mode_str ="1280x720M@60";
410 bits-per-pixel = <32>;
411 resets = <&sii902x_reset>;
412 reg = <0x39>;
413 };
414};
415
416&i2c3 {
417 clock-frequency = <100000>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_i2c3_1>;
420 status = "disabled";
421
422 ov564x: ov564x@3c {
423 compatible = "ovti,ov564x";
424 reg = <0x3c>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_csi_0>;
427 clocks = <&clks IMX6SL_CLK_CSI>;
428 clock-names = "csi_mclk";
429 AVDD-supply = <&vgen6_reg>; /* 2.8v */
430 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
431 pwn-gpios = <&gpio1 25 1>;
432 rst-gpios = <&gpio1 26 0>;
433 csi_id = <0>;
434 mclk = <24000000>;
435 mclk_source = <0>;
436 };
437};
438
439&iomuxc {
440 pinctrl-names = "default", "sleep";
441 pinctrl-0 = <&pinctrl_hog>;
442 pinctrl-1 = <&pinctrl_hog_sleep>;
443
444 hog {
445 pinctrl_hog: hoggrp {
446 fsl,pins = <
447 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
448 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
449 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
450 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
451 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
452 MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x80000000
453 MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x110b0
454 MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000
455 MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x80000000
456 MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x80000000
457 MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x80000000
458 MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x80000000
459 MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x170b0
460 MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
461 MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
462 MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
463 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
464 MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
465 MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
466 MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
467 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
468 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
469 >;
470 };
471
472 pinctrl_hog_sleep: hoggrp_sleep {
473 fsl,pins = <
474 MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x3080
475 MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x3080
476 MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x3080
477 >;
478 };
479 };
480};
481
482&kpp {
483 pinctrl-names = "default", "sleep";
484 pinctrl-0 = <&pinctrl_kpp_1>;
485 pinctrl-1 = <&pinctrl_kpp_1_sleep>;
486 linux,keymap = <
487 0x00000067 /* KEY_UP */
488 0x0001006c /* KEY_DOWN */
489 0x0002001c /* KEY_ENTER */
490 0x01000066 /* KEY_HOME */
491 0x0101006a /* KEY_RIGHT */
492 0x01020069 /* KEY_LEFT */
493 0x02000072 /* KEY_VOLUMEDOWN */
494 0x02010073 /* KEY_VOLUMEUP */
495 >;
496 status = "okay";
497};
498
499&lcdif {
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_lcdif_dat_0
502 &pinctrl_lcdif_ctrl_0>;
503 lcd-supply = <&reg_lcd_3v3>;
504 display = <&display>;
505 status = "okay";
506
507 display: display {
508 bits-per-pixel = <16>;
509 bus-width = <24>;
510
511 display-timings {
512 native-mode = <&timing0>;
513 timing0: timing0 {
514 clock-frequency = <33500000>;
515 hactive = <800>;
516 vactive = <480>;
517 hback-porch = <89>;
518 hfront-porch = <164>;
519 vback-porch = <23>;
520 vfront-porch = <10>;
521 hsync-len = <10>;
522 vsync-len = <10>;
523 hsync-active = <0>;
524 vsync-active = <0>;
525 de-active = <1>;
526 pixelclk-active = <0>;
527 };
528 };
529 };
530};
531
532&pwm1 {
533 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&pinctrl_pwm1_0>;
535 pinctrl-1 = <&pinctrl_pwm1_0_sleep>;
536 status = "okay";
537};
538
539&pxp {
540 status = "okay";
541};
542
543&spdif {
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_spdif_1>;
546 status = "okay";
547};
548
549&ssi2 {
550 fsl,mode = "i2s-slave";
551 status = "okay";
552};
553
554&uart1 {
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_uart1_1>;
557 status = "okay";
558};
559
560&usbotg1 {
561 vbus-supply = <&reg_usb_otg1_vbus>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_usbotg1_1>;
564 disable-over-current;
565 imx6-usb-charger-detection;
566 status = "okay";
567};
568
569&usbotg2 {
570 vbus-supply = <&reg_usb_otg2_vbus>;
571 dr_mode = "host";
572 disable-over-current;
573 status = "okay";
574};
575
576&usdhc1 {
577 pinctrl-names = "default", "state_100mhz", "state_200mhz";
578 pinctrl-0 = <&pinctrl_usdhc1_1>;
579 pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
580 pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
581 bus-width = <8>;
582 cd-gpios = <&gpio4 7 0>;
583 wp-gpios = <&gpio4 6 0>;
584 keep-power-in-suspend;
585 enable-sdio-wakeup;
586 status = "okay";
587};
588
589&usdhc2 {
590 pinctrl-names = "default", "state_100mhz", "state_200mhz";
591 pinctrl-0 = <&pinctrl_usdhc2_1>;
592 pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
593 pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
594 cd-gpios = <&gpio5 0 0>;
595 wp-gpios = <&gpio4 29 0>;
596 keep-power-in-suspend;
597 enable-sdio-wakeup;
598 status = "okay";
599};
600
601&usdhc3 {
602 pinctrl-names = "default", "state_100mhz", "state_200mhz";
603 pinctrl-0 = <&pinctrl_usdhc3_1>;
604 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
605 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
606 cd-gpios = <&gpio3 22 0>;
607 keep-power-in-suspend;
608 enable-sdio-wakeup;
609 status = "okay";
610}; 119};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-24 23:15:49 -0400