diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2014-03-10 02:38:19 -0400 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:56 -0400 |
| commit | 839479a02802a4d3493bb01790f812f01f898a38 (patch) | |
| tree | 36ca13330688d6960b5faf544fbf352b3de4767d | |
| parent | 4cd4b027fa46eabddcfb9f81331bca76932c1ced (diff) | |
ENGR00302472-2 ARM: imx6q: Add imx6sx LDB mux ctrl bit definitions
This patch adds LDB mux ctrl bit definitions for imx6sx.
The bit DISP_MUX_LDB_MUX_CTRL is defined in the register IOMUXC_GPR5.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index 260c55b589e9..45127146a1b8 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |||
| @@ -393,4 +393,8 @@ | |||
| 393 | #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17) | 393 | #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17) |
| 394 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13) | 394 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13) |
| 395 | 395 | ||
| 396 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) | ||
| 397 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) | ||
| 398 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) | ||
| 399 | |||
| 396 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ | 400 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |