diff options
author | Robby Cai <R63905@freescale.com> | 2014-03-11 06:41:45 -0400 |
---|---|---|
committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:58 -0400 |
commit | 0bbdbb89b92a70997d3a33075bc34e948eea8d9d (patch) | |
tree | 5730cd456d1b56682a1fd88fb64e6700a5769974 | |
parent | b14266fa5337375ce4b4008e8eb8315afda5227b (diff) |
ENGR00302869-1 ARM: dts: imx6qdl: add cfg_clk for MIPI CSI2
MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.
Signed-off-by: Robby Cai <R63905@freescale.com>
-rw-r--r-- | Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt | 4 | ||||
-rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt b/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt index 4b502809fc2d..d10f23721f34 100644 --- a/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt +++ b/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt | |||
@@ -27,8 +27,8 @@ for SOC imx6qdl.dtsi: | |||
27 | compatible = "fsl,imx6q-mipi-csi2"; | 27 | compatible = "fsl,imx6q-mipi-csi2"; |
28 | reg = <0x021dc000 0x4000>; | 28 | reg = <0x021dc000 0x4000>; |
29 | interrupts = <0 100 0x04>, <0 101 0x04>; | 29 | interrupts = <0 100 0x04>, <0 101 0x04>; |
30 | clocks = <&clks 138>, <&clks 53>; | 30 | clocks = <&clks 138>, <&clks 53>, <&clks 204>; |
31 | clock-names = "dphy_clk", "pixel_clk"; | 31 | clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; |
32 | status = "disabled"; | 32 | status = "disabled"; |
33 | }; | 33 | }; |
34 | 34 | ||
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 01414a575ab6..79af4b686e81 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
@@ -960,13 +960,13 @@ | |||
960 | compatible = "fsl,imx6q-mipi-csi2"; | 960 | compatible = "fsl,imx6q-mipi-csi2"; |
961 | reg = <0x021dc000 0x4000>; | 961 | reg = <0x021dc000 0x4000>; |
962 | interrupts = <0 100 0x04>, <0 101 0x04>; | 962 | interrupts = <0 100 0x04>, <0 101 0x04>; |
963 | clocks = <&clks 138>, <&clks 53>; | 963 | clocks = <&clks 138>, <&clks 53>, <&clks 204>; |
964 | /* Note: clks 138 is hsi_tx, however, the dphy_c | 964 | /* Note: clks 138 is hsi_tx, however, the dphy_c |
965 | * hsi_tx and pll_refclk use the same clk gate. | 965 | * hsi_tx and pll_refclk use the same clk gate. |
966 | * In current clk driver, open/close clk gate do | 966 | * In current clk driver, open/close clk gate do |
967 | * use hsi_tx for a temporary debug purpose. | 967 | * use hsi_tx for a temporary debug purpose. |
968 | */ | 968 | */ |
969 | clock-names = "dphy_clk", "pixel_clk"; | 969 | clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; |
970 | status = "disabled"; | 970 | status = "disabled"; |
971 | }; | 971 | }; |
972 | 972 | ||