ENGR00318063-3: ARM: imx6sx: fix ocram_sels mux setting

The current imx6sx clock driver combines two mux clocks ocram_alt_sel
and ocram_sel into one, while ocram_alt_sel is a glitchy mux and
ocram_sel is a glitchless one.  Fix it to match the clock tree in
Reference Manual.

One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy ocram_alt_sel only when ocram_sel selects the
other path, i.e. periph.  Otherwise, a glitch could be generated on
ocram_alt_sel and get propagated into the divider ocram_podf.  In that
case, ocram_podf gets locked up and ocram clock has no output.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

2 files changed, 6 insertions, 3 deletions

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 0844e5ce2f32..e65fb6f58c6a 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -36,7 +36,8 @@ static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", };
 static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "osc", };
 static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
 static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
-static const char *ocram_sels[]         = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
+static const char *ocram_alt_sels[]     = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ocram_sels[]         = { "periph", "ocram_alt_sel", };
 static const char *audio_sels[]         = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
 static const char *gpu_axi_sels[]       = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
 static const char *gpu_core_sels[]      = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
@@ -224,7 +225,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         /*                                                name                reg           shift   width   parent_names       num_parents */
         clks[IMX6SX_CLK_STEP]               = imx_clk_mux("step",             base + 0xc,   8,      1,      step_sels,         ARRAY_SIZE(step_sels));
         clks[IMX6SX_CLK_PLL1_SW]            = imx_clk_mux("pll1_sw",          base + 0xc,   2,      1,      pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
-        clks[IMX6SX_CLK_OCRAM_SEL]          = imx_clk_mux("ocram_sel",        base + 0x14,  6,      2,      ocram_sels,        ARRAY_SIZE(ocram_sels));
+        clks[IMX6SX_CLK_OCRAM_ALT_SEL]      = imx_clk_mux("ocram_alt_sel",    base + 0x14,  7,      1,      ocram_alt_sels,    ARRAY_SIZE(ocram_alt_sels));
+        clks[IMX6SX_CLK_OCRAM_SEL]          = imx_clk_mux("ocram_sel",        base + 0x14,  6,      1,      ocram_sels,        ARRAY_SIZE(ocram_sels));
         clks[IMX6SX_CLK_PERIPH_PRE]         = imx_clk_mux("periph_pre",       base + 0x18,  18,     2,      periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
         clks[IMX6SX_CLK_PERIPH2_PRE]        = imx_clk_mux("periph2_pre",      base + 0x18,  21,     2,      periph2_pre_sels,   ARRAY_SIZE(periph2_pre_sels));
         clks[IMX6SX_CLK_PERIPH_CLK2_SEL]    = imx_clk_mux("periph_clk2_sel",  base + 0x18,  12,     2,      periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 421d8bb76f2f..0e3710cdd5f6 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -251,6 +251,7 @@
 #define IMX6SX_CLK_SAI2_IPG             238
 #define IMX6SX_CLK_ESAI_IPG             239
 #define IMX6SX_CLK_ESAI_MEM             240
-#define IMX6SX_CLK_CLK_END              241
+#define IMX6SX_CLK_OCRAM_ALT_SEL        241
+#define IMX6SX_CLK_CLK_END              242
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */