ENGR00319792 ARM: imx: need to make sure MMDC auto self refresh is enabled

When there is busfreq scaling between low power mode and audio bus
mode, the enabling of MMDC auto self-refresh code will be skipped
as they are both DLL off mode, it will cause DDR power increase,
so we just move the enabling of the MMDC auto self-refresh mode
to the end of busfreq change to make sure it is enabled after a
DDR freq change.

Signed-off-by: Anson Huang <b20788@freescale.com>

2 files changed, 10 insertions, 20 deletions

diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S
index 25406d45ccb8..8137f513c787 100644
--- a/arch/arm/mach-imx/ddr3_freq_imx6.S
+++ b/arch/arm/mach-imx/ddr3_freq_imx6.S
@@ -623,11 +623,6 @@ update_iomux:
         orr     r0, r0, #(0x1 << 29)
         str     r0, [r5, r2]
 
-        /* MMDC0_MAPSR adopt power down enable. */
-        ldr     r0, [r5, #MMDC0_MAPSR]
-        bic     r0, r0, #0x01
-        str     r0, [r5, #MMDC0_MAPSR]
-
         /* frc_msr + mu bypass */
         ldr     r0, =0x00000060
         str     r0, [r5, #MMDC0_MPMUR0]
@@ -867,11 +862,6 @@ cont15:
         cmp     r1, #0
         bgt     delay15
 
-        /* MMDC0_MAPSR adopt power down enable. */
-        ldr     r0, [r5, #MMDC0_MAPSR]
-        bic     r0, r0, #0x01
-        str     r0, [r5, #MMDC0_MAPSR]
-
         /* enable MMDC power down timer. */
         ldr     r0, [r5, #MMDC0_MDPDC]
         orr     r0, r0, #(0x55 << 8)
@@ -920,6 +910,11 @@ poll_conreq_clear_2:
 
 done:
 
+        /* MMDC0_MAPSR adopt power down enable. */
+        ldr     r0, [r5, #MMDC0_MAPSR]
+        bic     r0, r0, #0x01
+        str     r0, [r5, #MMDC0_MAPSR]
+
 #ifdef CONFIG_CACHE_L2X0
         /* Enable L2. */
         ldr     r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
diff --git a/arch/arm/mach-imx/ddr3_freq_imx6sx.S b/arch/arm/mach-imx/ddr3_freq_imx6sx.S
index f2e523f47a43..d0f692c39e64 100644
--- a/arch/arm/mach-imx/ddr3_freq_imx6sx.S
+++ b/arch/arm/mach-imx/ddr3_freq_imx6sx.S
@@ -406,11 +406,6 @@ update_iomux:
         orr     r8, r8, #(1 << 29)
         str     r8, [r4, #MMDC0_MPDGCTRL0]
 
-        /* MMDC0_MAPSR adopt power down enable. */
-        ldr     r8, [r4, #MMDC0_MAPSR]
-        bic     r8, r8, #0x1
-        str     r8, [r4, #MMDC0_MAPSR]
-
         /* frc_msr + mu bypass */
         ldr     r8, =0x00000160
         str     r8, [r4, #MMDC0_MPMUR0]
@@ -582,11 +577,6 @@ update_iomux1:
         ldr     r8, =40
         do_delay
 
-        /* MMDC0_MAPSR adopt power down enable. */
-        ldr     r8, [r4, #MMDC0_MAPSR]
-        bic     r8, r8, #0x01
-        str     r8, [r4, #MMDC0_MAPSR]
-
         /* enable MMDC power down timer. */
         ldr     r8, [r4, #MMDC0_MDPDC]
         orr     r8, r8, #(0x55 << 8)
@@ -633,6 +623,11 @@ poll_conreq_clear_2:
 
 done:
 
+        /* MMDC0_MAPSR adopt power down enable. */
+        ldr     r8, [r4, #MMDC0_MAPSR]
+        bic     r8, r8, #0x01
+        str     r8, [r4, #MMDC0_MAPSR]
+
 #ifdef CONFIG_CACHE_L2X0
         /* Enable L2. */
         ldr     r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)