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authorShawn Guo <shawn.guo@freescale.com>2014-05-25 22:57:22 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-06-25 09:17:20 -0400
commit32c6168061643d5c6dc0a450705cfd70861f7394 (patch)
tree7feba22807cbd79fb4a6f490544b7844bec4b4ca
parentc7b8e407591afb7d8976bb9fc3128f921282b7c6 (diff)
ENGR00318063-4: ARM: imx: drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags
All the users of function imx_clk_mux_flags() set CLK_SET_RATE_PARENT to request rate change propagatiopn up to parent. In this case, it should be good to clear flag CLK_SET_RATE_NO_REPARENT to let clk core find the best parent clock for the requested rate. Let's drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags(), so that function imx_clk_mux_flags_reparent() can just be saved. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c4
-rw-r--r--arch/arm/mach-imx/clk.h10
2 files changed, 2 insertions, 12 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index e65fb6f58c6a..41d6c332b3af 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -242,13 +242,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
242 clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 242 clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
243 clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 243 clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
244 clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 244 clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
245 clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux_flags_reparent("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT); 245 clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux_flags("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT);
246 clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); 246 clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
247 clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels)); 247 clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
248 clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 248 clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
249 clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); 249 clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
250 clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); 250 clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
251 clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux_flags_reparent("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT); 251 clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
252 clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 252 clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
253 clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 253 clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
254 clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels)); 254 clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 319a9660e4c2..0f9076909517 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -110,16 +110,6 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
110 int num_parents, unsigned long flags) 110 int num_parents, unsigned long flags)
111{ 111{
112 return clk_register_mux(NULL, name, parents, num_parents, 112 return clk_register_mux(NULL, name, parents, num_parents,
113 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
114 &imx_ccm_lock);
115}
116
117/* we can use this helper to register the clock which needs the re-parent. */
118static inline struct clk *imx_clk_mux_flags_reparent(const char *name,
119 void __iomem *reg, u8 shift, u8 width, const char **parents,
120 int num_parents, unsigned long flags)
121{
122 return clk_register_mux(NULL, name, parents, num_parents,
123 flags, reg, shift, width, 0, 113 flags, reg, shift, width, 0,
124 &imx_ccm_lock); 114 &imx_ccm_lock);
125} 115}