ENGR00318938-1 serial: imx: add UART save/restore during DSM enter/exit

When Mega/Fast mix is off, UART controller will lost power,
so need to add save/restore to make it work after resume.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>

1 files changed, 26 insertions, 0 deletions

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index e2f93874989b..62c0cd5fe7c7 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -226,6 +226,7 @@ struct imx_port {
         unsigned int            tx_bytes;
         unsigned int            dma_tx_nents;
         wait_queue_head_t       dma_wait;
+        unsigned int            saved_reg[11];
 };
 
 struct imx_port_ucrs {
@@ -1810,6 +1811,19 @@ static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
 
         uart_suspend_port(&imx_reg, &sport->port);
 
+        /* Save necessary regs */
+        sport->saved_reg[0] = readl(sport->port.membase + UCR1);
+        sport->saved_reg[1] = readl(sport->port.membase + UCR2);
+        sport->saved_reg[2] = readl(sport->port.membase + UCR3);
+        sport->saved_reg[3] = readl(sport->port.membase + UCR4);
+        sport->saved_reg[4] = readl(sport->port.membase + UFCR);
+        sport->saved_reg[5] = readl(sport->port.membase + UESC);
+        sport->saved_reg[6] = readl(sport->port.membase + UTIM);
+        sport->saved_reg[7] = readl(sport->port.membase + UBIR);
+        sport->saved_reg[8] = readl(sport->port.membase + UBMR);
+        sport->saved_reg[9] = readl(sport->port.membase + UBRC);
+        sport->saved_reg[10] = readl(sport->port.membase + IMX21_UTS);
+
         return 0;
 }
 
@@ -1818,6 +1832,18 @@ static int serial_imx_resume(struct platform_device *dev)
         struct imx_port *sport = platform_get_drvdata(dev);
         unsigned int val;
 
+        writel(sport->saved_reg[4], sport->port.membase + UFCR);
+        writel(sport->saved_reg[5], sport->port.membase + UESC);
+        writel(sport->saved_reg[6], sport->port.membase + UTIM);
+        writel(sport->saved_reg[7], sport->port.membase + UBIR);
+        writel(sport->saved_reg[8], sport->port.membase + UBMR);
+        writel(sport->saved_reg[9], sport->port.membase + UBRC);
+        writel(sport->saved_reg[10], sport->port.membase + IMX21_UTS);
+        writel(sport->saved_reg[0], sport->port.membase + UCR1);
+        writel(sport->saved_reg[1] | 0x1, sport->port.membase + UCR2);
+        writel(sport->saved_reg[2], sport->port.membase + UCR3);
+        writel(sport->saved_reg[3], sport->port.membase + UCR4);
+
         /* disable wakeup from i.MX UART */
         val = readl(sport->port.membase + UCR3);
         val &= ~UCR3_AWAKEN;