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authorLoren HUANG <b02279@freescale.com>2014-03-20 06:27:15 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:58:04 -0400
commit2da2e5b4425e79da040e941c8d96597c24fd2e02 (patch)
treeb4662cf3df07d117ee099e952789bfd88b0df4ee
parent8a8d01c68e555fec1bb4bb35331d432b1da63d08 (diff)
ENGR00303542-2 Change pu dummy for i.mx6sx
-Change pu dummy for i.mx6sx to allow gpu power operation Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Loren Huang <b02279@freescale.com>
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi9
-rw-r--r--arch/arm/mach-imx/anatop.c5
-rw-r--r--arch/arm/mach-imx/gpc.c13
3 files changed, 24 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 6a527c7a02b3..73285aa81334 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -72,6 +72,10 @@
72 }; 72 };
73 }; 73 };
74 74
75 pu_dummy: pudummy_reg {
76 compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
77 };
78
75 soc { 79 soc {
76 #address-cells = <1>; 80 #address-cells = <1>;
77 #size-cells = <1>; 81 #size-cells = <1>;
@@ -352,9 +356,12 @@
352 }; 356 };
353 357
354 gpc: gpc@020dc000 { 358 gpc: gpc@020dc000 {
355 compatible = "fsl,imx6q-gpc", "syscon"; 359 compatible = "fsl,imx6q-gpc";
356 reg = <0x020dc000 0x4000>; 360 reg = <0x020dc000 0x4000>;
357 interrupts = <0 89 0x04>; 361 interrupts = <0 89 0x04>;
362 clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>;
363 clock-names = "gpu3d_core", "ipg";
364 pu-supply = <&pu_dummy>;
358 }; 365 };
359 366
360 gpio1: gpio@0209c000 { 367 gpio1: gpio@0209c000 {
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 9bdea7ec68b2..a2795cc3c7bb 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 5 * License. You may obtain a copy of the GNU General Public License
@@ -112,6 +112,9 @@ void imx_anatop_pu_enable(bool enable)
112{ 112{
113 u32 val; 113 u32 val;
114 114
115 if (cpu_is_imx6sx())
116 return;
117
115 regmap_read(anatop, ANADIG_REG_CORE, &val); 118 regmap_read(anatop, ANADIG_REG_CORE, &val);
116 val &= ANADIG_REG_TARG_MASK << ANADIG_REG2_TARG_SHIFT; 119 val &= ANADIG_REG_TARG_MASK << ANADIG_REG2_TARG_SHIFT;
117 /* 120 /*
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 97343277d1e8..7b6035cf1a7b 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 2 * Copyright 2011-2014 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -225,6 +225,8 @@ static void imx_pu_clk(bool enable)
225 if (cpu_is_imx6sl()) { 225 if (cpu_is_imx6sl()) {
226 clk_prepare_enable(gpu2d_clk); 226 clk_prepare_enable(gpu2d_clk);
227 clk_prepare_enable(openvg_axi_clk); 227 clk_prepare_enable(openvg_axi_clk);
228 } else if (cpu_is_imx6sx()) {
229 clk_prepare_enable(gpu3d_clk);
228 } else { 230 } else {
229 clk_prepare_enable(gpu3d_clk); 231 clk_prepare_enable(gpu3d_clk);
230 clk_prepare_enable(gpu3d_shader_clk); 232 clk_prepare_enable(gpu3d_shader_clk);
@@ -237,6 +239,8 @@ static void imx_pu_clk(bool enable)
237 if (cpu_is_imx6sl()) { 239 if (cpu_is_imx6sl()) {
238 clk_disable_unprepare(gpu2d_clk); 240 clk_disable_unprepare(gpu2d_clk);
239 clk_disable_unprepare(openvg_axi_clk); 241 clk_disable_unprepare(openvg_axi_clk);
242 } else if (cpu_is_imx6sx()) {
243 clk_disable_unprepare(gpu3d_clk);
240 } else { 244 } else {
241 clk_disable_unprepare(gpu3d_clk); 245 clk_disable_unprepare(gpu3d_clk);
242 clk_disable_unprepare(gpu3d_shader_clk); 246 clk_disable_unprepare(gpu3d_shader_clk);
@@ -492,6 +496,13 @@ static int imx_gpc_probe(struct platform_device *pdev)
492 dev_err(gpc_dev, "failed to get clk!\n"); 496 dev_err(gpc_dev, "failed to get clk!\n");
493 return -ENOENT; 497 return -ENOENT;
494 } 498 }
499 } else if (cpu_is_imx6sx()) {
500 gpu3d_clk = devm_clk_get(gpc_dev, "gpu3d_core");
501 ipg_clk = devm_clk_get(gpc_dev, "ipg");
502 if (IS_ERR(gpu3d_clk) || IS_ERR(ipg_clk)) {
503 dev_err(gpc_dev, "failed to get clk!\n");
504 return -ENOENT;
505 }
495 } else { 506 } else {
496 gpu3d_clk = devm_clk_get(gpc_dev, "gpu3d_core"); 507 gpu3d_clk = devm_clk_get(gpc_dev, "gpu3d_core");
497 gpu3d_shader_clk = devm_clk_get(gpc_dev, "gpu3d_shader"); 508 gpu3d_shader_clk = devm_clk_get(gpc_dev, "gpu3d_shader");